Vertical neuron transistor with learning rate scheduling function and preparation method thereof
By designing vertical neuron transistors, combined with the coupling modulation of Schottky gate and ferroelectric gate, adjustable slope conductance update behavior with high linearity and symmetry is achieved, and the problems of slow convergence speed and objective function fluctuations caused by fixed learning rates in existing neural network hardware are solved, improving training efficiency and accuracy.
Patent Information
- Application Number
- CN202411989354.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-04-25
AI Technical Summary
During the training process, existing neural network hardware is unable to flexibly process a large amount of data that is frequently iterated due to the fixed learning rate.
A vertical neuron transistor is designed to realize the learning rate scheduling function by achieving adjustable slope conductance update behavior with high linearity and symmetry at the device level, and combining the coupling modulation of Schottky gate and ferroelectric gate.
It realizes adjustable slope conductance update behavior with high linearity and symmetry, can flexibly adjust the weight update slope, supports learning rate scheduling function, and improves the training efficiency and accuracy of neural network hardware.
Smart Images
Figure CN119894213A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor transistor devices, and in particular to a vertical neuron transistor and a preparation method thereof. Background Art
[0002] With the advancement of artificial intelligence, neuromorphic computing has become a promising paradigm to overcome the energy consumption limitations of von Neumann architectures. The performance and application potential of neural network technology mainly depend on its learning ability (i.e., the training process). Extensive research has focused on developing linear and symmetric analog programming methods to improve the training efficiency of neural network hardware. However, current research schemes can only produce fixed learning rates; however, during the training of neural networks, slower learning rates may lead to slow convergence and long training time, while, on the contrary, too fast learning rates may cause significant fluctuations in the objective function, making it impossible to reach the optimal value. Therefore, whether slow or fast, fixed learning rates cannot flexibly handle large amounts of data with frequent iterations.
[0003] Considering the relationship between learning rate and convergence, the ideal neural network training process should include learning rate scheduling. Specifically, learning rate scheduling allows the initial use of relatively high learning rates to quickly approximate different local optimal solutions, and then gradually reduces the speed to fine-tune to the global optimal solution. In order to achieve learning rate scheduling capabilities, two hardware requirements must be met at the device level: 1) maintain high linearity and symmetry of conductance update behavior, and 2) flexibly adjust the weight update slope over a wide range. However, most non-volatile memories lack this adjustability in memory properties, which hinders the hardware implementation of learning rate scheduling. Therefore, there is an urgent need to solve this substantial problem through reasonable material matching, device design, and physics to realize neuromorphic hardware systems with integrated learning rate scheduling capabilities. Summary of the invention
[0004] Purpose of the invention: In view of the above-mentioned prior art, a vertical neuron transistor with a learning rate scheduling function is proposed, which can achieve an adjustable slope conductance update behavior with high linearity and symmetry, and a preparation method of the device is proposed.
[0005] Technical solution: A vertical neuron transistor with a learning rate scheduling function, comprising a Si substrate, a SiO2 layer, a TiN layer as a Schottky gate, an insulating layer, a TiN gate layer as a ferroelectric gate, and a ferroelectric layer, which are arranged in sequence from bottom to top; wherein the width of the TiN gate layer as a ferroelectric gate is smaller than that of other layers; the common side of the ferroelectric layer, the insulating layer, the TiN layer as a Schottky gate, and the side of a partial thickness of the SiO2 layer together form a vertical sidewall structure; the upper surface of the SiO2 layer and the upper surface of the ferroelectric layer are respectively provided with a source and a drain, and the surface of the source, the drain and the vertical sidewall structure is provided with a continuous organic semiconductor layer; wherein the ferroelectric layer has a dipole that can produce stable polarization.
[0006] Furthermore, the material of the insulating layer is silicon dioxide, parylene, or hafnium oxide.
[0007] Furthermore, the material of the ferroelectric layer is polyvinylidene fluoride-trifluoroethylene, polyvinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene, or hafnium zirconium oxide.
[0008] Furthermore, the thickness of the ferroelectric layer is less than 20 nm.
[0009] Furthermore, the organic semiconductor layer is a p-type semiconductor.
[0010] Furthermore, the TiN layer as the Schottky gate and the TiN gate layer as the ferroelectric gate are used to couple and modulate the conductivity of the organic semiconductor layer, wherein the TiN layer as the Schottky gate is loaded with a step voltage sequence.
[0011] The preparation method of the vertical neuron transistor includes the following steps: using a Si / SiO2 composite substrate, sequentially growing a TiN layer as a Schottky gate, an insulating layer, a TiN gate layer as a ferroelectric gate, and a ferroelectric layer on the substrate; then using an etching process to etch away the ferroelectric layer, the insulating layer, the TiN layer as a Schottky gate, and a partial thickness of the SiO2 layer in a specific area to obtain the vertical sidewall structure; growing Au as a source and a drain on the upper surface of the SiO2 layer and the upper surface of the ferroelectric layer respectively; and finally growing the organic semiconductor layer.
[0012] Beneficial effects: The ferroelectric layer used in the device of the present invention has stable dipole polarization. The joint modulation of the conductivity of the organic semiconductor layer by the Schottky gate and the ferroelectric gate can enable the device of the present invention to achieve highly linear and symmetrical adjustable slope conductivity update behavior, which is used to construct a neuromorphic hardware system with integrated learning rate scheduling function. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 is a structural diagram of a specific example of the present invention; Figure 2is a preparation flow chart of a specific example of the present invention; Figure 3 A transfer characteristic curve diagram of a vertical neuron transistor in a ferroelectric transistor working mode manufactured according to an embodiment of the present invention; Figure 4 A transfer characteristic diagram of a vertical neuron transistor manufactured in an embodiment of the present invention in a metal semiconductor field effect transistor working mode; Figure 5 The modulation process (from nonlinear to linear) of the conductance updating behavior of the vertical neuron transistor manufactured in the embodiment of the present invention at various slopes; Figure 6 The step-shaped Schottky gate voltage sequence required by the vertical neuron transistor manufactured by the embodiment of the present invention when modulating the conductance update behavior; Figure 7 A durability test of the conductance updating behavior of the vertical neuron transistor produced in the embodiment of the present invention; Figure 8 It is the deviation between each actually measured conductance state and the ideal state in the conductance update behavior of the vertical neuron transistor manufactured in the embodiment of the present invention.
[0014] Fig. 9 The memory characteristics of the vertical neuron transistor manufactured according to the embodiment of the present invention. DETAILED DESCRIPTION
[0015] The present invention is described in detail below with reference to the accompanying drawings.
[0016] like Figure 1 As shown, a vertical neuron transistor with a learning rate scheduling function includes a Si substrate, a SiO2 layer, a TiN layer as a Schottky gate, an insulating layer, a TiN gate layer as a ferroelectric gate, and a ferroelectric layer arranged in sequence from bottom to top. From top to bottom, the ferroelectric layer, the insulating layer, the TiN layer (Schottky gate), and a partially thick SiO2 layer on one side are etched to form a vertical sidewall structure, and a source and a drain are arranged on the partially thick SiO2 layer retained after etching and above the ferroelectric layer, and a continuous organic semiconductor layer grows on the surface of the source, the drain, and the vertical sidewall structure.
[0017] The ferroelectric layer has a dipole that can generate stable polarization, and the thickness of the ferroelectric layer is less than 20nm. The insulating layer is made of silicon dioxide, parylene, or hafnium oxide. The ferroelectric layer is made of polyvinylidene fluoride-trifluoroethylene, polyvinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene, or hafnium zirconium oxide. The organic semiconductor layer is a p-type semiconductor.
[0018] like Figure 2 As shown, in this embodiment, the method for preparing a vertical neuron transistor with a learning rate scheduling function includes the following steps: Step 1: Using a Si / SiO2 composite substrate, ultrasonically clean the substrate with acetone, isopropanol and deionized water in sequence.
[0019] Step 2: A 20 nm thick TiN layer is patterned on the substrate using electron beam evaporation and photolithography to serve as a Schottky gate. A 25 nm thick hafnium oxide layer is then grown using atomic layer deposition to serve as an insulating layer. A 20 nm thick TiN layer is patterned using electron beam evaporation and photolithography to serve as a ferroelectric gate. The width of the ferroelectric gate is smaller than that of other layer structures to avoid damage in subsequent etching processes. A 15 nm thick hafnium zirconium oxide (Zr[Hf]O2) layer is then grown on the top of the device using atomic layer deposition to serve as a ferroelectric layer. The ferroelectric layer, insulating layer, TiN layer (Schottky gate), and a partially thick SiO2 layer are then etched away from top to bottom using ion beam etching and photolithography to obtain a vertical sidewall structure.
[0020] Step 3: Use metal thermal evaporation and photolithography to grow 30 nm Au on the SiO2 layer that remains partially thick after etching and on the ferroelectric layer, respectively, as the source and drain electrodes; finally, use the floating coffee ring effect and phase separation method to simultaneously grow continuous polymethyl methacrylate (PMMA) and organic small molecule layer C8-BTBT on the surface of the source, drain and vertical sidewall structure as the organic semiconductor layer, completing the following steps: Figure 1 The preparation of the artificial neuron transistor shown.
[0021] like Figure 3 As shown in FIG. 1 , it is a cyclic test curve of the transfer characteristics of the vertical neuron transistor prepared in this embodiment in the ferroelectric transistor working mode. It can be observed that all the transfer curves overlap well, showing the stable electrical performance of the device. At the same time, the transfer characteristic curve shows a counterclockwise hysteresis, which is due to the spontaneous polarization of the ferroelectric layer under the action of the external electric field. When the external electric field is removed, the ferroelectric layer still retains a certain residual polarization intensity, and the channel still has a certain conductivity. Only when the reverse electric field increases to a certain value, the residual polarization disappears completely and the device returns to the initial state.
[0022] like Figure 4 As shown, it is the transfer characteristic curve of the vertical neuron transistor prepared in this embodiment in the metal semiconductor field effect transistor working mode. It can be observed that the curve shows an almost negligible hysteresis window and a steep switching characteristic. This is because there is no dielectric layer in the metal semiconductor field effect transistor, which ensures that any change in the gate potential can be effectively transmitted to the semiconductor channel with an ideal energy barrier drop. Therefore, this transistor has an extremely low operating voltage and steep switching characteristics, allowing the channel conductance to be accurately adjusted over a wide range with a very small voltage span.
[0023] like Figures 5 to 7 As shown, it is the modulation process of the conductance update behavior of the vertical neuron transistor prepared in this embodiment at various slopes. If the Schottky gate does not contribute to the channel modulation (i.e., the same Schottky gate voltage sequence is used), nonlinear conductance update behavior can be observed due to the non-ideal switching process caused by interface defects or traps. Nonlinear weight update behavior can lead to incorrect conductance states, which brings challenges to the implementation of learning rate scheduling at the hardware level. When the channel conductance is modulated by the number of pulses, it can be observed that the step size of the conductance varies greatly in the early stage, while the step size changes less in the later stage. Therefore, based on this nonlinear behavior, a step voltage sequence is preset in the Schottky gate, and the device can complete the adjustable slope conductance update behavior with high linearity and symmetry by using the ferroelectric polarization effect and the coupled modulation of the Schottky gate. Preferably, the step voltage sequence can be determined by the deviation of each actually measured conductance state from the ideal state, wherein the ideal state is the conductance value of each conductance state when the linearity is 1.
[0024] like Figure 8 As shown, it is a durability test of the conductance update behavior of the vertical neuron transistor prepared in this embodiment. It can be observed that all the curves overlap well, demonstrating the stable electrical performance of the device.
[0025] like Fig. 9 The figure shows the storage characteristics of the vertical neuron transistor prepared in this embodiment. By changing the number of pulses applied to the ferroelectric gate, the channel current can be maintained at different levels, and the holding time is up to 10 3 seconds. This is because the ferroelectric dipoles polarize under the action of an electrical pulse that exceeds the coercive voltage of the ferroelectric layer. The channel current of the device can be maintained at a certain level due to the remanent polarization of the ferroelectric layer. As the number of applied electrical pulses increases, more dipoles in the ferroelectric layer polarize, resulting in a larger remanent polarization of the ferroelectric layer after the electrical pulse ends, which keeps the channel current at a higher level.
[0026] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A vertical neuron transistor with a learning rate scheduling function, characterized in that: It comprises a Si substrate, a SiO2 layer, a TiN layer as a Schottky gate, an insulating layer, a TiN gate layer as a ferroelectric gate, and a ferroelectric layer, which are arranged in sequence from bottom to top; wherein the width of the TiN gate layer as a ferroelectric gate is smaller than that of other layers; the common side of the ferroelectric layer, the insulating layer, the TiN layer as a Schottky gate, and the side of a partial thickness of the SiO2 layer together form a vertical sidewall structure; the upper surface of the SiO2 layer and the upper surface of the ferroelectric layer are respectively provided with a source and a drain, and the surface of the source, the drain and the vertical sidewall structure is provided with a continuous organic semiconductor layer; wherein the ferroelectric layer has a dipole that can produce stable polarization.
2. The vertical neuron transistor according to claim 1, characterized in that: The insulating layer is made of silicon dioxide, parylene, or hafnium oxide.
3. The vertical neuron transistor according to claim 1, characterized in that: The material of the ferroelectric layer is polyvinylidene fluoride-trifluoroethylene, polyvinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene, or hafnium zirconium oxide.
4. The vertical neuron transistor according to claim 1, characterized in that: The thickness of the ferroelectric layer is less than 20 nm.
5. The vertical neuron transistor according to claim 1, characterized in that: The organic semiconductor layer is a p-type semiconductor.
6. The vertical neuron transistor according to claim 5, characterized in that: The TiN layer as the Schottky gate and the TiN gate layer as the ferroelectric gate are used for coupling and modulating the conductivity of the organic semiconductor layer, wherein the TiN layer as the Schottky gate is loaded with a step voltage sequence.
7. The method for preparing a vertical neuron transistor according to any one of claims 1 to 6, characterized in that: The method comprises the following steps: using a Si / SiO2 composite substrate, sequentially growing a TiN layer as a Schottky gate, an insulating layer, a TiN gate layer as a ferroelectric gate, and a ferroelectric layer on the substrate; then etching away the ferroelectric layer, the insulating layer, the TiN layer as a Schottky gate, and a partial thickness of the SiO2 layer in a specific area using an etching process to obtain the vertical sidewall structure; growing Au as a source electrode and a drain electrode on the upper surface of the SiO2 layer and the upper surface of the ferroelectric layer respectively; and finally growing the organic semiconductor layer.