Complementary organic storage and calculation integrated NOT gate circuit and preparation method thereof

Abstract

The invention discloses a complementary organic storage and calculation integrated NOT gate circuit and a preparation method thereof, and belongs to the technical field of organic integrated circuits, the complementary organic storage and calculation integrated NOT gate circuit comprises a substrate, and a gate electrode, a ferroelectric gate polymer gate dielectric layer, an interface passivation layer and an organic semiconductor layer which are located on the substrate, the organic semiconductor layer comprises a p-type organic semiconductor layer and an n-type organic semiconductor layer, a source electrode and a drain electrode are arranged on the first electrode and the second electrode; the p-type organic transistor memory and the n-type organic transistor memory are connected in series and share one gate electrode as an input end VIN; and a source electrode on the p-type organic semiconductor layer is connected with a drain electrode on the n-type organic semiconductor layer to serve as an output end VOUT. According to the NOT gate circuit, a data storage function is added on the basis of executing the NOT logic operation; after the input signal is removed, the result of the non-logic operation can be permanently stored in the gate circuit, so that the working energy consumption can be obviously reduced; and the main body of the used material is an organic / polymer material, so that the method has the advantages of simple process, low-temperature preparation, low cost and suitability for flexible application.

Description

Technical Field

[0001] The present invention belongs to the technical field of organic integrated circuits, and in particular relates to a complementary organic NOT gate circuit integrating data storage and logic operation and a preparation method thereof. Background Art

[0002] Modern computers are based on the von Neumann architecture, in which the arithmetic unit and the memory are two separate units. With the development of chip technology, the time and energy consumption required for frequent data exchange between the arithmetic unit and the memory have gradually become a bottleneck problem restricting the improvement of computer performance due to the continuous reduction in transistor size, which is the so-called von Neumann bottleneck. In recent years, the development of integrated storage and computing integrated circuits, that is, integrating data storage and logical operations in the same unit chip, is regarded as one of the effective strategies to solve the von Neumann bottleneck.

[0003] Gate circuits are the basic units for building various functional integrated circuits. However, traditional gate circuits such as NOT, AND, OR, NAND, and NOR can only perform corresponding logical operations. In recent years, there have been increasing reports that researchers have connected transistor memories that can be erased in photoelectric or purely electrical modes with conventional transistors (or resistors) to form storage-computing integrated gate circuits [Nanotechnology, 2013, 24, 205-202; Nature 2020, 587, 72.; Adv. Funct. Mater. 2020, 30, 2002-506; IEEE Electron Device Lett., 2022, 43, 1902; ACS Nano 2023, 17, 6095; IEEE Electron Device Lett., 2023, 44, 610; etc.]. These reported storage-computing integrated gate circuits can realize logical operations such as NOT, NAND, and NOR, as well as data storage functions; they have laid the foundation for the development of storage-computing integrated circuits and provided an effective strategy for solving the von Neumann bottleneck. However, these reported storage-computing integrated gate circuits are composed of different types of semiconductor components and have a complex structure. The main materials used are inorganic semiconductors and inorganic insulating materials. The equipment required for the preparation process is expensive, the process is complicated, and the energy consumption is high.

[0004] Compared with inorganic transistor memory, organic transistor memory has inherent advantages such as wide material sources, low-temperature preparation, solution processing, and good mechanical flexibility. The preparation of storage-computing integrated gate circuits based on organic transistor memory can greatly simplify the process, save energy consumption, and reduce production costs. It is easier to develop flexible storage-computing integrated circuits that can be bent statically and dynamically, which can be widely used in price tags, the Internet of Things, biomedicine, wearable electronics and other fields. The storage-computing integrated NOT gate circuit is one of the basic units of the storage-computing integrated gate circuit. Compared with the storage-computing integrated NOT gate circuits of other structures, the complementary storage-computing integrated NOT gate circuit has more significant advantages in energy consumption. The construction of complementary organic storage-computing integrated NOT gate circuits requires two types of organic transistor memories, p-type and n-type. So far, the organic transistor memories that have been reported are all in p-type working mode; and n-type organic transistor memories have not been reported. Complementary organic storage-computing integrated NOT gate circuits composed of a p-type organic transistor memory and an n-type organic transistor memory have not been reported. Summary of the invention

[0005] In view of the von Neumann bottleneck problem faced by conventional gate circuits in the prior art, and the above-mentioned problems existing in the architecture, preparation process and procedures of the storage-computation integrated gate circuits in the prior art, the present invention provides a complementary organic storage-computation integrated NOT gate circuit and a preparation method thereof. The complementary organic storage-computation integrated NOT gate circuit is composed of a p-type organic transistor memory and an n-type organic transistor memory connected in series. Compared with the existing conventional NOT gate circuit, the complementary organic storage-computation integrated NOT gate circuit of the present invention has a data storage function added on the basis of being able to perform non-logical operations; that is, after the input signal is removed, the result of the non-logical operation can be permanently stored in the gate circuit. Compared with other existing storage-computation integrated NOT gate circuits, the complementary organic storage-computation integrated NOT gate circuit of the present invention works in a complementary mode, which can significantly reduce the working energy consumption; and the main material used is organic / polymer material, which has the advantages of simple process, low-temperature preparation, low cost and suitability for flexible applications.

[0006] The present invention is achieved through the following technical solutions:

[0007] A complementary organic storage and computing integrated NOT gate circuit comprises a substrate 1 and a gate electrode 2, a ferroelectric gate polymer gate dielectric layer 3, an interface passivation layer 4 and an organic semiconductor layer located thereon, wherein the organic semiconductor layer comprises a p-type organic semiconductor layer 5 and an n-type organic semiconductor layer 6, and source electrodes and drain electrodes are arranged on the p-type organic semiconductor layer 5 and the n-type organic semiconductor layer 6; wherein the gate electrode 2, the ferroelectric gate polymer gate dielectric layer 3, the interface passivation layer 4, the p-type organic semiconductor layer 5 and the drain electrode 7 and the source electrode 8 located thereon constitute a p-type organic transistor memory, and the gate electrode 2, the ferroelectric gate polymer gate dielectric layer 3, the interface passivation layer 4, the n-type organic semiconductor layer 6 and the drain electrode 9 and the source electrode 10 located thereon constitute an n-type organic transistor memory; the p-type organic transistor memory and the n-type organic transistor memory are connected in series mode, and share a gate electrode 2 as an input terminal V IN ; The source electrode 8 on the p-type organic semiconductor layer is connected to the drain electrode 9 on the n-type organic semiconductor layer as the output terminal V OUT The drain electrode 7 on the p-type organic semiconductor layer is connected to the operating voltage V DD , the source electrode 10 on the n-type organic semiconductor layer serves as the ground terminal GND.

[0008] Furthermore, the substrate 1 is made of one or more of glass, silicon, polyethylene terephthalate, polyethylene naphthalate or polyether sulfone.

[0009] Furthermore, the drain electrode, the source electrode, and the gate electrode 2 are made of one or more of indium tin oxide, gold, silver, copper, and aluminum.

[0010] Furthermore, the material of the ferroelectric polymer gate dielectric layer 3 is one of poly(vinylidene fluoride-trifluoroethylene) and vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer, or a combination of the two.

[0011] Furthermore, the material of the interface passivation layer 4 is one of tetratetradecane, polymethyl methacrylate, polystyrene, polyvinyl alcohol or polyvinyl pyrrolidone.

[0012] Furthermore, the material of the p-type organic semiconductor layer 5 is one of pentacene, copper phthalocyanine, zinc phthalocyanine, 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene, and 2,9-didecylnaphtho[2,3-b:2′,3′-f]thiophene[3,2-b]thiophene.

[0013] Furthermore, the material of the n-type organic semiconductor layer 6 is one of fullerene and fluorinated copper phthalocyanine.

[0014] Furthermore, the thickness of the source electrode, drain electrode and gate electrode is 20-120 nanometers; the thickness of the ferroelectric polymer gate dielectric layer is 100-1000 nanometers; the thickness of the interface passivation layer is 5-50 nanometers; and the thickness of the p-type organic semiconductor layer and the n-type organic semiconductor layer are both 20-100 nanometers.

[0015] On the other hand, the present invention also provides a method for preparing a complementary organic storage and computing integrated NOT gate circuit, comprising the following steps: using vacuum thermal deposition technology or solution method technology to sequentially prepare a gate electrode, a ferroelectric polymer gate dielectric layer, an interface passivation layer, a p-type semiconductor layer and an n-type semiconductor layer, a source electrode and a drain electrode on the surface of a substrate to obtain a complementary organic storage and computing integrated NOT gate circuit.

[0016] Furthermore, the preparation method specifically comprises the following steps:

[0017] Step 1: preparing gate electrodes of a p-type organic transistor memory and an n-type organic transistor memory on a substrate surface by using a vacuum thermal deposition technique, and patterning them by using a mask;

[0018] Step 2: preparing a ferroelectric polymer solution, and preparing a ferroelectric polymer gate dielectric layer on the surface of the gate electrode obtained in step 1 by a solution method; then heat-treating the ferroelectric gate dielectric layer to remove residual solvent in the ferroelectric gate dielectric layer; the heat treatment temperature is 100 to 150° C.; the time is 60 to 120 minutes; the mass concentration of the ferroelectric polymer solution is 2% to 15%;

[0019] Step 3: treating the prepared ferroelectric gate dielectric layer with oxygen plasma for 0.5 to 5 minutes;

[0020] Step 4: preparing a solution for an interface passivation layer, and preparing the interface passivation layer on the surface of the ferroelectric gate dielectric layer obtained in step 3 by a solution method;

[0021] Step 5: preparing a p-type organic semiconductor layer on the surface of the interface passivation layer obtained in step 4 by using a vacuum thermal deposition technique, and patterning it by using a mask;

[0022] Step 6: using vacuum thermal deposition technology to prepare an n-type organic semiconductor layer on the surface of the interface passivation layer obtained in step 4, and patterning it using a mask;

[0023] Step 7: Prepare a drain electrode and a source electrode on the surface of the p-type organic semiconductor layer and the n-type organic semiconductor layer obtained in step 5 and step 6 by using vacuum thermal deposition technology, and pattern them using a mask to obtain a complementary organic storage and computing integrated NOT gate circuit.

[0024] Furthermore, the solution method technology includes spin coating, blade coating, spray coating or drop coating.

[0025] Compared with the prior art, the advantages of the present invention are as follows:

[0026] (1) Compared with the conventional complementary organic NOT gate circuit, the complementary organic storage-computation integrated NOT gate circuit of the present invention not only can perform non-logical operations, but also has the function of data storage; that is, after the input signal is removed, the result of the non-logical operation can be permanently stored in the gate circuit. This lays the foundation for the development of storage-computation integrated integrated circuits;

[0027] (2) Compared with other existing storage-computation integrated NOT gate circuits, the present invention realizes an n-type organic transistor memory; and by connecting it with a p-type organic transistor memory, a storage-computation integrated NOT gate circuit working in a complementary mode is obtained, which can significantly reduce the working energy consumption.

[0028] (3) Compared with other existing storage-computing integrated NOT gate circuits, the main material of the complementary organic storage-computing integrated NOT gate circuit of the present invention is organic / polymer material, which can be used flexibly. Its preparation method has the obvious advantages of simple process, low-temperature preparation and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0030] Figure 1 A top plan view schematic diagram of a complementary organic storage and computing integrated NOT gate circuit provided by the present invention;

[0031] In the figure: substrate 1, gate electrode 2, ferroelectric polymer gate dielectric layer 3, interface passivation layer 4, p-type organic semiconductor layer 5, n-type organic semiconductor layer 6, drain electrode 7 and source electrode 8 of p-type organic transistor memory, drain electrode 9 and source electrode 10 of n-type organic transistor memory;

[0032] Figure 2 A schematic cross-sectional structure diagram of a complementary organic storage-computation integrated NOT gate circuit provided by the present invention;

[0033] Figure 3 A circuit diagram of the complementary organic storage and computing integrated NOT gate circuit provided by the present invention;

[0034] Figure 4 The transfer characteristics of the p-type organic transistor memory in the complementary organic memory-computing integrated NOT gate circuit provided in Example 1 of the present invention when the source-drain voltage is -5 volts;

[0035] Figure 5 The storage retention time characteristics of the p-type organic transistor memory in the complementary organic storage-computing integrated NOT gate circuit provided in Example 1 of the present invention;

[0036] Figure 6 The storage cycle durability of the p-type organic transistor memory in the complementary organic storage-computing integrated NOT gate circuit provided in Example 1 of the present invention;

[0037] Figure 7 The transfer characteristics of the n-type organic transistor memory in the complementary organic memory-computing integrated NOT gate circuit provided in Example 1 of the present invention when the source-drain voltage is 5 volts;

[0038] Figure 8 The storage retention time characteristics of the n-type organic transistor memory in the complementary organic storage-computing integrated NOT gate circuit provided in Example 1 of the present invention;

[0039] Fig. 9 The storage cycle durability of the n-type organic transistor memory in the complementary organic storage-computing integrated NOT gate circuit provided in Example 1 of the present invention;

[0040] Fig.10 The input voltage-output voltage characteristics of the complementary organic storage and computing integrated NOT gate circuit provided in Example 1 of the present invention when the working voltage is 5 volts;

[0041] Fig.11 The working durability of the complementary organic storage and computing integrated NOT gate circuit provided in Example 1 of the present invention in repeatedly performing NOT logic operations.

[0042] Fig.12 The storage retention time characteristics of the operation results (1 state and 0 state) of the complementary organic storage and calculation integrated NOT gate circuit provided in Example 1 of the present invention after undergoing a NOT logic operation. DETAILED DESCRIPTION

[0043] The embodiments of the technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention and are therefore only used as examples and cannot be used to limit the protection scope of the present invention.

[0044] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0045] Example 1

[0046] like Figure 1 and Figure 2As shown, the present invention provides a complementary organic storage and computing integrated NOT gate circuit, comprising a substrate 1 and a gate electrode 2, a ferroelectric gate polymer gate dielectric layer 3, an interface passivation layer 4 and an organic semiconductor layer located thereon, wherein the organic semiconductor layer comprises a p-type organic semiconductor layer 5 and an n-type organic semiconductor layer 6, and a source electrode and a drain electrode are arranged on the p-type organic semiconductor layer 5 and the n-type organic semiconductor layer 6; structurally, the gate electrode 2, the ferroelectric gate polymer gate dielectric layer 3, the interface passivation layer 4, the p-type organic semiconductor layer 5 and the drain electrode 7 and the source electrode 8 located thereon together form a p-type organic transistor memory, and the gate electrode 2, the ferroelectric gate polymer gate dielectric layer 3, the interface passivation layer 4, the n-type organic semiconductor layer 6 and the drain electrode 9 and the source electrode 10 located thereon together form an n-type organic transistor memory; the p-type organic transistor memory and the n-type organic transistor memory are connected in series mode, and share a gate electrode 2 as an input terminal V IN ; The source electrode 8 on the p-type organic semiconductor layer is connected to the drain electrode 9 on the n-type organic semiconductor layer as the output terminal V OUT The drain electrode 7 on the p-type organic semiconductor layer is connected to the operating voltage V DD , the source electrode 10 on the n-type organic semiconductor layer serves as the ground terminal GND.

[0047] In this embodiment, the material of the substrate is polyethylene naphthalate; the material of the gate electrode is metal aluminum, and its thickness is preferably 40-100 nanometers; the material of the ferroelectric polymer gate dielectric layer is vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer, and its thickness is preferably 300-700 nanometers; the material of the interface passivation layer is tetratetradecane, and its thickness is preferably 6-12 nanometers; the material of the p-type organic semiconductor is 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene, and its thickness is preferably 30-50 nanometers; the material of the n-type organic semiconductor is fluorinated copper phthalocyanine, and its thickness is preferably 30-50 nanometers; the material of the drain electrode and the source electrode is metal gold, and its thickness is preferably 30-50 nanometers.

[0048] In the present invention, all substances are commercially available products.

[0049] Performance Testing:

[0050] The electrical performance of the prepared complementary organic storage-computing integrated NOT gate circuit was tested using an Agilent B1500A semiconductor test analyzer, and all tests were carried out in an atmospheric environment at room temperature.

[0051] The complementary organic storage-computing integrated NOT gate circuit provided in Example 1 is composed of a p-type organic transistor memory and an n-type organic transistor memory connected in series, and its top plan view and cross-sectional structure diagram are shown in FIG. Figure 1 and Figure 2 As shown;

[0052] In Example 1, the transfer characteristics of the p-type organic transistor memory at a source-drain voltage of -5 volts are as follows: Figure 4 As shown in Figure 2, its source-drain current increases significantly with the increase of negative gate voltage, showing a typical p-type working mode and a large hysteresis characteristic, which indicates that it has a storage function; the storage retention time characteristics of the p-type organic transistor memory are shown in Figure 2. Figure 5 As shown in the figure, after the erase / write operation was performed using a gate voltage pulse of positive / negative 20 volts, the source-drain current representing the storage logic 0 and 1 states showed very slight changes within the test time range of up to 20,000 seconds, indicating that it has stable storage retention characteristics; the storage cycle durability of the p-type organic transistor memory is shown in the figure Figure 6 As shown, during the 2000-cycle operation of repeated erasing / writing with positive / negative 20V gate voltage pulses, the source-drain current representing the storage logic 0 and 1 states can change repeatedly, and the value is very stable, which indicates that it has very reliable storage cycle durability.

[0053] In Example 1, the transfer characteristics of the n-type organic transistor memory at a source-drain voltage of 5 volts are as follows: Figure 7 As shown in Figure 2, its source-drain current increases significantly with the increase of the forward gate voltage, showing a typical n-type working mode and a large hysteresis characteristic, which indicates that it has a storage function; the storage retention time characteristics of the n-type organic transistor memory are shown in Figure 2. Figure 8 As shown in the figure, after the erase / write operation was performed using a negative / positive 20V gate voltage pulse, the source-drain current representing the storage logic 0 and 1 states showed very slight changes within the test time range of up to 20,000 seconds, indicating that it has stable storage retention characteristics; the storage cycle durability of the n-type organic transistor memory is shown in the figure Fig. 9 As shown, during the 2000-cycle operation of repeated erasing / writing with negative / positive 20V gate voltage pulses respectively, the source-drain current representing the storage logic 0 and 1 states can change repeatedly and the value is very stable, which indicates that it has very reliable storage cycle endurance.

[0054] In Example 1, the circuit diagram of the complementary organic storage and computing integrated NOT gate circuit is as follows: Figure 3 As shown, the common gate electrode serves as the input terminal (V IN ), the source electrode of the p-type organic transistor memory and the drain electrode of the n-type organic transistor memory are connected to each other as the output terminal (V OUT ); the drain electrode of the p-type organic transistor memory is connected to the operating voltage (V DD), the source electrode of the n-type organic transistor memory is used as the ground terminal (GND). The working voltage of the complementary organic memory-computing integrated NOT gate described in Example 1 is set to 5V, and the input voltage-output voltage characteristics of the test are as follows Fig.10 As shown, it is obvious that when the input voltage is negative (defined as the logic 0 state), the output voltage is close to 5 volts, corresponding to the logic 1 state; when the input voltage is positive (defined as the logic 1 state), the output voltage is close to 0 volts, corresponding to the logic 0 state; this presents a clear non-logical operation. Specifically, the positive / negative 20 volt input voltage is defined as the logic 1 / 0 state respectively; when the positive / negative 20 volt input voltage pulse is repeatedly applied to the input end, the low output voltage (0.08~0.20 volts) and the high output voltage (4.90~4.94 volts) can be measured repeatedly at the output end, corresponding to the logic 0 and 1 states respectively. This repeated test can survive 2000 cycles without obvious attenuation, as shown in FIG. Fig.11 As shown, this shows that the complementary organic storage and computing integrated NOT gate circuit has a clear logic operation function and strong working reliability. When a negative 20 volt input voltage pulse is added to the input end (i.e., input logic 0), its output voltage is close to 5 volts, corresponding to the logic 0 state, and the output voltage can be stably maintained for 20,000 seconds without obvious changes; when a positive 20 volt input voltage pulse is added to the input end (i.e., input logic 1), its output voltage is close to 0 volts, corresponding to the logic 0 state, and the output voltage increases slightly to 0.4 volts within the test time of 20,000 seconds, and can still be clearly maintained at the 0 state; the test data is as follows Fig.11 As shown, this presents a clear storage function with high working stability.

[0055] It can be seen from the test results that the p-type and n-type organic transistor memories in the complementary organic storage and computing integrated NOT gate circuit provided in the embodiment have very good storage working characteristics; the complementary organic storage and computing integrated NOT gate circuit provided by the present invention has both reliable and stable non-logical operations and (operation result) storage functions; and lays the foundation for the subsequent development of storage and computing integrated integrated circuits.

[0056] Example 2

[0057] This embodiment provides a method for preparing a complementary organic storage and computing integrated NOT gate circuit, comprising the following steps: using vacuum thermal deposition technology or solution method technology, sequentially preparing a gate electrode, a ferroelectric polymer gate dielectric layer, an interface passivation layer, a p-type and n-type semiconductor layer, and a source electrode / drain electrode on the surface of a substrate to obtain a complementary organic storage and computing integrated NOT gate circuit. Specifically comprising the following steps:

[0058] (1) Commercially purchased polyethylene naphthalate is used as a substrate; on the substrate, a vacuum thermal deposition technique is used to prepare gate electrodes of p-type and n-type organic transistor memories, which are patterned using a mask;

[0059] (2) preparing a ferroelectric polymer solution, and preparing a ferroelectric polymer gate dielectric layer on the surface of the gate electrode obtained in step 1 by a solution method; then heat-treating the ferroelectric gate dielectric layer to remove residual solvent in the ferroelectric gate dielectric layer; the heat treatment temperature is preferably 120 to 145° C.; the time is preferably 60 to 120 minutes; the mass concentration of the ferroelectric polymer solution is preferably 5% to 10%; the thickness of the obtained ferroelectric gate insulating layer can be optimized and adjusted by adjusting the concentration of the solution and specific solution method process preparation parameters (spin coating, scraping or drip coating rate, solvent atmosphere, etc.);

[0060] (3) treating the prepared ferroelectric gate dielectric layer with oxygen plasma, the treatment time is preferably 1 to 3 minutes;

[0061] (4) preparing a solution for an interface passivation layer, and preparing the interface passivation layer on the surface of the ferroelectric gate dielectric layer obtained in step 3 by a solution method; the thickness of the obtained interface passivation layer can be optimized and adjusted by adjusting the concentration of the solution and specific solution method process parameters (spin coating, scraping or drip coating rate, solvent atmosphere, etc.);

[0062] (5) preparing a p-type organic semiconductor layer on the surface of the interface passivation layer obtained in step 4 by using a vacuum thermal deposition technique, and patterning the layer by using a mask; the thickness of the obtained p-type organic semiconductor layer can be optimized and adjusted by specific preparation parameters;

[0063] (6) preparing an n-type organic semiconductor layer on the surface of the interface passivation layer obtained in step 4 by using a vacuum thermal deposition technique, and patterning the n-type organic semiconductor layer by using a mask; the thickness of the obtained n-type organic semiconductor layer can be optimized and adjusted by specific preparation parameters;

[0064] (7) Using vacuum thermal deposition technology to prepare source electrodes and drain electrodes of p-type and n-type organic transistor memories on the surfaces of the p-type and n-type organic semiconductor layers obtained in step 5 and step 6, and patterning them using a mask to obtain a complementary organic memory and computing integrated NOT gate circuit.

[0065] This embodiment has no special requirements on the vacuum thermal deposition technology or solution process used in the preparation process of each layer of thin film, and the common methods used by those skilled in the art can be used.

[0066] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0067] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0068] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A complementary organic storage and computing integrated NOT gate circuit, characterized in that: The invention comprises a substrate (1) and a gate electrode (2), a ferroelectric gate polymer gate dielectric layer (3), an interface passivation layer (4) and an organic semiconductor layer located thereon, wherein the organic semiconductor layer comprises a p-type organic semiconductor layer (5) and an n-type organic semiconductor layer (6), and a source electrode and a drain electrode are arranged on the p-type organic semiconductor layer (5) and the n-type organic semiconductor layer (6); wherein the gate electrode (2), the ferroelectric gate polymer gate dielectric layer (3), the interface passivation layer (4), the p-type organic semiconductor layer (5) and the drain electrode (7) and the source electrode (8) located thereon constitute a p-type organic transistor memory, and the gate electrode (2), the ferroelectric gate polymer gate dielectric layer (3), the interface passivation layer (4), the n-type organic semiconductor layer (6) and the drain electrode (9) and the source electrode (10) located thereon constitute an n-type organic transistor memory; the p-type organic transistor memory and the n-type organic transistor memory are connected in series mode, and share a gate electrode (2) as an input terminal V IN The source electrode (8) on the p-type organic semiconductor layer is connected to the drain electrode (9) on the n-type organic semiconductor layer as an output terminal V OUT The drain electrode (7) on the p-type organic semiconductor layer is connected to the operating voltage V DD , the source electrode (10) on the n-type organic semiconductor layer serves as a ground terminal GND.

2. A complementary organic storage and computing integrated NOT gate circuit as claimed in claim 1, characterized in that: The substrate (1) is made of one or more of glass, silicon, polyethylene terephthalate, polyethylene naphthalate or polyethersulfone; The material of the drain electrode, the source electrode and the gate electrode (2) is one or more of indium tin oxide, gold, silver, copper and aluminum.

3. A complementary organic storage and computing integrated NOT gate circuit as claimed in claim 1, characterized in that: The material of the ferroelectric polymer gate dielectric layer (3) is one of poly(vinylidene fluoride-trifluoroethylene) and vinylidene fluoride-trifluoroethylene-chlorotrifluoroethylene copolymer, or a combination of the two.

4. A complementary organic storage and computing integrated NOT gate circuit as claimed in claim 1, characterized in that: The material of the interface passivation layer (4) is one of tetratetradecane, polymethyl methacrylate, polystyrene, polyvinyl alcohol or polyvinyl pyrrolidone.

5. A complementary organic storage and computing integrated NOT gate circuit as claimed in claim 1, characterized in that: The material of the p-type organic semiconductor layer (5) is one of pentacene, copper phthalocyanine, zinc phthalocyanine, 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene, and 2,9-didecylnaphtho[2,3-b:2′,3′-f]thiophene[3,2-b]thiophene.

6. A complementary organic storage and computing integrated NOT gate circuit as claimed in claim 1, characterized in that: The material of the n-type organic semiconductor layer (6) is one of fullerene and fluorinated copper phthalocyanine.

7. A complementary organic storage and computing integrated NOT gate circuit as claimed in claim 1, characterized in that: The thickness of the source electrode, drain electrode and gate electrode is 20-120 nanometers; the thickness of the ferroelectric polymer gate dielectric layer is 100-1000 nanometers; the thickness of the interface passivation layer is 5-50 nanometers; the thickness of the p-type organic semiconductor layer and the n-type organic semiconductor layer are both 20-100 nanometers.

8. The method for preparing a complementary organic storage-computation integrated NOT gate circuit as claimed in claim 1, characterized in that: The method comprises the following steps: using vacuum thermal deposition technology or solution method technology, sequentially preparing a gate electrode, a ferroelectric polymer gate dielectric layer, an interface passivation layer, a p-type semiconductor layer and an n-type semiconductor layer, a source electrode and a drain electrode on the surface of a substrate to obtain a complementary organic storage and computing integrated NOT gate circuit.

9. The method for preparing a complementary organic storage-computation integrated NOT gate circuit as claimed in claim 8, characterized in that: The preparation method specifically comprises the following steps: Step 1: preparing gate electrodes of a p-type organic transistor memory and an n-type organic transistor memory on a substrate surface by using a vacuum thermal deposition technique, and patterning them by using a mask; Step 2: preparing a ferroelectric polymer solution, and preparing a ferroelectric polymer gate dielectric layer on the surface of the gate electrode obtained in step 1 by a solution method; then heat-treating the ferroelectric gate dielectric layer to remove residual solvent in the ferroelectric gate dielectric layer; the heat treatment temperature is 100 to 150° C.; the time is 60 to 120 minutes; the mass concentration of the ferroelectric polymer solution is 2% to 15%; Step 3: treating the prepared ferroelectric gate dielectric layer with oxygen plasma for 0.5 to 5 minutes; Step 4: preparing a solution for an interface passivation layer, and preparing the interface passivation layer on the surface of the ferroelectric gate dielectric layer obtained in step 3 by a solution method; Step 5: preparing a p-type organic semiconductor layer on the surface of the interface passivation layer obtained in step 4 by using a vacuum thermal deposition technique, and patterning it by using a mask; Step 6: using vacuum thermal deposition technology to prepare an n-type organic semiconductor layer on the surface of the interface passivation layer obtained in step 4, and patterning it using a mask; Step 7: Prepare drain electrodes and source electrodes on the surfaces of the p-type and n-type organic semiconductor layers obtained in Steps 5 and 6 using vacuum thermal deposition technology, and pattern them using a mask to obtain a complementary organic storage and computing integrated NOT gate circuit.

10. The method for preparing a complementary organic storage-computation integrated NOT gate circuit as claimed in claim 9, characterized in that: The solution-based techniques include spin coating, doctor blade coating, spray coating or drop coating.

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