Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a plate including an opening portion, a lower film disposed on the plate, a first substrate disposed on the lower film, a first connection line disposed on the first substrate, a pad portion inserted in a first contact hole passing through the first connection line, the first substrate, and the lower film, and a flexible film disposed on the lower film, wherein the pad portion is connected to the first connection line, and the flexible film includes a first lead electrode inserted in the opening portion of the board. The first lead electrode includes a lead portion protruding from an upper surface of the first lead electrode and passing through the pad portion.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0002] As the information age progresses, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices, such as, for example, smart phones, digital cameras, notebook computers, navigation devices, and smart TVs. The display device may be a flat panel display device, such as, for example, a liquid crystal display device, a field emission display device, or an organic light emitting display device. Among such flat panel display devices, a light emitting display device may display an image without a backlight unit that provides light to a display panel, because each pixel of the display panel may include a light emitting element that can emit light by itself. Summary of the invention

[0003] Aspects of the present disclosure provide a display device and a method of manufacturing the display device in which a pad portion is formed by filling a micropore with a conductive ink and the pad portion can easily connect a lead electrode arranged under a substrate and a connection line arranged over the substrate to each other.

[0004] Aspects of the present disclosure also provide a display device capable of reducing manufacturing time and manufacturing cost by minimizing the area of ​​a non-display region and simplifying a manufacturing process, and a method of manufacturing the display device.

[0005] However, the various aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0006] According to an embodiment, a display device includes a board, a lower film, a first substrate, a first connection line, a pad portion, and a flexible film, the board including an opening portion, the lower film arranged on the board, the first substrate arranged on the lower film, the first connection line arranged on the first substrate, the pad portion inserted into a first contact hole passing through the first connection line, the first substrate, and the lower film, wherein the pad portion is connected to the first connection line, and the flexible film includes a first lead electrode inserted into the opening portion of the board. The first lead electrode includes a pin portion protruding from an upper surface of the first lead electrode and passing through the pad portion.

[0007] A lower surface of the pad portion may be in contact with an upper surface of the first lead electrode.

[0008] A lower surface of the pad portion may be spaced apart from an upper surface of the first lead electrode.

[0009] The display device may further include a gate insulating layer disposed on the first substrate, a second connection line disposed on the gate insulating layer and connected to the first connection line, and an interlayer insulating layer disposed between the second connection line and the first connection line.

[0010] The display device may also include a second substrate arranged between the first substrate and the gate insulating layer, a semiconductor region of a transistor arranged on the second substrate, a gate electrode of the transistor arranged on the gate insulating layer, and a connection electrode arranged on the interlayer insulating layer and electrically connected to the transistor. The first connection line may include the same material as that of the connection electrode and be formed in the same process as that of the connection electrode. The second connection line may include the same material as that of the gate electrode of the transistor and be formed in the same process as that of the gate electrode of the transistor.

[0011] The display device may further include a printed circuit unit disposed under the board and including a driving integrated circuit. The flexible film may further include a second lead electrode electrically connected to the printed circuit unit.

[0012] According to an embodiment, a display device includes a board including a lead, a lower film arranged on the board, a first substrate arranged on the lower film, a first connection line arranged on the first substrate, and a pad portion inserted into a first contact hole passing through the first connection line, the first substrate, and the lower film, wherein the pad portion is connected to the first connection line. The lead includes a first portion arranged on an upper surface of the board, a second portion passing through the board and connected to the first portion, a third portion arranged on a lower surface of the board and connected to the second portion, and a pin portion protruding from an upper surface of the first portion and passing through the pad portion.

[0013] A lower surface of the pad portion may be in contact with an upper surface of the first portion of the lead.

[0014] A lower surface of the pad portion may be spaced apart from an upper surface of the first portion of the lead.

[0015] The display device may further include a display driver disposed on a lower surface of the board and electrically connected to the third portion of the lead.

[0016] According to an embodiment, a method for manufacturing a display device includes: sequentially stacking a lower film, a first substrate, a first connecting line, and a protective film; forming a first contact hole passing through the protective film, the first connecting line, the first substrate, and the lower film; providing the lower film including the first contact hole, the first substrate, the first connecting line, and the protective film on a stage; providing a print head above the first contact hole; supplying a positive voltage to the print head and a negative voltage to the stage through a power supply; injecting a conductive ink into the first contact hole through the print head; forming a pad portion by sintering the conductive ink; arranging a board below the lower film, the board including an opening portion exposing the pad portion; and connecting the first lead electrode of the flexible film to the pad portion by inserting the first lead electrode of the flexible film into the opening portion.

[0017] Injecting the conductive ink may include filling the first contact hole with the conductive ink by electrical attraction of the conductive ink having a positive charge.

[0018] Injecting the conductive ink may include applying the conductive ink in a linear direction through a print head, injecting a portion of the conductive ink into the first contact hole and applying another portion of the conductive ink onto the protective film.

[0019] The method of manufacturing a display device may further include removing the protective film and the conductive ink applied to the protective film after forming the pad part.

[0020] According to an embodiment, a method for manufacturing a display device includes: sequentially stacking a protective film, a lower film, a first substrate, and a first connection line; forming a first contact hole passing through the first connection line, the first substrate, the lower film, and the protective film; providing a stage including welding ink, the welding ink being provided at an upper portion of the stage; providing the protective film, the upper film, the first substrate, and the first connection line on the stage so that the first contact hole overlaps with the welding ink; sucking the welding ink into the first contact hole by a suction device; and forming a pad portion by sintering the welding ink.

[0021] The method of manufacturing a display device may also include: exposing a lower surface of the lower film by removing the protective film; arranging a board under the lower film, the board including an opening portion exposing the pad portion; and connecting the first lead electrode of the flexible film to the pad portion by inserting the first lead electrode of the flexible film into the opening portion.

[0022] Exposing the lower surface of the lower film may include arranging the lower surface of the pad part at the same plane as the lower surface of the lower film.

[0023] According to an embodiment, a method for manufacturing a display device includes: sequentially stacking a lower film, a first substrate, and a first connecting line; forming a first contact hole passing through the first connecting line, the first substrate, and the lower film; providing a first lead electrode, which is arranged on one side of the flexible film and includes a pin portion protruding from an upper surface of the first lead electrode; arranging the first lead electrode on the lower surface of the lower film by inserting the pin portion into the first contact hole; injecting conductive ink into the first contact hole by a printing head; and forming a pad portion by sintering the conductive ink.

[0024] The lead portion may pass through the pad portion and protrude from an upper surface of the pad portion.

[0025] The first lead electrode may be electrically connected to the first connection line through the pin portion and the pad portion.

[0026] By the display device and the method of manufacturing the display device according to the exemplary embodiment, by filling the micropores with conductive ink to form the pad portion, the pad portion can easily connect the lead electrode arranged under the substrate and the connection line arranged above the substrate to each other. Aspects of the display device and the method of manufacturing the display device support reducing manufacturing time and manufacturing cost by minimizing the size of the non-display area and simplifying the manufacturing process.

[0027] The effects of the present disclosure are not limited to the aforementioned effects, and various other effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0029] Figure 1 is a plan view showing a display device according to an exemplary embodiment;

[0030] Figure 2 is along Figure 1 A cross-sectional view taken along line II';

[0031] Figure 3 is a bottom view showing a display device according to an exemplary embodiment;

[0032] Figure 4 is a plan view showing a portion of a non-display area of ​​a display device according to an exemplary embodiment;

[0033] Figure 5 is a cross-sectional view showing a portion of a display device according to an exemplary embodiment;

[0034] Figure 6 is a cross-sectional view showing a portion of a display device according to another exemplary embodiment;

[0035] Figures 7 to 9 It is shown Figure 5 and Figure 6 A cross-sectional view of an example of a manufacturing process of a pad portion in a display device;

[0036] Figures 10 to 12 It is shown Figure 5 and Figure 6 A perspective view of an example of a manufacturing process of a pad portion in a display device of FIG.

[0037] Figures 13 to 16 It is shown Figure 5 and Figure 6 A cross-sectional view of another example of a manufacturing process of a pad portion in a display device;

[0038] Fig.17is a cross-sectional view showing a portion of a display device according to another exemplary embodiment;

[0039] Fig.18 is a cross-sectional view showing a portion of a display device according to another exemplary embodiment;

[0040] Fig.19 is a cross-sectional view showing a portion of a display device according to another embodiment;

[0041] Fig. 20 is a cross-sectional view showing a portion of a display device according to another exemplary embodiment; and

[0042] Figure 21 to Figure 23 It is shown Figures 17 to 20 A cross-sectional view of a manufacturing process of a pad portion in a display device. DETAILED DESCRIPTION

[0043] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of devices or methods using one or more of the disclosures disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or in the case of one or more equivalent arrangements. In other examples, structures and devices are shown in block diagram form to avoid unnecessary confusion of various embodiments. In addition, various embodiments may be different, but need not be exclusive, nor need to limit the present disclosure. For example, without departing from the present disclosure, the specific shape, configuration and characteristics of the embodiment may be used or implemented in other embodiments.

[0044] Unless otherwise specified, the embodiments shown should be understood as providing features of varying details of some of the ways in which the present disclosure can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter referred to individually or collectively as "elements") of the various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the present disclosure.

[0045] The use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, size, proportion, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0046] In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, similar reference numerals represent similar elements.

[0047] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, the element may be directly on, directly connected to, or coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical, electrical, and / or fluid connection with or without intervening elements.

[0048] In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, and therefore the X-axis, Y-axis and Z-axis can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0049] For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, XZ, or the like. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] Although the terms "first" and "second" etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element.

[0051] Spatially relative terms (such as, for example, "beneath", "below", "under", "lower", "above", "upper", "over", "higher", and "side" (e.g., as in "sidewall")) may be used herein for descriptive purposes and thereby describe the relationship of one element to another element as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are also intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, the elements described as being "below" or "beneath" other elements or features will subsequently be oriented "above" the other elements or features. Therefore, the term "below" can cover both the orientations of above and below. In addition, the device can be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein should be interpreted accordingly.

[0052] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include the plural forms. In addition, when the terms "comprises", "comprising", "includes" and / or "including" are used in this specification, the existence of the stated features, integers, steps, operations, elements, parts and / or clusters thereof is explained, but the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or clusters thereof is not excluded. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as terms of approximation and not as terms of degree, and thus, are utilized to take into account the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0053] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations that are schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments disclosed herein should not necessarily be construed as limited to the shapes of the particular illustrated regions, but rather are to include deviations in shape due to, for example, manufacturing. In this manner, the regions illustrated in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus are not necessarily intended to be limiting.

[0054] As is customary in the art, in terms of functional blocks, units, circuits and / or modules, some embodiments are described and shown in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units, parts and / or modules are physically implemented by electronic (or optical) circuits (such as, for example, logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connectors that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case where blocks, units, parts and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be selectively driven by firmware and / or software. It is also contemplated that each block, unit, part and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and processors that perform other functions (e.g., one or more programmed microprocessors and associated circuits). Moreover, without departing from the scope of the present disclosure, each block, unit, part and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units, parts and / or modules. Furthermore, the blocks, units, parts and / or modules of some embodiments may be physically combined into more complex blocks, units, parts and / or modules without departing from the scope of the present disclosure.

[0055] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless clearly defined as such herein, terms (such as, for example, terms defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal sense.

[0056] Hereinafter, detailed embodiments of the present disclosure are described with reference to the accompanying drawings.

[0057] Figure 1 is a plan view showing a display device according to an exemplary embodiment.

[0058] Reference Figure 1, the display device 10 may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs). As another example, the display device 10 may be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IOT) device. As another example, the display device 10 may be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs).

[0059] The display device 10 may have a shape similar to a rectangular shape in a plan view. For example, the display device 10 may be rectangular in a plan view. In an example, a corner where one side in the X-axis direction and one side in the Y-axis direction of the display device 10 intersect may be rounded or right angled according to a predetermined curvature. The shape of the display device 10 in a plan view is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, circular shapes, or elliptical shapes. For example, the display device 10 may be polygonal, circular, or elliptical.

[0060] The display device 10 may include a display area DA and a non-display area NDA. The display area DA may include a plurality of pixels configured to display an image. Each of the plurality of pixels may include an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, or a micro LED. Hereinafter, it will be mainly described that each of the plurality of pixels includes an organic light emitting diode, but the embodiments of the present disclosure are not limited thereto.

[0061] A plurality of pixels may be arranged along a plurality of rows and a plurality of columns in the display area DA. Each of the plurality of pixels may include an emission area EA defined by a pixel defining film or a dam, and may emit light having a predetermined peak wavelength through the emission area EA. The emission area EA may be an area in which light generated by a light emitting element of the display device 10 is emitted to the outside of the display device 10.

[0062] The display area DA of the display device 10 may include a light-blocking area BA surrounding the plurality of emission areas EA. The light-blocking area BA may prevent the colors of light emitted from the emission areas EA from being mixed.

[0063] The non-display area NDA may be arranged around the display area DA and surround the display area DA, and the non-display area NDA may not display an image. The non-display area NDA may include a scan driver SIC that supplies a scan signal to the display area DA. The scan driver SIC may be arranged on the left and right sides of the non-display area DA. The scan driver SIC may generate a scan signal based on a scan control signal. The scan control signal may include a start signal, a clock signal, and a source voltage, but is not limited thereto. The scan driver SIC may supply a scan signal to a scan line of the display area DA according to a set order.

[0064] Figure 2 is along Figure 1 A cross-sectional view taken along line II'.

[0065] Reference Figure 2 , the display area DA of the display device 10 may include a plurality of emission areas EA. Each of the emission areas EA may be a region in which light generated by the light emitting element ED is emitted to the outside of the display device 10.

[0066] The display device 10 may include a panel PLT, a lower film PRF, a first substrate SUB1, a blocking insulating layer BIL, a second substrate SUB2, a transistor layer TRL, a light emitting element layer EML, an encapsulation layer TFEL, a touch sensing unit TSU, a planarization layer OC, and an optical member POL.

[0067] The panel PLT may support the display device 10. The panel PLT may include a material having excellent permeability and heat resistance (eg, a material satisfying target permeability and heat resistance thresholds). For example, the panel PLT may be formed of glass fiber reinforced polymer (GFRP), but is not limited thereto.

[0068] The lower film PRF may be disposed on the panel PLT and protect the lower portion of the display device 10. For example, the lower film PRF may include at least one of acrylic resin, epoxy resin, phenol resin, polyamide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin. The lower film PRF may have a flexible property so that the lower film PRF can be bent, folded, or curled, but is not limited thereto.

[0069] The first substrate SUB1 may be arranged on the lower film PRF. The first substrate SUB1 may be a base substrate or a base member. The first substrate SUB1 may be a flexible substrate that can be bent, folded, or rolled. For example, the first substrate SUB1 may include an insulating material such as, for example, a polymer resin (e.g., polyimide (PI)), but is not limited thereto.

[0070] The blocking insulating layer BIL may be disposed on the first substrate SUB1. The blocking insulating layer BIL may include an inorganic film capable of preventing air or moisture from penetrating. For example, the blocking insulating layer BIL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0071] The second substrate SUB2 may be arranged on the blocking insulating layer BIL. The second substrate SUB2 may be a base substrate or a base member. The second substrate SUB2 may be a flexible substrate that can be bent, folded, or rolled. For example, the second substrate SUB2 may include an insulating material such as, for example, a polymer resin (e.g., polyimide (PI)), but is not limited thereto.

[0072] The transistor layer TRL may be arranged on the second substrate SUB2. The transistor layer TRL may include a plurality of transistors TR constituting a pixel circuit of a pixel. The transistor layer TRL may include a scan line, a data line DL, and a power line VL connected to the pixel. Each of the transistors TR may include a semiconductor region ACT, a drain electrode DE, a source electrode SE, and a gate electrode GE. In an example in which the scan driver SIC is formed on one side of the non-display area NDA, the scan driver SIC may include a transistor TR.

[0073] The transistor layer TRL may include an active layer ACTL, a gate insulating layer GI, a gate layer GTL, an interlayer insulating layer ILD, a first source metal layer SDL1 , a first via layer VIA1 , a second source metal layer SDL2 , and a second via layer VIA2 .

[0074] The active layer ACTL may be arranged on the second substrate SUB2. The active layer ACTL may include a semiconductor region ACT, a drain electrode DE, and a source electrode SE of the transistor TR. The semiconductor region ACT may overlap with the gate electrode GE, and the semiconductor region ACT may be insulated from the gate electrode GE by the gate insulating layer GI. The drain electrode DE and the source electrode SE may be provided by forming a conductor from the material of the semiconductor region ACT. The transistor TR may constitute a pixel circuit for each of the plurality of pixels (for example, a pixel circuit for each of the plurality of pixels may include a transistor TR).

[0075] The gate insulating layer GI may be disposed on the active layer ACTL. The gate insulating layer GI may insulate the semiconductor region ACT and the gate electrode GE of the transistor TR from each other. The gate insulating layer GI may include a contact hole through which the connection electrode CNE passes.

[0076] The gate layer GTL may be arranged on the gate insulating layer GI. The gate layer GTL may include a gate electrode GE of the transistor TR. The gate electrode GE may overlap the semiconductor region ACT, and the gate insulating layer GI is interposed between the gate electrode GE and the semiconductor region ACT. The gate electrode GE may receive a scan signal from a scan line. For example, the gate layer GTL may be formed as a single layer or a multilayer including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0077] An interlayer insulating layer ILD may be disposed on the gate layer GTL. The interlayer insulating layer ILD may insulate the gate layer GTL and the first source metal layer SDL1 from each other. The interlayer insulating layer ILD may include a contact hole through which the connection electrode CNE passes.

[0078] The first source metal layer SDL1 may be arranged on the interlayer insulating layer ILD. The first source metal layer SDL1 may include a connection electrode CNE. The connection electrode CNE may be inserted into a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GI, and the connection electrode CNE may be connected to the source electrode SE of the transistor TR. The connection electrode CNE may electrically connect the transistor TR and the anode connection electrode ANE to each other. The connection electrode CNE may supply a driving current received from the pixel circuit to the light emitting element ED through the anode connection electrode ANE. For example, the first source metal layer SDL1 may be formed as a single layer or a multilayer including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0079] The first via layer VIA1 may be disposed on the first source metal layer SDL1. The first via layer VIA1 may planarize the upper end of the pixel circuit and protect the pixel circuit. The first via layer VIA1 may include an organic insulating material such as, for example, polyimide (PI). The first via layer VIA1 may include a contact hole through which the anode connection electrode ANE passes.

[0080] The second source metal layer SDL2 may be disposed on the first source metal layer SDL1. The second source metal layer SDL2 may include an anode connection electrode ANE, a data line DL, and a power line VL. The second source metal layer SDL2 may include the same material as that included in the first source metal layer SDL1.

[0081] The anode connection electrode ANE may be inserted into a contact hole passing through the first via layer VIA1 to be connected to the connection electrode CNE. The anode connection electrode ANE may electrically connect the connection electrode CNE and the pixel electrode AE ​​of the light emitting element ED to each other. The anode connection electrode ANE may supply a driving current received from the connection electrode CNE to the light emitting element ED.

[0082] The data line DL may extend in the Y-axis direction in the display area DA. The data line DL may be electrically connected to the transistor TR. The data line DL may supply a data voltage to the pixel circuit.

[0083] The power line VL may extend in the Y-axis direction in the display area DA. The power line VL may be electrically connected to the transistor TR or the light emitting element ED. For example, the power line VL may be a high potential line, a low potential line, an initialization voltage line, a reference voltage line, or a bias voltage line, but is not limited thereto.

[0084] The second via layer VIA2 may be disposed on the second source metal layer SDL2. The second via layer VIA2 may planarize the upper end of the transistor layer TRL. The second via layer VIA2 may include an organic insulating material, such as, for example, polyimide (PI). The second via layer VIA2 may include a contact hole through which the pixel electrode AE ​​passes.

[0085] The light emitting element layer EML may be disposed on the transistor layer TRL. The light emitting element layer EML may include a light emitting element ED and a pixel defining layer PDL.

[0086] The light emitting element ED may be arranged in the emission area EA on the second through hole layer VIA2. The light emitting element ED of each of the plurality of pixels may include a pixel electrode AE, a light emitting layer EL and a common electrode CE. The pixel electrode AE ​​may be arranged on the second through hole layer VIA2. The pixel electrode AE ​​may overlap one of the plurality of emission areas EA defined by the pixel definition film PDL. For example, the pixel electrode AE ​​may receive a driving current from the pixel circuit through the anode connection electrode ANE and the connection electrode CNE.

[0087] The light-emitting layer EL may be arranged on the pixel electrode AE. For example, the light-emitting layer EL may be an organic light-emitting layer formed of an organic material, but is not limited thereto. In the case where the light-emitting layer EL is an organic light-emitting layer, when the pixel circuit of the pixel applies a predetermined voltage to the pixel electrode AE ​​and the common electrode CE receives a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layer EL through the hole transport layer and the electron transport layer, respectively, and the holes and electrons may be combined with each other in the light-emitting layer EL to emit light. For example, the pixel electrode may be an anode, and the common electrode may be a cathode, but embodiments of the present disclosure are not limited thereto.

[0088] As another example, the plurality of light emitting elements may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0089] The common electrode CE may be arranged on the light emitting layer EL. For example, the common electrode CE is not divided for each of the plurality of pixels, and the common electrode CE may be implemented in the form of an electrode common to all pixels. The common electrode CE may be arranged on the plurality of light emitting layers EL in the plurality of emission areas EA, and the common electrode CE may be arranged on the pixel defining film PDL in the light blocking area BA.

[0090] The pixel defining film PDL may be disposed in the light blocking area BA on the second via layer VIA2. The pixel defining film PDL may define a plurality of emission areas EA or a plurality of opening areas. A plurality of pixel electrodes AE of a plurality of pixels may be spaced apart and insulated from each other by the pixel defining film PDL.

[0091] The encapsulation layer TFEL may be arranged on the common electrode CE and may cover the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one inorganic film and prevent oxygen or moisture from penetrating into the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one organic film that protects the plurality of light emitting elements ED from foreign matter such as dust, for example.

[0092] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a bridge electrode BRG, a first insulating layer IL1, a touch electrode TE, and a second insulating layer IL2.

[0093] The bridge electrode BRG may be disposed on the encapsulation layer TFEL. The bridge electrode BRG may be disposed at a different layer from the touch electrodes TE, and may electrically connect adjacent touch electrodes TE to each other.

[0094] The first insulating layer IL1 may be disposed on the bridge electrode BRG. The first insulating layer IL1 may have insulating and optical functions. As an example, the first insulating layer IL1 may be an inorganic film including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. As another example, the first insulating layer IL1 may include an organic film.

[0095] The touch electrode TE may be arranged in the light blocking area BA on the first insulating layer IL1. The touch electrode TE may sense a touch input by a user in a capacitive manner. For example, the touch sensing unit TSU may sense a touch input in a mutual capacitance manner in which capacitance is formed between the plurality of touch electrodes TE or in a self-capacitance manner in which capacitance is formed in each of the plurality of touch electrodes TE. The touch electrode TE may be formed as a single layer formed of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0096] The second insulating layer IL2 may be disposed on the touch electrode TE. The second insulating layer IL2 may have insulating and optical functions. The second insulating layer IL2 may be formed of a material included in the first insulating layer IL1.

[0097] The planarization layer OC may be disposed on the touch sensing unit TSU and planarize an upper end of the touch sensing unit TSU. For example, the planarization layer OC may include an organic insulating material.

[0098] The optical member POL may be arranged on the planarization layer OC. The optical member POL may be attached to the touch sensing unit TSU by an optically clear adhesive (OCA) film or an optically clear resin (OCR). For example, the optical member POL may include a linear polarizer and a phase delay film, and the phase delay film may be a λ / 4 plate (quarter wave plate). The phase delay film and the linear polarizer may be sequentially stacked on the touch sensing unit TSU. The optical member POL may prevent color distortion due to external light reflection by reducing reflected light of external light.

[0099] Figure 3 is a bottom view showing a display device according to an exemplary embodiment.

[0100] Reference Figure 3 , a flexible film COF may be arranged under the panel PLT. The flexible film COF may be arranged at the edge of the lower surface of the display device 10. The lead electrode of the flexible film COF may be in contact with the lower surface of the pad portion PAD. The pad portion PAD may be arranged in the non-display area NDA, but is not limited thereto. The flexible film COF may supply the data voltage received from the printed circuit unit to the data line DL of the display area DA through the pad portion PAD. The flexible film COF may supply the source voltage received from the printed circuit unit to the power line VL of the display area DA through the pad portion PAD. The flexible film COF may supply the scan control signal to the scan driver SIC through the pad portion PAD. Refer to Figure 5The display device 10 may include a first connection line CWL1 arranged on the second substrate SUB2, a pad portion PAD passing through the first substrate SUB1 and the second substrate SUB2, and a flexible film COF and a printed circuit unit FPCA arranged under the lower film PRF, which can minimize the area of ​​the non-display area NDA.

[0101] Figure 4 is a plan view showing a portion of a non-display area of ​​a display device according to an exemplary embodiment.

[0102] Reference Figure 4 The non-display area NDA may include a signal line SL, a high potential line VDL, a low potential line VSL, and a touch line TL. The signal line SL, the high potential line VDL, the low potential line VSL, and the touch line TL may extend from the pad area PDA to the display area DA. The signal line SL may be connected to the data line DL (e.g., Figure 2 ) is electrically connected and supplies a data voltage, and the signal line SL can be connected to a scan driver SIC (eg, referring to Figure 3 ) is electrically connected and supplies a scan control signal. The high potential line VDL may be electrically connected to a power line VL (eg, referring to Figure 2 ), and supplies the high potential voltage to the pixel circuit. The low potential line VSL may be electrically connected to the light emitting element ED (for example, referring to Figure 2 ) of the common electrode CE (for example, referring to Figure 2 ), and supplies a low potential voltage. The touch line TL may be electrically connected to the touch sensing unit TSU (eg, referring to Figure 2 ) of the touch electrode TE (for example, referring to Figure 2 ), and supply a touch drive signal. The signal line SL, the high potential line VDL, the low potential line VSL, and the touch line TL may each be connected through the pad portion PAD from a flexible film COF (for example, see FIG. Figure 3 ) receives a signal or voltage.

[0103] The non-display area NDA may further include an antistatic circuit ESD. The antistatic circuit ESD may overlap the signal line SL and may be electrically connected to the signal line SL. Therefore, the antistatic circuit ESD may prevent static electricity introduced from the outside from being introduced into the display area DA through the signal line SL.

[0104] Figure 4 A solid line 101 indicates a boundary of the display device 10 corresponding to any one corner of the display device 10 . Figure 4 A solid line 102 is a virtual line indicating a boundary between the non-display area NDA and the display area DA of the display device 10 . Figure 4 The solid line 103 indicates that the encapsulation layer TFEL (for example, referring to Figure 2 ). Therefore, the signal line SL, the high potential line VDL, and the low potential line VSL may extend to the pad portion PAD along the non-display area NDA (for example, in the non-display area NDA) inside the boundary where the encapsulation layer TFEL is arranged. The signal line SL, the high potential line VDL, and the low potential line VSL may be arranged so that the signal line SL, the high potential line VDL, and the low potential line VSL do not exceed the encapsulation layer TFEL outside the encapsulation layer TFEL.

[0105] Figure 5 is a cross-sectional view showing a portion of a display device according to an exemplary embodiment. Hereinafter, the same configuration as that described herein will be briefly described or the description thereof will be omitted.

[0106] Reference Figure 2 and Figure 5 The display device 10 may include a panel PLT, a lower film PRF, a first substrate SUB1, a blocking insulating layer BIL, a second substrate SUB2, a transistor layer TRL, a light emitting element layer EML, an encapsulation layer TFEL, a dam DAM, an antistatic circuit ESD, a touch sensing unit TSU, a planarization layer OC, an optical member POL, a pad portion PAD, a flexible film COF and a printed circuit unit FPCA.

[0107] The first connection line CWL1 may be arranged on the interlayer insulating layer ILD. The first connection line CWL1 may include the same material as that of the first source metal layer SDL1 of the display area DA, and may be formed in the same process as that of the first source metal layer SDL1. A portion of the first connection line CWL1 may be in contact with a pad portion PAD passing through the first connection line CWL1. Another portion of the first connection line CWL1 may pass through the interlayer insulating layer ILD and contact the second connection line CWL2. The first connection line CWL1 may electrically connect the pad portion PAD and the second connection line CWL2 to each other. The first connection line CWL1 may supply a data voltage or a source voltage received from the pad portion PAD to the second connection line CWL2.

[0108] The second connection line CWL2 may be disposed on the gate insulating layer GI. The second connection line CWL2 may include the same material as that of the gate layer GTL of the display area DA, and may be formed in the same process as that of the gate layer GTL. The second connection line CWL2 may supply a data voltage received from the first connection line CWL1 to the data line DL, and the second connection line CWL2 may supply a source voltage received from the first connection line CWL1 to the power line VL. For example, the second connection line CWL2 may correspond to Figure 4 The signal line SL may be electrically connected to the signal line SL.

[0109] Alternatively, the second connection line CWL2 may be omitted. In this case, the first connection line CWL1 may be electrically connected to the data line DL or the power line VL.

[0110] The pad portion PAD may be arranged on the first connection line CWL1 and inserted into the first contact hole CNT1. The first contact hole CNT1 may pass through the first connection line CWL1, the interlayer insulating layer ILD, the gate insulating layer GI, the second substrate SUB2, the blocking insulating layer BIL, the first substrate SUB1, and the lower film PRF. The first contact hole CNT1 may be etched from the upper surface of the first connection line CWL1 and penetrate until the lower surface of the lower film PRF. The upper surface of the pad portion PAD may protrude from the upper surface of the first connection line CWL1, and the lower surface of the pad portion PAD may be arranged in the same plane as the lower surface of the lower film PRF. In the manufacturing process of the display device 10, the lower surface of the pad portion PAD may be exposed through the opening portion SOP of the board PLT. The pad portion PAD may electrically connect the first lead electrode LDE1 of the flexible film COF and the first connection line CWL1 to each other. The pad portion PAD may be formed as a single layer or multiple layers including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0111] As an example, the pad portion PAD may be formed by low temperature sintering of a conductive ink including nanoparticles and a polymer. The nanoparticles may include nanoscale metal particles, such as, for example, silver (Ag), copper (Cu), aluminum (Al), or chromium (Cr), and the polymer may include an acrylic resin or an epoxy resin, but the embodiments of the present disclosure are not limited thereto. The conductive ink may include a polymer as a binder for bonding the metal particles to each other, and the nanoparticles may be in close contact with each other (e.g., within a threshold distance) and aggregated by a sintering process. By including sintered nanoparticles, the pad portion PAD may have conductivity.

[0112] As another example, the pad portion PAD may be formed by low temperature sintering of metal organic decomposition ink (MOD Ink). The metal organic decomposition ink may include a liquid metal organic decomposition material smaller than nanoparticles, and the liquid metal organic decomposition material may be changed into a metal material through a sintering process. Therefore, the pad portion PAD may have conductivity.

[0113] The pad portion PAD may be formed by injecting conductive ink or metal paste into the first contact hole CNT1 and then sintering the conductive ink or metal paste using an intense pulse light (IPL) or a laser beam. The specific resistivity of the pad portion PAD may be reduced due to the close contact of metal particles with each other and agglomeration due to heat generated by the IPL or laser beam during the sintering process.

[0114] The first contact hole CNT1 may have a width in micrometer (μm) units. For example, the width of the first contact hole CNT1 may be 40 μm or less. The conductive ink may have a droplet size in nanometer (nm) units. For example, the droplet size of the conductive ink may be 500 nm or more. The display device 10 includes a plurality of micropores passing through the first connection line CWL1, the interlayer insulating layer ILD, the gate insulating layer GI, the second substrate SUB2, the blocking insulating layer BIL, the first substrate SUB1, and the lower film PRF, and therefore, various aspects of the display device 10 support minimizing the size of the non-display area NDA and simplifying the manufacturing process, which can reduce manufacturing time and manufacturing costs.

[0115] The encapsulation layer TFEL may include a first encapsulation layer TFE1 , a second encapsulation layer TFE2 , and a third encapsulation layer TFE3 .

[0116] The first encapsulation layer TFE1 may be arranged on the light emitting element layer EML. The first encapsulation layer TFE1 may include an inorganic material and prevent oxygen or moisture from penetrating into the light emitting element layer EML. The first encapsulation layer TFE1 may extend beyond the display area DA and the dam DAM to the edge of the planarization layer OC. For example, the first encapsulation layer TFE1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0117] The second encapsulation layer TFE2 may be arranged on the first encapsulation layer TFE1. The second encapsulation layer TFE2 may include an organic material that protects the light emitting element layer EML from foreign matter such as dust. The second encapsulation layer TFE2 may extend beyond the display area DA to the dam DAM. The second encapsulation layer TFE2 may fill and be formed in an area surrounded by the dam DAM. For example, the second encapsulation layer TFE2 may include an organic film formed of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, or the like. The second encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0118] The third encapsulation layer TFE3 may be arranged on the second encapsulation layer TFE2. The third encapsulation layer TFE3 may include an inorganic material and prevent oxygen or moisture from penetrating into the light emitting element layer EML. The third encapsulation layer TFE3 may extend to the edge of the planarization layer OC beyond the display area DA and the dam DAM. The third encapsulation layer TFE3 may be arranged on the second encapsulation layer TFE2 inside the dam DAM, and the third encapsulation layer TFE3 may be arranged on the first encapsulation layer TFE1 at the edge of the planarization layer OC. For example, the third encapsulation layer TFE3 may be formed of the same material included in the first encapsulation layer TFE1.

[0119] The dam DAM may surround the display area DA. The dam DAM may include the same material as that of the pixel defining film PDL and may be formed in the same process as that of the pixel defining film PDL. The dam DAM may have a predetermined height so that the second encapsulation layer TFE2 including an organic material does not extend beyond the dam DAM.

[0120] The antistatic circuit ESD may be arranged between the display area DA and the pad area PDA. The antistatic circuit ESD may include at least one transistor. The antistatic circuit ESD may be electrically connected to the second connection line CWL2. Therefore, the antistatic circuit ESD may prevent static electricity introduced from the outside from being introduced into the display area DA through the second connection line CWL2.

[0121] The plate PLT may include an opening portion SOP. The opening portion SOP of the plate PLT may be etched from the lower surface of the plate PLT and penetrate to the upper surface of the plate PLT. For example, the width of the lower portion of the opening portion SOP may be greater than the width of the upper portion of the opening portion SOP. In the manufacturing process of the display device 10, the lower surface of the lower film PRF and the lower surface of the pad portion PAD may be exposed through the opening portion SOP. The pad portion PAD may be electrically connected to the printed circuit unit FPCA through the flexible film COF inserted into the opening portion SOP.

[0122] The flexible film COF may be arranged below the lower film PRF. One side of the flexible film COF may be inserted into the opening portion SOP of the board PLT and electrically connected to the pad portion PAD. The flexible film COF may include a first lead electrode LDE1 arranged on an upper surface of one side of the flexible film COF and inserted into the opening portion SOP. The first lead electrode LDE1 may contact the lower surface of the pad portion PAD.

[0123] The flexible film COF may include a second lead electrode LDE2 disposed on an upper surface of the other side of the flexible film COF. The second lead electrode LDE2 may be electrically connected to a printed circuit unit FPCA disposed on a lower surface of the panel PLT. The flexible film COF may transmit a signal and a voltage of the printed circuit unit FPCA to the display area DA. The flexible film COF may supply a scan control signal to the scan driver SIC.

[0124] The printed circuit unit FPCA may be arranged on the lower surface of the panel PLT. The printed circuit unit FPCA may include at least one of a driving integrated circuit, a timing controller, and a power supply unit. The printed circuit unit FPCA may convert digital video data into an analog data voltage based on a data control signal, and may supply the analog data voltage to the data line DL of the display area DA through the flexible film COF. The printed circuit unit FPCA may supply a source voltage to the power line VL of the display area DA through the flexible film COF. The display device 10 may include a first connection line CWL1 arranged on the second substrate SUB2, a pad portion PAD passing through the first substrate SUB1 and the second substrate SUB2, and a flexible film COF and a printed circuit unit FPCA arranged under the lower film PRF, which may minimize the area of ​​the non-display area NDA.

[0125] Figure 6 is a cross-sectional view showing a portion of a display device according to another exemplary embodiment. Figure 6 The display device is similar to the display device in terms of the configuration of the panel PLT, lead LDL and display driver DIC. Figure 5 The display device is different, and the same configuration as that described in this document will be briefly described or its description will be omitted.

[0126] Reference Figure 2 and Figure 6 The display device 10 may include a panel PLT, a lower film PRF, a first substrate SUB1, a blocking insulating layer BIL, a second substrate SUB2, a transistor layer TRL, a light emitting element layer EML, an encapsulation layer TFEL, a dam DAM, an antistatic circuit ESD, a touch sensing unit TSU, a planarization layer OC, an optical member POL, a pad portion PAD and a display driver DIC.

[0127] The panel PLT may support the display device 10. The panel PLT may include a material having excellent permeability and heat resistance. For example, the panel PLT may be formed of glass fiber reinforced polymer (GFRP), but is not limited thereto.

[0128] The plate PLT may include a lead LDL. The lead LDL may include a first portion LDLa disposed on the upper surface of the plate PLT, a second portion LDLb connected to the first portion LDLa and passing through the plate PLT, and a third portion LDLc connected to the second portion LDLb and disposed on the lower surface of the plate PLT. The lead LDL may be formed in a thickness direction (e.g., Figure 1The lead LDL extends from the lower surface of the plate PLT to the upper surface of the plate PLT in the Z-axis direction (in the Z-axis direction shown in ). The first part LDLa of the lead LDL may contact the lower surface of the pad part PAD arranged on the upper surface of the plate PLT, and the third part LDLc of the lead LDL may be electrically connected to the display driver DIC arranged on the lower surface of the plate PLT. After the pad part PAD is completed, the plate PLT including the lead LDL may be attached to the lower surface of the lower film PRF. The plate PLT may be attached to the lower surface of the lower film PRF by an adhesive member (not shown). The pad part PAD may be electrically connected to the display driver DIC through the lead LDL built into the plate PLT.

[0129] The display driver DIC may be mounted on the lower surface of the panel PLT. The display driver DIC may be an integrated circuit (IC). The display driver DIC may convert digital video data into an analog data voltage based on a data control signal received from a timing controller (not shown), and the display driver DIC may supply the analog data voltage to the data line DL of the display area DA through the flexible film COF (or the lead LDL). The display driver DIC may supply a source voltage received from a power supply unit (not shown) to the power line VL of the display area DA through the flexible film COF (or the lead LDL). The display driver DIC may supply a scan control signal to the scan driver SIC through the flexible film COF (or the lead LDL). The display device 10 may include a first connection line CWL1 arranged on the second substrate SUB2, a pad portion PAD passing through the first substrate SUB1 and the second substrate SUB2, and the lead LDL and the display driver DIC arranged under the lower film PRF, which may minimize the area of ​​the non-display area NDA.

[0130] Figures 7 to 9 It is shown Figure 5 and Figure 6 A cross-sectional view of an example of a manufacturing process of a pad portion in a display device.

[0131] exist Figure 7 In the present invention, the manufacturing process may include arranging a first substrate SUB1 on the lower film PRF. The first substrate SUB1 may be a base substrate or a base member. The manufacturing process may include arranging a blocking insulating layer BIL on the first substrate SUB1. The blocking insulating layer BIL may include an inorganic film capable of preventing air or moisture from penetrating. The manufacturing process may include arranging a second substrate SUB2 on the blocking insulating layer BIL. The second substrate SUB2 may be a base substrate or a base member.

[0132] The manufacturing process may include disposing a gate insulating layer GI on the second substrate SUB2. The manufacturing process may include disposing an interlayer insulating layer ILD on the gate insulating layer GI. The manufacturing process may include disposing a first connection line CWL1 on the interlayer insulating layer ILD. Figure 2The first connection line CWL1 may include the same material as the first source metal layer SDL1 of the display area DA and may be formed in the same process as the first source metal layer SDL1. The manufacturing process may include disposing a protection film FM on the first connection line CWL1.

[0133] The first contact hole CNT1 may pass through the protection film FM, the first connection line CWL1, the interlayer insulating layer ILD, the gate insulating layer GI, the second substrate SUB2, the blocking insulating layer BIL, the first substrate SUB1 and the lower film PRF. The manufacturing process may include etching the first contact hole CNT1 from the upper surface of the protection film FM, and the first contact hole CNT1 may penetrate until the lower surface of the lower film PRF.

[0134] exist Figure 8 In the manufacturing process, the manufacturing process may include providing a protection film FM including a first contact hole CNT1, a first connection wire CWL1, an interlayer insulating layer ILD, a gate insulating layer GI, a second substrate SUB2, a blocking insulating layer BIL, a first substrate SUB1 and a lower film PRF on the stage STG.

[0135] For example, the manufacturing process may include applying conductive ink Ink to the first contact hole CNT1 by an electrohydrodynamic (EHD) inkjet printing method. The droplet of the conductive ink Ink may be smaller than the diameter of the first contact hole CNT1. The first contact hole CNT1 may have a width in micrometer (μm) units. For example, the width of the first contact hole CNT1 may be 40 μm or less.

[0136] The manufacturing process may include injecting the conductive ink Ink into the first contact hole CNT1 through the print head PRH by a pump. The diameter of the print head PRH may be 0.3 μm to 30 μm. The conductive ink Ink may have a droplet size in nanometer (nm) units. For example, the droplet size of the conductive ink Ink may be 500 nm or larger. The manufacturing process may include receiving a positive voltage (+) from a power supply at the print head PRH. The manufacturing process may include receiving a negative voltage (-) from a power supply at the stage STG. The description of injecting the conductive ink Ink through the print head PRH may also be referred to as discharging the conductive ink Ink through the print head PRH.

[0137] The manufacturing process may include arranging the first contact hole CNT1 between the print head PRH and the stage STG to form an electric field, and the conductive ink Ink may be discharged from the print head PRH and have a positive charge. The fluidity of the conductive ink Ink may be improved by electrical attraction, and the conductive ink Ink may fill the first contact hole CNT1 having a micro size. Therefore, the conductive ink Ink may be easily filled up to the lowest part of the first contact hole CNT1 by an electrohydrodynamic (EHD) jet printing method.

[0138] exist Fig. 9 In the present invention, the manufacturing process may include forming the pad portion PAD by low temperature sintering the conductive ink Ink including nanoparticles and polymer. The conductive ink Ink filling the first contact hole CNT1 may include a polymer as a binder for bonding the metal particles to each other, and the nanoparticles may be in close contact with each other and aggregated by the sintering process. The pad portion PAD may have conductivity by including the sintered nanoparticles. The manufacturing process may include removing the protective film FM after forming the pad portion PAD.

[0139] Combination Figure 5 The manufacturing process may include arranging a plate PLT including an opening portion SOP under the lower film PRF. The manufacturing process may include inserting a first lead electrode LDE1 of the flexible film COF into the opening portion SOP and pressing the first lead electrode LDE1 to a lower surface of the pad portion PAD.

[0140] Combination Figure 6 The manufacturing process may include arranging a plate PLT including a lead LDL under the lower film PRF. The manufacturing process may include pressing the lead LDL built into the plate PLT to the lower surface of the pad portion PAD.

[0141] Figures 10 to 12 It is shown Figure 5 and Figure 6 A perspective view of an example of a manufacturing process of a pad portion in a display device. Figures 10 to 12 It is shown Figure 8 and Fig. 9 A perspective view of a manufacturing process of a pad portion in a display device.

[0142] Reference Fig.10 , the manufacturing process may include applying the conductive ink Ink in a linear direction (eg, straight direction) by the print head PRH. In an example where the plurality of first contact holes CNT1 are arranged in three rows, the print head PRH may apply the conductive ink Ink three times, but the application method of the print head PRH is not limited thereto.

[0143] exist Fig.11 In the manufacturing process, the manufacturing process may include arranging the conductive ink Ink in a specific direction so that a portion of the conductive ink Ink fills the first contact holes CNT1 and the other portion of the conductive ink Ink is applied to the protective film FM between the first contact holes CNT1.

[0144] exist Fig.12 In the manufacturing process, the pad portion PAD may be formed by sintering the conductive ink Ink. The manufacturing process may include removing the protective film FM and the conductive ink Ink applied on the protective film FM, which may expose the first connection line CWL1 and the interlayer insulating layer ILD.

[0145] Figures 13 to 16It is shown Figure 5 and Figure 6 A cross-sectional view of another example of a manufacturing process of a pad portion in a display device. Fig.13 The described manufacturing process corresponds to the reference Figure 7 The following steps of the manufacturing process are described.

[0146] exist Fig.13 In the present invention, the manufacturing process may include providing a first connection line CWL1 including a first contact hole CNT1, an interlayer insulating layer ILD, a gate insulating layer GI, a second substrate SUB2, a blocking insulating layer BIL, a first substrate SUB1, and a lower film PRF on a protective film FM arranged on the stage STG. The manufacturing process may include providing a soldering ink SLD at an upper portion of the stage STG, and arranging the first contact hole CNT1 to overlap with the soldering ink SLD.

[0147] The welding ink SLD may include nanoparticles and polymers. The nanoparticles may include nanoscale metal particles, such as silver (Ag), copper (Cu), aluminum (Al), or chromium (Cr), and the polymer may include acrylic resin or epoxy resin, but the embodiments of the present disclosure are not limited thereto.

[0148] exist Fig.14 In the present invention, the manufacturing process may include sucking the welding ink SLD into the first contact hole CNT1 by the suction device SHD. The welding ink SLD may fill the first contact hole CNT1 from the lower portion of the first contact hole CNT1 to the upper portion of the first contact hole CNT1. The manufacturing process may include sucking the welding ink SLD until the welding ink SLD contacts the first connection line CWL1.

[0149] exist Fig.15 In the manufacturing process, the pad portion PAD may be formed by sintering the soldering ink SLD. The pad portion PAD may contact the side surface of the first connection wire CWL1 forming the first contact hole CNT1 and the upper surface of the first connection wire CWL1.

[0150] exist Fig.16 In the manufacturing process, the protective film FM and the portion of the pad portion PAD surrounded by the protective film FM may be removed. The lower surface of the lower film PRF and the lower surface of the pad portion PAD may be exposed. The lower surface of the pad portion PAD may be arranged in the same plane as the lower surface of the lower film PRF.

[0151] Combination Figure 5 The manufacturing process may include arranging a plate PLT including an opening portion SOP under the lower film PRF. The manufacturing process may include inserting a first lead electrode LDE1 of the flexible film COF into the opening portion SOP and pressing the first lead electrode LDE1 to a lower surface of the pad portion PAD.

[0152] Combination Figure 6 The manufacturing process may include arranging a plate PLT including a lead LDL under the lower film PRF. The manufacturing process may include pressing the lead LDL built into the plate PLT to the lower surface of the pad portion PAD.

[0153] Fig.17 is a cross-sectional view showing a portion of a display device according to another exemplary embodiment. Fig.17 The display device is similar to the display device in terms of the configuration of the first lead electrode LDE1. Figure 5 The display device is different, and the same configuration as that described in this document will be briefly described or its description will be omitted.

[0154] Reference Figure 2 and Fig.17 The display device 10 may include a panel PLT, a lower film PRF, a first substrate SUB1, a blocking insulating layer BIL, a second substrate SUB2, a transistor layer TRL, a light emitting element layer EML, an encapsulation layer TFEL, a dam DAM, an antistatic circuit ESD, a touch sensing unit TSU, a planarization layer OC, an optical member POL, a pad portion PAD, a flexible film COF and a printed circuit unit FPCA.

[0155] The pad portion PAD may be arranged on the first connection wire CWL1 and inserted into the first contact hole CNT1. The first contact hole CNT1 may pass through the first connection wire CWL1, the interlayer insulating layer ILD, the gate insulating layer GI, the second substrate SUB2, the blocking insulating layer BIL, the first substrate SUB1, and the lower film PRF. The first contact hole CNT1 may be etched from the upper surface of the first connection wire CWL1 and penetrate until the lower surface of the lower film PRF. The upper surface of the pad portion PAD may protrude from the upper surface of the first connection wire CWL1, and the lower surface of the pad portion PAD may be arranged in the same plane as the lower surface of the lower film PRF. The pad portion PAD may contact the pin portion PIN that passes through the pad portion PAD and protrudes from the upper surface of the first lead electrode LDE1. The pad portion PAD may electrically connect the first connection wire CWL1 and the first lead electrode LDE1 of the flexible film COF to each other.

[0156] The display device 10 includes a plurality of microholes passing through the first connection line CWL1, the interlayer insulating layer ILD, the gate insulating layer GI, the second substrate SUB2, the blocking insulating layer BIL, the first substrate SUB1 and the lower film PRF, and therefore, the various aspects of the display device 10 described herein can minimize the area of ​​the non-display area NDA and simplify the manufacturing process to reduce manufacturing time and manufacturing costs.

[0157] The board PLT may include an opening portion SOP. The opening portion SOP of the board PLT may be etched from the lower surface of the board PLT and penetrated to the upper surface of the board PLT. For example, the width of the lower portion of the opening portion SOP may be greater than the width of the upper portion of the opening portion SOP. The pad portion PAD may be electrically connected to the printed circuit unit FPCA through a flexible film COF inserted into the opening portion SOP.

[0158] The flexible film COF may be arranged below the lower film PRF. One side of the flexible film COF may be inserted into the opening portion SOP of the board PLT and may be electrically connected to the pad portion PAD. The flexible film COF may include a first lead electrode LDE1 arranged on an upper surface of one side of the flexible film COF and inserted into the opening portion SOP. The upper surface of the first lead electrode LDE1 may contact the lower surface of the pad portion PAD.

[0159] The first lead electrode LDE1 may include a pin portion PIN protruding from an upper surface of the first lead electrode LDE1. The pin portion PIN may pass through the pad portion PAD inserted into the first contact hole CNT1 and protrude from an upper surface of the pad portion PAD. The pin portion PIN may increase a contact area with the pad portion PAD, which may support easily connecting the pad portion PAD and the first lead electrode LDE1 to each other.

[0160] The display device 10 may include a first connection line CWL1 arranged on the second substrate SUB2, a pad portion PAD and a pin portion PIN passing through the first substrate SUB1 and the second substrate SUB2, and a flexible film COF and a printed circuit unit FPCA arranged under the lower film PRF, which can minimize the area of ​​the non-display area NDA.

[0161] Fig.18 is a cross-sectional view showing a portion of a display device according to another exemplary embodiment. Fig.18 The display device has a different configuration from that of the pad portion PAD. Fig.17 The display device is different, and the same configuration as that described in this document will be briefly described or its description will be omitted.

[0162] Reference Figure 2 and Fig.18 The display device 10 may include a panel PLT, a lower film PRF, a first substrate SUB1, a blocking insulating layer BIL, a second substrate SUB2, a transistor layer TRL, a light emitting element layer EML, an encapsulation layer TFEL, a dam DAM, an antistatic circuit ESD, a touch sensing unit TSU, a planarization layer OC, an optical member POL, a pad portion PAD, a flexible film COF and a printed circuit unit FPCA.

[0163] The pad portion PAD may be arranged on the first connection wire CWL1 and inserted into the first contact hole CNT1. The first contact hole CNT1 may pass through the first connection wire CWL1, the interlayer insulating layer ILD, the gate insulating layer GI, the second substrate SUB2, the blocking insulating layer BIL, the first substrate SUB1, and the lower film PRF. The first contact hole CNT1 may be etched from the upper surface of the first connection wire CWL1 and penetrate until the lower surface of the lower film PRF. The upper surface of the pad portion PAD may protrude from the upper surface of the first connection wire CWL1, and the lower surface of the pad portion PAD may be spaced apart from the upper surface of the first lead electrode LDE1. Therefore, the pad portion PAD may not be filled into the lower portion of the first contact hole CNT1. The pad portion PAD may contact the pin portion PIN passing through the pad portion PAD. The pad portion PAD may electrically connect the first lead electrode LDE1 of the flexible film COF and the first connection wire CWL1 to each other.

[0164] The flexible film COF may be arranged below the lower film PRF. One side of the flexible film COF may be inserted into the opening portion SOP of the board PLT and may be electrically connected to the pad portion PAD. The flexible film COF may include a first lead electrode LDE1 arranged on an upper surface of one side of the flexible film COF and inserted into the opening portion SOP. The upper surface of the first lead electrode LDE1 may be spaced apart from the lower surface of the pad portion PAD.

[0165] The first lead electrode LDE1 may include a pin portion PIN protruding from an upper surface of the first lead electrode LDE1. The pin portion PIN may pass through the pad portion PAD inserted into the first contact hole CNT1 and protrude from an upper surface of the pad portion PAD. The pin portion PIN may increase a contact area with the pad portion PAD and may easily connect the pad portion PAD and the first lead electrode LDE1 to each other.

[0166] The display device 10 may minimize the area of ​​the non-display area NDA by including a first connection line CWL1 disposed on the second substrate SUB2, a pad portion PAD and a pin portion PIN passing through the first and second substrates SUB1 and SUB2, and a flexible film COF and a printed circuit unit FPCA disposed under a lower film PRF.

[0167] Fig.19 is a cross-sectional view showing a portion of a display device according to another embodiment. Fig.19 The display device has a different configuration of the lead LDL. Fig.17 The display device is different, and the same configuration as that described in this document will be briefly described or its description will be omitted.

[0168] Reference Figure 2 and Fig.19The display device 10 may include a panel PLT, a lower film PRF, a first substrate SUB1, a blocking insulating layer BIL, a second substrate SUB2, a transistor layer TRL, a light emitting element layer EML, an encapsulation layer TFEL, a dam DAM, an antistatic circuit ESD, a touch sensing unit TSU, a planarization layer OC, an optical member POL, a pad portion PAD and a display driver DIC.

[0169] The pad portion PAD may be arranged on the first connection wire CWL1 and inserted into the first contact hole CNT1. The first contact hole CNT1 may pass through the first connection wire CWL1, the interlayer insulating layer ILD, the gate insulating layer GI, the second substrate SUB2, the blocking insulating layer BIL, the first substrate SUB1, and the lower film PRF. The first contact hole CNT1 may be etched from the upper surface of the first connection wire CWL1 and penetrate until the lower surface of the lower film PRF. The upper surface of the pad portion PAD may protrude from the upper surface of the first connection wire CWL1, and the lower surface of the pad portion PAD may be arranged in the same plane as the lower surface of the lower film PRF. The pad portion PAD may contact the upper surfaces of the pin portion PIN and the first portion LDLa of the lead LDL passing through the pad portion PAD. The pad portion PAD may electrically connect the lead LDL and the first connection wire CWL1 to each other.

[0170] The plate PLT may include a lead LDL. The lead LDL may include a first portion LDLa arranged on the upper surface of the plate PLT, a second portion LDLb connected to the first portion LDLa and passing through the plate PLT, and a third portion LDLc connected to the second portion LDLb and arranged on the lower surface of the plate PLT. The lead LDL may extend from the lower surface of the plate PLT to the upper surface of the plate PLT in the thickness direction of the plate PLT. The first portion LDLa of the lead LDL may contact the lower surface of the pad portion PAD arranged on the upper surface of the plate PLT, and the third portion LDLc of the lead LDL may be electrically connected to the display driver DIC arranged on the lower surface of the plate PLT. The plate PLT including the lead LDL may be attached to the lower surface of the lower film PRF. The plate PLT may be attached to the lower surface of the lower film PRF by an adhesive member (not shown). The pad portion PAD may be electrically connected to the display driver DIC by the lead LDL built into the plate PLT.

[0171] The lead LDL may include a pin portion PIN protruding from the upper surface of the first portion LDLa. The pin portion PIN may pass through the pad portion PAD inserted into the first contact hole CNT1 and protrude from the upper surface of the pad portion PAD. The pin portion PIN may increase the contact area with the pad portion PAD and may easily connect the pad portion PAD and the lead LDL to each other.

[0172] The display device 10 may include a first connection line CWL1 arranged on the second substrate SUB2, a pad portion PAD and a pin portion PIN passing through the first substrate SUB1 and the second substrate SUB2, and a lead LDL and a display driver DIC arranged under the lower film PRF, which can minimize the area of ​​the non-display area NDA.

[0173] Fig. 20 is a cross-sectional view showing a portion of a display device according to another exemplary embodiment. Fig. 20 The display device has a different configuration from that of the pad portion PAD. Fig.19 The display device is different, and the same configuration as that described in this document will be briefly described or its description will be omitted.

[0174] Reference Figure 2 and Fig. 20 The display device 10 may include a panel PLT, a lower film PRF, a first substrate SUB1, a blocking insulating layer BIL, a second substrate SUB2, a transistor layer TRL, a light emitting element layer EML, an encapsulation layer TFEL, a dam DAM, an antistatic circuit ESD, a touch sensing unit TSU, a planarization layer OC, an optical member POL, a pad portion PAD and a display driver DIC.

[0175] The pad portion PAD may be arranged on the first connection wire CWL1 and inserted into the first contact hole CNT1. The first contact hole CNT1 may pass through the first connection wire CWL1, the interlayer insulating layer ILD, the gate insulating layer GI, the second substrate SUB2, the blocking insulating layer BIL, the first substrate SUB1, and the lower film PRF. The first contact hole CNT1 may be etched from the upper surface of the first connection wire CWL1 and penetrate until the lower surface of the lower film PRF. The upper surface of the pad portion PAD may protrude from the upper surface of the first connection wire CWL1, and the lower surface of the pad portion PAD may be spaced apart from the upper surface of the first portion LDLa of the lead LDL. Therefore, the pad portion PAD may not be filled into the lower portion of the first contact hole CNT1. The pad portion PAD may be in contact with the pin portion PIN passing through the pad portion PAD. The pad portion PAD may electrically connect the lead LDL and the first connection wire CWL1 to each other.

[0176] The plate PLT may include a lead LDL. The lead LDL may include a first portion LDLa arranged on the upper surface of the plate PLT, a second portion LDLb connected to the first portion LDLa and passing through the plate PLT, and a third portion LDLc connected to the second portion LDLb and arranged on the lower surface of the plate PLT. The lead LDL may extend from the lower surface of the plate PLT to the upper surface of the plate PLT in the thickness direction of the plate PLT. The first portion LDLa of the lead LDL may not contact the lower surface of the pad portion PAD arranged on the upper surface of the plate PLT, but the third portion LDLc of the lead LDL may be electrically connected to the display driver DIC arranged on the lower surface of the plate PLT. The plate PLT including the lead LDL may be attached to the lower surface of the lower film PRF. The plate PLT may be attached to the lower surface of the lower film PRF by an adhesive member (not shown). The pad portion PAD may be electrically connected to the display driver DIC through the lead LDL built into the plate PLT.

[0177] The lead LDL may include a pin portion PIN protruding from the upper surface of the first portion LDLa. The pin portion PIN may pass through the pad portion PAD inserted into the first contact hole CNT1 and protrude from the upper surface of the pad portion PAD. The pin portion PIN may increase the contact area with the pad portion PAD and may easily connect the pad portion PAD and the lead LDL to each other.

[0178] The display device 10 may minimize the area of ​​the non-display area NDA by including a first connection line CWL1 disposed on the second substrate SUB2, a pad portion PAD and a pin portion PIN passing through the first and second substrates SUB1 and SUB2, and a lead line LDL and a display driver DIC disposed under the lower film PRF.

[0179] Figure 21 to Figure 23 It is shown Figures 17 to 20 A cross-sectional view of a manufacturing process of a pad portion in a display device.

[0180] exist Fig.21 In the present invention, the manufacturing process may include arranging a first substrate SUB1 on the lower film PRF. The first substrate SUB1 may be a base substrate or a base member. The manufacturing process may include arranging a blocking insulating layer BIL on the first substrate SUB1. The blocking insulating layer BIL may include an inorganic film capable of preventing air or moisture from penetrating. The manufacturing process may include arranging a second substrate SUB2 on the blocking insulating layer BIL. The second substrate SUB2 may be a base substrate or a base member.

[0181] The manufacturing process may include disposing a gate insulating layer GI on the second substrate SUB2. The manufacturing process may include disposing an interlayer insulating layer ILD on the gate insulating layer GI. The manufacturing process may include disposing a first connection line CWL1 on the interlayer insulating layer ILD. Figure 2, the first connection line CWL1 may include the same material as that of the first source metal layer SDL1 of the display area DA, and may be formed in the same process as that of the first source metal layer SDL1.

[0182] The first contact hole CNT1 may pass through the first connection line CWL1, the interlayer insulating layer ILD, the gate insulating layer GI, the second substrate SUB2, the blocking insulating layer BIL, the first substrate SUB1, and the lower film PRF. The manufacturing process may include etching the first contact hole CNT1 from the upper surface of the first connection line CWL1 so that the first contact hole CNT1 penetrates until the lower surface of the lower film PRF.

[0183] The manufacturing process may include providing a flexible film COF below the lower film PRF. The flexible film COF may include an upper surface arranged on one side of the flexible film COF and inserted into the opening portion SOP (eg, referring to Fig.18 ). The first lead electrode LDE1 may include a pin portion PIN protruding from an upper surface of the first lead electrode LDE1.

[0184] exist Fig. 22 In the embodiment, the upper surface of the first lead electrode LDE1 may be disposed on the lower surface of the lower film PRF, and the pin portion PIN may be inserted into the first contact hole CNT1. The pin portion PIN may be spaced apart from the inner sidewall of the first contact hole CNT1.

[0185] The manufacturing process may include injecting conductive ink Ink into the first contact hole CNT1 through a print head PRH. The print head PRH may have a diameter of 0.3 μm to 30 μm. The conductive ink Ink may have a droplet size in nanometer (nm) units. For example, the droplet size of the conductive ink Ink may be 500 nm or more. The conductive ink Ink may fill the first contact hole CNT1 into which the pin portion PIN is inserted.

[0186] exist Fig.23 In the present invention, the manufacturing process may include forming the pad portion PAD by low temperature sintering the conductive ink Ink including nanoparticles and polymer. The conductive ink Ink filled into the first contact hole CNT1 may include a polymer as a binder for bonding the metal particles to each other, and the nanoparticles may be in close contact with each other and aggregated by the sintering process. The pad portion PAD may have conductivity by including the sintered nanoparticles. The pin portion PIN may protrude from the upper surface of the pad portion PAD. The manufacturing process may include removing the protective film FM (e.g., referring to FIG. 1 ) after forming the pad portion PAD. Figure 8 ).

[0187] Combination Fig.17, the manufacturing process may include arranging a plate PLT including an opening portion SOP under the lower film PRF. The manufacturing process may include pressing a first lead electrode LDE1 of the flexible film COF to a lower surface of the pad portion PAD.

[0188] Combination Fig.19 The manufacturing process may include arranging a plate PLT including a lead LDL under the lower film PRF. The manufacturing process may include pressing the lead LDL built into the plate PLT to the lower surface of the pad portion PAD.

[0189] and Fig.23 Unlike the example shown in , the lower surface of the pad portion PAD may be spaced apart from the upper surface of the first lead electrode LDE1. In this case, the pad portion PAD may not be filled into the lower portion of the first contact hole CNT1. Fig.18 The pad portion PAD may contact the pin portion PIN passing through the pad portion PAD and electrically connect the first lead electrode LDE1 and the first connection wire CWL1 to each other. Fig. 20 , the pad portion PAD may make contact with the pin portion PIN passing through the pad portion PAD and electrically connect the lead line LDL and the first connection line CWL1 to each other.

[0190] The embodiments of the present disclosure support one or more processes (manufacturing processes) that support the features and embodiments described herein. According to the exemplary aspects described herein, descriptions of elements "arrangeable" and "formable", etc. include processes and techniques for arranging, forming, positioning, and modifying elements and the like.

Claims

1. A display device, comprising: a plate, the plate comprising an opening; a lower film, the lower film being arranged on the plate; a first substrate disposed on the lower film; A first connection line, wherein the first connection line is arranged on the first substrate; a pad portion inserted into a first contact hole passing through the first connection line, the first substrate, and the lower film, wherein the pad portion is connected to the first connection line; as well as a flexible film including a first lead electrode inserted into the opening portion of the board, The first lead electrode includes a pin portion protruding from an upper surface of the first lead electrode and passing through the pad portion.

2. The display device according to claim 1, wherein: A lower surface of the pad portion contacts the upper surface of the first lead electrode.

3. The display device according to claim 1, wherein: A lower surface of the pad portion is spaced apart from the upper surface of the first lead electrode.

4. The display device according to claim 1, further comprising: a gate insulating layer, wherein the gate insulating layer is arranged on the first substrate; a second connection line, the second connection line being arranged on the gate insulating layer and connected to the first connection line; as well as An interlayer insulating layer is disposed between the second connecting line and the first connecting line.

5. The display device according to claim 4, further comprising: a second substrate disposed between the first substrate and the gate insulating layer; a semiconductor region of a transistor, wherein the semiconductor region of the transistor is arranged on the second substrate; a gate electrode of the transistor, the gate electrode of the transistor being arranged on the gate insulating layer; as well as a connecting electrode disposed on the interlayer insulating layer and electrically connected to the transistor, wherein the first connection line comprises the same material as the connection electrode and is formed in the same process as the connection electrode, and The second connection line includes the same material as that of the gate electrode of the transistor and is formed in the same process as that of the gate electrode of the transistor.

6. The display device according to claim 1, further comprising a printed circuit unit disposed under the board and including a driving integrated circuit, in, The flexible film further includes a second lead electrode electrically connected to the printed circuit unit.

7. A display device, comprising: a board including leads; a lower film, the lower film being arranged on the plate; a first substrate disposed on the lower film; A first connection line, wherein the first connection line is arranged on the first substrate; as well as a pad portion inserted into a first contact hole passing through the first connection line, the first substrate, and the lower film, wherein the pad portion is connected to the first connection line, Wherein, the lead wire comprises: a first portion disposed on an upper surface of the plate; a second portion passing through the plate and connected to the first portion; a third portion disposed on a lower surface of the plate and connected to the second portion; and A lead portion protrudes from an upper surface of the first portion and passes through the pad portion.

8. The display device according to claim 7, wherein: A lower surface of the pad portion contacts the upper surface of the first portion of the lead.

9. The display device according to claim 7, wherein: A lower surface of the pad portion is spaced apart from the upper surface of the first portion of the lead. 10 . The display device according to claim 7 , further comprising a display driver disposed on the lower surface of the board and electrically connected to the third portion of the lead.

11. A method for manufacturing a display device, comprising: sequentially stacking a lower film, a first substrate, a first connecting line, and a protective film; forming a first contact hole passing through the protective film, the first connecting line, the first substrate and the lower film; providing the lower film including the first contact hole, the first substrate, the first connection line, and the protective film on a stage; providing a printing head over the first contact hole; supplying a positive voltage to the print head and a negative voltage to the stage via a power supply; injecting conductive ink into the first contact hole through the printing head; forming a pad portion by sintering the conductive ink; disposing a board below the lower film, the board including an opening portion exposing the pad portion; as well as By inserting the first lead electrode of the flexible film into the opening portion, the first lead electrode of the flexible film is connected to the pad portion.

12. The method according to claim 11, wherein: Injecting the conductive ink includes filling the first contact hole with the conductive ink by electrical attraction of the conductive ink having a positive charge.

13. The method according to claim 11, wherein: Injecting the conductive ink includes applying the conductive ink in a linear direction through the print head, injecting a portion of the conductive ink into the first contact hole and applying another portion of the conductive ink onto the protective film.

14. The method according to claim 13, further comprising: After the pad portion is formed, the protective film and the conductive ink applied onto the protective film are removed.

15. A method for manufacturing a display device, comprising: sequentially stacking a protective film, a lower film, a first substrate, and a first connecting line; forming a first contact hole passing through the first connection line, the first substrate, the lower film and the protective film; providing a stage including welding ink provided at an upper portion of the stage; providing the protective film, the lower film, the first substrate, and the first connection line on the stage so that the first contact hole overlaps with the soldering ink; Sucking the welding ink into the first contact hole by a suction device; as well as The land portion is formed by sintering the solder ink.

16. The method according to claim 15, further comprising: exposing the lower surface of the lower film by removing the protective film; disposing a board below the lower film, the board including an opening portion exposing the pad portion; as well as By inserting the first lead electrode of the flexible film into the opening portion, the first lead electrode of the flexible film is connected to the pad portion.

17. The method according to claim 16, wherein: Exposing the lower surface of the lower film includes arranging the lower surface of the pad part at the same plane as the lower surface of the lower film.

18. A method for manufacturing a display device, comprising: sequentially stacking a lower film, a first substrate, and a first connecting line; forming a first contact hole passing through the first connection line, the first substrate and the lower film; providing a first lead electrode disposed on one side of the flexible film and including a pin portion protruding from an upper surface of the first lead electrode; disposing the first lead electrode on the lower surface of the lower film by inserting the lead portion into the first contact hole; injecting conductive ink into the first contact hole through a printing head; as well as A pad portion is formed by sintering the conductive ink.

19. The method according to claim 18, wherein: The lead portion passes through the land portion and protrudes from an upper surface of the land portion.

20. The method according to claim 18, wherein: The first lead electrode is electrically connected to the first connection line through the pin portion and the pad portion.

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