Improved clock skewed trajectory planning

Abstract

The invention discloses trajectory planning for improving clock skew. In one aspect, a node array includes a plurality of nodes having clock distribution circuitry configured to distribute a clock signal to each of the nodes. The clock signal propagates in a first direction at least between adjacent nodes. The node (202) also includes a trajectory plan including a plurality of wires to convey communication signals propagating between adjacent nodes. The plurality of wires includes a first wire (404) configured to transmit a first communication signal in a direction opposite the first direction; and a second wire (402) configured to transmit a second communication signal in the first direction, where a width of the first wire is greater than a width of the second wire.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 371,951, filed on August 19, 2022, which is incorporated herein by reference in its entirety and for all purposes. Technical Field

[0003] The present disclosure relates generally to distributed timing and, more particularly, to techniques for reducing clock skew. Background Art

[0004] Artificial intelligence (AI) processors can be built using arrays of processing nodes. The nodes forming the array can communicate with their neighboring nodes in order to perform processing tasks. A clock signal can be provided to each node so that the nodes can be synchronized to enable communication between them. One technique for providing a clock signal to an array of nodes is distributed timing. Summary of the invention

[0005] In one aspect, a node array is provided having a trajectory planning for improving clock skew, the node array comprising: a first node, the first node comprising a computing circuit device and a plurality of conductors, the plurality of conductors being configured to transmit a communication signal generated by the first node to an adjacent node of the node array; a second node, the second node being one of the adjacent nodes; and a third node, the third node being one of the adjacent nodes, wherein the clock signal propagates from the second node to the first node and then to the third node in a first direction; and wherein the plurality of conductors of the first node comprise: a first conductor, the first conductor being configured to transmit a first communication signal to the second node in a direction opposite to the first direction, and a second conductor, the second conductor being configured to transmit a second communication signal to the third node in the first direction, wherein a width of the first conductor is greater than a width of the second conductor.

[0006] In some embodiments, the width of the first conductive line and the width of the second conductive line help meet setup time and hold time of electronic components in the second node and the third node.

[0007] In some embodiments, the plurality of conductors further include: a plurality of first conductors extending in a first direction and including first conductors, the plurality of first conductors being configured to transmit a plurality of first communication signals to a second node in a direction opposite to the first direction, and a plurality of second conductors extending in the first direction and including second conductors, the plurality of second conductors being configured to transmit a plurality of second communication signals to a third node in the first direction, wherein the plurality of first conductors are interlaced with the plurality of second conductors.

[0008] In some embodiments, the node array also includes: a fourth node, which is one of the adjacent nodes; and a fifth node, which is one of the adjacent nodes, wherein the clock signal propagates from the fourth node to the first node and then to the fifth node in a second direction perpendicular to the first direction, wherein the multiple conductors of the first node also include: a third conductor, which extends in the second direction and is configured to transmit a third communication signal to the fourth node in a direction opposite to the second direction; and a fourth conductor, which extends in the second direction and is configured to transmit a fourth communication signal to the fifth node in the second direction, wherein the width of the third conductor is greater than the width of the fourth conductor.

[0009] In some embodiments, the length of each of the first node, the second node, the third node, the fourth node, and the fifth node in the first direction is greater than the length in the second direction, the width of the first wire is greater than the width of the third wire, and the width of the second wire is greater than the width of the fourth wire.

[0010] In some embodiments, the plurality of conductors further include: a plurality of third conductors extending in the second direction and including third conductors, the plurality of third conductors being configured to transmit a plurality of third communication signals to a fourth node in a direction opposite to the second direction, and a plurality of fourth conductors extending in the second direction and including fourth conductors, the plurality of fourth conductors being configured to transmit a plurality of fourth communication signals to a fifth node in the second direction, wherein the plurality of third conductors are interlaced with the plurality of fourth conductors.

[0011] In some embodiments, the clock signal has a substantially fixed delay as it propagates between adjacent nodes.

[0012] In certain embodiments, a node of the node array is configured to operate with a timing offset compared to other nodes based on the timing at which the node receives a clock signal.

[0013] On the other hand, a node of a node array is provided, having a trajectory planning for improving clock skew in the node array, the node comprising: a computing circuit device configured to generate a communication signal; and a plurality of conductors configured to enable the communication signal to propagate to adjacent nodes of the node array, wherein the nodes of the node array are configured to receive a distributed clock signal, which propagates in at least a first direction between adjacent nodes, wherein the plurality of conductors comprise: a first conductor configured to transmit a first communication signal in a direction opposite to the first direction, and a second conductor configured to transmit a second communication signal in the first direction, wherein a width of the first conductor is greater than a width of the second conductor.

[0014] In certain embodiments, the width of the first conductive line and the width of the second conductive line facilitate meeting setup times and hold times of electronic components in respective destination nodes of the first communication signal and the second communication signal.

[0015] In some embodiments, the plurality of conductors further include: a plurality of first conductors extending in a first direction and including first conductors, the plurality of first conductors being configured to transmit a plurality of first communication signals in a direction opposite to the first direction, and a plurality of second conductors extending in the first direction and including second conductors, the plurality of second conductors being configured to transmit a plurality of second communication signals in the first direction, wherein the plurality of first conductors are interlaced with the plurality of second conductors.

[0016] In some embodiments, the clock signal also propagates in a second direction between adjacent nodes, the second direction being perpendicular to the first direction, and the plurality of conductors further include: a third conductor extending in the second direction and configured to transmit a third communication signal in a direction opposite to the second direction; and a fourth conductor extending on the third second and configured to transmit a fourth communication signal in the second direction, wherein a width of the third conductor is greater than a width of the fourth conductor.

[0017] In some embodiments, the length of the node in the first direction is greater than the length in the second direction, the width of the first conductive line is greater than the width of the third conductive line, and the width of the second conductive line is greater than the width of the fourth conductive line.

[0018] In some embodiments, the plurality of conductors further include: a plurality of third conductors extending in the second direction and including third conductors, the plurality of third conductors being configured to transmit a plurality of third communication signals in a direction opposite to the second direction, and a plurality of fourth conductors extending in the second direction and including fourth conductors, the plurality of fourth conductors being configured to transmit a plurality of fourth communication signals in the second direction, wherein the plurality of third conductors are interlaced with the plurality of fourth conductors.

[0019] In certain embodiments, the clock signal is further configured to be distributed with a substantially fixed delay when propagating between adjacent nodes.

[0020] In certain embodiments, a node is configured to operate with a timing offset compared to other nodes of the array of nodes based on the timing at which the node receives a clock signal.

[0021] On the other hand, a method for manufacturing a node array is provided, the method comprising: forming a first node, the first node comprising a computing circuit device and a plurality of conductors, the plurality of conductors being configured to transmit a communication signal generated by the first node to an adjacent node of the node array; forming a second node, the second node being one of the adjacent nodes; and forming a third node, the third node being one of the adjacent nodes, wherein a clock signal propagates from the second node to the first node and then to the third node in a first direction, and wherein the plurality of conductors of the first node comprise: a first conductor, the first conductor being configured to transmit a first communication signal to the second node in a direction opposite to the first direction, and a second conductor, the second conductor being configured to transmit a second communication signal in the first direction, wherein a width of the first conductor is greater than a width of the second conductor.

[0022] In some embodiments, a width of the first conductive line and a width of the second conductive line are selected to satisfy setup time and hold time of electronic components in the second node and the third node.

[0023] In some embodiments, the plurality of conductors further include: a plurality of first conductors extending in a first direction and including first conductors, the plurality of first conductors being configured to transmit a plurality of first communication signals to a second node in a direction opposite to the first direction, and a plurality of second conductors extending in the first direction and including second conductors, the plurality of second conductors being configured to transmit a plurality of second communication signals to a third node in the first direction, wherein the plurality of first conductors are interlaced with the plurality of second conductors.

[0024] In some embodiments, the node array also includes: a fourth node, which is one of the adjacent nodes; and a fifth node, which is one of the adjacent nodes, wherein the clock signal propagates from the fourth node to the first node and then to the fifth node in a second direction perpendicular to the first direction, and the multiple conductors of the first node also include: a third conductor, which extends in the second direction and is configured to transmit a third communication signal to the fourth node in a direction opposite to the second direction; and a fourth conductor, which extends in the second direction and is configured to transmit a fourth communication signal to the fifth node in the second direction, wherein the width of the third conductor is greater than the width of the fourth conductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic block diagram of an example chip according to aspects of the present disclosure.

[0026] Figure 2 is with an example node array such as Figure 1 A node clock level diagram associated with a node array).

[0027] Figure 3A portion of a node array including example clock propagation directions according to aspects of the present disclosure is illustrated.

[0028] Figure 4A and Figure 4B Example clock propagation directions and signal propagation directions for nodes of an array according to aspects of the present disclosure are illustrated.

[0029] Figure 5A and Figure 5B A number of example signal propagation directions for nodes of an array according to aspects of the present disclosure are illustrated. DETAILED DESCRIPTION

[0030] The following description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein may be implemented in a variety of different ways, for example, as defined and covered by the claims. In this specification, reference is made to the accompanying drawings in which the same reference numerals may indicate the same or functionally similar elements. It should be understood that the elements illustrated in the drawings are not necessarily drawn to scale. In addition, it should be understood that certain embodiments may include more elements than illustrated in the drawings and / or a subset of the elements illustrated in the drawings. In addition, some embodiments may encompass any suitable combination of features from two or more drawings. The titles provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims.

[0031] Node Array Introduction

[0032] The present disclosure relates to a clock distribution network in which clock signals arrive at each node of a node array at different times. Timing with a fixed offset can be referred to as average synchronous timing. Embodiments disclosed herein relate to an average synchronous clock network that can be modularly constructed from common circuit devices. The clock signals of such a network can be locally low-skew and averagely synchronized at a coarse level.

[0033] Traditionally, clock signals are built and routed at the top level of the chip, which increases the effort, area, and power consumption of the design. In this case, the clock distribution is a custom design at the top level of the chip. One approach is to route the clock signal in channels between sub-blocks. This can destroy the design and consume area. Another approach is to push the top-level clock down into the sub-blocks. This can slow down the design process and cause the same part of the design to bifurcate, creating unique copies. Traditional approaches can cause the clock signal to arrive at all receivers almost at the same time. The circuit can then operate in lock step.

[0034] In the clock distribution network disclosed herein, clocks arrive at different receivers at different times. Clock signals can be distributed through a two-dimensional (2D) array of nodes so that the clock signals arrive at different nodes with different timing offsets. Due to the clock distribution structure, the arrival times can be grouped by contours or waves on the die. At the local level, the circuit devices of the nodes can operate in lock step. More comprehensively, the circuit devices in different nodes of the node array can operate at timing offsets relative to each other. By having different nodes perform calculations at timing offsets relative to each other, the peak current from the power grid can be reduced. The quality of the power supply signal can also be improved by such calculations. The computing circuit device can be designed to process the arrival time difference of the clock signal.

[0035] The clock distribution network disclosed herein can simplify the top-level design and clock circuit device construction of the chip. Timing with fixed offset can be called average synchronous timing. The embodiments disclosed herein allow the modular construction of average synchronous clock networks with examples of common sub-part designs. The clock signals of such networks can be locally low-skew and averagely synchronous at a coarse level.

[0036] The clock distribution disclosed herein can be applied to any suitable chip. In some applications, the clock distribution disclosed herein can be applied to chips of arrays each including smaller computing nodes. Computing nodes can be referred to as processors or cores. In this way, clock signals can form arrival time waves on the array. Each computing node can receive low skew clock signals. The computing nodes of the array can be designed to have only interfaces to neighboring computing nodes to solve the arrival time difference (skew) of the average synchronous clock phase. For example, the chip with a clock distribution network disclosed herein can have a 35-phase average synchronous clock or a 41-phase average synchronous clock. The clock distribution described herein can be used in a square (equal rows and columns) node array, or in a rectangular node array with different numbers of rows and columns.

[0037] Figure 1 1 is a schematic block diagram of an example chip 100 according to aspects of the present disclosure. The chip 100 may be an integrated circuit die. The chip 100 may include a node array 102 (also referred to as a compute node array) with distributed timing, one or more serializer / deserializer (SerDes) clock blocks 104, a clock generator 106, and a clock controller 108. The SerDes clock block 104 may interface with other chips 100 forming an array of chips 100. In certain application examples, the node array 102 may be included on a chip 100 in a system on a wafer, on an array of chips 100 on a printed circuit board, etc. In certain applications, Figure 1The node array 102 may be implemented in a system on a wafer packaged in a wafer level packaging structure. Figure 1 As shown in the embodiment of FIG. 1 , the clock generator 106 can be implemented outside the node array 102. In some embodiments, the clock generator 106 can include a phase-locked loop (PLL). The clock generator 106 can be arranged to provide a clock signal to the computing nodes at the corners of the node array 102. The clock controller 108 can also be implemented outside the node array 102. The nodes within the node array 102 can include a node-to-node interface that can be configured for synchronous communication. The core to serializer / deserializer (SerDes) interface can be asynchronous.

[0038] exist Figure 1 In a node array 102 with distributed timing, each node can be an instance of a computing circuit (also referred to as a processing core or computing node). In some applications, most nodes can be implemented as instances of computing circuits, and one or more nodes can be implemented as instances of different circuits. Each node of the node array 102 can include an instance of substantially the same clock distribution circuit device, even if the other circuit devices of at least some nodes are different from the circuit devices of other nodes. In the node array 102, the nodes can be tiled and adjacent. For example, each node of the node array 102 can be independent and interconnected with (one or more) adjacent nodes. At the same time, the node array 102 can be implemented without using top-level wires or gates. Therefore, the nodes can be configured to communicate with adjacent nodes using lower-level wires through short connectors. In some embodiments, the nodes of the node array 102 can be stepped without mirroring or rotation. In some embodiments, the nodes can be connected to the power line (V DD / V SS ). For example, the height and width of each node can be a multiple of the power grid pitch. The power grid pitch can also be aligned with the bump pitch.

[0039] Each node of the node array 102 may include an instance of a substantially identical clock distribution circuit device. The node may be designed so that the output clock wire of the node is aligned with the input clock wire of its adjacent node. The node may be stepped and tiled in the node array so that the clock output wire is aligned and electrically connected to the clock input wire of the adjacent node arranged downstream to receive the clock signal. With such electrical connections, the node array can be implemented without channels or top-level wiring for clock distribution. In some embodiments, the fan-out of the clock distribution circuit device can be balanced for the inverter.

[0040] As described herein, a clock signal received at a root node may be propagated from the root node to two adjacent nodes by one delay unit. The root node may be located at a corner of the node array 102. The delay unit may be a fixed offset for a given node array. The delay unit may correspond to the delay from buffering the clock signal (e.g., using an inverter) and the wire delay associated with the clock signal propagating to its adjacent node(s).

[0041] One of the two adjacent nodes may be located in the same row as the root node, and the other of the two adjacent nodes may be located in the same column as the root node. The adjacent node is adjacent to the root node. As an example, the adjacent node is in Figure 2 In this example, the clock signal continues to propagate to the south and east of the root node in the node array with one more delay unit. This type of clock signal propagation continues through the clock distribution network in the node array 102 until the clock signal reaches the node located diagonally opposite the root node in the node array 102. In this example, a signal routed from the originating node that generates the signal to the neighboring node on the north or west side of the originating node can travel upstream and lose one delay unit in the node array 102, while a signal routed from the originating node to the neighboring node on the south or east side can travel downstream and gain one delay unit in the node array 102. Signals traveling upstream can be routed faster than signals traveling downstream to resolve the unit delay issue and meet setup and hold time specifications.

[0042] Figure 2 is with an example node array such as Figure 1 A node clock level diagram associated with a node array 102 of the array. The example node array 102 has 18 rows and 18 columns. For 18 rows and 18 columns, there can be 324 nodes. As another example, the node array 102 may include 360 ​​nodes arranged in rows and columns. The clock diagram includes the number of unit delays of the clock signal outputs of the nodes of the array. For example, the root node at the northwest corner has 1 unit delay. The two adjacent nodes receiving the clock signal from the root node have 2 unit delays. The nodes on the diagonal from the southwest side to the northeast side can have the same unit delay. Using the clock distribution circuit device described in this article, the unit delay can be a fixed offset. The nodes along these diagonals can receive clock signals with substantially the same timing delay. These diagonals can be referred to as phases or waves. The phases correspond to different clock signal arrival times in the nodes. Corresponding to Figure 2 The clock signal distribution of FIG. 3 may implement a 35-phase average synchronous phase clock. The number of phases of the average synchronous clock signal of the node array having the clock distribution circuit device described herein may be the number of rows plus the number of columns minus one.

[0043] In some embodiments, the clock signal may propagate in a wave that passes through the node array 102 in a row or column direction, rather than passing through the node array 102 in a wave formed along the diagonal of the node array. For example, each node may output a clock signal to the south side or to the east side, rather than outputting a clock signal to the south side and the east side. In this way, the clock signal may propagate in a wave that travels to the south side or the east side. However, aspects of the present disclosure are not limited to a specific direction of travel of the clock signal, and the clock signal may propagate along other diagonals and / or to the north side or to the west side.

[0044] When routing signals between nodes, you can consider Figure 2 A signal routed from the originating node generating the signal to a node on the north or west side can travel upstream and Figure 2 A signal routed from the starting node to a node on the south or east side can travel downstream and Figure 2 Signals traveling upstream can be routed faster than signals traveling downstream to resolve the unit delay problem and meet setup and hold time specifications.

[0045] In some embodiments, each node of the node array 102 can be an instance of a computing circuit. In some applications, most nodes include instances of computing circuits, and one or more remaining nodes include instances of different circuits, such as global nodes. A global node can refer to a node that does not include a circuit device for performing a processing task. In some embodiments, both computing nodes and global nodes can include a communication interface to enable communication with adjacent nodes. In some embodiments, the communication interface of a computing node can be the same as the communication interface of a global node.

[0046] Trajectory planning for reducing clock skew

[0047] Aspects of the present disclosure relate to trajectory planning (also referred to as routing planning) for signal communication between nodes that is “clock skew aware.” The trajectory planning described herein can improve upstream and downstream signal timing to reduce or eliminate skew resulting from the direction of signal travel relative to the direction of clock signal propagation.

[0048] Other aspects of the present disclosure provide techniques for limiting the width of metal tracks for heavily replicated functional designs with mesh clock distribution. Certain electronic design automation tools allow tracks to be limited by selecting the width, spacing and / or position of metal tracks under the guidance of a foundry design rule manual. Various aspects of the present disclosure also provide methods for limiting track planning of functional design units and assigning tracks to signals based on the direction of communication traffic. For example, a signal traveling with a clock signal (e.g., in the same direction) can be routed with a track of a smaller width, while a signal traveling against the clock signal (e.g., in the opposite direction) can be routed with a track of a larger width. Some or all of these signals can also be directionally staggered with each other (signal directions alternating) to reduce or minimize signal integrity issues (e.g., crosstalk). For example, in some applications, all signals can be directionally staggered.

[0049] Typically, the track along which the communication signal travels can have substantially the same width and spacing, regardless of the direction in which the signal travels. The width and spacing can be sized for the longest and / or shortest expected delay time. Such width and spacing can be designed to meet setup and hold time specifications. The use of tracks for staggered signals as described herein can also allow for higher frequency designs and reduce the area used by the track by minimizing the size of the wires (also referred to as tracks) used to meet the design goals. This can both reduce design-based and install more replica modules in the same physical area, thereby increasing the performance of each die.

[0050] Figure 3 1 illustrates a portion of a node array 102 including an example clock propagation direction according to aspects of the present disclosure. Figure 3 As shown, a portion of node array 102 includes a plurality of nodes 202. Nodes 202 are arranged in rows and columns. In some embodiments, a clock signal may propagate through node array 102 in both vertical and horizontal directions. Figure 3 As shown, the clock signal may propagate in a first direction 204 between nodes 202 from top to bottom, and the clock signal may propagate in a second direction 206 between nodes 202 from left to right. Figure 3 As shown, the clock signal can propagate in two orthogonal directions in the node array 102. Figure 2 As illustrated, the clock signal may propagate through the node array 102 with a delay.

[0051] Figure 4A and Figure 4B 1 illustrates example clock propagation directions and signal propagation directions of nodes 202 of array 102 according to aspects of the present disclosure. Specifically, Figure 4A The diagram illustrates horizontal conductors configured to allow communication signals to propagate in a horizontal direction. Figure 4B Illustrated are vertical conductors configured to allow communication signals to propagate in a vertical direction.

[0052] refer to Figure 4A , the node 202 includes a first horizontal conductor 402 configured to propagate communication signals between nodes from left to right in the second direction 206. The node 202 also includes a second horizontal conductor 404 configured to propagate communication signals between nodes from right to left in a direction opposite to the second direction 206. The arrows at the ends of the horizontal lines 402 and 404 in the figure are for illustration purposes only to show the signal propagation direction.

[0053] refer to Figure 4B , the node 202 also includes a first vertical conductor 406 configured to propagate communication signals between nodes from top to bottom in the first direction 204. The node 202 also includes a second vertical conductor 408 configured to propagate communication signals between nodes from bottom to top in a direction opposite to the first direction 204. The arrows at the ends of the vertical conductors 406 and 408 in the figure are for illustration purposes only to show the signal propagation direction.

[0054] In some embodiments, first horizontal conductive line 402 and second horizontal conductive line 404 may be formed in a different layer than first vertical conductive line 406 and second vertical conductive line 408. Vertical conductive lines 406 and 408 may extend 404 in first direction 204 orthogonal to second direction 206 in which horizontal conductive line 402 extends.

[0055] The communication signals between nodes 202 are designed to arrive at the destination node 202 (e.g., adjacent nodes are adjacent to the node 202 they leave) to meet the setup time and hold time specifications. As used herein, setup time generally refers to the minimum amount of time that the input of an electronic component remains stable before the clock edge to ensure that the component can correctly read its input. Hold time used herein generally refers to the minimum amount of time that the input of an electronic component remains stable after the clock edge to ensure that the component can correctly read its input. Setup time and hold time can be defined for any electrical component that reads an input signal at a timing defined by a clock signal, including, for example, flip-flops, registers, memories, processors, multiplexers, decoders, etc.

[0056] Because in Figure 4ACommunication signals propagating from left to right along the second direction 206 (e.g., via the first horizontal conductor 402) propagate in the second direction 206, these signals can have longer propagation delays and still meet the setup and hold times. The timing at which the communication signal will settle at the input of the node 202 to meet the setup and hold times of the node 202 depends on the time when the clock signal will arrive at the node 202. For example, since the communication signal traveling along the first horizontal conductor 402 propagates in the second direction 206, the communication signal propagating along the first horizontal conductor 402 can arrive at the adjacent node at an earlier time relative to the clock signal propagating along the second direction 206 to the adjacent node than the communication signal propagating along the second horizontal conductor 404 traveling in the opposite direction of the clock signal.

[0057] The communication signal propagating in the opposite direction to the clock signal (e.g., along the second horizontal conductor 404 or the second vertical conductor 408) can be designed to have a shorter propagation delay than the communication signal propagating in the same direction as the clock signal (e.g., along the first horizontal conductor 402 or the first vertical conductor 406). Therefore, the communication signal propagating in the same direction as the clock signal can be considered to have the benefit of the clock propagation time, while the communication signal propagating in the opposite direction to the clock signal can be considered to have the penalty of the clock propagation time.

[0058] In order to achieve longer propagation delays for communication signals propagating in the same direction as a clock signal and shorter propagation delays for communication signals propagating in an opposite direction to the clock signal, aspects of the present disclosure relate to techniques for tuning wire delays to meet setup time and hold time specifications in a node array 102 having an average synchronous clock.

[0059] The propagation delay along communication wire 402-408 can be related to the RC delay of wire 402-408. In certain embodiments, the length of wire 402-408 can be determined by the spacing of node 202, and the height of wire 402-408 can be determined by the process for forming wire (such as photolithography) and metal layer. Therefore, the width of wire 402-408 is a design parameter, and this design parameter can be used to adjust the propagation delay introduced by wire 402-408. In certain embodiments, the first horizontal wire 402 and the first vertical wire 406 for transmitting signals in the same direction as clock propagation can be formed to have a relatively small width, to increase propagation delay, and the second horizontal wire 404 and the second vertical wire 408 for transmitting signals in the direction opposite to clock propagation can be formed to have a relatively large width, to reduce propagation delay. The specific width of wire 402-408 can be formed to make the signal propagated on wire 402-408 meet the setup time and hold time of the electronic components in destination node 202. In one embodiment, the width of the conductors 402 - 408 may be selected such that the communication signals propagating on the conductors 402 - 408 arrive substantially midway between the setup time and the hold time, however, aspects of the present disclosure are not limited in this regard.

[0060] In some embodiments, nodes 202 may not have a square shape, and therefore, the time it takes for a signal to travel vertically through a given node 202 may be different than the time it takes for a signal to travel horizontally through the node 202. For example, in some embodiments, the length of a node 202 in the horizontal direction may be greater than the length in the vertical direction. In these embodiments, the width of the first horizontal conductor 402 may be greater than the width of the first vertical conductor 406, and the width of the second horizontal conductor 404 may be greater than the width of the second vertical conductor 408. However, when the amount of delay introduced by the difference in the relative lengths of the horizontal and vertical lengths of a node is negligible, the conductors (whether horizontal or vertical) traveling in the same direction relative to the clock signal may be substantially identical.

[0061] Figure 5A and Figure 5B FIG. 1 illustrates a plurality of example wires having signal propagation directions of a node 202 of a node array 102 according to aspects of the present disclosure. Figure 5A , each node 202 can be connected to its horizontally adjacent nodes 202 via a plurality of horizontal communication conductors 402 and 404. Figure 5B As shown, each node 202 may be connected to its vertically adjacent nodes 202 via a plurality of vertical communication conductors 406 and 408 .

[0062] The proximity of adjacent communication wires 402-408 may cause crosstalk between the wires 402-408. For example, when two signals propagate in the same direction, induced currents between the wires 402-408 may cause crosstalk along the length of the wires 402-408. One technique to reduce this source of crosstalk is to place the communication wires 402-408 farther apart. However, increasing the spacing between the communication wires 402-408 may reduce the amount of bandwidth available for communication between nodes 202. Therefore, if Figure 5A and Figure 5B As shown, aspects of the present disclosure relate to staggering communication conductors 402-408 based on the direction in which signals propagate on the conductors. For example, each conductor in the first horizontal conductor 402 is adjacent to one or more conductors in the second horizontal conductor 404, and vice versa, so that the signals on any two adjacent conductors 402 and 404 propagate in opposite directions. Similarly, each conductor in the first vertical conductor 406 is adjacent to one or more conductors in the second vertical conductor 408, and vice versa, so that the signals on any two adjacent conductors 406 and 408 propagate in opposite directions. In certain applications, by staggering horizontal conductors 402, 404 and / or vertical conductors 406, 408 based on the direction of the signals propagating thereon, crosstalk between adjacent conductors 402, 404 and / or 406, 408 can be limited to a single position along the propagation path (e.g., a point where opposite signals meet when traveling between nodes 202).

[0063] Depending on the implementation, thousands of wires 402-408 may be used for a block of a trace planning design. These communication wires 402-408 may connect adjacent nodes 202 in a tiled and stepped node array 102. In some embodiments, the communication wires 402-408 may connect nodes 202 in a lower level of metal.

[0064] In some embodiments, the trajectory plan for the communication conductors 402-408 can be generated in an automatic manner by re-defining the designed trajectory plan and assigning those trajectories (e.g., trajectories 402-408) based on the directionality of the signals communicated on the conductors. Compared to other trajectory plans, the trajectory plan designed according to aspects of the present disclosure can achieve a higher number of conductors 402-408 per given node 202 length, which can translate into a higher bandwidth design. In addition, the trajectory plan can also address the unique clock skew associated with the average synchronous timing of the node array by adjusting the delay introduced by the communication conductors 402-408. In addition, the use of appropriately sized wiring can also allow the use of higher frequency designs, which can provide lower latency and / or higher performance.

[0065] In addition, other attempts to address signal delays and / or crosstalk may involve designing wire size and / or spacing for worst-case scenarios. This will result in wire widths that are wider than required to meet setup and hold time specifications, and wire density that is lower than that achievable according to aspects of the present disclosure. Compared to such designs, aspects of the present disclosure may provide higher bandwidth (e.g., by using a greater number of communication wires in the same area) and lower latency signals (e.g., via directional staggered wires to reduce crosstalk).

[0066] In some embodiments, the clock distribution network can be configured to propagate the clock signal in the row or column direction so that the clock signal does not travel along Figure 2 The diagonal lines are shown passing through node array 102. In these embodiments, the trace plan can include conductors having different widths when the conductors extend in the same or opposite directions as the clock signal, and conductors having substantially the same width when the conductors extend in a direction perpendicular to the propagation direction of the clock signal.

[0067] in conclusion

[0068] The foregoing disclosure is not intended to limit the disclosure to the precise form disclosed or to the specific field of use. Therefore, it is contemplated that various alternative embodiments and / or modifications to the disclosure (whether explicitly described or implied herein) are possible in light of the present disclosure. Having thus described the embodiments of the present disclosure, one of ordinary skill in the art will recognize that changes may be made in form and detail without departing from the scope of the present disclosure. Therefore, the present disclosure is limited only by the claims.

[0069] In the foregoing description, the present disclosure has been described with reference to specific embodiments. However, as will be appreciated by those skilled in the art, the various embodiments disclosed herein may be modified or implemented in various other ways without departing from the spirit and scope of the present disclosure. Therefore, the description is considered to be illustrative and is intended to teach those skilled in the art to make and use the various embodiments of the disclosed vent assembly. It should be understood that the disclosed forms shown and described herein will be considered as representative embodiments. Equivalent elements, materials, processes or steps may replace those representedly illustrated and described herein. In addition, certain features of the present disclosure may be utilized independently of the use of other features, all of which are obvious to those skilled in the art who benefit from the description of the present disclosure. Expressions such as "including", "comprising", "incorporating", "consisting of", "having", "is" used to describe and claim the present disclosure are intended to be interpreted in a non-exclusive manner, i.e., allowing items, components or elements not explicitly described to also exist. References to the singular should also be interpreted as involving the plural.

[0070] In addition, various embodiments disclosed herein are used for illustration and explanation purposes and shall not be construed as limitations to the present disclosure.All joint references (such as attachment, pasting, coupling, connection, etc.) are only used to help readers understand the present disclosure, and will not create limitations, particularly about the position, orientation or use of the system and / or method disclosed herein. Therefore, if any, joint references should be interpreted broadly. In addition, this type of joint reference does not necessarily mean that two elements are directly connected to each other. In addition, all numerical terms, such as but not limited to "first (first)", "second (second)", "third (third)", "primary (primary)", "secondary (secondary)", "main (main)" or any other common and / or numerical terms, should also be regarded as identifiers only, to help readers understand the various elements, embodiments, variations and / or modifications of the present disclosure, and any limitations can not be created, particularly about relative to or exceeding the order or preference of any element, embodiment, variation and / or modification of another element, embodiment, variation and / or modification.

[0071] It should also be understood that one or more of the elements shown in the drawings / figures may also be implemented in a more separate or integrated manner, or even removed or rendered inoperable in some cases, as may be useful depending on the particular application.

Claims

1. A node array having trajectory planning for improving clock skew, the node array comprising: a first node, the first node comprising computing circuitry and a plurality of conductors configured to transmit communication signals generated by the first node to adjacent nodes of the node array; a second node, the second node being one of the neighboring nodes; as well as a third node, the third node being one of the neighboring nodes, wherein a clock signal propagates in a first direction from the second node to the first node to the third node; as well as The plurality of wires of the first node include: a first conductor configured to transmit a first communication signal to the second node in a direction opposite to the first direction, and a second conductor configured to transmit a second communication signal to the third node in the first direction, The width of the first conductive line is greater than the width of the second conductive line. 2 . The node array of claim 1 , wherein the width of the first conductive line and the width of the second conductive line help meet setup time and hold time of electronic components in the second node and the third node.

3. The node array of claim 1, wherein the plurality of conductors further comprises: a plurality of first conductors extending in the first direction and including the first conductors, the plurality of first conductors being configured to transmit a plurality of first communication signals to the second node in the direction opposite to the first direction, and a plurality of second conductors extending in the first direction and including the second conductors, the plurality of second conductors being configured to transmit a plurality of second communication signals to the third node in the first direction, The plurality of first conductive lines are interlaced with the plurality of second conductive lines.

4. The node array according to claim 1, wherein the node array further comprises: a fourth node, the fourth node being one of the adjacent nodes; as well as a fifth node, the fifth node being one of the neighboring nodes, wherein the clock signal propagates from the fourth node to the first node to the fifth node in a second direction perpendicular to the first direction, The plurality of wires of the first node further include: a third wire extending in the second direction and configured to transmit a third communication signal to the fourth node in a direction opposite to the second direction; as well as a fourth wire extending in the second direction and configured to transmit a fourth communication signal to the fifth node in the second direction, The width of the third conductive line is greater than the width of the fourth conductive line.

5. The node array according to claim 4, wherein: The length of each of the first node, the second node, the third node, the fourth node and the fifth node in the first direction is greater than the length in the second direction, The width of the first conductive line is greater than the width of the third conductive line, and The width of the second conductive line is greater than the width of the fourth conductive line.

6. The node array of claim 4, wherein the plurality of conductors further comprises: a plurality of third wires extending in the second direction and including the third wires, the plurality of third wires being configured to transmit a plurality of third communication signals to the fourth node in the direction opposite to the second direction, and a plurality of fourth conductors extending in the second direction and including the fourth conductor, the plurality of fourth conductors being configured to transmit a plurality of fourth communication signals to the fifth node in the second direction, The plurality of third conductive lines are interlaced with the plurality of fourth conductive lines.

7. The node array of claim 1, wherein the clock signal has a substantially fixed delay when propagating between adjacent nodes.

8. The node array of claim 1, wherein a node of the node array is configured to operate with a timing offset compared to other nodes based on a timing at which the node receives the clock signal.

9. A node of a node array having a trajectory plan for improving clock skew in the node array, the node comprising: computing circuitry configured to generate a communication signal; as well as a plurality of conductors configured to enable the communication signal to propagate to adjacent nodes of the node array, wherein the nodes of the node array are configured to receive a distributed clock signal, the distributed clock signal propagating in at least a first direction between the adjacent nodes, wherein the plurality of conductors comprises: a first conductor configured to transmit a first communication signal in a direction opposite to the first direction, and a second conductor configured to transmit a second communication signal in the first direction, The width of the first conductive line is greater than the width of the second conductive line.

10. The node of claim 9, wherein the width of the first conductive line and the width of the second conductive line facilitate meeting setup time and hold time of electronic components in respective destination nodes of the first communication signal and the second communication signal.

11. The node of claim 9, wherein the plurality of conductors further comprises: a plurality of first conductors extending in the first direction and including the first conductors, the plurality of first conductors being configured to transmit a plurality of first communication signals in the direction opposite to the first direction, and a plurality of second conductors extending in the first direction and including the second conductors, the plurality of second conductors being configured to transmit a plurality of second communication signals in the first direction, The plurality of first conductive lines are interlaced with the plurality of second conductive lines.

12. The node according to claim 9, wherein: The clock signal also propagates between the adjacent nodes in a second direction, the second direction being perpendicular to the first direction, and The plurality of conductors further comprises: a third conductive line extending in the second direction and configured to transmit a third communication signal in a direction opposite to the second direction; and a fourth wire extending in the second direction and configured to transmit a fourth communication signal in the second direction, The width of the third conductive line is greater than the width of the fourth conductive line.

13. A node according to claim 12, wherein: The length of the node in the first direction is greater than the length in the second direction, The width of the first conductive line is greater than the width of the third conductive line, and The width of the second conductive line is greater than the width of the fourth conductive line.

14. The node of claim 12, wherein the plurality of conductors further comprises: a plurality of third conductors extending in the second direction and including the third conductors, the plurality of third conductors being configured to transmit a plurality of third communication signals in the direction opposite to the second direction, and a plurality of fourth conductors extending in the second direction and including the fourth conductor, the plurality of fourth conductors being configured to transmit a plurality of fourth communication signals in the second direction, The plurality of third conductive lines are interlaced with the plurality of fourth conductive lines.

15. The node of claim 9, wherein the clock signal is further configured to be distributed with a substantially fixed delay when propagating between adjacent nodes.

16. The node of claim 9, wherein the node is configured to operate with a timing offset compared to other nodes of the node array based on a timing at which the node receives the clock signal.

17. A method for manufacturing a node array, the method comprising: forming a first node, the first node comprising computing circuitry and a plurality of conductors configured to transmit communication signals generated by the first node to adjacent nodes of the node array; forming a second node, the second node being one of the adjacent nodes; as well as forming a third node, the third node being one of the adjacent nodes, wherein a clock signal propagates in a first direction from the second node to the first node to the third node, and The plurality of wires of the first node include: a first conductor configured to transmit a first communication signal to the second node in a direction opposite to the first direction, and a second conductor configured to transmit a second communication signal in the first direction, The width of the first conductive line is greater than the width of the second conductive line.

18. The method of claim 17, wherein: The width of the first conductive line and the width of the second conductive line are selected to meet setup time and hold time of electronic components in the second node and the third node.

19. The method of claim 17, wherein the plurality of conductors further comprises: a plurality of first conductors extending in the first direction and including the first conductors, the plurality of first conductors being configured to transmit a plurality of first communication signals to the second node in the direction opposite to the first direction, and a plurality of second conductors extending in the first direction and including the second conductors, the plurality of second conductors being configured to transmit a plurality of second communication signals to the third node in the first direction, The plurality of first conductive lines are interlaced with the plurality of second conductive lines.

20. The method of claim 17, wherein the node array further comprises: a fourth node, the fourth node being one of the adjacent nodes; as well as a fifth node, the fifth node being one of the neighboring nodes, wherein the clock signal propagates from the fourth node to the first node to the fifth node in a second direction perpendicular to the first direction, The plurality of conductors of the first node further include: a third wire extending in the second direction and configured to transmit a third communication signal to the fourth node in a direction opposite to the second direction; as well as a fourth wire extending in the second direction and configured to transmit a fourth communication signal to the fifth node in the second direction, The width of the third conductive line is greater than the width of the fourth conductive line.

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