Clock phase error calibration device and method

Abstract

The invention provides a clock phase error calibration device and method. The clock phase error calibration device comprises a delay chain, a clock data recovery circuit, a phase error detection circuit and a calibration logic circuit, the delay chain is used for outputting a plurality of delay clock signals with different phases under the control of a control code value; the clock data recovery circuit sequentially selects two delay clock signals of which the expected phase error is a set error value from a plurality of delay clock signals; the phase error detection circuit is used for detecting a detection phase error between the two delay clock signals selected by the clock data recovery circuit; and the calibration logic circuit is used for outputting a control code value for controlling the delay chain to adjust the delay of the delay clock signal according to the direct current voltage point corresponding to the detection phase error, so that the real phase error between the delay clock signal and two of the delay clock signals approaches to the set error value.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a clock phase error calibration method and method. Background Art

[0002] With the continuous upgrading of integrated circuit technology, the operating speed and throughput of chips are constantly improving, and the requirements for clock quality are also increasing. Among them, phase error is an important indicator of high-speed clocks; for high-speed serdes interfaces, the clock quality of the clock data recovery device directly determines the performance of the serdes. For clock data recovery circuits, the phase error of multi-phase input clocks directly affects the linearity performance of the clock data recovery circuit.

[0003] However, the high-speed clock sent from the PLL may cause the clock phase error to deteriorate due to process mismatch, long-distance transmission, circuit design mismatch, etc. Therefore, designing a multi-phase clock phase error calibration circuit is an inevitable choice. Summary of the invention

[0004] The purpose of the present application is to provide a clock phase error calibration method and apparatus, aiming to solve the problem in the related art that digital clock calibration cannot achieve high-speed and high-precision clock calibration, and analog digital clock calibration is easily affected by the mismatch of the detection circuit itself.

[0005] According to a first aspect of the present application, there is provided a clock phase error calibration device, comprising: a delay chain, a clock data recovery circuit, a phase error detection circuit and a calibration logic circuit;

[0006] The delay chain is used to output a plurality of delayed clock signals with different phases under the control of the control code value, and the expected phase error between any one of the plurality of delayed clock signals and two of the plurality of delayed clock signals is a set error value;

[0007] The clock data recovery circuit sequentially selects two delayed clock signals whose expected phase errors are set error values ​​from a plurality of delayed clock signals;

[0008] The phase error detection circuit is used to detect the detection phase error between the two delayed clock signals selected by the clock data recovery circuit;

[0009] The calibration logic circuit is used to control the delay chain to adjust the control code value of the delay of the delayed clock signal according to the DC voltage point output corresponding to the detected phase error, so that the actual phase error between the delayed clock signal and two of the delayed clock signals approaches the set error value.

[0010] In an optional implementation, the clock data recovery circuit includes: a first signal selector and a second signal selector;

[0011] The first signal selector receives half of the delayed clock signals from the delay chain and selects one delayed clock signal therefrom; the expected phase error between two of the delayed clock signals received by the first signal selector is an even multiple of the set error value;

[0012] The second signal selector receives the other half of the delayed clock signals from the delay chain and selects one delayed clock signal therefrom; the expected phase error between the two delayed clock signals received by the second signal selector is also an even multiple of the set error value;

[0013] The delayed clock signals selected by the first signal selector and the second signal selector each time constitute a clock signal combination to be detected, and the first signal selector and the second signal selector cyclically select a plurality of different clock signal combinations to be detected.

[0014] In an optional implementation, the phase error detection circuit includes: an XOR logic circuit;

[0015] The XOR logic circuit receives the two delayed clock signals selected by the clock data recovery circuit, and detects a detection phase error between the two delayed clock signals selected by the clock data recovery circuit through an XOR logic operation.

[0016] In an optional implementation, the calibration logic circuit includes: a comparator, a digital-to-analog converter, and a calibration algorithm circuit;

[0017] The comparator receives a first voltage signal corresponding to the detected phase error output by the phase error detection circuit and a second voltage signal output by the digital-to-analog converter, and outputs an adjustment signal for adjusting the second voltage signal by comparing the first voltage signal with the second voltage signal;

[0018] The calibration algorithm circuit outputs the adjustment signal to the digital-to-analog converter, and updates the DC voltage point corresponding to the second voltage signal according to the adjustment signal;

[0019] The digital-to-analog converter outputs the adjusted second voltage signal to the comparator according to the adjustment signal, so that the adjusted second voltage signal is closer to the first voltage signal than before the adjustment;

[0020] After the adjusted second voltage signal meets the set conditions, the calibration algorithm circuit determines the updated DC voltage point as the DC voltage point for detecting the phase error, and outputs the control code value corresponding to the detected phase error according to the DC voltage point corresponding to the detected phase error.

[0021] In an optional embodiment, the calibration algorithm circuit predetermines the DC voltage point corresponding to the detected phase error of each of the clock signal combinations to be detected, and determines the DC total voltage point corresponding to the total phase error of all the clock signal combinations to be detected based on the DC voltage point corresponding to each of the clock signal combinations to be detected;

[0022] During the clock calibration process, the calibration algorithm circuit determines the current DC voltage point for the clock signal combination to be detected currently output by the clock data recovery circuit, and compares the current DC voltage point with the total DC voltage point, and adjusts the control code value of the delayed clock signal with a larger phase among the two delayed clock signals currently selected by the clock data recovery circuit according to the comparison result.

[0023] In an optional implementation, the control code value is determined based on a difference between a DC average voltage point and a current DC voltage point; the DC average voltage point is determined based on the total DC voltage point and the total number of types of the clock signal combinations to be detected;

[0024] Under the control of the control code value, the delay chain adjusts the delay of the delayed clock signal with a larger phase among the two delayed clock signals currently selected by the clock data recovery circuit, and the adjusted delay length is related to the difference.

[0025] According to a second aspect of the present application, a clock phase error calibration method is provided, comprising:

[0026] The delay chain outputs a plurality of delayed clock signals with different phases under the control of the control code value, and the expected phase error between any one of the plurality of delayed clock signals and two of the plurality of delayed clock signals is a set error value;

[0027] The clock data recovery circuit receives the multiple delayed clock signals, and sequentially selects two delayed clock signals whose expected phase errors are set error values ​​from the multiple delayed clock signals;

[0028] The phase error detection circuit receives and detects a detection phase error between two delayed clock signals selected by the clock data recovery circuit;

[0029] The calibration logic circuit controls the delay chain to adjust the control code value of the delay of the delayed clock signal according to the DC voltage point output corresponding to the detected phase error, so that the actual phase error between the delayed clock signal and two of the delayed clock signals approaches the set error value.

[0030] In an optional implementation, the clock data recovery circuit receives the multiple delayed clock signals, and sequentially selects two delayed clock signals whose expected phase errors are set error values ​​from the multiple delayed clock signals, including:

[0031] The clock data recovery circuit receives half of the delayed clock signals from the delay chain by using a first signal selector, selects one delayed clock signal from the delayed clock signal and outputs it to the phase error detection circuit; the expected phase error between the two delayed clock signals received by the first signal selector is an even multiple of the set error value;

[0032] The clock data recovery circuit also uses a second signal selector to receive the other half of the delayed clock signals from the delay chain, and selects one delayed clock signal from them and outputs it to the phase error detection circuit; the expected phase error between the delayed clock signals received by the second signal selector is also an even multiple of the set error value; wherein the delayed clock signals selected by the first signal selector and the second signal selector each time constitute a clock signal combination to be detected, and the first signal selector and the second signal selector select multiple different clock signal combinations to be detected in turn in a cyclic manner.

[0033] In an optional implementation, the phase error detection circuit receives and detects a detection phase error between two delayed clock signals selected by the clock data recovery circuit, including:

[0034] The phase error detection circuit receives the two delayed clock signals selected by the clock data recovery circuit using an exclusive OR logic circuit, and detects the detection phase error between the two delayed clock signals selected by the clock data recovery circuit through an exclusive OR logic operation.

[0035] In an optional implementation, the calibration logic circuit outputs a control code value for controlling the delay chain to adjust the delay of the delayed clock signal according to the DC voltage point corresponding to the detected phase error, including:

[0036] The calibration logic circuit receives the first voltage signal corresponding to the detected phase error output by the phase error detection circuit by using a comparator, compares the first voltage signal with the second voltage signal output by the digital-to-analog converter, and outputs an adjustment signal for adjusting the second voltage signal according to the comparison result;

[0037] The calibration logic circuit outputs the adjustment signal to the digital-to-analog converter using a calibration algorithm circuit, and updates a DC voltage point corresponding to the second voltage signal according to the adjustment signal;

[0038] The digital-to-analog converter outputs the adjusted second voltage signal to the comparator according to the adjustment signal, so that the adjusted second voltage signal is closer to the first voltage signal than before the adjustment;

[0039] After the adjusted second voltage signal meets the set conditions, the calibration algorithm circuit determines the updated DC voltage point as the DC voltage point for detecting the phase error, and outputs the control code value of the delayed clock signal with a larger phase among the two delayed clock signals selected by the clock data recovery circuit corresponding to the detected phase error according to the DC voltage point corresponding to the detected phase error.

[0040] In an optional embodiment, the method further comprises:

[0041] The calibration algorithm circuit predetermines the DC voltage point corresponding to the detected phase error of each of the clock signal combinations to be detected, and determines the DC total voltage point corresponding to the total phase error of all the clock signal combinations to be detected based on the DC voltage point corresponding to each of the clock signal combinations to be detected;

[0042] Outputting the control code value of the delayed clock signal with a larger phase among the two delayed clock signals selected by the clock data recovery circuit corresponding to the detected phase error according to the DC voltage point of the detected phase error comprises:

[0043] The DC voltage point is compared with the DC total voltage point, and the control code value of the delayed clock signal with a larger phase among the two delayed clock signals currently selected by the clock data recovery circuit is adjusted according to the comparison result.

[0044] In an optional implementation, the control code value is determined based on a difference between a DC average voltage point and a current DC voltage point; the DC average voltage point is determined based on the total DC voltage point and the total number of types of the clock signal combinations to be detected;

[0045] The delay chain outputs a plurality of delayed clock signals with different phases under the control of the control code value, including:

[0046] Under the control of the control code value, the delay chain adjusts the delay of the delayed clock signal with a larger phase among the two delayed clock signals currently selected by the clock data recovery circuit, and the adjusted delay length is related to the difference.

[0047] Compared with the related art, the technical solution of this application has the following advantages:

[0048] The clock phase error calibration device proposed in the present application has high calibration speed and calibration accuracy, and is not affected by the errors of the calibration logic circuit and the phase error detection circuit. The error between the multi-phase clock signals finally adjusted is small, thereby being able to generate a high-quality data sampling clock clk_pmix.

[0049] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0051] Figure 1 is a structural diagram of a clock phase error calibration device according to an exemplary embodiment of the present application.

[0052] Figure 2 is a timing logic diagram of clock phase error detection according to an exemplary embodiment of the present application.

[0053] Figure 3 It is a schematic diagram of the calibration logic and the corresponding relationship with the DC voltage points according to the exemplary embodiment of the present application.

[0054] Figure 4 It is a flowchart of a clock phase error calibration method according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0056] In the related art, the clock phase error calibration methods mainly include: digital clock calibration and analog clock calibration. Due to the constraints of the delay unit, digital clock calibration often cannot achieve high-speed and high-precision clock calibration. There are many analog clock phase error calibration methods, the main difference lies in the difference in the multi-phase clock phase error detection method, which can often achieve high-speed and high-precision calibration, but the calibration result is easily affected by the mismatch of the detection circuit itself.

[0057] Based on the above analysis, this application uses high-speed serdes (serializer and deserializer) interface IP to design a high-speed multi-phase clock phase error calibration device based on clock data recovery circuit, delay line, phase error detection circuit and calibration logic circuit. The device has the characteristics of high speed, high precision and is not affected by the error of the error detection circuit.

[0058] In the related art, the idea of ​​clock phase error calibration is: detect the DC voltage of the clock phase error, judge the size of the DC operating point, and feedback to adjust the strength of the rising or falling edge of the clock drive, so as to achieve clock delay control. Such clock phase error calibration is easily affected by the DC operating point deviation. The present application determines the DC operating point of the clock through multiple detections and compares it with the single detection result, thereby eliminating the errors caused by the detection circuit and calibration logic itself.

[0059] like Figure 1 As shown, the present application exemplarily provides a clock phase error calibration device, the device comprising: a delay chain, a clock data recovery circuit, a phase error detection circuit and a calibration logic circuit;

[0060] The delay chain is used to output a plurality of delayed clock signals with different phases under the control of the control code value, and the expected phase error between any one of the plurality of delayed clock signals and two of the plurality of delayed clock signals is a set error value;

[0061] The clock data recovery circuit sequentially selects two delayed clock signals whose expected phase errors are set error values ​​from a plurality of delayed clock signals;

[0062] The phase error detection circuit is used to detect the detection phase error between the two delayed clock signals selected by the clock data recovery circuit;

[0063] The calibration logic circuit is used to control the delay chain to adjust the control code value of the delay of the delayed clock signal according to the DC voltage point output corresponding to the detected phase error, so that the actual phase error between the delayed clock signal and two of the delayed clock signals approaches the set error value.

[0064] Exemplarily, the delay line is a clock driving circuit based on a single-ended clock with adjustable delay, which is used to achieve fine adjustment of the high-speed clock; the clock data recovery circuit can be a key circuit in high-speed serdes applications, which is used to output a high-speed clock after the delay of the delay line is adjusted, and provide a data sampling clock for the next stage; the phase error detection circuit is used to sequentially detect the detection phase error xor between multiple delayed clock signals with different phases <n>, where n represents the number of multiple delayed clock signals, and is also the number of combinations of two delayed clock signals whose expected phase error is the set error value. For the convenience of description, the combination of two delayed clock signals whose expected phase error is the set error value is referred to as the clock signal combination to be detected in the following text; the calibration logic circuit converts the corresponding DC voltage point code according to the detected phase error detected by the phase error detection circuit <n>; Calibrate the logic circuit according to the DC voltage point code <n>A delay instruction is issued to the delay circuits of the delayed clock signals with different phases, wherein the delay chain includes a plurality of delay circuits, and each delay circuit corresponds to a delayed clock signal.

[0065] For example, Figure 1 As shown, there are 8 delayed clock signals, namely clk0°, clk45° (the expected phase error with clk0° is 45 degrees), clk90° (the expected phase error with clk45° is 45 degrees), clk135° (the expected phase error with clk90° is 45 degrees), clk180° (the expected phase error with clk135° is 45 degrees), clk225° (the expected phase error with clk180° is 45 degrees), clk270° (the expected phase error with clk225° is 45 degrees), clk315° (the expected phase error with clk270° is 45 degrees, and the expected phase error with clk0° is also 45 degrees). The phases of the above 8 delayed clock signals are different, and the expected phase error between any one of them and the other two is 45 degrees, that is, Figure 1 In the illustrated embodiment, the error value is set to 45 degrees. It is understandable that the error value is not limited to 45 degrees and can be set according to actual needs. Figure 1 In the embodiment shown, clk0° can form a clock signal combination to be detected with clk45°, and the expected phase error is a set error value. clk45° can form a clock signal combination to be detected with clk90°, and so on. clk315° can form a clock signal combination to be detected with clk0°, and the expected phase error is the set error value. There are a total of 8 clock signal combinations to be detected with the expected phase error being the set error value, which is the same as the number of delayed clock signals.

[0066] It can be understood that, taking into account the process deviation of the phase error detection circuit itself, the detected phase error of the clock signal combination to be detected may not be the actual phase error of the two delayed clock signals. The actual phase error is recorded as Δphase<7:0>, and the error caused by the process deviation of the phase error detection circuit itself is recorded as Δoffset1. Then the detected phase error xor<7:0>=Δphase<7:0>+Δoffsetl.

[0067] Exemplarily, when the calibration logic circuit adjusts the control code value of the delay of the delayed clock signal according to the detected phase error output, the above Δoffset1 will be considered, and finally the actual phase error of the two delayed clock signals in each clock signal combination to be detected is adjusted as close to the set error value as possible, until the difference between the actual phase error and the set error value is within the set threshold range, and the set threshold range can be a smaller range centered on 0 degrees. The clock data recovery circuit can output the two delayed clock signals whose actual phase errors after calibration are close to the set error value to the phase interpolator PI, so as to output the data sampling clock signal clk_pmix whose phase can be precisely controlled.

[0068] In some optional embodiments, the clock data recovery circuit includes: a first signal selector and a second signal selector;

[0069] The first signal selector receives half of the delayed clock signals from the delay chain and selects one delayed clock signal therefrom; the expected phase error between two of the delayed clock signals received by the first signal selector is an even multiple of the set error value;

[0070] The second signal selector receives the other half of the delayed clock signals from the delay chain and selects one delayed clock signal therefrom; the expected phase error between the two delayed clock signals received by the second signal selector is also an even multiple of the set error value;

[0071] The delayed clock signals selected by the first signal selector and the second signal selector each time constitute a clock signal combination to be detected, and the first signal selector and the second signal selector cyclically select a plurality of different clock signal combinations to be detected.

[0072] For example, Figure 1 As shown, the selection signal sel<7:0> can be set so that the first signal selector and the second signal selector synchronously output two delayed clock signals at a time, and the two delayed clock signals synchronously output each time form a clock signal combination to be detected. The first signal selector and the second signal selector can sequentially select and output two delayed clock signals in various clock signal combinations to be detected. For example, the first signal selector receives clk0°, clk90°, clk180°, clk270° from the delay chain and selects to output them in a set order, and the second signal selector receives clk45°, Clk135°, clk225°, clk315° from the delay chain and outputs them in a set order, so that each time the delayed clock signal selected and output by the first signal selector and the second signal selector constitutes a clock signal combination to be detected. After 8 selections and outputs, 8 clock signal combinations to be detected can be obtained. Of course, it can be understood that the selection and output process is executed cyclically, that is, it is cycled every 8 times, and each time one of the clock signal combinations to be detected is selected and output.

[0073] In some optional embodiments, the phase error detection circuit includes: an XOR logic circuit;

[0074] The XOR logic circuit receives the two delayed clock signals selected by the clock data recovery circuit, and detects a detection phase error between the two delayed clock signals selected by the clock data recovery circuit through an XOR logic operation.

[0075] Exemplarily, after the phase error detection circuit receives two delayed clock signals that can form a clock signal combination to be detected from the first signal selector and the second signal selector, it uses an XOR logic circuit to detect the phase error. For the convenience of description, the detected phase error can be referred to as a detected phase error. Figure 1 In the embodiment shown, after 8 times, the detection phase errors xor<7:0> of the two delayed clock signals in the 8 clock signal combinations to be detected can be detected in turn. As described above, due to the process deviation of the detection circuit itself, there will be a certain detection error of Δoffset1, and the same error Δoffset1 will be introduced in each error detection.

[0076] In some optional embodiments, the calibration logic circuit includes: a comparator, a digital-to-analog converter, and a calibration algorithm circuit;

[0077] The comparator receives a first voltage signal corresponding to the detected phase error output by the phase error detection circuit and a second voltage signal output by the digital-to-analog converter, and outputs an adjustment signal for adjusting the second voltage signal by comparing the first voltage signal with the second voltage signal;

[0078] The calibration algorithm circuit outputs the adjustment signal to the digital-to-analog converter, and updates the DC voltage point corresponding to the second voltage signal according to the adjustment signal;

[0079] The digital-to-analog converter outputs the adjusted second voltage signal to the comparator according to the adjustment signal, so that the adjusted second voltage signal is closer to the first voltage signal than before the adjustment;

[0080] After the adjusted second voltage signal meets the set conditions, the calibration algorithm circuit determines the updated DC voltage point as the DC voltage point for detecting the phase error, and outputs the control code value of the delayed clock signal with a larger phase among the two delayed clock signals selected by the clock data recovery circuit corresponding to the detected phase error according to the DC voltage point corresponding to the detected phase error.

[0081] Exemplarily, the positive end of the comparator is connected to the output of the phase error detection circuit, and the phase error detection circuit converts the detected phase error of the clock signal combination to be detected into a first voltage signal and outputs it. Therefore, the positive end of the comparator receives the first voltage signal corresponding to the detected phase error, and the negative end of the comparator receives the second voltage signal output by the digital-to-analog converter. The comparator outputs an adjustment signal by comparing the first voltage signal and the second voltage signal. The adjustment signal is a digital signal and can be 0 or 1, which is used to indicate that the first voltage signal is greater than the second voltage signal, or the first voltage signal is less than the second voltage signal, respectively.

[0082] The calibration algorithm circuit can output an adjustment signal to the digital-to-analog converter, and the digital-to-analog converter can adjust the second voltage signal output to the comparator according to the adjustment signal. For example, if the adjustment signal indicates that the first voltage signal is greater than the second voltage signal, the second voltage signal is adjusted higher. If the adjustment signal indicates that the first voltage signal is less than the second voltage signal, the second voltage is adjusted lower. The comparator re-compares the first voltage signal and adjusts the second voltage signal, thereby outputting a new adjustment signal. After multiple adjustments in the above process, the adjustment signal will flip (that is, the adjustment signal changes from 0 to 1, or from 1 to 0), which means that the first voltage signal and the second voltage signal are almost equal. At this time, it can be considered that the second voltage signal meets the set conditions and the second voltage signal has been adjusted.

[0083] For example, the DC voltage point can be understood as a digital signal representing the voltage magnitude, so the DC voltage point for detecting the phase error can be understood as a digital signal of the magnitude of the first voltage signal corresponding to the detected phase error. The calibration algorithm circuit will initially set an initial DC voltage point corresponding to the initial second voltage signal, such as Figure 1 The code <7:0> shown in the figure, and the calibration algorithm circuit will adjust the DC voltage point once each time it receives an adjustment signal, and the digital-to-analog conversion circuit will also increase the second voltage signal accordingly each time it receives an adjustment signal. The adjustment size of the DC voltage point can correspond to the adjustment size of the second voltage signal. For example, if the DC voltage point increases by one number, the second voltage signal is increased by a set value, and if the DC voltage point decreases by one number, the second voltage signal is reduced by a set value. After the second voltage signal meets the set conditions, the final DC voltage point can be used as a DC voltage point corresponding to the detection phase error of the clock signal combination to be detected, so that the control code value of the control delay chain can be output according to the final DC voltage point. In other words, after the second voltage signal meets the set conditions, the final DC voltage point is the DC voltage point corresponding to the second voltage signal, and at this time the second voltage signal is adjusted to be equal to or almost equal to the first voltage signal, so the DC voltage point is also the DC voltage point of the first voltage signal corresponding to the detection phase error. Furthermore, the delay chain can adjust the delay of the delayed clock signal with a larger phase in the clock signal combination to be detected corresponding to the detection phase error xor<7:0> according to the DC voltage point of the first voltage signal corresponding to the detection phase error, so that the actual phase error Δphase<7:0> of the clock signal combination to be detected output to the clock data recovery circuit next time is the set error value, such as 45 degrees.

[0084] In some optional embodiments, the calibration algorithm circuit predetermines the DC voltage point corresponding to the detected phase error of each of the clock signal combinations to be detected, and determines the DC total voltage point corresponding to the total phase error of all the clock signal combinations to be detected based on the DC voltage point corresponding to each of the clock signal combinations to be detected;

[0085] During the clock calibration process, the calibration algorithm circuit determines the current DC voltage point for the clock signal combination to be detected currently output by the clock data recovery circuit, and compares the current DC voltage point with the total DC voltage point, and adjusts the control code value of the delayed clock signal with a larger phase among the two delayed clock signals currently selected by the clock data recovery circuit according to the comparison result.

[0086] Exemplarily, the correction algorithm circuit can determine the DC voltage points corresponding to the detection phase errors of all different types of clock signal combinations to be detected after multiple calculations, and by adding the DC voltage points corresponding to the detection phase errors of all different types of clock signal combinations to be detected, the DC total voltage point corresponding to the total phase error of the detection phase errors of all clock signal combinations to be detected can be obtained. The DC average voltage point of the DC total voltage point (that is, the DC total voltage point is averaged to multiple clock signal combinations to be detected, such as Figure 1 The 8 clock signal combinations to be detected in the embodiment shown, whose DC average voltage point is the DC total voltage point divided into 8 parts on average, is actually the adjustment target of the DC voltage point corresponding to the detection phase error of each clock signal combination to be detected in the subsequent clock calibration process. Therefore, in the clock calibration process, after the calibration algorithm circuit receives the detection phase error of each clock signal combination to be detected, it determines its DC voltage point, and compares the DC voltage point with the DC average voltage point of the DC total voltage point, so as to determine the control code value for adjusting the delay of the delayed clock signal in the clock signal combination to be detected, so that the DC voltage point corresponding to the detection phase error of the clock signal combination to be detected after adjustment is equal to the DC average voltage point of the DC total voltage point. It can be seen that after the present application obtains multiple DC voltage points of the detection phase error of multiple different clock signal combinations to be detected through multiple detections, the multiple DC voltage points are compared with the DC voltage point of the detection phase error of a clock signal combination to be detected obtained by a subsequent single detection, so as to output the control code value of the delayed clock signal with a larger phase in the clock signal combination to be detected, thereby eliminating the error caused by the phase error detection circuit and the calibration logic circuit itself. Among them, comparing the multiple DC voltage points with the DC voltage point of the detected phase error of the clock signal combination to be detected obtained by a subsequent single detection can be understood as comparing the DC average voltage point of the multiple DC voltage points with the DC voltage point obtained by a single detection.

[0087] In some optional embodiments, the control code value is determined based on the difference between the DC average voltage point and the current DC voltage point; the DC average voltage point is determined based on the total DC voltage point and the total number of types of the clock signal combination to be detected;

[0088] Under the control of the control code value, the delay chain adjusts the delay of the delayed clock signal with a larger phase among the two delayed clock signals currently selected by the clock data recovery circuit, and the adjusted delay length is related to the difference.

[0089] Exemplarily, the control code value is actually the control code value corresponding to the difference between the DC average voltage point and the DC voltage point mentioned above. The control code value can be a digital signal, and the delay chain can determine the adjustment amplitude and adjustment direction (i.e., increase or decrease) of the delayed clock signal based on the control code value.

[0090] For example, Figure 2 As shown, the calibration logic circuit compares and determines the corresponding DC voltage point code<7:0> according to the detected phase error xor<7:0> in sequence. The mapping relationship is as follows: Figure 3 As shown in the figure, it can be seen that in the mapping process, the process deviation of the comparator in the calibration logic circuit will again bring a certain calibration error, recorded as Δoffset2, and the calibration error brought by each mapping process is certain. In other words, in the entire calibration process, there will be two points of manufacturing errors that will cause the accuracy loss of phase calibration, namely Δoffset1 and Δoffset2.

[0091] The calibration algorithm circuit linearly adds the DC voltage points corresponding to each combination of clock signals to be detected to obtain the DC total voltage point code_tot corresponding to the total phase error. Figure 1 Taking the embodiment shown as an example, code_tot is expressed as follows:

[0092] code_tot=code <0> +code <1> +code <2> +code <3> +code <4> +code <5> +code <6> +code <7> =Δphase0+Δphase1+Δphase2+Δphase3+Δphase4+Δphase5+Δphase6+Δphase7+8*Δoffset.

[0093] Among them, Δoffset=Δoffset1+Δoffset2; code <0> is the DC voltage point corresponding to the first clock signal combination to be detected, such as clk0° and clk45°. By analogy, there are a total of 8 DC voltage points code<7:0> for 8 clock signal combinations to be detected. Δphase0, ..., Δphase7 are the actual phase errors corresponding to the 8 clock signal combinations to be detected.

[0094] From the above formula, we can find that Δphase0+Δphase1+Δphase2+Δphase3+Δphase4+Δphase5+Δphase6+Δphase7 is exactly equal to one clock cycle, so if we use code_tot-8*code <n>As the basis for judging the phase error, the calibration will not be affected by the Δoffset. Figure 3 As shown, by comparing code_tot and 8*code <n>, can output the control code value delay ctr1 code that controls how the delay chain delays<n+1> , the code here <n>Indicates the DC voltage point corresponding to the detected phase error based on the current clock signal combination n to be detected, code<n+1> Indicates the DC voltage point corresponding to the detection phase error to which the next clock signal combination n to be detected needs to be adjusted.

[0095] For example, for the first clock signal combination to be detected,

[0096] code_tot-8*code <0> =Δphase0+Δphase1+Δphase2+Δphase3+Δphase4+Δphase5+Δphase6+Δphase7+8*Δoffset-8*Δphase0-8*Δoffset

[0097] =Δphase0+Δphase1+Δphase2+Δphase3+Δphase4+Δphase5+Δphase6+Δphase7-8*Δphase0.

[0098] The clock phase error calibration device proposed in the present application has high calibration speed and calibration accuracy, and is not affected by the errors of the calibration logic circuit and the phase error detection circuit. The error between the multi-phase clock signals finally adjusted is small, thereby being able to generate a high-quality data sampling clock clk_pmix.

[0099] Accordingly, if Figure 4 As shown, the present application exemplarily proposes a clock phase error calibration method, including:

[0100] In step S401, the delay chain outputs a plurality of delayed clock signals with different phases under the control of the control code value, and the expected phase error between any one of the plurality of delayed clock signals and two of the plurality of delayed clock signals is a set error value;

[0101] In step S402, the clock data recovery circuit receives the multiple delayed clock signals, and sequentially selects two delayed clock signals whose expected phase errors are the set error value from the multiple delayed clock signals;

[0102] In step S403, the phase error detection circuit receives and detects a detection phase error between two delayed clock signals selected by the clock data recovery circuit;

[0103] In step S404, the calibration logic circuit controls the delay chain to adjust the control code value of the delay of the delayed clock signal according to the DC voltage point output corresponding to the detected phase error, so that the actual phase error between the delayed clock signal and two of the delayed clock signals approaches the set error value.

[0104] In some optional embodiments, the clock data recovery circuit receives the multiple delayed clock signals, and sequentially selects two delayed clock signals whose expected phase errors are set error values ​​from the multiple delayed clock signals, including:

[0105] The clock data recovery circuit receives half of the delayed clock signals from the delay chain by using a first signal selector, selects one delayed clock signal from the delayed clock signal and outputs it to the phase error detection circuit; the expected phase error between the two delayed clock signals received by the first signal selector is an even multiple of the set error value;

[0106] The clock data recovery circuit also uses a second signal selector to receive the other half of the delayed clock signals from the delay chain, and selects one delayed clock signal from them and outputs it to the phase error detection circuit; the expected phase error between the delayed clock signals received by the second signal selector is also an even multiple of the set error value; wherein the delayed clock signals selected by the first signal selector and the second signal selector each time constitute a clock signal combination to be detected, and the first signal selector and the second signal selector select multiple different clock signal combinations to be detected in turn in a cyclic manner.

[0107] In some optional embodiments, the phase error detection circuit receives and detects a detection phase error between two delayed clock signals selected by the clock data recovery circuit, including:

[0108] The phase error detection circuit receives the two delayed clock signals selected by the clock data recovery circuit using an exclusive OR logic circuit, and detects the detection phase error between the two delayed clock signals selected by the clock data recovery circuit through an exclusive OR logic operation.

[0109] In some optional embodiments, the calibration logic circuit outputs a control code value for controlling the delay chain to adjust the delay of the delayed clock signal according to the DC voltage point corresponding to the detected phase error, including:

[0110] The calibration logic circuit receives the first voltage signal corresponding to the detected phase error output by the phase error detection circuit by using a comparator, compares the first voltage signal with the second voltage signal output by the digital-to-analog converter, and outputs an adjustment signal for adjusting the second voltage signal according to the comparison result;

[0111] The calibration logic circuit outputs the adjustment signal to the digital-to-analog converter using a calibration algorithm circuit, and updates a DC voltage point corresponding to the second voltage signal according to the adjustment signal;

[0112] The digital-to-analog converter outputs the adjusted second voltage signal to the comparator according to the adjustment signal, so that the adjusted second voltage signal is closer to the first voltage signal than before the adjustment;

[0113] After the adjusted second voltage signal meets the set conditions, the calibration algorithm circuit determines the updated DC voltage point as the DC voltage point for detecting the phase error, and outputs the control code value of the delayed clock signal with a larger phase among the two delayed clock signals selected by the clock data recovery circuit corresponding to the detected phase error based on the DC voltage point for detecting the phase error.

[0114] In some optional embodiments, the method further includes:

[0115] The calibration algorithm circuit predetermines the DC voltage point corresponding to the detected phase error of each of the clock signal combinations to be detected, and determines the DC total voltage point corresponding to the total phase error of all the clock signal combinations to be detected based on the DC voltage point corresponding to each of the clock signal combinations to be detected;

[0116] Outputting the control code value of the delayed clock signal with a larger phase among the two delayed clock signals selected by the clock data recovery circuit corresponding to the detected phase error according to the DC voltage point of the detected phase error comprises:

[0117] The DC voltage point is compared with the DC total voltage point, and the control code value of the delayed clock signal with a larger phase among the two delayed clock signals currently selected by the clock data recovery circuit is adjusted according to the comparison result.

[0118] In some optional embodiments, the control code value is determined based on the difference between the DC average voltage point and the current DC voltage point; the DC average voltage point is determined based on the total DC voltage point and the total number of types of the clock signal combination to be detected;

[0119] The delay chain outputs a plurality of delayed clock signals with different phases under the control of the control code value, including:

[0120] Under the control of the control code value, the delay chain adjusts the delay of the delayed clock signal with a larger phase among the two delayed clock signals currently selected by the clock data recovery circuit, and the adjusted delay length is related to the difference.

[0121] The above method can be implemented by the clock phase error calibration device provided in the above embodiment. The specific implementation method can refer to the description of the clock phase error calibration device in the above embodiment, which will not be repeated here.

[0122] It is understood that the circuit structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above embodiments according to the use requirements, and should not limit the concept of the present application to the specific details of the above examples.

[0123] Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that he or she may still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A clock phase error calibration device, characterized in that: include: Delay chain, clock data recovery circuit, phase error detection circuit and calibration logic circuit; The delay chain is used to output a plurality of delayed clock signals with different phases under the control of the control code value, and the expected phase error between any one of the plurality of delayed clock signals and two of the plurality of delayed clock signals is a set error value; The clock data recovery circuit sequentially selects two delayed clock signals whose expected phase errors are set error values ​​from a plurality of delayed clock signals; The phase error detection circuit is used to detect the detection phase error between the two delayed clock signals selected by the clock data recovery circuit; The calibration logic circuit is used to control the delay chain to adjust the control code value of the delay of the delayed clock signal according to the DC voltage point output corresponding to the detected phase error, so that the actual phase error between the delayed clock signal and two of the delayed clock signals approaches the set error value.

2. The clock phase error calibration device according to claim 1, characterized in that: The clock data recovery circuit comprises: a first signal selector and a second signal selector; The first signal selector receives half of the delayed clock signals from the delay chain and selects one delayed clock signal therefrom; the expected phase error between two of the delayed clock signals received by the first signal selector is an even multiple of the set error value; The second signal selector receives the other half of the delayed clock signals from the delay chain and selects one delayed clock signal therefrom; the expected phase error between the two delayed clock signals received by the second signal selector is also an even multiple of the set error value; The delayed clock signals selected by the first signal selector and the second signal selector each time constitute a clock signal combination to be detected, and the first signal selector and the second signal selector cyclically select a plurality of different clock signal combinations to be detected.

3. The clock phase error calibration device according to claim 1, characterized in that: The phase error detection circuit comprises: an XOR logic circuit; The XOR logic circuit receives the two delayed clock signals selected by the clock data recovery circuit, and detects a detection phase error between the two delayed clock signals selected by the clock data recovery circuit through an XOR logic operation.

4. The clock phase error calibration device according to any one of claims 1 to 3, characterized in that: The calibration logic circuit includes: a comparator, a digital-to-analog converter and a calibration algorithm circuit; The comparator receives a first voltage signal corresponding to the detected phase error output by the phase error detection circuit and a second voltage signal output by the digital-to-analog converter, and outputs an adjustment signal for adjusting the second voltage signal by comparing the first voltage signal with the second voltage signal; The calibration algorithm circuit outputs the adjustment signal to the digital-to-analog converter, and updates the DC voltage point corresponding to the second voltage signal according to the adjustment signal; The digital-to-analog converter outputs the adjusted second voltage signal to the comparator according to the adjustment signal, so that the adjusted second voltage signal is closer to the first voltage signal than before the adjustment; After the adjusted second voltage signal meets the set conditions, the calibration algorithm circuit determines the updated DC voltage point as the DC voltage point for detecting the phase error, and outputs the control code value of the delayed clock signal with a larger phase among the two delayed clock signals selected by the clock data recovery circuit corresponding to the detected phase error according to the DC voltage point corresponding to the detected phase error.

5. The clock phase error calibration device according to claim 4, characterized in that: The calibration algorithm circuit predetermines the DC voltage point corresponding to the detected phase error of each of the clock signal combinations to be detected, and determines the DC total voltage point corresponding to the total phase error of all the clock signal combinations to be detected based on the DC voltage point corresponding to each of the clock signal combinations to be detected; During the clock calibration process, the calibration algorithm circuit determines the current DC voltage point for the clock signal combination to be detected currently output by the clock data recovery circuit, and compares the current DC voltage point with the total DC voltage point, and adjusts the control code value of the delayed clock signal with a larger phase among the two delayed clock signals currently selected by the clock data recovery circuit according to the comparison result.

6. The clock phase error calibration device according to claim 5, characterized in that: The control code value is determined based on the difference between the DC average voltage point and the current DC voltage point; the DC average voltage point is determined based on the total DC voltage point and the total number of types of the clock signal combination to be detected; Under the control of the control code value, the delay chain adjusts the delay of the delayed clock signal with a larger phase among the two delayed clock signals currently selected by the clock data recovery circuit, and the adjusted delay length is related to the difference.

7. A clock phase error calibration method, characterized in that: include: The delay chain outputs a plurality of delayed clock signals with different phases under the control of the control code value, and the expected phase error between any one of the plurality of delayed clock signals and two of the plurality of delayed clock signals is a set error value; The clock data recovery circuit receives the multiple delayed clock signals, and sequentially selects two delayed clock signals whose expected phase errors are set error values ​​from the multiple delayed clock signals; The phase error detection circuit receives and detects a detection phase error between two delayed clock signals selected by the clock data recovery circuit; The calibration logic circuit controls the delay chain to adjust the control code value of the delay of the delayed clock signal according to the DC voltage point output corresponding to the detected phase error, so that the actual phase error between the delayed clock signal and two of the delayed clock signals approaches the set error value.

8. The clock phase error calibration method according to claim 7, characterized in that: The clock data recovery circuit receives the multiple delayed clock signals and sequentially selects two delayed clock signals whose expected phase errors are set error values ​​from the multiple delayed clock signals, including: The clock data recovery circuit receives half of the delayed clock signals from the delay chain by using a first signal selector, selects one delayed clock signal from the delayed clock signal and outputs it to the phase error detection circuit; the expected phase error between the two delayed clock signals received by the first signal selector is an even multiple of the set error value; The clock data recovery circuit also uses a second signal selector to receive the other half of the delayed clock signals from the delay chain, and selects one delayed clock signal from them and outputs it to the phase error detection circuit; the expected phase error between the delayed clock signals received by the second signal selector is also an even multiple of the set error value; wherein the delayed clock signals selected by the first signal selector and the second signal selector each time constitute a clock signal combination to be detected, and the first signal selector and the second signal selector select multiple different clock signal combinations to be detected in turn in a cyclic manner.

9. The clock phase error calibration method according to claim 7, characterized in that: The phase error detection circuit receives and detects the two delayed clock signals selected by the clock data recovery circuit, including: The phase error detection circuit receives the two delayed clock signals selected by the clock data recovery circuit by using an exclusive OR logic circuit, and detects the detection phase error between the two delayed clock signals selected by the clock data recovery circuit by an exclusive OR logic operation.

10. The clock phase error calibration method according to any one of claims 7 to 9, characterized in that: The calibration logic circuit outputs a control code value for controlling the delay chain to adjust the delay of the delayed clock signal according to the DC voltage point corresponding to the detected phase error, including: The calibration logic circuit receives the first voltage signal corresponding to the detected phase error output by the phase error detection circuit by using a comparator, compares the first voltage signal with the second voltage signal output by the digital-to-analog converter, and outputs an adjustment signal for adjusting the second voltage signal according to the comparison result; The calibration logic circuit outputs the adjustment signal to the digital-to-analog converter using a calibration algorithm circuit, and updates a DC voltage point corresponding to the second voltage signal according to the adjustment signal; The digital-to-analog converter outputs the adjusted second voltage signal to the comparator according to the adjustment signal, so that the adjusted second voltage signal is closer to the first voltage signal than before the adjustment; After the adjusted second voltage signal meets the set conditions, the calibration algorithm circuit determines the updated DC voltage point as the DC voltage point for detecting the phase error, and outputs the control code value of the delayed clock signal with a larger phase among the two delayed clock signals selected by the clock data recovery circuit corresponding to the detected phase error according to the DC voltage point corresponding to the detected phase error.

11. The clock phase error calibration method according to claim 10, characterized in that: The method further comprises: The calibration algorithm circuit predetermines the DC voltage point corresponding to the detected phase error of each of the clock signal combinations to be detected, and determines the DC total voltage point corresponding to the total phase error of all the clock signal combinations to be detected based on the DC voltage point corresponding to each of the clock signal combinations to be detected; Outputting the control code value of the delayed clock signal with a larger phase among the two delayed clock signals selected by the clock data recovery circuit corresponding to the detected phase error according to the DC voltage point of the detected phase error comprises: The DC voltage point is compared with the DC total voltage point, and the control code value of the delayed clock signal with a larger phase among the two delayed clock signals currently selected by the clock data recovery circuit is adjusted according to the comparison result.

12. The clock phase error calibration method according to claim 11, characterized in that: The control code value is determined based on the difference between the DC average voltage point and the current DC voltage point; the DC average voltage point is determined based on the total DC voltage point and the total number of types of the clock signal combination to be detected; The delay chain outputs a plurality of delayed clock signals with different phases under the control of the control code value, including: Under the control of the control code value, the delay chain adjusts the delay of the delayed clock signal with a larger phase among the two delayed clock signals currently selected by the clock data recovery circuit, and the adjusted delay length is related to the difference.

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