Storage system, method of operating the same, and computer readable storage medium

Abstract

This disclosure provides a storage system and its operation method, as well as a computer-readable storage medium. The storage system includes: a non-volatile memory comprising multiple storage areas, each storage area including multiple first storage groups located in a first area and multiple second storage groups located in a second area, the first area supporting physical addressing and the second area not supporting physical addressing; and a memory controller coupled to the non-volatile memory, configured to: perform wear leveling by swapping the first storage groups having a first set of write counts with the second storage groups having a second set of write counts; wherein the first set of write counts is the largest set of write counts among the multiple sets of write counts corresponding to the multiple first storage groups, and the second set of write counts is the smallest set of write counts among the multiple sets of write counts corresponding to the multiple second storage groups.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a storage system and its operation method, and a computer-readable storage medium. Background Technology

[0002] Non-volatile memory (NVM) is widely used in various fields, including embedded systems such as computers and network interconnection devices, as well as voice, image, and data storage products such as digital cameras and digital recorders. As these products demand increasingly higher storage capacities, the manufacturing process of NVM is shrinking, leading to increasingly severe challenges to its reliability. In particular, due to its inherent physical characteristics, NVM has limited write endurance. If a specific memory location in NVM is written to multiple times, exceeding its write endurance, that location cannot be reliably used for subsequent storage operations, thus affecting the overall data storage performance of the memory. Therefore, maximizing the lifespan of NVM by using different memory locations in a balanced manner has become a pressing issue. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a storage system, including: a non-volatile memory comprising a plurality of storage regions, each storage region including a plurality of first storage groups located in a first region and a plurality of second storage groups located in a second region, wherein the first region supports physical addressing and the second region does not support physical addressing; and

[0004] The memory controller coupled to the non-volatile memory is configured to perform wear leveling by swapping a first memory group having a first set of write counts with a second memory group having a second set of write counts; wherein the first set of write counts is the largest set of write counts among the multiple sets of write counts corresponding to the plurality of first memory groups, and the second set of write counts is the smallest set of write counts among the multiple sets of write counts corresponding to the plurality of second memory groups.

[0005] Secondly, embodiments of this disclosure provide an operation method for a storage system, the storage system including a non-volatile memory and a memory controller coupled to the non-volatile memory, the non-volatile memory including multiple storage areas, each storage area including multiple first storage groups located in a first area and multiple second storage groups located in a second area, the first area supporting physical addressing, and the second area not supporting physical addressing; the operation method includes:

[0006] Wear leveling is performed by swapping a first storage group with a first set of write counts with a second storage group with a second set of write counts; the first set of write counts is the largest set of write counts among the multiple sets of write counts corresponding to the plurality of first storage groups, and the second set of write counts is the smallest set of write counts among the multiple sets of write counts corresponding to the plurality of second storage groups.

[0007] Thirdly, embodiments of this disclosure provide a computer-readable storage medium storing a computer program that, when executed by a processor, performs the operation method as described in any of the second aspects. Attached Figure Description

[0008] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this disclosure and should not be construed as limiting the scope of this disclosure.

[0009] Figure 1 A block diagram of a storage system provided in an embodiment of this disclosure;

[0010] Figure 2 A block diagram of a storage area provided in an embodiment of this disclosure;

[0011] Figure 3 This is a schematic diagram showing the distribution of group write counts corresponding to storage groups in different storage areas according to an embodiment of the present disclosure.

[0012] Figure 4 for Figure 3 A mapping table between logical addresses and physical addresses;

[0013] Figure 5 This is a schematic diagram showing the distribution of group write counts in different storage areas after wear leveling processing, according to an embodiment of this disclosure.

[0014] Figure 6 for Figure 5 A mapping table between logical addresses and physical addresses;

[0015] Figure 7 This is a schematic diagram showing the distribution of group write counts corresponding to storage groups in different storage areas, provided in another embodiment of this disclosure.

[0016] Figure 8 This is a schematic diagram showing the distribution of group write counts for different storage groups in different storage areas after wear leveling processing, provided in another embodiment of this disclosure.

[0017] Figure 9 for Figure 8A mapping table between logical addresses and physical addresses;

[0018] Figure 10 This is a schematic diagram illustrating the usage process of a dual Bloom filter provided in an embodiment of the present disclosure;

[0019] Figure 11 A flowchart illustrating an operation method of a storage system provided in an embodiment of this disclosure;

[0020] Figure 12 A block diagram of a computer-readable storage medium provided according to an embodiment of the present disclosure;

[0021] Figure 13 A block diagram of a system provided according to an embodiment of this disclosure. Detailed Implementation

[0022] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0023] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0024] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0025] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0027] New types of non-volatile memories, such as Flash memory, Phase Change Memory (PCM), Resistive Random Access Memory (RRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), and Nantero's CNT Random Access Memory (NRAM), offer advantages such as high access speed, low power consumption, and non-volatility, leading to their increasingly widespread application. However, most non-volatile memories (e.g., Flash, PCM, RRAM, FRAM) have a limited number of write cycles, and this limit decreases as storage capacity increases, resulting in a shorter lifespan. For example, Flash memory typically has a write cycle limit of 10... 4 PCM can typically write 10 times. 8 RRAM can write 10 times. 5 Second-class.

[0028] Taking PCM as an example, the basic principle of PCM is as follows: A short-duration electrical pulse with a large signal value is applied to the phase-change memory cell. Under Joule heating and other effects, a portion of the initially crystalline phase-change memory layer melts because its temperature exceeds the melting temperature. After the electrical pulse is interrupted, the molten portion cools rapidly and remains in an amorphous state with low atomic order, thus completing the transition from low resistance to high resistance. This is the reset process. The molten portion in this process is called the programming volume. If a short-duration electrical pulse with a small signal value is applied, causing the temperature within the programming volume to reach above the crystallization temperature but below the melting temperature, and this is sustained for a sufficient time for the amorphous structure within the programming volume to crystallize, a low-resistance state is obtained. This is the set process. The PCM read process involves applying a short-duration electrical pulse to the phase-change memory cell, keeping the phase-change memory layer below the crystallization temperature, and measuring the resistance of the phase-change memory cell.

[0029] Phase-change memory (PCM) materials, as the storage medium in PCMs, directly impact the device's performance. PCM wear is primarily related to the number of write cycles. With a uniform distribution of write cycles, PCM wear is also relatively uniform, maintaining its phase-change characteristics and stability, preventing thermal drift and phase-change failure due to excessive writing, and allowing PCMs to achieve a lifespan of over 5 years. However, in practical applications, due to the unevenness of data access patterns and write operations, the number of write cycles in a PCM can be unevenly distributed among the storage cells. This can lead to severe wear on some storage cells, causing them to fail within a short period (e.g., weeks or months), resulting in PCM malfunction. Therefore, to avoid the failure of a single storage cell leading to the failure of the entire PCM, wear leveling is typically used to distribute the number of write cycles evenly across different storage cells.

[0030] Wear leveling is one of the main methods to improve the lifespan of non-volatile memory (NVM). It distributes write operations to NVM across various target addresses to achieve a more uniform level of wear across different memory locations. However, traditional wear leveling requires a high swapping frequency, resulting in significant storage space and performance overhead. Furthermore, the data swapping granularity used in related technologies is fixed and limited, hindering flexible and finer-grained wear leveling for NVM. In addition, traditional wear leveling is vulnerable to malicious attacks. For example, phase-change memory (PCM) can perform in-situ write operations, meaning it doesn't require a prior erase operation; instead, it directly replaces previously written data with newly written data in its original location. Based on this, malicious attackers can detect changes in the logical-to-physical address mapping during wear leveling, deduce the new location of the memory block to be swapped, and repeatedly perform in-situ write operations at a specific location, causing the PCM to fail rapidly.

[0031] In view of the above, embodiments of the present disclosure provide a storage system, a method of operating the same, and a computer-readable storage medium.

[0032] Figure 1 This is a block diagram of a storage system provided according to an embodiment of the present disclosure. Figure 1 As shown, according to a first aspect of the present disclosure, a storage system 100 is provided, the storage system 100 including: a non-volatile memory 110 including a plurality of storage areas 111.

[0033] Figure 2 A block diagram of a storage area provided in an embodiment of this disclosure, in conjunction with Figure 1 and Figure 2 Each storage area 111 includes a plurality of first storage groups 1111 located in a first region and a plurality of second storage groups 1112 located in a second region. The first region supports physical addressing, while the second region does not. The storage system 100 also includes a memory controller 120 coupled to the non-volatile memory 110, configured to perform wear leveling by swapping the first storage group 1111 having a first set of write counts with the second storage group 1112 having a second set of write counts; wherein the first set of write counts is the largest set of write counts among the plurality of sets of write counts corresponding to the plurality of first storage groups 1111, and the second set of write counts is the smallest set of write counts among the plurality of sets of write counts corresponding to the plurality of second storage groups 1112.

[0034] Here, each first storage group in the first region has a logical address and a corresponding physical address. The fact that the first region supports physical addressing means that external devices (e.g., hosts) can directly access the first region through the mapping relationship between logical addresses and physical addresses.

[0035] Each second storage group in the second region has a logical address and a corresponding physical address. The fact that the second region does not support physical addressing means that the logical address of the second storage group is not visible to external devices (e.g., hosts). Therefore, external devices cannot directly access the second region through the mapping relationship between the logical address and the physical address of the second storage group. In other words, external devices cannot perform read or write operations on the second storage group of the second region.

[0036] In some implementations, the second storage group in the second region can be used to store dirty data.

[0037] It should be noted that the first set of write counts is the maximum group write count among all group write counts corresponding to all first storage groups in the first region. The second set of write counts is the minimum group write count among all group write counts corresponding to all second storage groups in the second region.

[0038] In this embodiment of the disclosure, each storage area in the non-volatile memory is divided into a first region that supports physical addressing and a second region that does not support physical addressing. During wear leveling, the first storage group with a first set of write counts is swapped with the second storage group with a second set of write counts to transfer the first storage group with the first set of write counts from the first region to the second region. This prevents the first storage group with the largest set of write counts from still being in the first region that supports physical access after wear leveling, and avoids the risk that the first storage group with the largest set of write counts will still be physically accessed after wear leveling.

[0039] In some embodiments, the storage system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, or any other suitable electronic device having non-volatile memory 110 therein.

[0040] In some embodiments, the memory controller 120 can control the overall operation of the storage system 100. The memory controller 120 can store data in the non-volatile memory 110, or can read data stored in the non-volatile memory 110.

[0041] In some embodiments, the non-volatile memory 110 may include one of phase-change memory, resistive random access memory, magnetic random access memory, and carbon nanotube random access memory.

[0042] In some embodiments, the memory controller 120 may also store various information (e.g., mapping tables) required for the operation of the storage system 100 in the non-volatile memory 110 or in the volatile memory of the memory controller 120.

[0043] The memory controller 120 may also be configured to manage various functions relating to data stored or to be stored in the non-volatile memory 110, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 120 is also configured to process error correction codes (ECCs) relating to data read from or written to the non-volatile memory 110.

[0044] The memory controller 120 can also perform any other suitable functions, such as formatting the non-volatile memory 110. The memory controller 120 can communicate with external devices according to a specific communication protocol. For example, the memory controller 120 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0045] In this embodiment of the disclosure, both the first storage group and the second storage group include a first number of storage units; or, both the first storage group and the second storage group include a second number of storage units. The first number is greater than the second number.

[0046] For example, the non-volatile memory 110 can be divided into multiple memory regions, and then each memory region can be divided into multiple memory groups. Both the first memory group and the second memory group include a second number of memory cells.

[0047] In some embodiments, the size of the first and second storage groups can be the same as the size of a codeword (CW), where the codeword includes user data, error correction codes (ECCs), and metadata. The size of the codeword is typically determined by the size of the user data, the size of the ECCs, and the size of the metadata. The size of the user data is usually determined based on the actual amount of data to be stored or transmitted; the user data can be in bits, bytes, words, or other units, depending on the storage system and data transmission requirements. ECCs are redundant information added to the user data to detect and correct errors in data transmission or storage. The size of the ECCs depends on the size of the user data and the required error correction capabilities. The metadata contains information about the codeword, such as the data format, checksum type, error detection and correction scheme, and a mapping table from logical addresses to physical addresses. The size of the metadata depends on the design and implementation of the storage system and the required management and control capabilities. In general, different storage systems may choose different codeword sizes to meet their performance, reliability, and storage requirements. It is understood that a codeword can include multiple storage units, and the number of storage units included in a codeword can be adjusted according to actual needs.

[0048] In one specific implementation, the error correction code (ECC) is 256 bytes in size, and the codeword size is 4 KB. It can be understood that the first and second memory groups are also 4 KB in size. Taking the non-volatile memory 110 as a phase-change memory as an example, the second group size is 2. 12 .

[0049] In some embodiments, the ratio of the first quantity to the second quantity is in the range of 2. 4 Up to 2 12 For example, the ratio of the first quantity to the second quantity ranges from 2. 4 2 8 Or 2 12 .

[0050] In some embodiments, the size of the first and second storage groups can be the same as the size of a storage block. Typically, a storage block is 512KB (4KB * 2). 7 ) or 1024KB (4KB*2) 8 (and even larger.) It is understandable that a storage block can include multiple storage units, and the number of storage units included in a storage block can be adjusted according to the actual situation.

[0051] In one specific embodiment, the size of the storage block is 1024KB. It can be understood that the size of the first storage group and the second storage group is also 1024KB. Taking the non-volatile memory 110 as a phase-change memory as an example, then the first quantity is 2. 20 .

[0052] It should be noted that the first and second quantities in the above embodiments are merely examples. The storage area, the first storage group, and the second storage group can be divided into different sizes according to the actual size and type of the non-volatile memory.

[0053] In traditional wear leveling, a small data exchange granularity may lead to frequent data movement and copying, increasing space overhead, while a large data exchange granularity may cause wear leveling problems. This disclosure flexibly divides the data exchange granularity of wear leveling into different levels. It can divide the size of the first and second storage groups into a first number of storage units at the first granularity level, or into a second number of storage units at the second granularity level. In other words, this disclosure can reasonably divide the data exchange granularity of wear leveling according to the actual size of the non-volatile memory, thereby improving the flexibility and precision of wear leveling processing for non-volatile memory.

[0054] In this embodiment, wear leveling can be performed on non-volatile memory at different granularity levels, which can greatly improve the flexibility and precision of wear leveling for non-volatile memory. In this embodiment, the memory controller 120 is specifically configured to: compare a first set of write counts with a second set of write counts; when the first set of write counts is greater than the second set of write counts, perform wear leveling by swapping the first memory group with the first set of write counts with the second memory group with the second set of write counts.

[0055] In this embodiment of the disclosure, the memory controller 120 is specifically configured to perform wear leveling by swapping data stored in a first memory group having a first set of write counts and data stored in a second memory group having a second set of write counts; and swapping the logical address of the first memory group having a first set of write counts and the logical address of the second memory group having a second set of write counts.

[0056] Figure 3 This is a schematic diagram showing the distribution of group write counts corresponding to storage groups in different storage areas according to an embodiment of this disclosure. Figure 4 for Figure 3 A mapping table between logical addresses and physical addresses. For example... Figure 3 and Figure 4As shown, the storage area includes multiple first storage groups located in a first region and second storage groups located in a second region. The logical addresses and physical addresses of the first and second storage groups have a one-to-one mapping relationship. Each first storage group has a group write count, and each second storage group also has a group write count, as shown below. Figure 3 The Write count shown is the current group write count for each storage group.

[0057] refer to Figure 3 It can be seen that the group write count of the first storage group corresponding to the physical address 2 mapped by logical address 2 is 6K, which is the maximum value among all group write counts of the first storage group; that is, the first group write count is 6K. The group write count of the second storage group corresponding to the physical address M mapped by logical address M is 5K, which is the minimum value among all group write counts of the second storage group; that is, the second group write count is 5K. At this time, the first group write count is greater than the second group write count.

[0058] It should be noted that, Figure 3 The number of second storage groups shown is merely an example and is not intended to limit the number of second storage groups in the embodiments of this disclosure.

[0059] Figure 5 This is a schematic diagram showing the distribution of group write counts for different storage groups in different storage areas after wear leveling, according to an embodiment of this disclosure. Figure 6 for Figure 5 A mapping table between logical addresses and physical addresses. (See reference) Figure 5 and Figure 6 The memory controller 120 is configured to: swap the data stored in the first memory group corresponding to the physical address 2 mapped by logical address 2 and the data stored in the second memory group corresponding to the physical address M mapped by logical address M; and swap the logical address of the first memory group corresponding to physical address 2 and the logical address of the second memory group corresponding to physical address M to perform wear leveling.

[0060] like Figure 5 and Figure 6As shown, after wear leveling, physical address 2 corresponds to logical address M, and physical address M corresponds to logical address 2. Since the first memory group with the first set of write counts is swapped to the second region that does not support physical access, the first memory group with the first set of write counts will not be physically accessed in subsequent write operations. Even if a malicious attack program can detect the change in the logical address to physical address mapping during wear leveling and deduce the new location to be swapped, it will not be able to launch a brute-force attack on the second region that does not support physical access. In other words, the storage system in this embodiment can resist malicious attacks during wear leveling.

[0061] In some embodiments, when both the first storage group and the second storage group include a first number of storage cells, the memory controller 120 is configured to update the mapping table between the logical address and the physical address of each storage group in the storage area after wear leveling, and store the mapping table in the volatile memory of the memory controller 120.

[0062] In some implementations, when both the first storage group and the second storage group include a first number of storage cells, Figure 4 and Figure 6 The mapping table shown is stored in the volatile memory (e.g., Static Random Access Memory, SRAM) of the memory controller 120. Since the first and second memory groups have a first number of memory cells, the total number of first and second memory groups is relatively small for the entire non-volatile memory. Therefore, the space occupied by the mapping table reflecting the correspondence between logical addresses and physical addresses of the first and second memory groups is also small. Thus, storing the mapping table in the memory controller speeds up access to the mapping table without occupying excessive space or adding extra burden to the memory controller. In a specific example, when the size of the first and second memory groups is the same as the size of the memory block, the mapping table reflecting the correspondence between logical addresses and physical addresses of the first and second memory groups is stored in the volatile memory of the memory controller.

[0063] In other embodiments, when both the first and second storage groups include a second number of storage cells, the memory controller is configured to update the mapping table between the logical and physical addresses of each storage group in the storage region after wear leveling, and store the mapping table in non-volatile memory 110. Exemplarily, when both the first and second storage groups include a second number of storage cells, Figure 4 and Figure 6The mapping table shown is stored in the metadata of the non-volatile memory 110 of the memory controller 120.

[0064] Since the first and second memory groups have a second number of memory cells, the total number of first and second memory groups in the entire non-volatile memory is relatively large. Therefore, the mapping table reflecting the correspondence between logical addresses and physical addresses of the first and second memory groups occupies a large amount of space. Storing this mapping table in the memory controller's volatile memory would significantly reduce the memory controller's space utilization, increase its workload, and impact system performance. Therefore, to balance space efficiency and system performance, the mapping table is stored in the metadata of the non-volatile memory. In a specific example, when the size of the first and second memory groups is the same as the codeword size, the mapping table reflecting the correspondence between logical addresses and physical addresses of the first and second memory groups is stored in the codeword's metadata. When the memory controller needs to access the mapping table, it must read the metadata to obtain it.

[0065] In this embodiment of the present disclosure, the memory controller is further configured to: when the first group of write counts is less than or equal to the second group of write counts, perform wear leveling by exchanging the first storage group with the first group of write counts with the third group of write counts; wherein the third group of write counts is the smallest group of write counts among the multiple group write counts corresponding to the multiple first storage groups.

[0066] Wear leveling is performed by swapping the data stored in the first storage group with the first set of write counts and the data stored in the first storage group with the third set of write counts; and by swapping the logical address of the first storage group with the first set of write counts and the logical address of the first storage group with the third set of write counts.

[0067] Figure 7 This is a schematic diagram showing the distribution of group write counts corresponding to storage groups in different storage areas according to another embodiment of this disclosure. Figure 7 The mapping table between logical addresses and physical addresses can be found in [reference]. Figure 4 .like Figure 4 and Figure 7 As shown, the group write count of the first memory group corresponding to physical address 2, which is mapped to logical address 2, is 4K. This group write count is the maximum value among all first memory groups, i.e., the first group write count is 4K. The group write count of the second memory group corresponding to physical address M, which is mapped to logical address M, is 5K. This second memory group write count is the minimum value among all second memory groups, i.e., the second group write count is 5K. The first group write count is less than the second group write count.

[0068] The group write count of the first storage group corresponding to the physical address 7 mapped by logical address 7 is 6. The group write count of the first storage group is the minimum value among all the group write counts of the first storage groups, that is, the write count of the third group is 6.

[0069] Figure 8 This is a schematic diagram showing the distribution of group write counts for different storage groups in different storage areas after wear leveling, provided in another embodiment of this disclosure. Figure 9 for Figure 8 A mapping table between logical addresses and physical addresses. (See reference) Figure 8 and Figure 9 The memory controller 120 is configured to: swap the data stored in the first memory group corresponding to the physical address 2 mapped by logical address 2 and the data stored in the first memory group corresponding to the physical address 7 mapped by logical address 7; and swap the logical address of the first memory group corresponding to physical address 2 and the logical address of the second memory group corresponding to physical address 7 to perform wear leveling.

[0070] like Figure 8 and Figure 9 As shown, after wear leveling, physical address 2 corresponds to logical address 7, and physical address 7 corresponds to logical address 2. Since the first group of write counts is less than the second group of write counts, it means that the first storage group with the first group of write counts can still withstand a certain number of write operations. Therefore, by swapping the first storage group with the largest group of write counts and the first storage group with the smallest group of write counts in the first region to perform wear leveling, the wear level of multiple first storage groups can be balanced.

[0071] In some embodiments, when both the first and second storage groups include a first number of storage cells, the memory controller 120 is configured to: update the mapping table between the logical and physical addresses of each storage group in the storage region after wear leveling, and store the mapping table in the volatile memory of the memory controller 120. Exemplarily, when both the first and second storage groups include a first number of storage cells, Figure 9 The mapping table shown is stored in the volatile memory (e.g., static random access memory) of the memory controller 120.

[0072] In other embodiments, when both the first and second storage groups include a second number of storage cells, the memory controller is configured to update the mapping table between the logical and physical addresses of each storage group in the storage region after wear leveling, and store the mapping table in non-volatile memory 110. Exemplarily, when both the first and second storage groups include a second number of storage cells, Figure 9The mapping table shown is stored in the metadata of the non-volatile memory 110 of the memory controller 120.

[0073] In this embodiment of the present disclosure, the memory controller 120 is configured to compare the first set of write counts with a first preset threshold before comparing the first set of write counts with the second set of write counts;

[0074] When the first group of write counts is greater than the first preset threshold, the first group of write counts is compared with the second group of write counts.

[0075] by Figure 7 Taking an example, the first preset threshold is set to 3500. The group write count of the first memory group corresponding to the physical address 2 mapped by logical address 2 is 4K. This group write count is the maximum value among all group write counts of the first memory groups, i.e., the first group write count is 4K. When the first group write count is greater than the first preset threshold, the memory controller begins wear leveling.

[0076] Understandably, when the first set of write counts is greater than the first preset threshold and the second set of write counts, the memory controller 120 is configured to: swap the first storage group with the first set of write counts in the first region and the second storage group with the second set of write counts in the second region to perform wear leveling.

[0077] When the first group of write counts is greater than the first preset threshold but less than the second group of write counts, the memory controller 120 is configured to: swap the first storage group with the first group of write counts and the first storage group with the third group of write counts in the first region to perform wear leveling.

[0078] When the first group of write counts is less than or equal to the first preset threshold, the memory controller 120 is configured to not perform wear leveling.

[0079] In some embodiments, the memory controller is configured to compare a first set of write counts with a first preset threshold within a preset period, the preset period ranging from 1s to 5s.

[0080] In this embodiment of the disclosure, the first preset threshold increases as the electrical distance (ED) between the first memory group corresponding to the first group of write counts and the voltage source increases.

[0081] In some embodiments, the first memory group corresponding to the first set of write counts that is closer to the voltage source is more susceptible to the effects of the voltage source. For example, voltage surges or leakage from the voltage source will accelerate the damage to the first memory group. It is understood that as the electrical distance between the first memory group corresponding to the first set of write counts and the voltage source decreases, the overall lifespan of the first memory group also decreases. Consequently, the upper limit of the number of write cycles for the first memory group, i.e., the first preset threshold, will also decrease, so as to perform wear leveling before the first memory group reaches its upper limit of the number of write cycles, thereby preventing the first memory group from reaching its lifespan prematurely.

[0082] The greater the electrical distance between the first storage group corresponding to the first group of write counts and the voltage source, the less the first storage group is affected by the voltage source. The overall lifespan of the first storage group will not be reduced due to voltage surges or leakage. Therefore, the upper limit of the number of writes of the first storage group, i.e., the first preset threshold, will be greater.

[0083] Table 1 shows an example of the electrical distance between the first memory group corresponding to the first write count and the voltage source, and a first preset threshold. As shown in Table 1, "NN" indicates that the electrical distance between the first memory group corresponding to the first write count and the voltage source is near, with a corresponding first preset threshold of 400. "MM" indicates that the electrical distance between the first memory group corresponding to the first write count and the voltage source is middle, with a corresponding first preset threshold of 800. "FF" indicates that the electrical distance between the first memory group corresponding to the first write count and the voltage source is far, with a corresponding first preset threshold of 1600.

[0084] Table 1

[0085] Electrical distance (ED) First preset threshold NN 400 MM 800 FF 1600

[0086] It should be noted that the values ​​of the first preset threshold shown in Table 1 are merely examples and are not intended to limit the range of the first preset threshold in the embodiments of this disclosure.

[0087] In this embodiment of the disclosure, the group write count is obtained by counting using a dual Bloom filter.

[0088] Figure 10 This diagram illustrates the usage of a dual Bloom filter according to an embodiment of the present disclosure. In a dual Bloom filter, one Bloom filter stores forward data (e.g., inserted elements), and the other Bloom filter stores reverse data (e.g., deleted elements). When an element is inserted, it is inserted into both the forward and reverse Bloom filters. To check if an element exists, both the forward and reverse Bloom filters need to be checked simultaneously; only if both filters determine that the element may exist can it be determined that the element exists.

[0089] like Figure 10 As shown, when the size of the first and second memory groups is the same as the size of the memory block, a mapping table reflecting the correspondence between the logical addresses and physical addresses of the first and second memory groups is stored in the SRAM of the memory controller. Figure 10 The LBAID shown is the logical block address of a different first memory group within a memory area. When a new LBA is accessed, the corresponding LBA ID (e.g., ...) is used to access the memory. Figure 10 The LBAID3 shown will be inserted into the forward Bloom filter CBF1 and the reverse Bloom filter CBF2. Specifically, LBAID3 is used as input, and three hash values ​​(H1, H2, H3) are calculated using three different hash functions. The corresponding bit in the bit array of the forward Bloom filter is set to 1, indicating that LBAID3 exists in the forward Bloom filter CBF1. Similarly, LBAID3 is used as input, and three hash values ​​are calculated using three different hash functions. The corresponding bit in the bit array of the reverse Bloom filter CBF2 is set to 1, indicating that LBAID3 exists in the reverse Bloom filter CBF2.

[0090] Subsequent alternating queries on the forward Bloom filter CBF1 and the reverse Bloom filter CBF2 can be performed using the same hash function to calculate the hash value and check whether the corresponding bit is 1 to determine whether the corresponding LBAID3 exists in the forward Bloom filter CBF1 and the reverse Bloom filter CBF2.

[0091] For example, with the element to be queried (e.g., LBA ID3) as input, multiple hash values ​​are calculated using the hash function of the forward Bloom filter CBF1 at second 0. In the bit array of the forward Bloom filter CBF1, it is checked whether all bits of the corresponding calculated hash value are 1. If any bit is 0, it can be determined that the element does not exist in the forward Bloom filter CBF1, and the group write count is not increased.

[0092] Using the element to be queried (e.g., LBA ID3) as input, multiple hash values ​​are calculated using the hash function of the forward Bloom filter CBF1. In the bit array of the forward Bloom filter CBF1, it is checked whether all bits of the corresponding calculated hash value are 1. If any bit is 0, it can be determined that the element does not exist in the forward Bloom filter CBF1, and the group write count does not increase. At second 1, using the element to be queried (e.g., LBA ID3) as input, multiple hash values ​​are calculated using the hash function of the reverse Bloom filter CBF2. In the bit array of the reverse Bloom filter CBF2, it is checked whether all bits of the corresponding calculated hash value are 1. If any bit is 0, it can be determined that the element does not exist in the reverse Bloom filter CBF2, and the group write count does not increase.

[0093] Thus, after alternating queries of the forward Bloom filter CBF1 and the reverse Bloom filter CBF2, if all the corresponding hash values ​​in both the forward Bloom filter CBF1 and the reverse Bloom filter CBF2 are 1, it indicates that the element may exist in the double Bloom filter, and the group write count of the first storage group corresponding to LBA ID3 increases.

[0094] Dual Bloom filters can store massive amounts of group write counts for both the first and second memory groups, avoiding excessive consumption of storage system resources. Furthermore, by using the relationship between the group write counts and a first preset threshold, they help perform wear leveling, thereby improving the lifespan and performance of non-volatile memory.

[0095] In some embodiments, during the process of alternately querying two Bloom filters, the previous Bloom filter can be cleared after each query so that the Bloom filter state can be reset for the next query.

[0096] like Figure 10 As shown, at second 0, the forward Bloom filter CBF1 is queried. Using the element to be queried as input, multiple hash values ​​are calculated using the hash function of the forward Bloom filter CBF1. The bit array of the forward Bloom filter CBF1 is checked to see if all bits of the corresponding calculated hash value are 1. If any bit is 0, it can be determined that the element does not exist in the forward Bloom filter CBF1. After the query ends at second 0, the bit array of the forward Bloom filter CBF1 is cleared, and the state of the forward Bloom filter CBF1 is reset for use in the next query.

[0097] In the first second, the reverse Bloom filter CBF2 is queried. Using the element to be queried as input, multiple hash values ​​are calculated using the hash function of CBF2. The bit array of CBF2 is checked to see if all bits of the corresponding calculated hash value are 1. If any bit is 0, it can be determined that the element does not exist in CBF2. After the first second of querying, the bit array of CBF2 is cleared, and the state of both the forward and reverse Bloom filters CBF2 is reset for use in the next query.

[0098] At subsequent time points, the two Bloom filters are queried alternately, and previously queried Bloom filters are cleared to achieve periodic query operations. In this way, through the above-mentioned alternating query and clearing operations, interference from previous query information to subsequent queries can be avoided, and the memory usage of Bloom filters can also be reduced.

[0099] In this embodiment of the disclosure, the storage system includes a storage-class memory (SCM); the non-volatile memory includes a phase-change memory.

[0100] In the existing storage hierarchy, there is a gap in storage speed and capacity between Dynamic Random Access Memory (DRAM) and non-volatile memory (e.g., NAND flash memory), limiting further improvements in computing power. To address this, a storage-level memory that places its storage speed and capacity between DRAM and non-volatile memory is proposed. For example, the storage densities of DRAM, PCM, and NAND can be 1X, 1X to 4X, and 4X respectively; the read latency of DRAM, PCM, and NAND can be 50 nanoseconds, 50 to 100 nanoseconds, and 10 to 25 microseconds respectively. It can be seen that the storage speed (read latency and write latency) and storage capacity (storage density) of PCM allow it to occupy a good position between DRAM and non-volatile memory, serving as an intermediate memory.

[0101] Currently, there are many types of storage media for storage-class memory, with the most mainstream including phase-change memory, resistive random access memory, magnetic random access memory, and carbon nanotube random access memory.

[0102] The storage system in this embodiment divides each storage area of ​​the non-volatile memory into a first region supporting physical addressing and a second region not supporting physical addressing. During wear leveling, a first storage group with a first set of write counts is swapped with a second storage group with a second set of write counts. This transfers the first storage group with the first set of write counts from the first region to the second region, preventing the first storage group with the largest set of write counts from remaining in the first region supporting physical access after wear leveling. This avoids the risk of the first storage group with the largest set of write counts still being physically accessed after wear leveling. This effectively improves the wear leveling effect of non-volatile memory, such as phase-change memory, resists malicious program attacks, and extends service life.

[0103] According to a second aspect of the present disclosure, a method for operating a storage system is provided. The storage system includes: a non-volatile memory and a memory controller coupled to the non-volatile memory. The non-volatile memory includes a plurality of storage regions, each storage region including a plurality of first storage groups located in a first region and a plurality of second storage groups located in a second region. The first region supports physical addressing, and the second region does not support physical addressing. The method for operating the storage system includes:

[0104] Wear leveling is performed by swapping a first storage group with a first set of write counts with a second storage group with a second set of write counts; the first set of write counts is the largest set of write counts among the multiple sets of write counts corresponding to the multiple first storage groups, and the second set of write counts is the smallest set of write counts among the multiple sets of write counts corresponding to the multiple second storage groups.

[0105] For example, non-volatile memory can be divided into multiple memory regions, and then each memory region can be divided into multiple memory groups. Both the first and second memory groups include a second number of memory cells. The size of the first and second memory groups is the same as the size of a codeword, where the codeword includes user data, error correction codes (ECC), and metadata. A codeword may include multiple memory cells, and the number of memory cells included in a codeword can be adjusted according to actual needs.

[0106] In one specific implementation, the error correction code (ECC) is 256 bytes in size, and the codeword size is 4 KB. It can be understood that the first and second memory groups are also 4 KB in size. Taking the non-volatile memory 110 as a phase-change memory as an example, the second group size is 2. 12 .

[0107] In some embodiments, the ratio of the first quantity to the second quantity is in the range of 2. 4 Up to 2 12 For example, the ratio of the first quantity to the second quantity ranges from 2.4 2 8 Or 2 12 .

[0108] In some embodiments, the size of the first and second storage groups can be the same as the size of a storage block. Typically, a storage block is 512KB (4KB * 2). 7 ) or 1024KB (4KB*2) 8 (and even larger.) It is understandable that a storage block can include multiple storage units, and the number of storage units included in a storage block can be adjusted according to the actual situation.

[0109] In one specific embodiment, the size of the storage block is 1024KB. It can be understood that the size of the first storage group and the second storage group is also 1024KB. Taking the non-volatile memory 110 as a phase-change memory as an example, then the first quantity is 2. 20 .

[0110] It should be noted that the first and second quantities in the above embodiments are merely examples. The storage area, the first storage group, and the second storage group can be divided into different sizes according to the actual size and type of the non-volatile memory.

[0111] It is understood that the first storage group and the second storage group, comprising a first number of storage cells, have a first granularity level, and the first storage group and the second storage group, comprising a second number of storage cells, have a second granularity level. In the embodiments of this disclosure, wear leveling processing of non-volatile memory can be performed at different granularity levels, which can greatly improve the flexibility and fineness of wear leveling processing of non-volatile memory.

[0112] Figure 11 This is a flowchart illustrating an operation method of a storage system provided in an embodiment of this disclosure. The following will be combined with... Figures 3 to 9 as well as Figure 11 This section provides a detailed explanation of how to perform wear leveling.

[0113] like Figure 11 As shown, in step S101, the memory controller acquires a first preset threshold, multiple group write counts of multiple first storage groups, and multiple group write counts of multiple second storage groups.

[0114] In step S102, the first group write count is compared with a first preset threshold to determine whether the first group write count is greater than the first preset threshold. The first group write count is the maximum value among all group write counts of the first storage group.

[0115] If the write count of the first group is less than or equal to the first preset threshold, then step S104 is executed, that is, wear leveling is not performed.

[0116] If the write count of the first group is greater than the first preset threshold, then step S103 is executed. In step S103, the write count of the first group is compared with the write count of the second group, where the write count of the first group is the minimum value among all group write counts of the second storage groups. It is then determined whether the write count of the first group is greater than the write count of the second group. (Reference) Figure 3 and Figure 4 The group write count of the first memory group corresponding to the physical address 2 mapped by logical address 2 is 6K. This group write count is the maximum value among all group write counts of the first memory group, i.e., the first group write count is 6K. The group write count of the second memory group corresponding to the physical address M mapped by logical address M is 5K. This group write count is the minimum value among all group write counts of the second memory group, i.e., the second group write count is 5K.

[0117] When the write count of the first group is greater than the write count of the second group, step S105 is executed, which performs wear leveling by swapping the data stored in the first storage group with the first group write count and the data stored in the second storage group with the second group write count; and by swapping the logical address of the first storage group with the first group write count and the logical address of the second storage group with the second group write count.

[0118] refer to Figure 5 and Figure 6 Wear leveling is performed by swapping the data stored in the first storage group corresponding to the physical address 2 mapped by logical address 2 and the data stored in the second storage group corresponding to the physical address M mapped by logical address M; and swapping the logical address of the first storage group corresponding to physical address 2 and the logical address of the second storage group corresponding to physical address M.

[0119] like Figure 5 and Figure 6 As shown, after wear leveling, physical address 2 corresponds to logical address M, and physical address M corresponds to logical address 2. Since the first storage group with the first set of write counts is swapped to the second region that does not support physical access, the first storage group with the first set of write counts will not be physically accessed in subsequent write operations. It can be understood that the storage system in this embodiment can resist malicious attacks when performing wear leveling.

[0120] When the write count of the first group is less than or equal to the write count of the second group, step S106 is executed. In step S106, the data stored in the first storage group with the first group write count and the data stored in the first storage group with the third group write count are swapped; and the logical address of the first storage group with the first group write count and the logical address of the first storage group with the third group write count are swapped to perform wear leveling.

[0121] refer to Figure 4 and Figure 7 The group write count of the first memory group corresponding to physical address 2, mapped to logical address 2, is 4K. This group write count is the maximum value among all first memory groups, meaning the first group write count is 4K. The group write count of the second memory group corresponding to physical address M, mapped to logical address M, is 5K. This second memory group write count is the minimum value among all second memory groups, meaning the second group write count is 5K. The first group write count is less than the second group write count.

[0122] The group write count of the first storage group corresponding to the physical address 7 mapped by logical address 7 is 6. The group write count of the first storage group is the minimum value among all the group write counts of the first storage groups, that is, the write count of the third group is 6.

[0123] refer to Figure 8 and Figure 9 Wear leveling is performed by swapping the data stored in the first storage group corresponding to the physical address 2 mapped by logical address 2 and the data stored in the first storage group corresponding to the physical address 7 mapped by logical address 7; and swapping the logical address of the first storage group corresponding to physical address 2 and the logical address of the second storage group corresponding to physical address 7.

[0124] like Figure 8 and Figure 9 As shown, after wear leveling, physical address 2 corresponds to logical address 7, and physical address 7 corresponds to logical address 2. Since the first group of write counts is less than the second group of write counts, it means that the first storage group with the first group of write counts can still withstand a certain number of write operations. Therefore, by swapping the first storage group with the largest group of write counts and the first storage group with the smallest group of write counts in the first region to perform wear leveling, the wear level of multiple first storage groups can be balanced.

[0125] After executing step S105 or step S106, step S107 is executed, which is to update the mapping table between the logical address and physical address of each storage group in the storage area after wear leveling.

[0126] In some embodiments, when both the first and second storage groups include a first number of storage cells, the mapping table between the logical and physical addresses of each storage group in the storage region is updated after wear leveling, and the mapping table is stored in the volatile memory of the memory controller 120. Exemplarily, when both the first and second storage groups include a first number of storage cells, Figure 4 and Figure 6The mapping table shown is stored in the volatile memory of the memory controller 120.

[0127] In other embodiments, when both the first storage group and the second storage group include a second number of storage cells; after wear leveling, the mapping table between the logical and physical addresses of each storage group in the storage region is updated, and the mapping table is stored in the non-volatile memory 110. Exemplarily, when both the first and second storage groups include a second number of storage cells, Figure 4 and Figure 6 The mapping table shown is stored in the metadata of the non-volatile memory 110 of the memory controller 120.

[0128] refer to Figure 12 , Figure 12 This is a block diagram of a computer-readable storage medium provided according to an embodiment of the present disclosure. Figure 12 As shown, this disclosure provides a readable storage medium 200 storing a computer program 210. When executed by a processor, the computer program 210 can implement the operation method of the storage system as described above. The operation method includes: performing wear leveling by exchanging a first storage group having a first set of write counts with a second storage group having a second set of write counts; the first set of write counts is the largest group write count among multiple group write counts corresponding to multiple first storage groups, and the second set of write counts is the smallest group write count among multiple group write counts corresponding to multiple second storage groups.

[0129] refer to Figure 13 , Figure 13 This is a block diagram of a system provided according to an embodiment of the present disclosure. Figure 13 As shown, system 300 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, or any other suitable electronic device having non-volatile memory 310 (e.g., PCM).

[0130] like Figure 13 As shown, system 300 may include a host 330 and a storage system, the storage system including a memory controller 320 and at least one non-volatile memory 310. The host 330 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 330 may be configured to send data to or receive data from the non-volatile memory 310. Figure 13The illustration shows that the memory controller 320 is connected to four non-volatile memories 310. In fact, the present disclosure does not impose a special limitation on the number of non-volatile memories 310 connected to the memory controller 320. The number of non-volatile memories 310 connected to the memory controller 320 may be less than four (e.g., one); or the number of non-volatile memories 310 connected to the memory controller 320 may be greater than four (e.g., five).

[0131] In some embodiments, the memory controller 320 may be connected to the host 330 and the non-volatile memory 310, and is configured to control the non-volatile memory 310. The memory controller 320 may manage the data stored in the non-volatile memory 310 and communicate with the host 330.

[0132] In one specific example, the storage system may include at least one non-volatile memory 310 and a memory controller 320 coupled to the non-volatile memory 310; wherein, the storage system may include storage-class memory; the non-volatile memory 310 may include phase-change memory.

[0133] Still referencing Figure 13 As shown, the memory controller 320 includes a first communication interface 321, a second communication interface 322, a processing unit 323, a read-only memory (ROM) 324, a static random access memory (SRAM) 325, and a storage medium controller 326. The processing unit 323 and the host 330 communicate via the first communication interface 321 and the second communication interface 322. The processing unit 323 can also be connected to the storage medium controller 326 to control the storage medium controller 326. The storage medium controller 326 is connected to the non-volatile memory 310 to control the non-volatile memory 310. The processing unit 323 can also be connected to the read-only memory 324 and the SRAM 325. The processing unit 323 can retrieve data from the read-only memory 324 and can store some temporary data in the SRAM 325.

[0134] In some embodiments, the first communication interface 321 can be a Peripheral Component Interconnect Express (PCIE), that is, the first communication interface can be an interface set according to the high-speed serial computer expansion bus standard; the second communication interface 322 can be a Compute Express Link (CXL).

[0135] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0136] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A storage system, comprising: A non-volatile memory includes multiple memory regions, each memory region including multiple first memory groups located in a first region and multiple second memory groups located in a second region, the first region supporting physical addressing and the second region not supporting physical addressing; as well as A memory controller coupled to the non-volatile memory is configured to: compare a first set of write counts with a first preset threshold; when the first set of write counts is greater than the first preset threshold, compare the first set of write counts with a second set of write counts; and perform wear leveling by swapping a first memory group with the first set of write counts with a second memory group with the second set of write counts; wherein the first set of write counts is the largest set of write counts among the multiple sets of write counts corresponding to the plurality of first memory groups, and the second set of write counts is the smallest set of write counts among the multiple sets of write counts corresponding to the plurality of second memory groups; the first preset threshold increases as the electrical distance between the first memory group corresponding to the first set of write counts and the voltage source increases.

2. The storage system according to claim 1, wherein, The memory controller is specifically configured as follows: Compare the first group of write counts with the second group of write counts; When the first group of write counts is greater than the second group of write counts, wear leveling is performed by swapping the first storage group with the first group of write counts with the second storage group with the second group of write counts.

3. The storage system according to claim 2, wherein, The memory controller is also configured to: When the first group of write counts is less than or equal to the second group of write counts, wear leveling is performed by swapping the first storage group with the first group of write counts with the third group of write counts; wherein, the third group of write counts is the smallest group of write counts among the multiple group write counts corresponding to the multiple first storage groups.

4. The storage system according to claim 3, wherein, The memory controller is specifically configured as follows: Wear leveling is performed by swapping data stored in the first storage group with a first set of write counts and data stored in the second storage group with a second set of write counts; and by swapping the logical address of the first storage group with a first set of write counts and the logical address of the second storage group with a second set of write counts. or, By swapping the data stored in the first storage group having a first set of write counts with the data stored in the first storage group having a third set of write counts; Wear leveling is performed by swapping the logical address of the first storage group with the first set of write counts and the logical address of the first storage group with the third set of write counts.

5. The storage system according to claim 4, wherein, Both the first storage group and the second storage group include a first number of storage cells; the memory controller is configured to: update the mapping table between the logical address and the physical address of each storage group in the storage area after the wear leveling process, and store the mapping table in the volatile memory of the memory controller; or, Both the first storage group and the second storage group include a second number of storage cells; the memory controller is configured to update the mapping table between the logical address and the physical address of each storage group in the storage area after the wear leveling process, and store the mapping table in the non-volatile memory; The first quantity is greater than the second quantity.

6. The storage system according to claim 5, wherein, The group write count is obtained by counting using a dual Bloom filter.

7. The storage system according to claim 1, wherein, The storage system includes a storage-class storage system; the non-volatile memory includes a phase-change memory.

8. A method of operating a storage system, the storage system comprising a non-volatile memory and a memory controller coupled to the non-volatile memory, the non-volatile memory comprising a plurality of storage regions, each storage region comprising a plurality of first storage groups located in a first region and a plurality of second storage groups located in a second region, the first region supporting physical addressing and the second region not supporting physical addressing; the method of operating the system comprising: The first group of write counts is compared with a first preset threshold. When the first group of write counts is greater than the first preset threshold, the first group of write counts is compared with a second group of write counts. Wear leveling is performed by swapping the first storage group with the first group of write counts with the second group of write counts. The first group of write counts is the largest group of write counts among the multiple group write counts corresponding to the multiple first storage groups, and the second group of write counts is the smallest group of write counts among the multiple group write counts corresponding to the multiple second storage groups. The first preset threshold increases as the electrical distance between the first storage group corresponding to the first group of write counts and the voltage source increases.

9. The operating method according to claim 8, wherein, The operation method further includes: Compare the first group of write counts with the second group of write counts; When the first group of write counts is greater than the second group of write counts, wear leveling is performed by swapping the first storage group with the first group of write counts with the second storage group with the second group of write counts.

10. The operating method according to claim 9, wherein, The operation method further includes: When the first group of write counts is less than or equal to the second group of write counts, wear leveling is performed by swapping the first storage group with the first group of write counts with the third group of write counts; wherein, the third group of write counts is the smallest group of write counts among the multiple group write counts corresponding to the multiple first storage groups.

11. The operating method according to claim 10, wherein, The operation method further includes: Wear leveling is performed by swapping data stored in the first storage group with a first set of write counts and data stored in the second storage group with a second set of write counts; and by swapping the logical address of the first storage group with a first set of write counts and the logical address of the second storage group with a second set of write counts. or, Wear leveling is performed by swapping the data stored in the first storage group with a first set of write counts and the data stored in the first storage group with a third set of write counts; and by swapping the logical address of the first storage group with a first set of write counts and the logical address of the first storage group with a third set of write counts.

12. The operating method according to claim 11, wherein, Both the first storage group and the second storage group include a first number of storage cells; the operation method further includes: updating the mapping table between the logical address and the physical address of each storage group in the storage area after the wear leveling process, and storing the mapping table in the volatile memory of the memory controller; or, Both the first storage group and the second storage group include a second number of storage cells; the operation method further includes: updating the mapping table between the logical address and the physical address of each storage group in the storage area after the wear leveling process, and storing the mapping table in the non-volatile memory; The first quantity is greater than the second quantity.

13. A computer-readable storage medium having a computer program stored thereon, the computer program performing the operating method as described in any one of claims 8 to 12 when executed by a processor.

Images