Circuit package with bump interconnect polymer enclosure and method of manufacture

Abstract

A circuit package having a polymer layer surrounding bump interconnects reduces the number of shorts between bump interconnects and reduces underlying filler delamination. The circuit package includes a first component coupled to a second component through a plurality of bump interconnects for communicating logic signals, data signals, and / or power. Bump interconnects extend from a surface of the first component and are coupled to contact pads on an opposing surface of the second component. A side surface of the bump interconnect extends in a direction from the second component to the first component. The circuit package includes a polymer layer disposed on a surface of the first component surrounding the bump interconnect and on a side surface of the bump interconnect. The polymer layer reduces shorting between side surfaces of adjacent bump interconnects and reduces delamination of underfill disposed between the first component and the second component.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 17 / 934,023, filed on September 21, 2022, entitled “CIRCUIT PACKAGES WITH BUMPINTERCONNECT POLYMER SURROUND AND METHOD OF MANUFACTURE,” which is incorporated herein by reference in its entirety. Background Art I. Technical field

[0003] The technology of the present disclosure relates generally to semiconductor packaging, and more particularly to flip chip packaging with bump interconnects.

[0004] II. Background Technology

[0005] Electronic devices (such as cellular phones, laptop computers and tablet computers) are powered by semiconductor devices, which continue to increase in performance even when their physical size is reduced. Semiconductor devices are included in circuit packages inside electronic devices. Semiconductor devices may include various components, including analog circuits, digital processing logic circuits and memory circuits coupled to each other in circuit packages. These components also need to be interconnected to other packages, external memory, power supplies, media ports and / or input / output devices, which involve many electrical interconnects to transmit clock signals, logic and control signals, data signals and / or power supply voltage signals. Bump interconnects can be used to transmit signals between semiconductor dies arranged face to face in a flip chip configuration. Bump interconnects are usually arranged in an array on a first component and interconnected with an array of contact pads on the opposite surface of a second component. The arrays are aligned with each other so that the solder tips of the bump interconnects correspond to the contact pads. The solder is heated and the components are pressed together. When the solder cools, both mechanical bonding and electrical connection are formed between the bump interconnects and the contact pads. As electronic devices decrease in size, the size of circuit packages and the bump interconnects that connect them also decreases, which poses new challenges in package manufacturing. Summary of the invention

[0006] Aspects disclosed herein include circuit packages with bump interconnect polymer layers. Related methods for manufacturing circuit packages are also disclosed. An exemplary circuit package includes a first component coupled to a second component. The components are coupled to each other through a plurality of bump interconnects for transmitting logic signals, data signals and / or power. The bump interconnects extend from the surface of the first component and are coupled to contact pads on the opposite surface of the second component. In this regard, the side surface of the bump interconnects extends in a certain direction between the first component and the second component. The circuit package also includes a polymer layer disposed on the surface of the first component around the bump interconnects. In exemplary aspects, the polymer layer is also disposed on the side surface of the bump interconnects. In some examples, the bump interconnects are disposed at fine pitches, and the polymer layer reduces the occurrence of short circuits between the side surfaces of adjacent bump interconnects. The polymer layer electrically insulates adjacent bump interconnects from each other. Therefore, for example, in the case where solder from a solder tip contacts adjacent bump interconnects, the polymer layer can prevent electrical short circuits between the bump interconnects. In this way, the manufacture of circuit packages can increase yields. In some examples, an underfill is also disposed between the first component and the second component, and the polymer layer can reduce delamination of the underfill from the first surface.

[0007] In this regard, in one aspect, a circuit package is disclosed. The circuit package includes a first component and a second component, the first component includes a plurality of contact pads on a first surface, and the second component includes a plurality of bump interconnects on a second surface. Each of the plurality of bump interconnects is coupled to one of the plurality of contact pads on the first surface of the first component, and includes a side surface extending along a first direction between the first component and the second component. The circuit package also includes a polymer layer disposed on the second surface of the second component and on the side surface of each of the plurality of bump interconnects, surrounding each of the plurality of bump interconnects.

[0008] In another exemplary aspect, a method for manufacturing a circuit package is disclosed. The method includes: forming a first component including a plurality of contact pads on a first surface, and forming a second component including a plurality of bump interconnects on a second surface, wherein each of the plurality of bump interconnects is coupled to one of the plurality of contact pads on the first surface, and includes a side surface extending along a first direction orthogonal to the second surface. The method also includes: forming a passivation layer disposed on the second surface around each of the plurality of bump interconnects; and forming a polymer layer disposed on the passivation layer around each of the plurality of bump interconnects, and on the side surface of each of the plurality of bump interconnects.

[0009] In another exemplary aspect, a semiconductor die configured to be coupled to a circuit package is disclosed. The semiconductor die includes a plurality of bump interconnects on a surface of the semiconductor die, wherein each of the plurality of bump interconnects is configured to be coupled to a corresponding contact pad on a surface of a circuit component of the circuit package. Each of the plurality of bump interconnects includes: a side surface extending from the semiconductor die; and a polymer layer disposed on the surface of the semiconductor die and on the side surfaces of the plurality of bump interconnects, surrounding each of the plurality of bump interconnects. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional side view of an exemplary circuit package including a first component and a second component coupled with a bump interconnect surrounded by a polymer layer;

[0011] FIG. 2A to FIG. 2C is a diagrammatic representation of a circuit package during a manufacturing stage according to a conventional bulk reflow process;

[0012] FIG. 3A to FIG. 3B is a diagram of a circuit package in a manufacturing stage according to a first conventional thermal compression (TC) process;

[0013] FIG. 4A to FIG. 4B is a diagram of a circuit package in a manufacturing stage according to a second conventional TC process;

[0014] Figure 5 is based on FIG. 2A to FIG. 2C A cross-sectional side view of a bump interconnect of a conventional bulk reflow process as illustrated in FIG.

[0015] Figure 6 is based on FIG. 3A to FIG. 3B and FIG. 4A to FIG. 4B A cross-sectional side view of a bump interconnect of an illustrated conventional thermal compression process;

[0016] Figure 7 is an example for manufacturing Figure 1 A high-level flow chart of an exemplary circuit packaging method in;

[0017] FIG. 8A to FIG. 8C is a flow chart of a method for forming a circuit assembly, the circuit assembly comprising a circuit assembly for Figure 1 A bump interconnect surrounded by a polymer layer of a circuit package;

[0018] 9A to 9C yes FIG. 8A to FIG. 8C an illustration of a cross section of a component and bump interconnect at the manufacturing stages described in the flowchart in;

[0019] Fig.10 is a cross-sectional side view of a first example of a package assembly including a Figure 1 Bump interconnects used in circuit packaging;

[0020] Fig.11 is available in Figure 1 a cross-sectional side view of a second example of a package assembly bump interconnect employed in a circuit package of;

[0021] Fig.12 Yes, it can include Figure 1 A block diagram of an exemplary wireless communication device of a circuit package of FIG. 1 ; and

[0022] Fig.13 Yes, it can include Figure 1 A block diagram of an exemplary processor-based system of a circuit package. DETAILED DESCRIPTION

[0023] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] Aspects disclosed herein include circuit packages with bump interconnect polymer layers. Related methods for manufacturing circuit packages are also disclosed. An exemplary circuit package includes a first component coupled to a second component. The components are coupled to each other through a plurality of bump interconnects for transmitting logic signals, data signals and / or power. The bump interconnects extend from the surface of the first component and are coupled to contact pads on the opposite surface of the second component. The side surface of the bump interconnects extends in a certain direction between the first component and the second component. The circuit package also includes a polymer layer disposed on the surface of the first component around the bump interconnects. In exemplary aspects, the polymer layer is also disposed on the side surface of the bump interconnects. In some examples, the bump interconnects are disposed at fine pitches, and the polymer layer reduces the occurrence of short circuits between the side surfaces of adjacent bump interconnects. The polymer layer electrically insulates adjacent bump interconnects from each other. Therefore, for example, in the case where solder from a solder tip contacts adjacent bump interconnects, the polymer layer can prevent electrical short circuits between the bump interconnects. In this way, the manufacture of circuit packages can increase yields. In some examples, an underfill is also disposed between the first component and the second component, and the polymer layer can reduce delamination of the underfill from the first surface.

[0025] Figure 11 is a cross-sectional side view of an exemplary circuit package 100 including a first component 102 and a second component 104, which are coupled to each other through a bump interconnect 106. The first component 102 and the second component include a circuit (not shown) electrically coupled to each other through the bump interconnect 106. The circuit on each of the first component 102 and the second component 104 can be a passive or active circuit, wherein the active circuit can include a transistor circuit, and the passive circuit includes a passive component (e.g., a resistor, a capacitor, and an inductor) and an electrical interconnect (such as a lead trace and a via). For example, the second component 104 can be a semiconductor die (e.g., a chip) including a transistor circuit, and the first component 102 can be another semiconductor die including an active circuit. The first component 102 can be an interposer or a package substrate for interconnecting the second component 104 to another semiconductor die (not shown) or other components in an electronic device or system. The first component 102 and the second component 104 can be any other type of component in a circuit package using a bump interconnect 106. The bonding of components in a circuit package such as circuit package 100 may be referred to as flip chip (FC) bonding.

[0026] The bump interconnect 106 extends from the second surface 108 on the second component 104 to the contact pad 110 on the first surface 112 of the first component 102. The side surface 114 of the bump interconnect 106 extends between the second component 104 and the first component 102. That is, the side surface extends from the second surface 108 of the second component 104 toward the first surface 112 of the first component 102. Figure 1 As explained in further detail below, the circuit package 100 further includes a polymer layer 116 disposed on the second surface 108 around the bump interconnect 106 and also disposed on the side surface 114 of the bump interconnect 106 .

[0027] Each bump interconnect 106 includes a column 118, a contact pad 120, and a solder tip 122. The contact pad 120 is located on the second surface 108 of the second component 104 and has a pad surface 124 coupled to the column 118. The column 118 includes a base end 126 coupled to a contact area 128 of the pad surface 124. The base end 126 of the column 118 contacts the pad surface 124 in the contact area 128. The side surface 114 of the column 118 of the bump interconnect 106 extends from the pad surface 124. The contact area 128 may be larger than the base end 126. Therefore, the pad surface 124 also includes a second area 130 surrounding all or at least a portion of the contact area 128. The column 118 also includes a contact end 132 opposite to the base end 126. The bump interconnect 106 includes a solder tip 122 disposed on the contact end 132. During the manufacturing process, when the second component 104 and the first component 102 are positioned together, the solder tip 122 disposed on the contact end 132 is aligned with and can contact the contact pad 110. The solder tip 122 is heated (e.g., melted, softened) to a fluid state so that the solder of the solder tip 122 adheres to the contact pad 110 on the first component 102. When the solder tip 122 is cooled and solidified, the solder tip 122 electrically couples the post 118 and the contact pad 110, and can also create a mechanical bond between the contact end 132 of the post 118 and the contact pad 110.

[0028] As semiconductor packaging technology advances, the pitch P of the bump interconnect 106 100 The reduction allows the side surfaces 114 of the bump interconnects 106 to be closer to each other during the manufacturing process. In conventional circuit packages using bump interconnects with fine pitches, an electrical short circuit may be formed by a portion of a solder tip contacting the side surfaces of two adjacent bump interconnects.

[0029] In the exemplary aspects disclosed herein, the circuit package 100 includes a polymer layer 116 disposed on the side surfaces 114 of the bump interconnects 106, thereby electrically insulating the bump interconnects 106 from each other. Thus, the polymer layer 116 can prevent electrical shorts in the event that solder from the solder tips 122 contacts adjacent bump interconnects 106. In this way, the manufacturing of the circuit package 100 can improve yields.

[0030] The polymer layer 116 is also disposed on the second surface 108 of the second component 104, surrounding each bump interconnect 106. On the second surface 108, the thickness T measured along the Y-axis direction 116 The polymer layer 116 is disposed. In contrast, the polymer layer 116 disposed on the side surface 114 of the bump interconnect 106 is thicker than the thickness T in the Y-axis direction (eg, in the direction from the second surface 108 toward the first surface 112). 116In other words, the thickness T of the polymer layer 116 on the second surface 108 is 116 The side surface 114 of the bump interconnect 106 extends a distance DY1 in the Y-axis direction. The side surface 114 of the bump interconnect 106 extends an additional distance DY2 beyond the distance DY1 in the Y-axis direction. The polymer layer 116 disposed on the side surface 114 of each of the plurality of bump interconnects 106 extends in the Y-axis direction beyond the first thickness T 116 at least half of the additional distance DY2 (eg, distance DY1).

[0031] On the other hand, the circuit package 100 includes an underfill 134 that fills the space between the first component 102 and the second component 104 around the bump interconnect 106. For example, the underfill 134 can be an organic material in the form of a paste or a film. In some examples, the underfill 134 can be referred to as a molding compound. As further explained below, the circuit package 100 also includes a passivation layer 136 formed on the second surface 108 of the second component 104, surrounding the bump interconnect 106. In this regard, the polymer layer 116 can be disposed between the underfill 134 and the passivation layer 136. The polymer layer 116 can be an organic material, such as a polyimide, which has a better bond with the underfill 134 than the underfill 134 has with the passivation layer 136. In some examples, the underfill 134 can be an organic material, and the organic polyimide of the polymer layer 116 has a better bond with the underfill 134 than the underfill 134 has with the passivation layer 136 without the polymer layer 116. In this manner, polymer layer 116 may also reduce delamination of underfill 134 from second component 104. As explained below, polymer layer 116 need not be formed of a photopolymer material, and thus may not include a photopolymer material, which reduces the cost of polymer layer 116.

[0032] Further references Figure 1 The first surface 112 may further include a passivation layer 136 and / or other layers disposed around the contact pads 110 to protect the first surface 112 and provide better adhesion to the underfill 134 .

[0033] FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3B as well as FIG. 4A to FIG. 4B is a diagram of a conventional process for manufacturing a circuit package, and Figure 5 and Figure 6 is a diagram of a bump interconnect manufactured according to these processes. Figures 2A to 6 To show and Figure 1 The exemplary circuit package 100 and Figure 7 A to Figure 7 The exemplary method 700 in C forms a contrasting conventional aspect.

[0034] FIG. 2A to FIG. 2C The circuit package 200 is illustrated in a manufacturing stage according to a conventional high volume reflow process. Figure 2A , a first component 202 and a second component 204 are shown. The second component 204 includes bump interconnects 206 on an upper surface 208. The first component 202 includes contact pads 210 on a lower surface 212. The contact pads 210 on the lower surface 212 are arranged in an array pattern corresponding to the array pattern of the bump interconnects 206 on the upper surface 208. The pattern of the bump interconnects 206 may be equal to or greater than a center-to-center pitch P of 60 micrometers (μm), such as 80 μm. 200 The bump interconnect 206 has a diameter equal to or greater than 35 μm. The bump interconnect includes a pillar 218 and a solder tip 222. Figure 5 Further details of the bump interconnect 206 are provided.

[0035] exist Figure 2B In the embodiment of the present invention, the first component 202 and the second component 204 are placed (e.g., on a conveyor) in an oven or heater and heated to a sufficient temperature so that the solder tips 222 become fluid and adhere to the contact pads 210 on the lower surface 212. Upon cooling, the solder tips 222 return to a solid state and form a mechanical bond that electrically couples the bump interconnects 206 to the corresponding contact pads 210.

[0036] exist Figure 2C In the embodiment, an underfill 234 has been injected or otherwise provided to fill the space between the first component 202 and the second component 204 and around the bump interconnect 206. It should be noted that a polymer layer 216 (e.g., an organic polymer) is formed on the upper surface 208 to provide a strong bond to the underfill 234. The bump interconnect 206 includes a pillar 218 coupled to the contact pad 220. The polymer layer 216 is also provided to reduce the FIG. 2A to FIG. 2C The stress caused by the pillars 218 and the contact pads 220 expanding and contracting at different rates during the heating and cooling phases of the process in FIG. Figure 5 further discussed.

[0037] As described above, technological improvements have reduced the size of semiconductor dies, interposers, substrates, etc., but the number of input and output connections to such components may remain the same or even increase. As a result, arrays of bump interconnects having finer pitches (e.g., in the range of 20 μm to 30 μm, and more specifically, 25 μm) and diameters in the range of 10 μm to 20 μm (e.g., 13 μm) have been developed.

[0038] FIG. 3A to FIG. 3Bis an illustration of a circuit package 300 in a stage of manufacturing according to a first conventional thermal compression process. The thermal compression process is used for a circuit package 300 that employs fine pitch bump interconnects 306. Due in part to the smaller pitch of the bump interconnects 306, the difficulties associated with manufacturing using a high volume reflow process increase. FIG. 3A to FIG. 3B In the illustrated thermal compression (TC) process, the circuit package 300 is manufactured in smaller batches using the apparatus 340. Figure 3A As shown, the device 340 picks up and holds the second component 304, and heats the second component 304 to soften (e.g., to a fluid state) the solder tip 322. The second component 304 is pressed against the first component 302, thereby compressing the solder tip 322 to the contact pad 310 on the second component 304. When the second component 304 cools, the bump interconnect 306 is bonded to the contact pad 310 on the surface 312. The device 340 is configured to heat the second component 304 without heating the first component 302. Therefore, the first component 302 does not experience a heating and cooling (e.g., expansion and contraction) cycle, which helps to reduce the stress between the bump interconnect 306 and the contact pad 310 on the first surface 308. Figure 3B Circuit package 300 is illustrated after underfill 334 has been added (eg, by injection or otherwise) in the space between first component 302 and second component 304 .

[0039] FIG. 4A to FIG. 4B 4 illustrates a stage of manufacturing a circuit package 400 according to a second conventional thermal compression process. Here, a device 440 heats a second component 404 having bump interconnects 406 on an upper surface 408, such as Figure 3A As shown in FIG. 4 , the device 440 heats the second component 404 to melt the solder tip 422. However, unlike adding the underfill 434 (such as Figures 3A to 3B ), but in Figure 4A At the stage shown in FIG. 4 , an underfill 434 is added or disposed on the surface 412 of the first component 402 . Figure 4B A second component 404 is shown being pressed together with a first component 402 to couple solder tips 422 to contact pads 410 on the first component 402. Bump interconnects 406 may be pushed through underfill 434, and air / gas may be expelled during this process, leaving underfill 434 filling the space between the first component 402 and the second component 404. As shown in FIG. 3A to FIG. 3B In the example of FIG. 4 , the first component 402 does not undergo a heating and cooling cycle, which reduces stress in the bump interconnects 406 in the completed circuit package 400 .

[0040] Because the first components 302 and 402 do not undergo heating and cooling cycles, this reduces stress in the circuit packages 300 and 400, thereby reducing stress on polymer layers such as FIG. 2A to FIG. 2C In addition, FIG. 2A to FIG. 2C The polymer layer 216 in the second component 204 is formed by adding a layer of photosensitive polymer material to the second component 204 and patterning the polymer material using a photolithography method to form openings for the bump interconnects 406. However, as the bump interconnect pitch decreases and the bump interconnect diameter decreases, the size of the openings in the polymer layer 216 will also decrease, and the photolithography method is not able to produce sufficiently small openings in the polymer material for the polymer layer 216.

[0041] As the need for stress reduction provided by the polymer layer 216 decreases with finer pitch bump interconnects, and as the bump interconnect pitch decreases the polymer layer has become more challenging to manufacture, there has been a shift from using a polymer layer 216 based on FIG. 3A to FIG. 3B as well as FIG. 4A to FIG. 4B The circuit packages 300 and 400 manufactured by the thermal compression method omit the polymer layer.

[0042] Figure 5 is a cross-sectional side view of a bump interconnect 500, which is based on FIG. 2A to FIG. 2C 500 is an example of a conventional mass reflow process formed by the illustrated embodiment. That is, the bump interconnect 500 is not a fine pitch bump interconnect, so it can be formed by the mass reflow method described above. The bump interconnect 500 includes a contact pad 502 formed on a component 504. The contact pad 502 is formed of a conductive material (such as a metal). A protective passivation layer 506 is disposed on an upper surface 508 of the component 504 around the contact pad 502. The bump interconnect 500 includes a column 510 and an under-bump metal (UBM) 512 between the column 510 and the contact pad 502. The UBM 512 can provide a better bond to the contact pad 502 than the material of the column 510, which is selected to have a lower resistance (for example).

[0043] As described above, the bump interconnect 500 is larger (e.g., in area) than a fine pitch bump interconnect, and the stress associated with the heating and cooling cycles increases with the area of ​​the bump interconnect 500. To reduce such stress, the contact between the UBM 512 and the contact pad 502 is limited to a region 514 having a smaller diameter than the pillar 510. Limiting the contact area includes forming a passivation layer 506 and a polymer layer 516 on an outer region 518 of the contact pad 502 before forming the UBM 512 on the region 514. In detail, the passivation layer 506 and the polymer layer 516 are respectively disposed on the contact pad 502 and patterned to form an opening corresponding to the region 514. The UBM 512 is formed on the region 514 to couple to the contact pad 502. The UBM also extends outward onto the outer region 518 (e.g., on the polymer layer 516 and the passivation layer 506). In the outer region 518, the UBM 512 has no contact to the contact pad 502, which reduces lateral stress that may be induced between the UBM 512 and the contact pad 502 during heating and cooling cycles. Note that the polymer layer 516 is below the pillar 510 (e.g., between the pillar 510 and the contact pad 502), but not on the side surface 520 of the bump interconnect 500. The bump interconnect 500 also includes a solder tip 522.

[0044] and Figure 5 Compared to the larger pitch bump interconnect 500 shown in FIG. Figure 6 is based on FIG. 3A to FIG. 3B or FIG. 4A to FIG. 4B 6 is a cross-sectional side view of a fine pitch bump interconnect 600 of a conventional thermal compression process as illustrated in FIG. In addition to having a smaller center-to-center distance between adjacent bump interconnects in the bump interconnect array, the diameter of the bump interconnect 600 is also smaller than the diameter of the bump interconnect 500. The bump interconnect 600 includes a contact pad 602 (e.g., a metal pad) disposed on a surface 604 and a passivation layer 606 disposed on the surface 604 surrounding the contact pad 602. As described above, typical photolithographic processing methods cannot pattern a polymer (e.g., polyimide) having an opening that is small enough to produce a limited contact area (e.g., corresponding to a contact pad) for a fine pitch bump interconnect. Figure 5608 and contact pad 602. The area 514 in the embodiment of the present invention is not limited to the area 514 in the embodiment of the present invention. For the use of fine pitch bump interconnects, this prevents the polymer from being used in the same manner as it is used for larger size bump interconnects. Fortunately, because the area of ​​the bump interconnect 600 is small, the contact area with the surface 604 is small, so the amount of stress generated during the heating and cooling cycle is less than the amount of stress generated by the larger bump interconnect. Therefore, there is less need to reduce the contact area between the UBM 608 and the contact pad 602, and the polymer layer without reducing the contact area has no problem in terms of thermal stress. It should be noted that the passivation layer 606 disposed on the surface 604 around the contact 602 can also be disposed on a portion of the contact pad 602, but is not disposed between the UBM 608 and the contact pad 602.

[0045] However, the absence of a polymer layer allows the underfill to be disposed directly on the passivation layer 606. The passivation layer 606 is an inorganic material that does not adhere well to the organic underfill. Therefore, a weaker organic / inorganic bond may increase the incidence of underfill delamination, thereby making an electronic device containing a circuit package having bump interconnects 600 less reliable.

[0046] Figure 7 is an example for manufacturing Figure 1 700 of an exemplary method for a circuit package 100 in FIG. 700. The method includes forming a first component 102 including a plurality of contact pads 110 on a first surface 112 (block 702). The method includes forming a second component 104 including a plurality of bump interconnects 106 on a second surface 112, wherein each of the plurality of bump interconnects 106 is coupled to one of the plurality of contact pads 110 on the first surface 108 and includes a side surface 114 extending in a direction (Y axis) between the second surface 108 and the first surface 112 (block 704). The method also includes forming a polymer layer 116 disposed on the side surface 114 of each of the plurality of bump interconnects 106 and on the second surface 108 of the second component 104, surrounding each of the plurality of bump interconnects 106 (block 706).

[0047] FIG. 8A to FIG. 8C is used to form Figure 1 8. A flow chart of exemplary aspects of a method 800 of a second component 104 of a circuit package 100 in an embodiment of the present invention is provided, the second component including a bump interconnect 106 surrounded by a polymer layer 116. 9A to 9C is an illustration of a cross-section of the second component 104 at the manufacturing stages 900A- 900C described in process blocks 802 , 804 , and 806 , respectively. 9A to 9C Zhongyu Figure 1 Identical features will be numbered identically.

[0048] Fig. 8A The method of forming a bump interconnect 106 on a second surface 108 includes forming a contact pad 120 surrounded by a passivation layer 136 on the second surface 108, forming a pillar 118 on the contact pad 120, and forming a solder tip 122 on the pillar 118 (block 802), as shown in FIG. Fig. 9A These steps of method 800 may be performed according to conventional processes.

[0049] Figure 8B The formation of a polymer layer 116 on the second surface 108 is described (block 804), which may also include spin coating the polymer layer 116 onto the passivation layer 136 and onto the bump interconnects 106, such as Fig. 9B As shown. Spin coating is only one example of forming a polymer material on the second surface 108. As described above, the polymer layer 116 can be a polyimide. Specifically, the polymer layer 116 can be an organic polyimide, which will bond well with an organic underfill to reduce delamination.

[0050] Figure 8C Removing the polymer layer 116 from the solder tip 122 (block 806) is described, as Fig. 9C As shown. Removing the polymer layer 116 from the solder tip 122 may include, but is not limited to, etching or dry etching the polymer layer 116 with oxygen or nitrogen plasma. Although the polymer layer 116 is removed from the solder tip 122, the polymer layer 116 may be removed from less than half of the side surface 114 of the pillar 118. The polymer layer 116 will remain on at least 50% of the side surface 114 of the polymer layer 116 that extends beyond the second surface 108.

[0051] After block 806, processing may be resumed according to conventional steps for thermocompression TC bonding, such as Figure 3A To Figure 3B or FIG. 4A to FIG. 4B as shown in .

[0052] Fig.10 is a cross-sectional side view of assembly 1000, corresponding to Figure 1 1000. Component 1000 may be a semiconductor die, an interposer, or some other packaged component, such as a module substrate. Component 1000 has contact pads 1002 formed on surface 1004 to provide points at which external circuits may be electrically coupled to internal circuitry (not shown) of component 1000. Surface 1004 is protected by a passivation layer 1006 formed in an area on surface 1004 surrounding contact pads 1002.

[0053] The assembly 1000 also includes a post 1008 on the contact pad 1002. Specifically, a base end 1010 of the post 1008 is coupled to an area 1012 of a pad surface 1014 of the contact pad 1002. The area 1012 does not cover the entire pad surface 1014 of the contact pad 1002. Therefore, the pad surface 1014 also includes a second area 1016 surrounding the base end 1010 of the post 1008. The post 1008 also has a contact end 1018 opposite the base end 1010. A solder tip 1020 is disposed on the contact end 1018. In addition, the post 1008 includes a side surface 1022 extending from the surface 1004. The side surface 1022 extends in a direction from the surface 1004 toward another component within the circuit package 100. In some examples, the side surface 1022 extends in a direction orthogonal to the surface 1004.

[0054] Bump interconnect 1024 includes contact pad 1002, pillar 1008, and solder tip 1020. Figure 8B and Fig. 9B The process described above forms a layer having a thickness T on the surface 1004. 116 The polymer layer 1026 is formed on the side surface 1022 and the polymer layer is also formed on the side surface 1022. On the surface 1004, the polymer layer 1026 surrounds the bump interconnect 1024.

[0055] exist Fig.10 In the assembly 1000, the passivation layer 1006 does not extend onto the second region 1016 of the pad surface 1014. Therefore, when the polymer layer 1026 is added, the polymer layer 1026 is disposed directly onto the second region 1016 of the pad surface 1014 of the contact pad 1002 around the base end 1010 of the pillar 1008.

[0056] Fig.11 is a cross-sectional side view of another assembly 1100, corresponding to Figure 1 In the second component 104. Except as described herein, Fig.11 Component 1100 in Fig.10 1100. Component 1100 includes a contact pad 1102 on a surface 1104 and a passivation layer 1106 disposed on the surface 1104 around the contact pad 1102. Component 1100 includes a bump interconnect 1108 including pillars 1110. Each of the pillars 1110 has a base end 1112 coupled to a first region 1114 of a pad surface 1116 of the contact pad 1102. Each of the pad surfaces 1116 includes a second region 1118 surrounding the first region 1114, which is below the base end 1112 of the pillar 1110.

[0057] As shown, the passivation layer 1106 is disposed on the second region 1118. In this manner, the passivation layer 1106 is disposed between the polymer layer 1120 and the second region 1118 of the pad surface 1116 of the contact pad 1102 surrounding the pillar 1110. In some examples, the passivation layer 1106 is disposed directly between the polymer layer 1120 and the second region 1118 of the pad surface 1116 of the contact pad 1102, and directly between a portion 1122 of the pillar 1110 and the second region 1118 of the pad surface 1116 of the contact pad 1102.

[0058] The passivation layer 1106 may extend onto the second region 1118 of the contact pad 1102 to reduce the first region 1114, thereby reducing stress caused by heating and cooling cycles.

[0059] Fig.11 The bump interconnects 1108 each have a Fig.11 The Y-axis direction is the central axis C extending in the longitudinal direction of the bump interconnect 1108. The distance D C2C is the center-to-center spacing distance from the central axis C of the first bump interconnect 1108 to the central axis C of the nearest adjacent bump interconnect 1108. In some examples of fine pitch bump interconnects, the center-to-center spacing distance D C2C In some examples, the center-to-center spacing distance D C2C In the range between 5μm and 25μm.

[0060] Fig.11 The bump interconnects 1108 and Figure 1 The bump interconnects 106 and Fig.10 The bump interconnect 1024 in the embodiment may be a controller collapsed chip connection (C4) bump, which may be Figure 1 , Fig.10 and Fig.11 The components 104, 1000 and 1100 are arranged in a two-dimensional array.

[0061] According to various aspects disclosed herein, a circuit package including a polymer layer on the side surface of the bump interconnect to reduce short circuits and delamination can be provided or integrated into any processor-based device. Non-limiting examples include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablets, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotors.

[0062] Fig.12 An exemplary wireless communication device 1200 is illustrated that includes radio frequency (RF) components formed of one or more integrated circuits (ICs) 1202 and may include an exemplary circuit package that includes a polymer layer disposed on side surfaces of bump interconnects between components, such as Figure 1 , Fig.10 and Fig.11 As illustrated in and according to any aspect disclosed herein. As an example, the wireless communication device 1200 may include or be arranged in any of the above-mentioned devices. Fig.12 As shown, the wireless communication device 1200 includes a transceiver 1204 and a data processor 1206. The data processor 1206 may include a memory for storing data and program codes. The transceiver 1204 includes a transmitter 1208 and a receiver 1210 that support two-way communication. In general, the wireless communication device 1200 may include any number of transmitters 1208 and / or receivers 1210 for any number of communication systems and frequency bands. All or part of the transceiver 1204 may be implemented on one or more analog ICs, RFICs, mixed signal ICs, etc.

[0063] The transmitter 1208 or the receiver 1210 may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is converted between RF and baseband in multiple stages, such as from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Fig.12In the wireless communication device 1200 in FIG. 1 , the transmitter 1208 and the receiver 1210 are implemented using a direct conversion architecture.

[0064] In the transmit path, the data processor 1206 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1208. In the exemplary wireless communication device 1200, the data processor 1206 includes digital-to-analog converters (DACs) 1212(1), 1212(2) to convert the digital signals generated by the data processor 1206 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0065] Within transmitter 1208, low pass filters 1214(1), 1214(2), respectively, filter the I and Q analog output signals to remove undesired signals caused by the preceding digital-to-analog conversion. Amplifiers (AMPs) 1216(1), 1216(2), respectively, amplify the signals from low pass filters 1214(1), 1214(2) and provide I and Q baseband signals. Up converter 1218 upconverts the I and Q baseband signals via mixers 1220(1), 1220(2) with I and Q TX LO signals from a transmit (TX) local oscillator (LO) signal generator 1222 to provide upconverted signals 1224. Filter 1226 filters the upconverted signals 1224 to remove undesired signals caused by the upconversion of the signals and noise in the receive band. A power amplifier (PA) 1228 amplifies the up-converted signal 1224 from the filter 1226 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1230 and transmitted via an antenna 1232. Either the low pass filter 1214(1) and the low pass filter 1214(2) or the filter 1226 may be an acoustic wave filter (AW filter) package 1203.

[0066] In the receive path, antenna 1232 receives a signal transmitted by a base station and provides a received RF signal, which is routed through a duplexer or switch 1230 and provided to a low noise amplifier (LNA) 1234. The duplexer or switch 1230 is designed to operate with a specific receive (RX) and TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1234 and filtered by filter 1236 to obtain the desired RF input signal. Down-conversion mixers 1238 (1), 1238 (2) mix the output of filter 1236 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1240 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1242(1), 1242(2) and further filtered by low pass filters 1244(1), 1244(2) to obtain I and Q analog input signals, which are provided to the data processor 1206. In this example, the data processor 1206 includes analog-to-digital converters (ADCs) 1246(1), 1246(2) to convert the analog input signals into digital signals to be further processed by the data processor 1206.

[0067] exist Fig.12 In the wireless communication device 1200 of the embodiment of the present invention, the TX LO signal generator 1222 generates I and Q TX LO signals for up-conversion, and the RX LO signal generator 1240 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 1248 receives timing information from the data processor 1206 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 1222. Similarly, the RX PLL circuit 1250 receives timing information from the data processor 1206 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 1240.

[0068] like Figure 1 , Fig.10 and Fig.11As illustrated in and according to any aspect disclosed herein, a wireless communication device 1200, which may each include an exemplary circuit package including a polymer layer disposed on a side surface of a bump interconnect between components, may be provided in or integrated into any processor-based device. Non-limiting examples include: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multirotor aircraft.

[0069] Fig.13 An example of a processor-based system 1300 is illustrated, which includes a circuit including an exemplary circuit package including a polymer layer disposed on the side surfaces of bump interconnects between components, such as Figure 1 , Fig.10 and Fig.11 , and according to any aspect disclosed herein. In this example, the processor-based system 1300 includes one or more central processing units (CPUs) 1302, which may also be referred to as CPUs or processor cores, each CPU including one or more processors 1304. The CPU 1302 may have a cache memory 1306 coupled to the processor 1304 for fast access to temporarily stored data. The CPU 1302 is coupled to a system bus 1308 and may interactively couple master devices and slave devices included in the processor-based system 1300. As is well known, the CPU 1302 communicates with these other devices by exchanging address, control, and data information on the system bus 1308. For example, the CPU 1302 may communicate a bus transaction request to a memory controller 1310, which is an example of a slave device. Although in Fig.13 Not illustrated in the figure, but multiple system buses 1308 may be provided; each system bus 1308 forming a different fabric.

[0070] Other master devices and slave devices may be connected to the system bus 1308. Fig.13As illustrated, as examples, these devices may include a memory system 1312 (which includes a memory controller 1310 and one or more memory arrays 1314), one or more input devices 1316, one or more output devices 1318, one or more network interface devices 1320, and one or more display controllers 1322. Input devices 1316 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 1318 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface device 1320 may be any device configured to allow data exchange to and from network 1324. Network 1324 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth, etc. TM Networks and the Internet. Network interface device 1320 may be configured to support any type of communication protocol desired.

[0071] The CPU 1302 may also be configured to access a display controller 1322 via the system bus 1308 to control information transmitted to one or more displays 1326. The display controller 1322 transmits information to be displayed to the display 1326 via one or more video processors 1328, which process the information to be displayed into a format suitable for the display 1326. The display 1326 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, or a light emitting diode (LED) display, etc.

[0072] It will be further understood by those skilled in the art that various exemplary logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of the two. For example, the main device and auxiliary device described herein may be used in any circuit, hardware component, IC or IC chip. The memory disclosed herein may be a memory of any type and size, and may be configured to store any type of information desired. In order to clearly illustrate this interchangeability, the functionality of various exemplary components, blocks, modules, circuits and steps has been generally described above. How such functionality is implemented depends on specific applications, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the functionality described in different ways for each specific application, but such specific implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0073] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in cooperation with a DSP core, or any other such configuration).

[0074] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0075] It is also noted that the operational steps described in any exemplary aspect of this article are described in order to provide examples and discussions. The described operations can be performed in many different orders except for the illustrated order. In addition, the operations described in a single operational step can actually be performed in several different steps. In addition, one or more operational steps discussed in the exemplary aspects can be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications can be made to the operational steps illustrated in the flow chart. It will be equally understood by those skilled in the art that various techniques and methods can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0076] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

[0077] Specific implementation examples are described in the following numbered clauses:

[0078] 1. A circuit package, comprising:

[0079] a first component comprising a plurality of contact pads on a first surface;

[0080] a second component including a plurality of bump interconnects on a second surface, wherein each of the plurality of bump interconnects is coupled to one of the plurality of contact pads on the first surface of the first component, and including a side surface extending in a first direction between the first surface and the second surface; and

[0081] A polymer layer is disposed on the side surface of each of the plurality of bump interconnects and on the second surface of the second component, surrounding each of the plurality of bump interconnects.

[0082] 2. A circuit package according to clause 1, wherein:

[0083] The polymer layer disposed on the second surface comprises a first thickness along the first direction; and

[0084] The polymer layer disposed on the side surface of each of the plurality of bump interconnections extends further than the first thickness in the first direction.

[0085] 3. A circuit package according to clause 2, wherein:

[0086] The side surface of each of the plurality of bump interconnects extends beyond the first thickness of the polymer layer by a first distance along the first direction; and

[0087] The polymer layer disposed on the side surface extends at least half of the first distance along the first direction.

[0088] 4. The circuit package of any one of clauses 1 to 3, wherein the polymer layer comprises polyimide.

[0089] 5. The circuit package of clause 4, wherein the polyimide does not contain a photosensitive polymer.

[0090] 6. The circuit package of any one of clauses 1 to 5, further comprising an organic underfill on the polymer layer between the first component and the second component surrounding each bump interconnect of the plurality of bump interconnects.

[0091] 7. The circuit package of any one of clauses 1 to 6, further comprising a passivation layer disposed between the polymer layer and the second surface of the second component around each of the plurality of bump interconnects.

[0092] 8. The circuit package of any one of clauses 1 to 7, each of the plurality of bump interconnects further comprising:

[0093] a contact pad disposed on the second surface, the contact pad comprising a pad surface having a first area; and

[0094] A column, comprising:

[0095] a base surface coupled to the pad surface in the first region; and

[0096] The side surfaces extend from the pad surface.

[0097] 9. The circuit package of clause 8, wherein in each of the plurality of bump interconnects, the polymer layer is disposed directly on a second region of the pad surface surrounding the contact pad of the stud.

[0098] 10. The circuit package of clause 8 or clause 9, wherein in each of the plurality of bump interconnects, the passivation layer is disposed between the polymer layer and a second region of the pad surface surrounding the contact pad of the post.

[0099] 11. A circuit package according to any one of clauses 8 to 10, wherein the passivation layer is directly disposed between the polymer layer and the second area of ​​the contact surface of the contact pad, and is directly disposed along the first direction between a portion of the column and the second area of ​​the pad surface of the contact pad.

[0100] 12. The circuit package of any one of clauses 8 to 11, each bump interconnect of the plurality of bump interconnects further comprising:

[0101] a contact end of the post; and

[0102] a solder tip disposed on the contact end,

[0103] Wherein each of the plurality of bump interconnects coupled to one of the plurality of contact pads on the first surface of the first component further comprises the solder tip disposed between the contact end of the pillar and the contact pad.

[0104] 13. A circuit package according to any one of clauses 1 to 12, wherein:

[0105] Each of the plurality of bump interconnects includes a central axis extending along a longitudinal direction of the bump interconnect; and

[0106] A center-to-center spacing distance from a central axis of a first bump interconnect of the plurality of bump interconnects to a central axis of a nearest adjacent bump interconnect is between 20 microns and 30 microns.

[0107] 14. The circuit package of clause 13, wherein the center-to-center pitch distance is 25 microns.

[0108] 15. A circuit package according to any one of clauses 1 to 14, wherein:

[0109] A first one of the first assembly and the second assembly includes a semiconductor die; and

[0110] A second one of the first assembly and the second assembly includes one of a semiconductor die, an interposer, and a packaging substrate.

[0111] 16. The circuit package of any one of clauses 1 to 15, wherein the plurality of bump interconnects comprises controller collapsed chip connect (C4) bumps.

[0112] 17. The circuit package of any one of clauses 1 to 16, wherein the plurality of bump interconnects comprises a two-dimensional array of bump interconnects.

[0113] 18. A circuit package according to any one of clauses 1 to 17, wherein the circuit package is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

[0114] 19. A method of manufacturing a circuit package, comprising:

[0115] forming a first component including a plurality of contact pads on the first surface;

[0116] forming a second component including a plurality of bump interconnects on the second surface, wherein each of the plurality of bump interconnects is coupled to one of the plurality of contact pads on the first surface and includes a side surface extending in a first direction between the first surface and the second surface; and

[0117] A polymer layer is formed, the polymer layer being disposed on the side surface of each of the plurality of bump interconnections and on the second surface of the second component, surrounding each of the plurality of bump interconnections.

[0118] 20. The method according to clause 19, further comprising:

[0119] The plurality of bump interconnects on the second component are coupled to the plurality of contact pads on the first component using thermal compression bonding.

[0120] 21. The method of clause 19 or clause 20, wherein forming the polymer layer further comprises:

[0121] spin coating the polymer layer onto the second surface of the second component and the side surfaces and end surfaces of each of the plurality of bump interconnects; and

[0122] The polymer layer is etched from the end surface of each of the plurality of bump interconnects.

[0123] 22. A semiconductor die configured to be coupled in a circuit package, the semiconductor die comprising:

[0124] a plurality of bump interconnects on a surface of the semiconductor die, wherein:

[0125] Each bump interconnect of the plurality of bump interconnects is configured to couple to a corresponding contact pad on a surface of a circuit component of the circuit package; and

[0126] Each bump interconnect of the plurality of bump interconnects includes: a side surface extending from the semiconductor die; and

[0127] A polymer layer is disposed on the surface of the semiconductor die and on the side surface of each of the plurality of bump interconnects, surrounding each of the plurality of bump interconnects.

Claims

1. A circuit package, comprising: a first component comprising a plurality of contact pads on a first surface; a second component comprising a plurality of bump interconnects on a second surface, wherein each of the plurality of bump interconnects is coupled to one of the plurality of contact pads on the first surface of the first component, and comprising a side surface extending in a first direction between the first surface and the second surface; as well as A polymer layer is disposed on the side surface of each of the plurality of bump interconnects and on the second surface of the second component, surrounding each of the plurality of bump interconnects.

2. The circuit package according to claim 1, wherein: The polymer layer disposed on the second surface comprises a first thickness along the first direction; and The polymer layer disposed on the side surface of each of the plurality of bump interconnections extends further than the first thickness in the first direction.

3. The circuit package according to claim 2, wherein: The side surface of each of the plurality of bump interconnects extends beyond the first thickness of the polymer layer by a first distance along the first direction; and The polymer layer disposed on the side surface extends at least half of the first distance along the first direction. The circuit package of claim 1 , wherein the polymer layer comprises polyimide. The circuit package of claim 4 , wherein the polyimide does not contain a photosensitive polymer. 6 . The circuit package of claim 5 , further comprising an organic underfill on the polymer layer surrounding each of the plurality of bump interconnects between the first component and the second component. 7 . The circuit package of claim 1 , further comprising a passivation layer disposed between the polymer layer and the second surface of the second component around each of the plurality of bump interconnects.

8. The circuit package of claim 1 , each of the plurality of bump interconnects further comprising: a contact pad disposed on the second surface, the contact pad comprising a pad surface having a first area; as well as A column, comprising: a base surface coupled to the pad surface in the first region; as well as The side surfaces extend from the pad surface. 9 . The circuit package of claim 8 , wherein in each of the plurality of bump interconnects, the polymer layer is disposed directly on a second region of the pad surface surrounding the contact pad of the stud. 10 . The circuit package of claim 8 , wherein in each of the plurality of bump interconnects, the passivation layer is disposed between the polymer layer and a second region of the pad surface surrounding the contact pad of the stud.

11. The circuit package of claim 10, wherein the passivation layer is disposed directly between the polymer layer and the second region of the contact surface of the contact pad, and directly between a portion of the pillar and the second region of the pad surface of the contact pad along the first direction.

12. The circuit package of claim 8, each of the plurality of bump interconnects further comprising: a contact end of the column; as well as a solder tip disposed on the contact end, Wherein each of the plurality of bump interconnects coupled to one of the plurality of contact pads on the first surface of the first component further comprises the solder tip disposed between the contact end of the pillar and the contact pad.

13. The circuit package of claim 1, wherein: Each of the plurality of bump interconnects includes a central axis extending along a longitudinal direction of the bump interconnect; as well as A center-to-center spacing distance from a central axis of a first bump interconnect of the plurality of bump interconnects to a central axis of a nearest adjacent bump interconnect is between 20 microns and 30 microns.

14. The circuit package of claim 13, wherein the center-to-center pitch distance is 25 microns.

15. The circuit package of claim 1, wherein: A first one of the first assembly and the second assembly includes a semiconductor die; and A second one of the first assembly and the second assembly includes one of a semiconductor die, an interposer, and a packaging substrate.

16. The circuit package of claim 1, wherein the plurality of bump interconnects comprises controller collapsed chip connect (C4) bumps.

17. The circuit package of claim 1, wherein the plurality of bump interconnects comprises a two-dimensional array of bump interconnects.

18. The circuit package of claim 1, wherein the circuit package is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; drones; and multirotors.

19. A method of manufacturing a circuit package, comprising: forming a first component including a plurality of contact pads on the first surface; forming a second component including a plurality of bump interconnects on the second surface, wherein each of the plurality of bump interconnects is coupled to one of the plurality of contact pads on the first surface and includes a side surface extending in a first direction between the first surface and the second surface; as well as A polymer layer is formed, the polymer layer being disposed on the side surface of each of the plurality of bump interconnections and on the second surface of the second component, surrounding each of the plurality of bump interconnections.

20. The method according to claim 19, further comprising: The plurality of bump interconnects on the second component are coupled to the plurality of contact pads on the first component using thermal compression bonding.

21. The method of claim 19, wherein forming the polymer layer further comprises: spin coating the polymer layer onto the second surface of the second component and onto side surfaces and end surfaces of each of the plurality of bump interconnects; as well as The polymer layer is etched from the end surface of each of the plurality of bump interconnects.

22. A semiconductor die configured to be coupled in a circuit package, the semiconductor die comprising: a plurality of bump interconnects on a surface of the semiconductor die, wherein: Each bump interconnect of the plurality of bump interconnects is configured to couple to a corresponding contact pad on a surface of a circuit component of the circuit package; and Each bump interconnect of the plurality of bump interconnects includes: a side surface extending from the semiconductor die; and A polymer layer is disposed on the surface of the semiconductor die and on the side surface of each of the plurality of bump interconnects, surrounding each of the plurality of bump interconnects.

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