Package including flexible substrate

Abstract

A package includes a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to the first surface of the substrate; wherein the backside of the second integrated device is coupled to the backside of the first integrated device by an adhesive. The substrate includes at least one dielectric layer and a plurality of interconnects. The substrate includes a flexible portion configured to bend such that the backside of the first integrated device faces the backside of the second integrated device in the package.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application S / N. 17 / 951,702 filed in the United States Patent and Trademark Office on September 23, 2022, the entire contents of which are incorporated herein by reference as if fully set forth in its entirety below and for all applicable purposes.

[0003] field

[0004] Various features relate to a package having a substrate.

[0005] background

[0006] A package may include a substrate and an integrated device. These components are coupled together to provide a package that can perform various functions. The performance of a package and its components may depend on the quality of the joints between the various components of the package. There is a continuing need to provide a package that includes robust and reliable joints between the various components. In addition, there is a continuing need to include a package that includes a more compact form factor so that the package can be implemented in smaller devices.

[0007] Overview

[0008] Various features relate to a package having a substrate.

[0009] One example provides a package including a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to the first surface of the substrate, wherein a back side of the second integrated device is coupled to a back side of the first integrated device by an adhesive. The substrate includes at least one dielectric layer and a plurality of interconnects.

[0010] Another example provides an apparatus including a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to the first surface of the substrate, wherein a back side of the second integrated device is coupled to a back side of the first integrated device by an adhesive. The substrate includes at least one dielectric layer and a plurality of interconnects.

[0011] Another example provides a method for manufacturing a package. The method provides a substrate including at least one dielectric layer and a plurality of interconnects. The method couples a first integrated device to a first surface of the substrate. The method couples a second integrated device to the first surface of the substrate. The method bends the substrate and couples the back side of the second integrated device to the back side of the first integrated device through an adhesive. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Various features, characteristics and advantages will become apparent when the detailed description set forth below is read in conjunction with the accompanying drawings in which like reference numerals designate corresponding features throughout.

[0014] Figure 1 A cross-sectional profile view of an exemplary package including a flexible substrate and an integrated device is illustrated.

[0015] Figure 2 A cross-sectional profile view of an exemplary package including a flexible substrate and an integrated device is illustrated.

[0016] Figure 3 A cross-sectional profile view of an exemplary package including a flexible substrate and an integrated device is illustrated.

[0017] Figure 4 A cross-sectional profile view of an exemplary package including a flexible substrate and an integrated device is illustrated.

[0018] Figure 5 A cross-sectional profile view of an exemplary package including a flexible substrate and an integrated device is illustrated.

[0019] Figure 6 A cross-sectional profile view of an exemplary package including a flexible substrate and an integrated device is illustrated.

[0020] Figure 7 A cross-sectional profile view of an exemplary package including a flexible substrate and an integrated device is illustrated.

[0021] Figure 8 A cross-sectional profile view of an exemplary package including a flexible substrate and an integrated device is illustrated.

[0022] Fig. 9 A cross-sectional profile view of an exemplary package including a flexible substrate and an integrated device is illustrated.

[0023] Fig.10 A cross-sectional profile view of an exemplary package including a flexible substrate and an integrated device is illustrated.

[0024] Fig.11 A cross-sectional profile view of an exemplary package including a flexible substrate and an integrated device is illustrated.

[0025] Fig.12 A plan view of an exemplary package including a flexible substrate and an integrated device is illustrated.

[0026] Fig.13A -13B illustrates an exemplary process for manufacturing a package including a flexible substrate and an integrated device.

[0027] Fig.14 An example flow chart for manufacturing a package including a flexible substrate and an integrated device is illustrated.

[0028] Fig.15 An exemplary process for manufacturing a flexible substrate is illustrated.

[0029] Fig.16 Various electronic devices are illustrated that may integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein.

[0030] Detailed Description

[0031] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those of ordinary skill in the art that these aspects can be practiced without these specific details. For example, circuits may be shown with block diagrams to avoid burying these aspects in unnecessary details. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid burying these aspects of the present disclosure.

[0032] The present disclosure describes a package, including a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to the first surface of the substrate; wherein the back side of the second integrated device is coupled to the back side of the first integrated device by an adhesive. The substrate includes at least one dielectric layer and a plurality of interconnects. The substrate includes a flexible portion configured to bend so that the back side of the first integrated device in the package faces the back side of the second integrated device. The package may include a plurality of solder interconnects. The substrate includes a first portion and a second portion, and when the substrate is bent, the first portion faces the second portion. The plurality of solder interconnects are coupled to the first portion and the second portion. The use of a flexible substrate helps to provide a package with a more compact form factor, which allows the package to be implemented in a smaller device. In addition, the use of solder interconnects to couple to different portions of the flexible substrate helps to provide a more direct electrical path between the integrated devices coupled to different portions of the flexible substrate, which can lead to improved performance of the integrated devices and the package.

[0033] Exemplary package including integrated device and flexible substrate

[0034] Figure 1A cross-sectional cutaway view of a package 100 including a flexible substrate is illustrated. The package 100 includes a substrate 102, an integrated device 103, an integrated device 105, and an integrated device 107. The integrated device 103 may be a first integrated device. The integrated device 105 may be a second integrated device. The integrated device 107 may be a third integrated device. The substrate 102 includes a flexible substrate. The substrate 102 includes a flexible portion that can be configured to bend at least 180 degrees. The package 100 is coupled to a board 108 (e.g., a printed circuit board) via a plurality of solder interconnects 190. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The package 100 is coupled to a plurality of board interconnects 182 of the board 108 (e.g., a printed circuit board) via a plurality of solder interconnects 190. The substrate 102 includes a first surface and a second surface. The substrate 102 may be coupled to the board 108 such that a first portion of the second surface of the substrate 102 faces the board 108. For example, the substrate 102 can be coupled to the board 108 so that the first portion of the solder resist layer 140 in the second surface of the substrate 102 faces the board 108. Examples of the first and second portions of the substrate are described below. Fig.12 and 13A Explanation and description.

[0035] Substrate 102 includes a first surface and a second surface. Substrate 102 includes a dielectric layer 110, a dielectric layer 120, a dielectric layer 125, a solder resist layer 140, and a plurality of interconnects 122 (e.g., a plurality of substrate interconnects). Dielectric layer 120 may include a reinforcing dielectric layer. Dielectric layer 120 (e.g., a reinforcing dielectric layer) may be optional. Dielectric layer 110 and / or dielectric layer 125 may include prepreg. A plurality of interconnects 122 include interconnects 122a and interconnects 122b. Interconnect 122a may include an interconnect located on a first metal layer (e.g., M1) of substrate 102. Interconnect 122a may be located at least in a flexible portion of substrate 102. Interconnect 122b may include an interconnect located on a second metal layer (e.g., M2) of substrate 102. Interconnect 122b may be located at least in a flexible portion of substrate 102. In some implementations, the first surface of substrate 102 includes dielectric layer 110. In some implementations, the second surface of the substrate 102 includes a solder resist layer 140 .

[0036] Figure 1The substrate 102 is illustrated as being bent so that a portion of the dielectric layer 110 faces another portion of the dielectric layer 110. However, in some implementations, the substrate 102 may be bent so that a portion of the solder resist layer 140 faces another portion of the solder resist layer 140. Thus, the substrate 102 may be bent in many different ways and is not limited to the ways shown in the drawings. In some implementations, when the substrate 102 is bent so that a portion of the solder resist layer 140 faces another portion of the solder resist layer 140, the first surface of the substrate 102 may include the solder resist layer 140, and the second surface of the substrate 102 may include the dielectric layer. In some implementations, the first surface of the substrate 102 may be an inner surface of the substrate 102, and the second surface of the substrate 102 may be an outer surface of the substrate 102.

[0037] The integrated device 103 includes a front side (e.g., a first back side) and a back side (e.g., a first back side). The integrated device 103 is coupled to a first portion of a first surface of the substrate 102 through a plurality of solder interconnects 130 such that the front side of the integrated device 103 faces the first portion of the first surface of the substrate 102. For example, the integrated device 103 is coupled to a first plurality of interconnects 122 of the substrate 102 through a plurality of solder interconnects 130 such that the front side of the integrated device 103 faces the first portion of the first surface of the substrate 102. The integrated device 103 may include a chiplet.

[0038] The integrated device 105 includes a front side (e.g., a second back side) and a back side (e.g., a second back side). The integrated device 105 is coupled to a second portion of the first surface of the substrate 102 through a plurality of solder interconnects 150 such that the front side of the integrated device 105 faces the second portion of the first surface of the substrate 102. For example, the integrated device 105 is coupled to a second plurality of interconnects 122 of the substrate 102 through a plurality of solder interconnects 150 such that the front side of the integrated device 105 faces the second portion of the first surface of the substrate 102. The integrated device 105 may include a chiplet.

[0039] Integrated device 103 may be coupled to integrated device 105 via adhesive 104. For example, the back side of integrated device 103 may be coupled to the back side of integrated device 105 via adhesive 104. Thus, the back side of integrated device 103 may face the back side of integrated device 105, and vice versa.

[0040] The integrated device 107 includes a front side (e.g., a third back side) and a back side (e.g., a third back side). The integrated device 107 is coupled to the second portion of the second surface of the substrate 102 through a plurality of solder interconnects 170, such that the front side of the integrated device 107 faces the second portion of the second surface of the substrate 102. For example, the integrated device 107 is coupled to a third plurality of interconnects in the plurality of interconnects 122 of the substrate 102 through a plurality of solder interconnects 170, such that the front side of the integrated device 107 faces the second portion of the second surface of the substrate 102.

[0041] The integrated device 103 is configured to be electrically coupled to the integrated device 105 and / or the integrated device 107 through the substrate 102. For example, the electrical path between the integrated device 103 and the integrated device 105 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 150. The electrical path between the integrated device 103 and the integrated device 107 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 170. The electrical path between the integrated device 105 and the integrated device 107 may include at least one solder interconnection of the plurality of solder interconnections 150, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 170.

[0042] Figure 1 An example of a package that is more compact and occupies less active area laterally is illustrated. By bending and / or folding substrate 102 at least 180°, package 100 occupies less lateral space at the expense of a slightly thicker package, which can allow the package to fit into spaces and / or devices that have little lateral space but plenty of vertical space.

[0043] Figure 2 The configuration of package 200 including a flexible substrate is illustrated. Package 200 is similar to package 100 and thus includes the same or similar components arranged in a similar manner as package 100.

[0044] Package 200 includes substrate 102, integrated device 203, integrated device 205, and integrated device 107. Integrated device 203 may be a first integrated device. Integrated device 205 may be a second integrated device. Integrated device 107 may be a third integrated device. Integrated device 203 includes metallization 232, die 230 (e.g., semiconductor die), and encapsulation layer 234. Die 230 is coupled to metallization 232. Encapsulation layer 234 is coupled to die 230 and metallization 232. Encapsulation layer 234 encapsulates die 230. Metallization 232 may include at least one dielectric layer and a plurality of interconnects. Metallization 232 may be a redistribution portion including at least one dielectric layer and a plurality of redistribution interconnects.

[0045] The integrated device 205 includes a metallization 252, a die 250 (e.g., a semiconductor die), and an encapsulation layer 254. The die 250 is coupled to the metallization 252. The encapsulation layer 254 is coupled to the die 250 and the metallization 252. The encapsulation layer 254 encapsulates the die 250. The metallization 252 may include at least one dielectric layer and a plurality of interconnects. The metallization 252 may be a redistribution portion including at least one dielectric layer and a plurality of redistribution interconnects.

[0046] The integrated device 203 includes a front side (e.g., a first back side) and a back side (e.g., a first back side). The front side of the integrated device 203 may include a metallization layer 232, and the back side of the integrated device 203 may include an encapsulation layer 234. The integrated device 203 is coupled to a first portion of the first surface of the substrate 102 through a plurality of solder interconnects 130, such that the front side of the integrated device 203 faces the first portion of the first surface of the substrate 102. For example, the integrated device 203 is coupled to a first plurality of interconnects in the plurality of interconnects 122 of the substrate 102 through a plurality of solder interconnects 130, such that the front side of the integrated device 203 faces the first portion of the first surface of the substrate 102.

[0047] The integrated device 205 includes a front side (e.g., a second back side) and a back side (e.g., a second back side). The front side of the integrated device 205 may include a metallization layer 252, and the back side of the integrated device 205 may include an encapsulation layer 254. The integrated device 205 is coupled to a second portion of the first surface of the substrate 102 through a plurality of solder interconnects 150, such that the front side of the integrated device 205 faces the second portion of the first surface of the substrate 102. For example, the integrated device 205 is coupled to a second plurality of interconnects in the plurality of interconnects 122 of the substrate 102 through a plurality of solder interconnects 150, such that the front side of the integrated device 205 faces the second portion of the first surface of the substrate 102.

[0048] Integrated device 203 may be coupled to integrated device 205 via adhesive 104. For example, the back side of integrated device 203 may be coupled to the back side of integrated device 205 via adhesive 104. Thus, encapsulation layer 234 of integrated device 203 may be coupled to encapsulation layer 254 of integrated device 205 via adhesive 104. The back side of integrated device 203 may face the back side of integrated device 205, and vice versa.

[0049] The integrated device 203 is configured to be electrically coupled to the integrated device 205 and / or the integrated device 107 through the substrate 102. For example, the electrical path between the integrated device 203 and the integrated device 205 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 150. The electrical path between the integrated device 203 and the integrated device 107 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 170. The electrical path between the integrated device 205 and the integrated device 107 may include at least one solder interconnection of the plurality of solder interconnections 150, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 170.

[0050] Figure 3 The configuration of package 300 including a flexible substrate is illustrated. Package 300 is similar to packages 100 and 200 and thus includes the same or similar components arranged in a similar manner as packages 100 and 200.

[0051] Package 300 includes substrate 102, integrated device 203, integrated device 205, package 307, and a plurality of solder interconnects 380. Package 307 includes package substrate 371, integrated device 370, integrated device 372, a plurality of wire bonds 375, and encapsulation layer 378. Package substrate 371 may include at least one dielectric layer and a plurality of interconnects (not shown). Integrated device 203 and integrated device 205 may be connected to the substrate 102 in a manner similar to that of FIG. Figure 2 is coupled to the substrate 102 in a manner similar to that described in .

[0052] Package 307 includes a front side (e.g., a third front side) and a back side (e.g., a third back side). The front side of package 307 may include package substrate 371, and the back side of package 307 may include encapsulation layer 378. Package 307 is coupled to a second portion of the second surface of substrate 102 through a plurality of solder interconnects 170, such that the front side of package 307 faces the second portion of the second surface of substrate 102. For example, package 307 is coupled to a third plurality of interconnects among the plurality of interconnects 122 of substrate 102 through a plurality of solder interconnects 170, such that the front side of package 307 faces the second portion of the second surface of substrate 102.

[0053] The plurality of solder interconnects 380 may include a first plurality of solder interconnects 380a and a second plurality of solder interconnects 380b. The plurality of solder interconnects 380 are coupled to at least two different portions of the first surface of the substrate 102, wherein the two different portions of the first surface of the substrate 102 face each other. For example, the first plurality of solder interconnects 380a may be coupled to a first specific portion of the first surface of the substrate 102 and to a second specific portion of the first surface of the substrate 102, wherein the first specific portion of the first surface of the substrate 102 faces the second specific portion of the first surface of the substrate 102. The second plurality of solder interconnects 380b may be coupled to a third specific portion of the first surface of the substrate 102 and to a fourth specific portion of the first surface of the substrate 102, wherein the third specific portion of the first surface of the substrate 102 faces the fourth specific portion of the first surface of the substrate 102. The second plurality of solder interconnects 380a may be located between the integrated device 203 and the flexible portion, folded portion, and / or bent portion of the substrate 102. The second plurality of solder interconnects 380 b may be located between the integrated device 205 and the flexible, folded, and / or bent portions of the substrate 102 .

[0054] The integrated device 203 is configured to be electrically coupled to the integrated device 205 and / or the package 307 through the substrate 102. For example, the electrical path between the integrated device 203 and the integrated device 205 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 150. The electrical path between the integrated device 203 and the integrated device 205 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, at least one solder interconnection of the plurality of solder interconnections 380, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 150.

[0055] The electrical path between the integrated device 203 and the package 307 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 170. The electrical path between the integrated device 203 and the package 307 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, at least one solder interconnection of the plurality of solder interconnections 380, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 170.

[0056] The electrical path between the integrated device 205 and the package 307 may include at least one solder interconnect of the plurality of solder interconnects 150 , at least one solder interconnect of the plurality of solder interconnects 122 , and at least one solder interconnect of the plurality of solder interconnects 170 .

[0057] Figure 4 The configuration of package 400 including a flexible substrate is illustrated. Package 400 is similar to package 100, package 200, and / or package 300 and thus includes the same or similar components arranged in a similar manner as package 100, package 200, and / or package 300. Package 400 includes substrate 102, integrated device 203, integrated device 205, package 307, and a plurality of solder interconnects 380. Figure 4 It is illustrated that a portion of the substrate 102 has been removed to facilitate bending of the flexible portion of the substrate 102. For example, portions of the dielectric layer 110 and / or the dielectric layer 120 may have been removed in the flexible portion of the substrate 102.

[0058] Figure 5 A package 500 including a flexible substrate is illustrated. The package 500 is similar to Figure 1 The package 100 thus includes Figure 1 The same or similar components are arranged in a similar manner to package 100. However, Figure 5 Package 500 in does not include integrated device 107 .

[0059] Figure 6 Package 600 is illustrated as including a flexible substrate. Package 600 is similar to package 100, package 300, and package 500 and thus includes the same or similar components arranged in a similar manner as package 100, package 300, and / or package 500.

[0060] The package 600 includes a substrate 102, an integrated device 103, an integrated device 105, and a plurality of solder interconnects 380. The integrated device 103 is configured to be electrically coupled to the integrated device 105 through the substrate 102. For example, the electrical path between the integrated device 103 and the integrated device 105 may include at least one solder interconnect in the plurality of solder interconnects 130, at least one solder interconnect in the plurality of solder interconnects 122, and at least one solder interconnect in the plurality of solder interconnects 150. The electrical path between the integrated device 103 and the integrated device 105 may include at least one solder interconnect in the plurality of solder interconnects 130, at least one solder interconnect in the plurality of solder interconnects 122, at least one solder interconnect in the plurality of solder interconnects 380, at least one solder interconnect in the plurality of solder interconnects 122, and at least one solder interconnect in the plurality of solder interconnects 150.

[0061] Figure 7 Package 700 is illustrated as including a flexible substrate. Package 700 is similar to package 300 and / or package 600 and thus includes the same or similar components arranged in a similar manner as package 300 and / or package 600.

[0062] The integrated device 103 is configured to be electrically coupled to the integrated device 105 and / or the package 307 through the substrate 102. For example, the electrical path between the integrated device 103 and the integrated device 105 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 150. The electrical path between the integrated device 103 and the integrated device 105 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, at least one solder interconnection of the plurality of solder interconnections 380, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 150.

[0063] The electrical path between the integrated device 103 and the package 307 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 170. The electrical path between the integrated device 103 and the package 307 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, at least one solder interconnection of the plurality of solder interconnections 380, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 170.

[0064] The electrical path between the integrated device 105 and the package 307 may include at least one solder interconnect of the plurality of solder interconnects 150 , at least one solder interconnect of the plurality of solder interconnects 122 , and at least one solder interconnect of the plurality of solder interconnects 170 .

[0065] Figure 8 Package 800 is illustrated as including a flexible substrate. Package 800 is similar to package 400 and thus includes the same or similar components arranged in a similar manner as package 400. Package 800 includes substrate 102, integrated device 103, integrated device 105, package 307, and a plurality of solder interconnects 380. Figure 8 It is illustrated that a portion of the substrate 102 has been removed to facilitate bending of the flexible portion of the substrate 102. For example, portions of the dielectric layer 110 and / or the dielectric layer 120 may have been removed in the flexible portion of the substrate 102.

[0066] Fig. 9 Package 900 is illustrated as including a flexible substrate. Package 900 is similar to package 500 and thus includes the same or similar components arranged in a similar manner as package 500. Package 900 includes substrate 102, integrated device 203, and integrated device 205.

[0067] Integrated device 203 is configured to be electrically coupled to integrated device 205 through substrate 102. For example, the electrical path between integrated device 203 and integrated device 205 may include at least one solder interconnect of plurality of solder interconnects 130, at least one solder interconnect of plurality of solder interconnects 122, and at least one solder interconnect of plurality of solder interconnects 150.

[0068] Fig.10 Package 1000 is illustrated as including a flexible substrate. Package 1000 is similar to package 800 and package 900 and thus includes the same or similar components arranged in a similar manner as package 800 and package 900. Package 1000 includes substrate 102, integrated device 203, integrated device 205, and a plurality of solder interconnects 380.

[0069] The integrated device 203 is configured to be electrically coupled to the integrated device 205 through the substrate 102. For example, the electrical path between the integrated device 203 and the integrated device 205 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 150. The electrical path between the integrated device 203 and the integrated device 205 may include at least one solder interconnection of the plurality of solder interconnections 130, at least one solder interconnection of the plurality of solder interconnections 122, at least one solder interconnection of the plurality of solder interconnections 380, at least one solder interconnection of the plurality of solder interconnections 122, and at least one solder interconnection of the plurality of solder interconnections 150.

[0070] Fig.11 Package 1100 is illustrated as including a flexible substrate. Package 1100 is similar to package 1000 and thus includes the same or similar components arranged in a similar manner as package 1000. Package 1000 includes substrate 102, integrated device 203, integrated device 205, and a plurality of solder interconnects 380. Fig.11 It is illustrated that a portion of the substrate 102 has been removed to facilitate bending of the flexible portion of the substrate 102. For example, portions of the dielectric layer 110 and / or the dielectric layer 120 may have been removed in the flexible portion of the substrate 102.

[0071] It is worth noting that other implementations can use Figure 1-11 Any combination of the configurations shown in .

[0072] Fig.12 Illustrated is a plan view of package 1200, which includes substrate 102, plurality of interconnects 1222, plurality of interconnects 1224, plurality of interconnects 1226, integrated device 1203, and integrated device 1205. Substrate 102 includes a flexible portion. Fig.12 12 is in an expanded position. Multiple interconnects 1222, multiple interconnects 1224, and multiple interconnects 1226 may represent multiple interconnects 122. Integrated device 1203 may represent integrated device 103 or integrated device 203. Integrated device 1205 may represent integrated device 105 or integrated device 205. In some implementations, integrated device 1203 may be configured to be electrically coupled to integrated device 1205 via multiple interconnects 1222. In some implementations, when substrate 102 is bent, multiple solder interconnects 380 ( Fig.12 1203) may be used to couple to the plurality of interconnects 1224 and the plurality of interconnects 1226. In some implementations, the integrated device 1203 may be configured to be electrically coupled to the integrated device 1205 at least through the plurality of interconnects 1224, the plurality of solder interconnects 380, and the plurality of interconnects 1226.

[0073] Fig.12 A first surface of the substrate 102 including a first portion 1230 and a second portion 1250 may be illustrated. Fig.12It is illustrated that the integrated device 1203 is coupled to the first portion 1230 of the first surface of the substrate 102, and the integrated device 1205 is coupled to the second portion 1250 of the first surface of the substrate 102. The plurality of interconnects 1224 may be located in the first portion 1230 of the substrate 102 (e.g., located in the first portion 1230 of the first surface of the substrate 102). The plurality of interconnects 1226 may be located in the second portion 1250 of the substrate 102 (e.g., located in the second portion 1250 of the first surface of the substrate 102). When the substrate 102 is folded, the first portion 1230 of the first surface of the substrate 102 may face the second portion 1250 of the first surface of the substrate 102. The plurality of solder interconnects 380 may be coupled to the first portion 1230 of the first surface of the substrate 102 and to the second portion 1250 of the first surface of the substrate 102. For example, the plurality of solder interconnects 380 may be coupled to the plurality of interconnects 1224 and the plurality of interconnects 1226. In some implementations, the first portion 1230 of the first surface of the substrate 102 can correspond to a first portion of the substrate's dielectric layer 110. In some implementations, the second portion 1250 of the first surface of the substrate 102 can correspond to a second portion of the substrate's dielectric layer 110.

[0074] The integrated device (e.g., 103, 105, 107) may include a die (e.g., a bare semiconductor die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or a combination thereof. The integrated device (e.g., 103, 105, 107) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device. In some implementations, the integrated device may be a chiplet. Chiplets may be manufactured using processes that provide better yields than other processes used to manufacture other types of integrated devices, which may reduce the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). Thus, for example, a single integrated device may be divided into several chiplets. As mentioned, using several chiplets that perform several functions may reduce the overall cost of the package relative to using a single chip to perform all functions of the package. In some implementations, one or more chiplets and / or one or more integrated devices (e.g., 103, 105, 107) described in the present disclosure may be manufactured using the same technology node or two or more different technology nodes. For example, an integrated device (e.g., 105) may be manufactured using a first technology node, and a chiplet (e.g., 103) may be manufactured using a second technology node that is not as advanced as the first technology node. In such examples, the integrated device (e.g., 107) may include components (e.g., interconnects, transistors) having a first minimum size, and the chiplet (e.g., 103) may include components (e.g., interconnects, transistors) having a second minimum size, where the second minimum size is greater than the first minimum size. In some implementations, the packaged integrated device 107 and the integrated device 109 may be manufactured using the same technology node or different technology nodes. In some implementations, the packaged chiplet (e.g., 103) and another chiplet (e.g., 105) may be manufactured using the same technology node or different technology nodes.

[0075] Exemplary process for making a package including a flexible substrate

[0076] In some implementations, manufacturing a package includes several processes. Figures 13A-13B Exemplary processes for providing or manufacturing a package including a flexible substrate are described. In some implementations, Figures 13A-13B The process can be used to provide or manufacture the Figure 4 However, the process may be used to provide or manufacture any package described in the present disclosure (eg, 100, 200, 300, 500, 600, 700, 800, 900, 1000, 1100).

[0077] It should be noted that Figures 13A-13B The steps of the present invention may combine one or more processes in order to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified.

[0078] Fig.13A Stage 1 of the present invention illustrates a state after manufacturing or providing substrate 102. Substrate 102 includes dielectric layer 110, dielectric layer 120, dielectric layer 125, solder resist layer 140, and a plurality of interconnects 122. Substrate 102 may be used Fig.15 13 . Stage 1 illustrates an example of a first portion 1230 of substrate 102 and an example of a second portion 1250 of substrate 102. It is noteworthy that different implementations may define the first and second portions of a substrate and / or the first and second portions of a first surface of a substrate differently. The first portion 1230 may include a first portion of the first surface of the substrate and / or a first portion of the second surface of the substrate. The second portion 1250 may include a second portion of the first surface of the substrate and / or a second portion of the second surface of the substrate. The designation of the first surface of substrate 102 and the second surface of substrate 102 is exemplary. In some implementations, the first surface and the second surface shown in stage 1 of FIG. 13 may be interchanged. In some implementations, the first surface of substrate 102 may include a dielectric layer 110, and the second surface of substrate 102 may include a solder resist layer 140, as described above at least in Figure 1-11 Described in .

[0079] Stage 2 illustrates a state after removing portions of dielectric layer 110 and portions of dielectric layer 120. Portions of dielectric layer 110 and / or portions of dielectric layer 120 are removed to help provide a substrate having a flexible portion. Laser processes and / or photolithography processes may be used to remove portions of dielectric layer 110 and dielectric layer 120.

[0080] Stage 3 illustrates a state after the integrated device 203 and the integrated device 205 are coupled to the first surface of the substrate 102. The integrated device 203 may be coupled to a first portion of the first surface of the substrate 102 through a plurality of solder interconnects 130. The integrated device 205 may be coupled to a second portion of the first surface of the substrate 102 through a plurality of solder interconnects 150. A solder reflow process may be used to couple the integrated device 203 and / or the integrated device 205 to the substrate 102.

[0081] Stage 4 illustrates a state after zain couples the plurality of solder interconnects 1380 to the first surface of the substrate 102. A solder reflow process may be used to couple the plurality of solder interconnects 1380 to the substrate 102. The plurality of solder interconnects 1380 may include a first plurality of solder interconnects 1380a, a second plurality of solder interconnects 1380b, a third plurality of solder interconnects 1380c, and a fourth plurality of solder interconnects 1380d.

[0082] like Fig. 13B , stage 5 illustrates a state after the substrate 102 is folded and the back side of the integrated device 203 is coupled to the back side of the integrated device 205. The first plurality of solder interconnects 1380a are coupled to the fourth plurality of solder interconnects 1380d to form the first plurality of solder interconnects 380a. The second plurality of solder interconnects 1380b are coupled to the third plurality of solder interconnects 1380c to form the second plurality of solder interconnects 380b.

[0083] Stage 6 illustrates a state after the package 307 is coupled to the substrate 102 through the plurality of solder interconnects 170. A solder reflow process may be used to couple the package 307 to the substrate 102. Stage 6 may illustrate a package 400 including the substrate 102, the integrated device 203, the integrated device 205, the package 307, and the plurality of solder interconnects 380.

[0084] It is worth noting that the above process may be modified such that integrated device 203 , integrated device 205 , and plurality of solder interconnects 1380 are coupled to the second surface of substrate 102 , and package 307 is coupled to the first surface of substrate 102 .

[0085] Example flow chart of a method for manufacturing a package including a flexible substrate

[0086] In some implementations, manufacturing a package includes several processes. Fig.14 An example flow chart of a method 1400 for providing or manufacturing a package including a flexible substrate is illustrated. In some implementations, Fig.14 The method 1400 may be used to provide or manufacture the Figure 4However, the method 1400 may be used to provide or manufacture any package described in the present disclosure (eg, 100, 200, 300, 500, 600, 700, 800, 900, 1000, 1100).

[0087] It should be noted that Fig.14 The method of the present invention may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified.

[0088] The method provides (at 1405) a flexible substrate including at least one dielectric layer and a plurality of interconnects. Fig.13A Stage 1 of the present invention illustrates an example of a state after manufacturing or providing a substrate 102. The substrate 102 includes a dielectric layer 110, a dielectric layer 120, a dielectric layer 125, a solder resist layer 140, and a plurality of interconnects 122. The substrate 102 may be used Fig.15 It is manufactured according to the process shown in .

[0089] The method optionally forms (at 1410) one or more openings in the substrate. Forming the openings may include removing portions of the substrate. Forming the openings and / or removing portions of the substrate may help the substrate become flexible or more flexible. Fig.13A 1 illustrates an example of a state after removing portions of dielectric layer 110 and portions of dielectric layer 120. Portions of dielectric layer 110 and / or portions of dielectric layer 120 are removed to help provide a substrate having a flexible portion. Laser processes and / or photolithography processes may be used to remove portions of dielectric layer 110 and dielectric layer 120.

[0090] The method couples (at 1415) a first integrated device and a second integrated device to a first surface of a substrate. Fig.13A 3 illustrates an example of a state after the integrated device 203 (e.g., the first integrated device) and the integrated device 205 (e.g., the second integrated device) are coupled to the first surface of the substrate 102. The integrated device 203 may be coupled to the first portion of the first surface of the substrate 102 through the plurality of solder interconnects 130. The integrated device 205 may be coupled to the second portion of the first surface of the substrate 102 through the plurality of solder interconnects 150. A solder reflow process may be used to couple the integrated device 203 and / or the integrated device 205 to the substrate 102.

[0091] The method may optionally (at 1420) couple a plurality of solder interconnects to the substrate. Fig.13AStage 4 of FIG. 1 illustrates an example of a state after coupling the plurality of solder interconnects 1380 to the first surface of the substrate 102. A solder reflow process may be used to couple the plurality of solder interconnects 1380 to the substrate 102. The plurality of solder interconnects 1380 may include a first plurality of solder interconnects 1380a, a second plurality of solder interconnects 1380b, a third plurality of solder interconnects 1380c, and a fourth plurality of solder interconnects 1380d.

[0092] The method bends (at 1425) the substrate and couples the back side of the integrated device to the back side of another integrated device. Fig. 13B Stage 5 of 13 illustrates an example of a state after the substrate 102 is folded and / or bent and the back side of the integrated device 203 is coupled to the back side of the integrated device 205. The first plurality of solder interconnects 1380a is coupled to the fourth plurality of solder interconnects 1380d to form the first plurality of solder interconnects 380a. The second plurality of solder interconnects 1380b is coupled to the third plurality of solder interconnects 1380c to form the second plurality of solder interconnects 380b.

[0093] The method couples (at 1430 ) a package to the second surface of the substrate 102 . Fig. 13B Stage 6 of illustrative embodiment illustrates an example of a state after the package 307 is coupled to the substrate 102 through the plurality of solder interconnects 170. A solder reflow process may be used to couple the package 307 to the substrate 102. Stage 6 may illustrate a package 400 including the substrate 102, the integrated device 203, the integrated device 205, the package 307, and the plurality of solder interconnects 380.

[0094] Exemplary Process for Making Flexible Substrates

[0095] In some implementations, manufacturing a package includes several processes. Fig.15 Exemplary processes for providing or manufacturing a flexible substrate are described. In some implementations, Fig.15 The process may be used to provide or manufacture the substrate 102. However, Fig.15 The process of A can be used to manufacture any substrate described in this disclosure.

[0096] It should be noted that Fig.15 The process of one or more stages may be combined to simplify and / or clarify the process for providing or manufacturing a substrate. In some implementations, the order of each process may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure.

[0097] like Fig.15As shown in , stage 1 illustrates a state after providing and / or forming a dielectric layer 120. The dielectric layer 120 may be formed on a carrier (not shown). The dielectric layer 120 may be formed using a deposition and / or lamination process. The dielectric layer 120 may be a reinforcement.

[0098] Stage 2 illustrates a state after providing and / or forming dielectric layer 125. Dielectric layer 125 may be formed on dielectric layer 120. Dielectric layer 125 may include prepreg. Dielectric layer 125 may be formed using a deposition and / or lamination process.

[0099] Stage 3 illustrates a state after a plurality of cavities 1510 are formed in the dielectric layer 120 and the dielectric layer 125. The plurality of cavities 1510 may be formed using a photolithography process (eg, exposure and development) or a laser process.

[0100] Stage 4 illustrates a state after forming a plurality of interconnects 122 in and on dielectric layer 120 and / or dielectric layer 125, including in and on plurality of cavities 1510. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0101] Stage 5 illustrates a state after forming the dielectric layer 110 over the dielectric layer 120 and forming the solder resist layer 140 over the dielectric layer 125. The dielectric layer 110 and the solder resist layer 140 may be formed using a deposition and / or lamination process.

[0102] Stage 6 illustrates a state after a plurality of openings 1520 are formed in the dielectric layer 110. The plurality of openings 1520 may be formed using a photolithography process (eg, exposure and development) or a laser process.

[0103] Stage 7 illustrates a state after a plurality of openings 1530 are formed in the solder resist layer 140. A photolithography process or a laser process may be used to form the plurality of openings 1530. Stage 7 may illustrate an example of the substrate 102.

[0104] Different implementations may use different processes to form the metal layer(s) and / or interconnects. In some implementations, the metal layer(s) may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process.

[0105] Exemplary Electronic Devices

[0106] Fig.16Various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or systems-on-chip (SoC) are illustrated. For example, a mobile phone device 1602, a laptop computer device 1604, a fixed location terminal device 1606, a wearable device 1608, or a motor vehicle 1610 may include a device 1600 as described herein. The device 1600 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Fig.16 The devices 1602, 1604, 1606, and 1608, and the vehicle 1610 illustrated in the figure are merely exemplary. Other electronic devices can also feature the device 1600, including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0107] Figure 1-12 , 13A-13B and / or 14-16, one or more of the components, processes, features and / or functions illustrated in the embodiments of the present invention may be rearranged and / or combined into a single component, process, feature or function, or implemented in several components, processes or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 1-12 , 13A-13B and / or 14-16 and their corresponding descriptions in this disclosure are not limited to die and / or IC. In some implementations, Figure 1-12 , 13A-13B and / or 14-16 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink, and / or an interposer.

[0108] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various components, assemblies, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, for clarity, not all components and / or parts are shown. In some instances, the positioning, location, size, and / or shape of the various components and / or assemblies in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0109] The wording "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be interpreted as superior or superior to other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the features, advantages, or modes of operation discussed. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other - even if they are not in direct physical contact with each other. Object A coupled to object B may be coupled to at least a portion of object B. The term "electrically coupled" may mean that two objects are coupled together directly or indirectly so that an electric current (e.g., signal, power, ground) can be transferred between the two objects. Two electrically coupled objects may or may not have an electric current transfer between the two objects. The use of the terms "first", "second", "third", and "fourth" (and / or anything higher than the fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, the component referred to as the second component may be the first component, the second component, the third component, or the fourth component. The terms "encapsulate", "encapsulate" and / or any derivatives thereof refer to an object that may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may be considered a bottom component, and vice versa. As described in the present disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. Further note that the term "above" as used in the context of a component being located above another component in the present application may be used to indicate that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component being above a second component may mean: (1) the first component is above the second component, but not directly contacting the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component that is "in" a second component may be partially in the second component or completely in the second component. A value of about X-XX may mean a value between X and XX (inclusive). The value(s) between X and XX may be discrete or continuous. As used in the present disclosure, the term "about 'value X'" or "approximately value X" means within ten percent of 'value X'.For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0110] In some implementations, interconnection is an element or component that allows or facilitates electrical connection between two points, elements and / or components in a device or package. In some implementations, interconnection may include traces, through-holes, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnections. In some implementations, interconnection may include a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal), grounding, and / or power. Interconnection may include more than one element or component. Interconnection may be defined by one or more interconnections. Interconnection may include one or more metal layers. Interconnection may be a part of a circuit. Different implementations may use different processes and / or procedures to form interconnection. In some implementations, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spraying, and / or electroplating processes may be used to form interconnection.

[0111] It should also be noted that the various disclosures contained herein may be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe an operation as a sequential process, many operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0112] Further examples are described below to facilitate understanding of the present disclosure.

[0113] Aspect 1: A package includes a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to the substrate, wherein a back side of the second integrated device is coupled to a back side of the first integrated device by an adhesive. The substrate includes at least one dielectric layer and a plurality of interconnects.

[0114] Aspect 2: The package of aspect 1, further comprising a plurality of solder interconnects, wherein the substrate comprises a first portion and a second portion, wherein the first portion faces the second portion, and wherein the plurality of solder interconnects are coupled to the first portion and the second portion.

[0115] Aspect 3: The package according to any of aspects 1 to 2, wherein the substrate comprises a flexible portion configured to bend so that a back side of the first integrated device in the package faces a back side of the second integrated device.

[0116] Aspect 4: The package of aspects 1 to 3, wherein the at least one dielectric layer comprises a reinforced dielectric layer.

[0117] Aspect 5: The package of aspects 1 to 4, wherein the first integrated device comprises: a first metallization portion; a first semiconductor die; and a first encapsulation layer.

[0118] Aspect 6: The package of aspect 5, wherein the second integrated device comprises: a second metallization portion; a second semiconductor die; and a second encapsulation layer, wherein the second encapsulation layer of the second integrated device is coupled to the first encapsulation layer of the first integrated device by an adhesive.

[0119] Aspect 7: The package of aspects 1 to 6, further comprising a third integrated device coupled to the second surface of the substrate.

[0120] Aspect 8: The package of aspects 1 to 6, further comprising another package coupled to the second surface of the substrate.

[0121] Aspect 9: The package of aspects 1 to 8, wherein the substrate comprises a flexible portion, the flexible portion comprising an opening in the at least one dielectric layer.

[0122] Aspect 10: The package of aspects 1 to 9, wherein the second integrated device is located over the first integrated device such that a back side of the second integrated device faces a back side of the first integrated device.

[0123] Aspect 11: The package of aspects 1 to 10, wherein the first integrated device comprises a first chiplet, and wherein the second integrated device comprises a second chiplet.

[0124] Aspect 12: The package as described in Aspects 1 to 11 further includes a plurality of solder interconnects, wherein the substrate includes a flexible portion, the flexible portion is configured to bend so that the back side of the first integrated device in the package faces the back side of the second integrated device, wherein the substrate includes a first portion and a second portion, wherein the first portion faces the second portion, wherein the plurality of solder interconnects are coupled to the first portion and the second portion, wherein there are no solder interconnects between the first integrated device and the flexible portion of the substrate, and wherein there are no solder interconnects between the second integrated device and the flexible portion of the substrate.

[0125] Aspect 13: An apparatus comprising a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to the substrate, wherein a back side of the second integrated device is coupled to a back side of the first integrated device by an adhesive. The substrate comprises at least one dielectric layer; and a plurality of interconnects.

[0126] Aspect 14: The apparatus of aspect 13, further comprising a plurality of solder interconnects, wherein the substrate comprises a first portion and a second portion, wherein the first portion faces the second portion, and wherein the plurality of solder interconnects are coupled to the first portion and the second portion.

[0127] Aspect 15: The apparatus of any of aspects 13 to 14, wherein the substrate comprises a flexible portion configured to bend so that a back side of the first integrated device in the package faces a back side of the second integrated device.

[0128] Aspect 16: The apparatus of aspects 13 to 15, wherein the at least one dielectric layer comprises a reinforced dielectric layer.

[0129] Aspect 17: The apparatus of aspects 13 to 16, wherein the first integrated device comprises a first metallization portion; a first semiconductor die; and a first encapsulation layer.

[0130] Aspect 18: The apparatus of aspect 17, wherein the second integrated device comprises a second metallization portion; a second semiconductor die; and a second encapsulation layer, wherein the second encapsulation layer of the second integrated device is coupled to the first encapsulation layer of the first integrated device by an adhesive.

[0131] Aspect 19: The apparatus of any of aspects 13 to 18, further comprising a third integrated device coupled to the second surface of the substrate.

[0132] Aspect 20: The package of aspects 13 to 18, wherein the substrate comprises a flexible portion, the flexible portion comprising an opening in the at least one dielectric layer.

[0133] Aspect 21: A method for manufacturing a package. The method provides a substrate including at least one dielectric layer and a plurality of interconnects. The method couples a first integrated device to a first surface of the substrate. The method couples a second integrated device to the first surface of the substrate. The method bends the substrate and couples a back side of the second integrated device to a back side of the first integrated device via an adhesive.

[0134] Aspect 22: The method of aspect 21, further coupling a plurality of solder interconnects to the first portion and the second portion of the substrate, wherein bending the substrate causes the first portion to face the second portion.

[0135] Aspect 23: The method of any of aspects 21 to 22, wherein the substrate comprises a flexible portion configured to bend so that a back side of the first integrated device in the package faces a back side of the second integrated device.

[0136] Aspect 24: The method of aspects 21 to 23, wherein the at least one dielectric layer comprises a reinforcement dielectric layer.

[0137] Aspect 25: The method of aspects 21 to 24, wherein the first integrated device comprises a first metallization portion, a first semiconductor die, and a first encapsulation layer.

[0138] The various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative rather than limiting the scope of the appended claims. Thus, the teachings of the present disclosure may be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: A substrate, comprising: at least one dielectric layer; and Multiple interconnections; a first integrated device coupled to the first surface of the substrate; and A second integrated device is coupled to the first surface of the substrate, wherein a back side of the second integrated device is coupled to the back side of the first integrated device by an adhesive.

2. The package of claim 1, further comprising a plurality of solder interconnects, The substrate comprises a first portion and a second portion, wherein the first portion faces the second portion, and in, The plurality of solder interconnects are coupled to the first portion and the second portion. 3 . The package of claim 1 , wherein the substrate comprises a flexible portion configured to bend so that a back side of the first integrated device in the package faces a back side of the second integrated device. The package of claim 1 , wherein the at least one dielectric layer comprises a reinforced dielectric layer.

5. The package of claim 1 , wherein the first integrated device comprises: a first metallized portion; a first semiconductor die; as well as The first encapsulating layer.

6. The package according to claim 5, The second integrated device comprises: a second metallization portion; a second semiconductor die; as well as The second encapsulating layer, The second encapsulation layer of the second integrated device is coupled to the first encapsulation layer of the first integrated device through the adhesive.

7. The package of claim 1, further comprising a third integrated device coupled to the second surface of the substrate.

8. The package of claim 1, further comprising another package coupled to the second surface of the substrate.

9. The package of claim 1, wherein the substrate comprises a flexible portion, the flexible portion comprising an opening in the at least one dielectric layer.

10. The package of claim 1, wherein the second integrated device is located over the first integrated device such that a back side of the second integrated device faces a back side of the first integrated device.

11. The package according to claim 1, wherein the first integrated device comprises a first chiplet, and The second integrated device includes a second chiplet.

12. The package of claim 1, further comprising a plurality of solder interconnects, wherein the substrate comprises a flexible portion, the flexible portion being configured to bend so that the back side of the first integrated device in the package faces the back side of the second integrated device, The substrate comprises a first portion and a second portion, wherein the first portion faces the second portion, wherein the plurality of solder interconnects are coupled to the first portion and the second portion, wherein there is no solder interconnection between the first integrated device and the flexible portion of the substrate, and There is no solder interconnection between the second integrated device and the flexible portion of the substrate.

13. A device comprising: A substrate, comprising: at least one dielectric layer; and Multiple interconnections; a first integrated device coupled to the first surface of the substrate; and A second integrated device is coupled to the first surface of the substrate, wherein a back side of the second integrated device is coupled to the back side of the first integrated device by an adhesive.

14. The apparatus of claim 13, further comprising a plurality of solder interconnects, The substrate comprises a first portion and a second portion, wherein the first portion faces the second portion, and Wherein the plurality of solder interconnects are coupled to the first portion and the second portion.

15. The apparatus of claim 13, wherein the substrate comprises a flexible portion configured to bend so that a back side of the first integrated device in the package faces a back side of the second integrated device.

16. The apparatus of claim 13, wherein the at least one dielectric layer comprises a reinforced dielectric layer.

17. The apparatus of claim 13, wherein the first integrated device comprises: a first metallized portion; a first semiconductor die; as well as The first encapsulating layer.

18. The device according to claim 17, The second integrated device comprises: a second metallization portion; a second semiconductor die; as well as The second encapsulating layer, The second encapsulation layer of the second integrated device is coupled to the first encapsulation layer of the first integrated device through the adhesive.

19. The apparatus of claim 13, further comprising a third integrated device coupled to the second surface of the substrate.

20. The apparatus of claim 13, wherein the substrate comprises a flexible portion, the flexible portion comprising an opening in the at least one dielectric layer.

21. A method for manufacturing a package, comprising: A substrate is provided, the substrate comprising: at least one dielectric layer; and Multiple interconnections; coupling a first integrated device to the first surface of the substrate; and coupling a second integrated device to the first surface of the substrate; and The substrate is bent and a back side of the second integrated device is coupled to a back side of the first integrated device by an adhesive.

22. The method of claim 21, further coupling a plurality of solder interconnects to a first portion and a second portion of the substrate, wherein bending the substrate causes the first portion to face the second portion.

23. The method of claim 21, wherein the substrate comprises a flexible portion configured to bend so that a back side of the first integrated device in the package faces a back side of the second integrated device.

24. The method of claim 21, wherein the at least one dielectric layer comprises a reinforcement dielectric layer.

25. The method of claim 21, wherein: The first integrated device includes: a first metallization portion; a first semiconductor die; and The first encapsulating layer.

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