High performance hybrid bond interconnect system

Abstract

A high performance hybrid bond interconnect structure and a method for generating a high performance hybrid bond interconnect structure are disclosed. The interconnect structure may include a first plurality of die stacks bonded to a carrier. A protective layer may be disposed over at least a portion of the first plurality of die stacks and the second plurality of die stacks. A bridge layer including conductive interconnects provides electrical communication between the plurality of die stacks.

Description

Technical Field

[0001] The field relates to high performance three-dimensional joined structures and methods of forming high performance three-dimensional joined structures. Background Art

[0002] In semiconductor device packaging arrangements, integrated device chip stacking is used for many applications. For example, three-dimensional (3D) integration techniques typically utilize packaging in which two or more integrated device dies are stacked on top of each other and electrically connected to each other. Conventional methods for producing 3D integrated devices can limit product yields due to stresses applied to the die and substrate during assembly. Therefore, there is still a continuing need for improved systems and methods for stacking integrated device dies. Summary of the invention

[0003] In one embodiment, the bonding structure may include: a carrier; a first plurality of die stacks, each die stack including a plurality of dies, each die stack in the first plurality of die stacks being bonded to the carrier; a protective layer over at least a portion of the first plurality of die stacks; and a bridging layer including a non-conductive bridge layer and a lateral conductive interconnect; wherein the lateral conductive interconnect provides electrical connectivity between the first plurality of die stacks.

[0004] In some embodiments, the bonding structure may include a plurality of contact features at least partially embedded in a non-conductive bridge layer, wherein the lateral conductive interconnect provides electrical communication between at least two of the plurality of contact features. In some embodiments, the bonding structure may include at least one die stack directly bonded to the bridge layer without an adhesive. In some embodiments, the bonding structure may include a second plurality of die stacks directly bonded to the bridge layer and a bridging element directly bonded to the second plurality of die stacks. In some embodiments, the bonding structure may include at least one test pad at least partially embedded in the bridge layer, wherein the test pad is electrically connected to the first plurality of stacks and the second plurality of stacks. In some embodiments, the bonding structure may include a bridging element directly bonded to the bridge layer without an adhesive. In some embodiments, the bonding structure may include a cavity between the first stack and the second stack. In some embodiments, each stack in the first plurality of stacks includes a first die bonded to a second die without an adhesive. In some embodiments, the first non-conductive bonding layer of at least one of the plurality of stacks is directly bonded to a second non-conductive bonding layer of a carrier without an intermediate adhesive, wherein the first contact feature of at least one of the plurality of stacks is directly bonded to the second contact feature of the carrier without an intermediate adhesive. In some embodiments, the material of the protective layer is the same as the material of the bridge layer.

[0005] In another embodiment, the bonding structure may include: a first die stack including a first plurality of dies; a second die stack including a second plurality of dies; a protective layer disposed at least near lateral sides of the first die stack and the second die stack and between the first die stack and the second die stack; and a bridging layer disposed over the first die stack, the second die stack and the protective layer, the bridging layer providing electrical connectivity between the first die stack and the second die stack.

[0006] In some embodiments, a first plurality of dies within a first die stack are directly hybrid bonded. In some embodiments, a second plurality of dies within a second die stack are directly hybrid bonded. In some embodiments, the first die stack and the second die stack are directly hybrid bonded to a carrier. In some embodiments, the first die stack and the second die stack are directly hybrid bonded to a bridging element. In some embodiments, the bonding structure may include: a third die stack including a third plurality of dies, wherein the third die stack is directly hybrid bonded to a bridging layer, and a fourth die stack including a fourth plurality of dies, wherein the fourth die stack is directly hybrid bonded to a bridging layer. In some embodiments, the bonding structure may include a bridging element bonded to the third die stack and the fourth die stack. In some embodiments, the bonding structure may include at least one test pad embedded in the bridging layer, the test pad being configured to be electrically connected to the first die stack, the second die stack, the third die stack, and the fourth die stack.

[0007] In another embodiment, a method of forming a bonded structure is disclosed. The method may include: directly bonding a first plurality of stacks to a carrier, wherein each stack in the first plurality of stacks includes at least one die in contact with the carrier; providing a protective layer at least partially over at least a portion of the plurality of stacks; planarizing the protective material; and forming a non-conductive bridging layer including a non-conductive bridge layer and a lateral conductive interconnect, wherein the lateral conductive interconnect provides electrical connectivity between the first plurality of die stacks.

[0008] In some embodiments, the method may include forming a first plurality of contact features at least partially embedded in a non-conductive bridge layer, wherein a lateral conductive interconnect provides electrical connectivity between at least two of the first plurality of contact features. In some embodiments, the protective material is planarized to expose the contact features of the plurality of stacks. In some embodiments, each stack includes at least a first die bonded to a second die. In some embodiments, the method may include bonding the second plurality of stacks to the non-conductive bridging layer. In some embodiments, each stack in the second plurality of stacks is configured to be electrically connected to each stack in the first plurality of stacks. In some embodiments, the non-conductive bridging element is directly bonded to the second plurality of stacks. In some embodiments, the bridging element is directly bonded to the non-conductive bridging layer. In some embodiments, providing the protective layer further includes forming a cavity between the first stack and the second stack. In some embodiments, the non-conductive bridging layer further includes a test pad configured to be electrically connected to the first plurality of stacks.

[0009] In another embodiment, the bonding structure may include: a carrier; a first die stack having a first top die and a first bottom die, the first bottom die of the first stack being bonded to the carrier; a bridging layer including a non-conductive layer and a conductive interconnect, the bridging layer being disposed above the first top die of the first stack; and a second die stack having a second bottom die bonded (e.g., directly hybrid bonded) to an upper surface of the bridging layer, wherein the conductive interconnect of the bridging layer provides electrical connectivity between the first die stack and the second die stack.

[0010] In some embodiments, the bonded structure may include a third die stack bonded to the carrier, the bridging layer disposed over a third top die of the third stack.

[0011] In another embodiment, the bonding structure may include: a carrier having a non-conductive layer and a conductive feature at least partially embedded in the non-conductive layer; a first die stack having a first top die and a first bottom die, the first top die and the first bottom die of the first die stack each having a corresponding non-conductive layer and a conductive feature, the first bottom die of the first die stack being bonded to the carrier; a bridging layer including a non-conductive layer and a conductive interconnect, the bridging layer being disposed above the first top die of the first stack; and a second die stack having a second bottom die bonded (e.g., directly hybrid bonded) to an upper surface of the bridging layer, wherein the conductive interconnect of the bridging layer provides electrical connectivity between the first die stack and the second die stack.

[0012] In some embodiments, the bonding structure may include a third die stack bonded to the carrier, with a bridging layer disposed over a third top die of the third stack. In some embodiments, the conductive interconnect of the bridging layer includes a printed wire. In some embodiments, the bonding structure may include a wire bond connecting the first die stack and the second die stack.

[0013] For the purpose of summarizing the present disclosure and the advantages achieved over the prior art, some objects and advantages of the present disclosure are described herein. Not all such objects or advantages may be achieved in any particular embodiment. Thus, for example, those skilled in the art will recognize that the present invention may be implemented or performed in a manner that achieves or optimizes one advantage or a group of advantages taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0014] All of these embodiments are intended to be within the scope of the invention disclosed herein. These and other embodiments will become apparent to those skilled in the art from the following detailed description of the preferred embodiments with reference to the accompanying drawings, and the invention is not limited to any particular (one or more) preferred embodiments disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A-1B A microelectronic structure of conventional design is schematically shown.

[0016] Figure 2A-2G An example method for microelectronic device fabrication is schematically illustrated.

[0017] Figure 3A-3H Methods for forming microelectronic structures according to various embodiments are illustrated.

[0018] Figure 4A-4F Methods for forming microelectronic structures according to various embodiments are illustrated. DETAILED DESCRIPTION

[0019] Various embodiments disclosed herein can enable multiple arrays or stacks of monolithic integrated device dies (e.g., semiconductor devices, integrated circuit devices, etc.) to be mounted and electrically connected to each other via direct bonding to a carrier (e.g., a package substrate, a wafer, another integrated device die, a substrate, etc.). Forming multiple stacks (e.g., arrays) of directly bonded dies on a carrier can induce significant stress within the carrier material. Stress within the carrier material can reduce the flatness of the device and affect device yield during downstream production steps. In addition, electrical connectivity between a separate die of a first stack and a separate die of a second stack may be challenging because the only connectivity path between the first stack and the second stack passes through the carrier. Therefore, connectivity between two dies in adjacent die stacks may experience hysteresis or signal delay.

[0020] In some embodiments, protective materials that may include one or more protective layers may be applied on and around the die stack to reduce the stress caused by the stack in the carrier material and improve the flatness of the carrier. In addition, various embodiments disclosed herein promote effective electrical connectivity between separate die in the stack by using a bridging layer and / or a bridging element. Bridging layers and / or bridging elements may be produced on top of multiple stacks and configured to allow a stack to be electrically connected to other stacks through a bridging layer or a bridging element. In some embodiments, a bonded bridging die (e.g., a semiconductor device, an integrated circuit device, etc.) may electrically connect a first die stack to a second die stack. In some embodiments, a non-conductive (e.g., dielectric) bridging layer may be formed (e.g., deposited) and patterned with electrical contacts and traces to electrically connect multiple adjacent die stacks.

[0021] Thus, in various embodiments, the first die may be bonded (eg, using a hybrid direct bonding technique such as that used by Xperi, Inc. of San Jose, California) to form a first die bonded to the substrate. In some embodiments, a first die stack may be formed by directly bonding a series of dies on top of a first die. In some embodiments, each die in the stack is electrically connected to each other die in the same stack. Through substrate vias (TSVs) may provide vertical electrical connectivity between vertically adjacent dies in the stack. In some embodiments, a second die stack may be bonded to a carrier that is laterally adjacent to the first die stack. As in the first die stack, each individual die in the second die stack may be electrically connected to each other die in the second die stack. In various embodiments, one or more protective support materials may be provided over the first die stack and the second die stack. In some embodiments, conventional polishing or etching processes, such as chemical mechanical polishing (CMP) processes, may be used to flatten the support material. In some embodiments, one or more bridging layers may be deposited on the first die stack and the second die stack. In some embodiments, electrical contact structures and / or traces may be formed on, through, and / or within the bridging layer such that a topmost die of a first stack is in electrical communication with a topmost die of a second stack via the bridging layer.

[0022] Another advantage of forming a bonded stack structure according to the disclosed embodiments is that efficient direct bonding can be used to create larger and more complex 3D stack structures while maintaining low carrier stress and reducing signal path lengths while optimizing production yields. After depositing the bridging layer, in some embodiments, additional stacks can be directly bonded on top of the bridging dielectric layer. In some embodiments, a bridging element (e.g., a bridging die) can be provided additionally or alternatively to bridge the topmost dies of adjacent stacks. In some embodiments, additional stacks bonded to the top of the bridging dielectric layer or the bridging die can be electrically connected to the first die stack and the second die stack via the bridging dielectric layer or the bridging die.

[0023] Figure 1A-1B A conventional bonding structure on a carrier (e.g., a wafer, a printed circuit board, etc.) is schematically shown. Conventionally, a first die stack 101 (e.g., a semiconductor device, an integrated circuit device, etc.) is attached to a carrier 103 (e.g., a substrate, a wafer, another integrated device die, etc.) via a carrier bonding layer 115. In some arrangements, the stack 101 can be attached with an adhesive such as solder. In other arrangements, the stack 101 can be directly hybrid bonded to the carrier 103 without an adhesive. In various embodiments, the carrier 103 can include a wafer, a singulated integrated device die, a semiconductor interposer, a recombinant element, etc. The carrier bonding layer 115 can have a plurality of conductive contacts 117 at least partially embedded in the layer. Although depicted as a single layer, the carrier bonding layer 115 can include one or more dielectric layers. The second die stack 105 can be laterally adjacent to the first die stack 101 and attached to the carrier 103. In some arrangements, the stack 101 can be attached with an adhesive such as solder. In other arrangements, the stack 105 can be directly hybrid bonded to the carrier 103 without an adhesive.

[0024] Both the first die stack 101 and the second die stack 105 may include a plurality of individual dies 107 bonded to each other. Figure 1A, a first die stack 101 includes five (5) individual dies 107 bonded to one another. A first die 109 may include a front bonding layer 111 and a back bonding layer 113. Both the front 111 and back 113 bonding layers may include one or more dielectric layers and may have a plurality of conductive contacts 117 at least partially embedded in the front 111 and back 113 dielectric layers. A second die 119 including the front bonding layer 111 and the back bonding layer 113 may be bonded to the first die 109, wherein the plurality of conductive contacts may be at least partially embedded in the layers 111 and 113. Additional dies 107 may be bonded to the first die 109 and the second die 119 to form the first stack 101. Similar to the first stack, a second stack 105 may be formed in a laterally adjacent position on the carrier 103. Each die 107 of the second stack 105 may have a front side 111 and a back side 113 bonding layer, and a plurality of conductive contacts 117 may be at least partially embedded in the front side 111 and the back side 113 bonding layer. As with the first stack 101, the second stack 105 may include a stack of dies 107, wherein a first die 119 of the second stack 105 is attached (e.g., directly hybrid bonded) to the carrier 103, a second die 121 of the second stack 105 is bonded (e.g., directly hybrid bonded) to the first die 119, and so on. This stack bonding configuration may be repeated until a desired number of dies are bonded into the second stack 105. Each die (or each die except the topmost die in some arrangements) may include a through substrate via (TSV) (not shown) to provide vertical electrical connectivity between vertically adjacent dies. As the number of dies within the first 101 and second 105 stacks increases, the stress on the carrier 103 and the communication path length between the dies of the first 101 and second 105 stacks also increase.

[0025] Figure 1B The first stack 101 and the second stack 105 bonded to the carrier 103 are schematically illustrated. Figure 1BIn the configuration of , the stress on the carrier 103 may be high and may cause significant bending (unevenness) of the carrier 103. In addition, the signal path 123 between the topmost die (e.g., the 15th die 125) of the second stack 105 to the topmost die (e.g., the 15th die 127) of the first stack 101 is long. For example, for a 50μm thick direct-bonded die, the electrical path between the 15th die 127 of the first stack 101 and the bonding layer 115 of the carrier 103 is approximately 700μm (50×14 dies). Based on the foregoing, when considering the lateral traces in the bonding layer of the carrier, the electrical path between the 15th die 127 of the first stack 101 and the 15th die 125 of the second stack 105 is greater than 1400μm. The long signal path 123 may cause significant delays and slow signal processing when communicating between remote dies such as die 125 and 127. Furthermore, all electrical communications between the second stack 105 and the first stack 101 run through the carrier 103 along the signal path 123. Furthermore, there is no lateral support to support the first stack 101 and the second stack 105. This lack of lateral support can reduce the yield of downstream end products using devices having large first 101 and second 105 stacks.

[0026] Figure 2A-2G An example process for forming a plurality of die stacks (eg, semiconductor devices, integrated circuit devices, etc.) on a carrier 201 (eg, a wafer, a substrate, a die, etc.) is schematically illustrated. Figure 2A A carrier 201 having a first stack 209 and a second stack 211 is schematically illustrated, each stack having one die 207 and 213. In some embodiments, the carrier 201 includes a bonding layer 203 (e.g., one or more dielectric layers) having an at least partially embedded conductive contact 205. Although schematically shown as a single layer, it should be understood that the bonding layer 203 may include multiple dielectric layers. Multiple electrical contacts 205 may be at least partially embedded in the bonding layer 203. The first die 207 of the first stack 209 and the first die 213 of the second stack 211 may be directly hybrid bonded to the carrier 201. The first die 207 of the first stack 209 and the first die 213 of the second stack 211 may include a front 215 and a back 217 bonding layer. Both the front 215 and back 217 bonding layers may include one or more dielectric layers or sublayers. Multiple conductive contacts 205 may be at least partially embedded in the front 215 and back 217 bonding layers. Although not shown, a plurality of through substrate vias (TSVs) may provide electrical connectivity between the contacts 205 on the front side 215 bonding layer and the contacts 205 on the back side 217 bonding layer.

[0027] exist Figure 2BIn the embodiment of the present invention, a pair of second dies 219 and 221 (e.g., semiconductor devices, integrated circuit devices, etc.) can be directly hybrid bonded to the first die 207 of the first stack 209 and the first die 213 of the second stack 211, respectively. In some embodiments, the pair of second dies 219 and 221 each include a front bonding layer 223 and a back bonding layer 225. In some embodiments, one or both of the front bonding layer 223 and the back bonding layer 225 can be a dielectric layer having a conductive contact 205 at least partially embedded. Although described as a single layer 223 and 225, it should be understood that the layers 223 and 225 can include multiple dielectric layers or sub-layers. A pair of second dies 219 and 221 can be directly bonded to a pair of first dies 207 and 213 via bonding layers 217 and 223, respectively. Although not shown, multiple through-substrate vias (TSVs) can provide electrical connectivity between the contacts 205 on the front 223 bonding layer and the contacts 205 on the back 225 bonding layer.

[0028] exist Figure 2C In the embodiment of the present invention, a pair of third dies 227 and 229 can be directly bonded to a pair of second dies 219 and 221, respectively. In some embodiments, the pair of third dies 227 and 229 each include a front side 231 and a back side 233 bonding layer. In some embodiments, one or both of the front side 231 and the back side 233 bonding layers can be a dielectric layer with a conductive contact 205 at least partially embedded. Although illustrated as a single layer 231 and 233, it should be understood that the layers 231 and 235 can include multiple dielectric layers. In some embodiments, multiple conductive contacts 205 can be at least partially embedded in one or both of the front side 231 and the back side 233 bonding layers. The front bonding layer 231 of a pair of third dies 227 and 229 can be bonded to the back bonding layer 225 of a pair of second dies 219 and 221, respectively. Although not shown, multiple through substrate vias (TSVs) can provide electrical connectivity between the contacts 205 on the front side 231 bonding layer and the contacts 205 on the back side 233 bonding layer.

[0029] exist Figure 2D In Figure 2A-2CIn a similar manner, more pairs of dies 241 and 243 are added to the stack. More dies 241 and 243 can be bonded to the dies of the first stack 209 and the second stack 211. Any suitable number of dies can be provided in each stack 209, 211. Each stack 209, 211 may include the same number of stacked dies or different number of stacked dies. As more dies 241 and 243 can be bonded to the first stack 209 and the second stack 211, the longer the electrical communication path 244 (e.g., signal path) between the dies 245 of the first stack 209 and the dies 247 of the second stack 211 is. The longer the electrical communication path 244 may result in a slower processing speed between the stacks. In addition, because the first stack 209 can only be connected to the second stack 211 via the carrier 201, the signal path remains longer and the signal speed decreases as more dies 241 and 243 are added to the first stack 209 and the second stack 211, respectively. For example, the topmost die of the first stack 209 is connected to the topmost die of the second stack 211 via TSVs formed through the lower die of the first stack 209, traces in the carrier 201, and TSVs formed through the lower die of the second stack 211. The long signal path 244 between the two topmost dies (and between other dies in the stacks 209, 211) introduces hysteresis and delays that can degrade electrical performance.

[0030] exist Figure 2E In the embodiment of the present invention, a protective layer 245 can be deposited on and around the first stack 209 and the second stack 211 and over the exposed portion of the carrier dielectric layer 203. The protective layer 245 may include a coating or a molding compound that provides some lateral support to the first stack 209 and the second stack 211 during singulation or planarization. For example, the protective layer 245 may include an organic polymer such as an epoxy resin. In other embodiments, the protective layer 245 may include one or more inorganic dielectric materials (e.g., silicon oxide). In some embodiments, the protective layer 245 may include a laminate of multiple layers, including (e.g., inorganic and organic dielectric layers).

[0031] exist Figure 2F , the first stack 209 and the second stack 211 may be singulated. During singulation, the protective layer 245 may provide some lateral support and protection to the first stack 209 and the second stack 211. However, due to the stress generated in the carrier 201 by the first stack 209 and the second stack 211, the carrier 201 may experience significant stress during singulation, which may result in cracking and lower yield.

[0032] exist Figure 2G2, a monolithic module 250 may be produced from a plurality of stacked dies. The module may include a single die stack 252 or a plurality of die stacks 254 mounted (e.g., bonded) to a carrier 201. In a module 250 having a plurality of die stacks 254, all communications between adjacent die stacks 252 occur via the carrier 201. In addition, because there is little lateral support between the plurality of die stacks 254, the carrier 201 may deform or develop defects, such as cracks, due to stresses generated by the plurality of die stacks 254. When devices are produced using a module 250 having a plurality of die stacks 252 or 254, deformation of the carrier 201 may result in lower efficiency and yield.

[0033] Figure 3A-3H A method for forming a microelectronic structure according to one embodiment is illustrated. Figure 3A A pair of stacks 301 and 303 are shown, each stack may include a plurality of bonded dies 305 bonded (eg, directly hybrid bonded) to a carrier 307. Unless otherwise specified, Figure 3A Embodiment and production Figure 3A The method can be used with Figure 2A-2D Similar parts and structures are the same or substantially similar. For example, production Figure 3A The steps of the structure can be combined with the above Figure 2A-2D The steps described are the same or substantially similar.

[0034] Figure 3BA first protective layer 309 disposed on the stacks 301, 303 is illustrated. The first protective layer 309 may be disposed (e.g., deposited) on the carrier 307, the first stack 301, and the second stack 303. Depositing the first protective layer 309 may create an empty cavity 310 (e.g., without any material or protective layer 310) between the first stack 301 and the second stack 303. The first protective layer 309 may include a material with a low coefficient of thermal expansion. The first protective layer 309 may include an organic or inorganic non-conductive material. In some embodiments, the first protective layer 309 may include a silicon-containing dielectric layer, which may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, or even silicate. In some embodiments, the first protective layer 309 may include a plurality of layers of different dielectric materials. For example, a nitrogen-containing dielectric layer may be coated on the surfaces of the stacked dies 301 and 303 and the exposed bonding surfaces of the carrier 307. An oxygen-containing dielectric layer may be coated on the nitrogen-containing dielectric layer. In some embodiments, the first protective layer may include a granular composite material. Depending on the properties of the first protective material 309, the exposed surfaces of the stacked dies 301, 303 and the carrier may be treated with a nitrogen-containing plasma before applying the first protective layer 309. For example, in some embodiments, the first protective layer 309 may include a sealant or a molding compound, such as a non-conductive epoxy. In some embodiments, the use of a material with a low coefficient of thermal expansion may be beneficial for reducing stress on the carrier 307. In some embodiments, the thermal expansion of the first protective layer may be less than 20ppm / °C, less than 15ppm / °C, or less than 10ppm / °C. In some embodiments, the first protective layer 309 may include a porous material, or a portion of the first protective layer 309 may include a porous material. In some embodiments, the substrate of the topmost die of the stack 301 and 303 may include an embedded through-substrate via (TSV) (not shown). In this case, a portion of the substrate of the topmost die may be selectively removed to expose the protruding TSV and its encapsulation liner. The first protective layer 309 may be formed over the exposed surface of the substrate of the topmost die and the top surface of the carrier 307. In some embodiments, selectively removing portions of the substrate of the topmost die may include forming a temporary protective layer over the exposed top surface of the carrier. After forming the protruding TSVs, the carrier and bonded die stacks 301 and 303 may be cleaned to remove any unwanted defect-forming materials and the temporary protective layer protecting the carrier surface. The cleaned surface may then be coated with a first protective layer 309.

[0035] During device operation, the first stack 301 and the second stack 303 generate heat. Due to the low thermal expansion coefficient of the first protective layer 309, the heat generated by the first stack 301 and the second stack 303 (or the devices in the carrier 307) will not generate heat on the carrier 307 or the stacked devices 301 and 303. Figures 2A-2DThe first protective layer 309 can provide lateral support for the stacks 301 and 303. In some embodiments, the lateral support of the stacks 301 and 303 can prevent the stacks 301 and 303 from being damaged during additional processing steps (such as planarization and etching).

[0036] Figure 3C The planarization of the first protective layer 309 is illustrated. The first protective layer 309 can be planarized using chemical mechanical processing (CMP) or other suitable methods. The planarization step can include polishing the first protective layer 309 deposited on the back bonding surface of the topmost tube core of the stack 301 and 303 to expose or form a flat and smooth bonding surface and embedded conductive pads. In other embodiments, the planarization process can polish away a portion of the first protective layer 309 to form a flat and smooth residual first protective layer on the bonding surface of the topmost tube core of the stack 301 and 303. As previously described, in some embodiments including protruding TSVs embedded in the protective layer 309, the first protective layer 309 can be planarized to remove portions of the first protective layer 302 and portions of the protruding TSVs to expose the conductive layer within the TSV. Because the first protective layer 309 can provide lateral support for the stack 301 and 303, the planarization of the first protective layer 309 does not damage or adversely affect the functionality of the stack 301, 303 and the carrier 307.

[0037] Figure 3DThe deposition of the second protective layer 311 is illustrated. The second protective layer 311 may include a material having a low coefficient of thermal expansion, such as an inorganic dielectric. The second protective layer 311 may include a semiconductor-containing dielectric layer, such as a silicon-containing dielectric layer, which may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon carbonitride. In some embodiments, the second protective layer 311 may include a plurality of layers of different dielectric materials. For example, a nitrogen-containing dielectric layer may be coated on the surface of the stacked dies 301 and 303 and the exposed surface of the carrier 311. An oxygen-containing dielectric layer may be coated on the nitrogen-containing dielectric layer. In some embodiments, the second protective layer may include a particle composite material. Depending on the properties of the second protective material 311, the exposed surfaces of the stacked dies 301, 303 and the first protective layer 309 on the carrier 307 may be treated with a nitrogen-containing plasma before applying the second protective layer 311. The second protective layer 311 may be disposed (e.g., deposited) on and around the pair of stacks 301 and 303 and the first protective layer 309. The second protective layer 311 can provide further lateral support for the stacks 301 and 303 and reduce stress on the carrier 307 in a similar manner as the first protective layer 309. The second protective layer 311 can also fill the cavity (e.g., empty vertical space) between the first stack 301 and the second stack 303. The second protective layer 311 can include an organic or inorganic non-conductive material. For example, in some embodiments, the second protective layer 311 can include a sealant or a molding compound, such as a non-conductive epoxy.

[0038] Figure 3E Planarization of the second protective layer 311 is illustrated. The second protective layer 311 may be planarized using chemical mechanical processing (CMP) or other suitable methods. Because the second protective layer 311 may provide lateral support for the stacks 301 and 303, planarization of the second protective layer 311 may not damage or adversely affect the functionality of the stacks 301 and 303. In some embodiments, the second protective layer 311 may not be provided. In such embodiments, the first protective layer 309 may bridge the gap 310 between the first bagged die 301 and the second stacked die 303 and may be sufficient for subsequent processing operations after planarization of the layer 309.

[0039] Figure 3FThe deposition of a bridging layer 312 is illustrated, and the bridging layer 312 includes a non-conductive bridge layer 313 on the back side of the first 301 and second 303 stacks and the first protective layer 309 and the second protective layer 311. The non-conductive bridge layer 313 may include a non-conductive layer (e.g., a dielectric layer). Although illustrated as a single layer, the bridge layer 313 may include multiple dielectric layers or sub-layers. In some embodiments, the non-conductive bridge layer 313 may include an inorganic dielectric, such as silicon oxide, silicon nitride, etc. The bridge layer 313 may be a bridging layer deposited on both the first stack 301 and the second stack 303. Therefore, the non-conductive bridge layer 313 may not include a separate discrete element attached, bonded, or bonded on the stacks 301, 303. In contrast, the non-conductive bridge layer 313 may be deposited over the topmost die 304, portions of the first protective layer 309 (e.g., portions of the first protective layer 309 disposed around the respective stacks 301, 303), and portions of the second protective layer 311 (e.g., portions of the second protective layer 311 disposed between portions of the first protective layer 309 between the stacks 301, 303).

[0040] Figure 3G Conductive structures 315 and conductive interconnect layers 314 are illustrated as being formed in the non-conductive bridge layer 313. In some embodiments, the bridge layer 312 may include a non-conductive bridge layer 313 with a conductive interconnect layer 314. The conductive structures 315 may be patterned at least partially in the non-conductive bridge layer 313 and may be in electrical communication with the first 301 and second stacks 303. Additional electrical interconnect layers 314 may be patterned on or at least partially in the non-conductive bridge layer 313. The electrical interconnect layer 314 may be configured to electrically connect the first stack 301 with the second stack 303. In some embodiments, the electrical connection between the first stack 301 and the second stack 303 through the electrical interconnect layer 314 may result in more than one electrical communication path 317 between the dies 319 of the adjacent stacks 301, 303. In some embodiments, the die 319 of the second stack 303 may be in communication with the die 319 of the first stack 301 through the carrier 307 or through the electrical interconnect layer 314. For example, some dies 319 (e.g., dies in the upper portion of the stacks 301, 303) may be connected via TSVs in the respective stacks 301, 303 and the interconnect layer 314. Other dies 319 (e.g., dies in the lower portion of the stacks 301, 303) may be connected via TSVs in the respective stacks 301, 303 and traces (not shown) in the carrier 307. In some embodiments, having more than one electrical communication path 317 from the second stack 303 to the first stack 301 may result in increased signal speed and reduced energy consumption. It should be understood that although in Figure 3A-3G307, two adjacent stacks 301, 303 are shown, but in some embodiments, more than two adjacent stacks 301, 303 may be provided on the carrier 307. For example, two, three, four or more die stacks may be provided on the carrier, at least partially encapsulated by (one or more) protective layers 309, 311, and electrically connected by a bridge layer 312. In some embodiments, the bridge layer may include a planarized non-conductive layer 309 or 311 that bridges a gap 310 between the first conductive die stack 301 and the second conductive die stack 303. In this embodiment, a conductive structure 315 and a conductive interconnect layer 314 may be formed in the non-conductive bridge layer 309 or 311. The conductive structure 315 may be patterned at least partially in the non-conductive bridge layer 309 or 311, and may be in electrical communication with the first stack 301 and the second stack 303, respectively. A further electrical interconnect layer 314 may be patterned on or at least partially in the non-conductive bridging layer 309 or 311 .

[0041] In some embodiments, instead of using a deposited conductive interconnect layer 314, wire bonding can be used to form a bridge that electrically connects the corresponding conductive structure 315 to an adjacent die stack. In some embodiments, the conductive interconnect layer 314 may include printed conductive nanometal particles. For example, in some embodiments, the printed (e.g., deposited) conductive interconnect layer 314 may include silver nanoparticles. After forming the printed (e.g., deposited) circuit, the nanoparticles of the circuit may be densified by thermal treatment, such as in an oven or by a rapid thermal annealing furnace such as RTP or by laser annealing. In some embodiments, the printed circuit may be densified in a microwave oven, preferably at a temperature below 180°C, which is typically used for oven processing temperatures. In some embodiments, the resistivity of the printed conductive interconnect layer 314 may be less than 5μΩcm, less than 4μΩcm, or less than 3μΩcm.

[0042] Figure 3H The bonding of the third 321 and fourth 323 stacks that can be formed on top of the interconnect layer 314 and the bridge layer 312 is illustrated. Similar to the first 301 and second 303 stacks, the third 321 and fourth 323 stacks can be formed by bonding the die 325 to each other as described above (e.g., by direct hybrid bonding). Although both the third 321 and fourth 323 stacks are illustrated as including five (5) die 325, it should be understood that both the third 321 and fourth 323 stacks can include more than five die 325 or less than five die 325. In some embodiments, the non-conductive bridge layer 309, 311, or 314 can include, for example, Figure 4F The test pad 431 shown is used to test, for example Figure 3HThe electrical yield, continuity, resistance and other desired electrical functionality between the various dies and stacks (including the circuits in the carrier 307) can be measured. Electrical testing can be provided to characterize device yield and known good dies before singulation operations. In some embodiments, Figure 3H The structure shown can be singulated into multiple devices as explained above.

[0043] Figure 4A-4F Other embodiments of 3D stacking are illustrated that enable the formation of a stack 403 with multiple electrical connection routes. Unless otherwise specified, Figure 4A-4F The components are usually similar to Figure 3A-3H For example, as explained above, and as Figure 4A As shown, a carrier 401 (e.g., a wafer, a substrate, etc.) may have a plurality of stacks 403 bonded to a surface of the carrier 401. As explained above, a first protective layer 405 may be deposited on and around the plurality of stacks 403. The first protective layer 405 may be planarized, and if desired, a second protective layer 407 may be deposited on the first protective layer 405. As above, in some embodiments, the second protective layer 407 may be planarized. A bridging layer 410 may be formed on top of the plurality of stacks 403 and the first 405 and second 407 protective layers or on the first planarized protective layer 405. The bridging layer 410 may include a non-conductive bridging layer 409 (e.g., a dielectric layer) and a plurality of electrical contact features 412. In other embodiments, a portion of the first protective layer 405 may be used as a bridging layer 410 (e.g., a portion of the protective layer 405 may remain disposed on the stack and patterned with a conductor). The non-conductive bridging layer 409 may include one or more dielectric layers or sub-layers. As above, the electrical interconnect structure 411 may be patterned on the non-conductive bridging layer 409 or at least partially embedded in the non-conductive bridging layer 409. The electrical interconnect structure 411 may include a plurality of electrical vias and traces and may be configured to electrically connect the plurality of stacks 403 to each other. Figure 3HDifferent, the bridging die 413 can be bonded to (e.g., directly hybrid bonded to) the dielectric bridging layer 409. In such embodiments, the bridging layer 410 can be used as a bonding layer, which can be prepared for direct bonding as described herein. In some embodiments, the bridging die 413 can be directly hybrid bonded to the bonding surface of the bridging layer 410. In other embodiments, the bridging die 413 can be attached to the bridging layer 410 with an adhesive (e.g., with solder). The bridging die 413 may include a semiconductor device, a wafer, or other semiconductor device or element. In some embodiments, the bridging die 413 includes a bonding layer 415, which may include one or more dielectric layers or sublayers. In some embodiments, the bonding layer 415 can be deposited on the bridging layer 410 and directly bonded to the corresponding bonding surface or layer of the tube die 413. In some embodiments, the bonding layer 415 can be formed on the tube die 413 and then directly bonded to the bridging layer 410. A series of electrical contact structures 417 can be patterned on the bonding layer 415 or at least partially in the bonding layer 415. The bridging die 413 may provide additional support to the plurality of stacks 403 and add additional desired functionality to the 3D microstructure 400. The bridging die 411 may be in electrical communication or contact with the plurality of stacks 403 and the carrier 401.

[0044] like Figure 4B As shown, in some embodiments, the carrier 401 may have a plurality of stacks 403 bonded to a surface of the carrier 401. As explained above, a first protective layer 405 may be deposited over and around the plurality of stacks 403. The first protective layer 405 may be planarized, and if desired, a second protective layer 407 may be deposited over the first protective layer 405. As above, in some embodiments, the second protective layer 407 may be planarized. A bridging element 413 may be bonded to the plurality of stacks 403. The bridging element 413 (e.g., a wafer) semiconductor element, an integrated circuit device, or the like may include a bonding layer 415. The bonding layer 415 may include one or more dielectric layers or sub-layers. A plurality of contact features 416 may be at least partially embedded within the bonding layer 415. Figure 4A Different, in Figure 4B In the embodiment of the present invention, the bridging element 413 may allow electrical communication between the plurality of stacks 403 through conductive features in the bonding layer of the bridging element 413 .

[0045] like Figure 4C As shown, in some embodiments, the method explained above can be set as follows Figure 3H The structure described. In production Figure 3HFollowing the described structure, a second plurality of stacks 417 can be bonded on top of the bridging layer 410, each stack including one or more die 419. The bridging layer 410 can include a non-conductive bonding layer 409 (e.g., a dielectric layer) and a plurality of contact features 412. A bridging die 413 including a bonding layer 415 can be bonded to (e.g., directly hybrid bonded to) the second plurality of stacks 417. Although shown as a layer, the bonding layer 415 can include one or more dielectric layers or sub-layers. The contact structure 421 can be patterned on the bonding layer 415 or at least partially in the bonding layer 415. The first plurality of stacks 403 can be electrically connected to each other through the dielectric bridging layer 409 or the carrier 401. The second plurality of stacks 417 can be electrically connected to each other through the dielectric bridging layer 409 and / or through the bridging die 413. The second plurality of stacks 417 can be electrically connected to the first plurality of stacks through the dielectric bridging layer 409. As Figure 4C As shown, the bridging die 413 may bridge the gap 418 between adjacent stacks 417 .

[0046] like Figure 4D As shown, in some embodiments, substantially similar methods and components can be used to provide Figure 4B However, Figure 4D Differently, after the plurality of stacks 403 are bonded to the carrier 401, the first protective layer 405 can be deposited on and above the plurality of stacks 403 and the carrier 401. As described above, CMP or other suitable methods can be used to planarize the first protective layer 405. After the first protective layer 405 is planarized, a bridging bonding layer can be deposited on the plurality of stacks 403 and the first protective layer 405, but the second protective layer is not deposited. Depositing the bridging bonding layer 409 can form a cavity 423 between the plurality of stacks 403. The cavity 423 or the inter-die cavity can lead to further flexibility in the carrier 401. The cavity 423 can allow the microstructure to move slightly and relieve the stress accumulated between the plurality of stacks 403 and on the carrier 401. In some embodiments, the bridging bonding layer can be omitted, or the bridging bonding layer can be made on the surface of the bridging die 413. The bridging die 413 can be bonded on the die stacks 401 and 403 to provide connectivity between all bonded dies and the carrier 401.

[0047] like Figure 4E As shown, in some embodiments, a substantially similar structure to 3A with substantially similar components can be fabricated. The structure includes a carrier 401 and a plurality of die stacks 403. After bonding the plurality of die stacks 403, a first protective layer 409 can be deposited on and around the plurality of die stacks 403. Figure 3A The first protective layer 409 will then be covered by the second protective layer. Figure 4EIn the embodiment, no second protective layer is provided. Figure 4E In the embodiment, a bridging layer 410 made of the same material as the first protective layer 409 may be provided on the protective layer 409. The bridging layer 410 may include a plurality of contact structures 425 patterned on or in the bridging layer 410. Similarly, the bridging interconnect structure 411 may be at least partially formed in the bridging layer 410. In some embodiments, the electrical contact structure 425 may include a redistribution layer. In some embodiments, the redistribution layer or the contact structure may be made of copper. In some embodiments, the plurality of stacks 403 may be electrically connected to other stacks through the bridging interconnect structure 411 or through the carrier 401.

[0048] like Figure 4F As shown, in some embodiments, a Figure 4C . As described above, the first plurality of stacks 403 can be bonded (e.g., directly hybrid bonded) to the carrier 401. The first protective layer 405 can be deposited on and around the first plurality of die stacks 403. In some embodiments, the first protective layer 405 can be planarized. Then, the second protective layer 407 can be deposited on the first protective layer 405. The second protective layer 407 can be planarized, and a bridging bonding layer 409 is deposited on the first plurality of stacks 403. In some embodiments, the first 405 and second 407 protective layers and the bridging layer 409 can include similar or dissimilar dielectric materials. In some embodiments, the first protective layer or the second protective layer can include a bridging layer. The second plurality of stacks 419 can be bonded to the bridging bonding layer 409 in turn, and the bridging die 413 can be bonded to the second plurality of die stacks 419. However, similar to Figure 4C Different, in Figure 4F 4, a test pad structure 431 may be patterned into the bridge bonding layer 409 and electrically connected to the electrical interconnect structure 411 and the first plurality of die stacks 403 and the second plurality of die stacks 419 and the carrier 401. The test pad structure 431 may allow a manual or automated probe to test the functionality of any of the first plurality of die stacks 403, the second plurality of die stacks 419, the carrier 401, or the bridge die 413.

[0049] In some embodiments, Figure 4F The stacked structure may be encapsulated, and the encapsulant may be planarized. The planarized surface may be attached to another carrier (not shown) to expose the back surface of the carrier 401. The back surface of the carrier may be processed to bond to a bridge layer 409 of another substrate, such as Figure 4EAs shown. The resulting structure may include more than one bridge layer 409. The bridge layer 409 may be used as an interposer (one or more) of the stacked die array on both sides of the interconnect bridge layer 409. Processing the back side of the carrier 401 may include thinning, polishing, and exposing the embedded conductors in the carrier 401. In some embodiments, a planar bonding surface with embedded conductors may be formed on the back side of the carrier 401. In some embodiments, the back side of the carrier 401 may include a solderable block or an alloy block. Similarly, depending on the design parameters, the solderable block or the alloy block may be provided as a conductive feature on the bridge layer 409.

[0050] Example of direct bonding

[0051] Various embodiments disclosed herein relate to a direct bonding structure, in which two elements can be directly bonded to each other without an intermediate adhesive. The structure of the direct bonding includes two elements, and it can be directly bonded to each other without an intermediate adhesive. Two or more semiconductor elements (such as integrated device die, wafer, etc.) can be stacked or bonded to form a bonding structure. The conductive contact pad of the first element can be electrically connected to the corresponding conductive contact pad of the second element. Any suitable number of elements can be stacked in the bonding structure. For example, the third element can be stacked on the second element, the fourth element can be stacked on the third element, and so on. Additionally or alternatively, one or more additional elements can be stacked adjacent to each other laterally along the first element. In some embodiments, the additional elements stacked laterally can be smaller than the second element. In some embodiments, the additional elements stacked laterally can be twice smaller than the second element.

[0052] In some embodiments, elements are directly bonded to each other without adhesive. In various embodiments, non-conductive material or dielectric material can be used as the first bonding layer of the first element, and the first bonding layer can be directly bonded to the corresponding non-conductive or dielectric field region of the second bonding layer used as the second element without adhesive. The non-conductive bonding layer can be arranged on each front side of the device, such as the semiconductor (e.g., silicon) part of the element. Active devices and / or circuit devices can be patterned and / or otherwise arranged in the device part or on the device part. Active devices and / or circuit devices can be arranged on the front side of the device part or near it, and / or arranged on the relative back side of the device part or near it. Non-conductive material can be referred to as the non-conductive bonding area or bonding layer of the first element. In some embodiments, the non-conductive bonding layer of the first element can be directly bonded to the corresponding non-conductive bonding layer of the second element using dielectric to dielectric bonding technology. For example, a non-conductive bond or dielectric-to-dielectric bond is formed without an adhesive using direct bonding techniques disclosed in at least U.S. Pat. Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference in their entirety and for all purposes. It should be understood that in various embodiments, the bonding layer may include a non-conductive material, such as a dielectric material, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or may include carbon, such as silicon carbide, silicon carbonitride, low-K dielectric materials, SICOH dielectrics, silicon carbonitride, or diamond-like carbon, or materials including diamond surfaces. Despite the inclusion of carbon, such carbon-containing ceramic materials may be considered inorganic.

[0053] In various embodiments, direct hybrid bonding can be formed without an intermediate adhesive. For example, the non-conductive bonding surface can be polished to a high smoothness. The bonding surface can be cleaned and exposed to plasma and / or an etchant to activate the surface. In some embodiments, the surface can be terminated with a substance after activation or during activation (e.g., during a plasma and / or etching process). Without being limited by theory, in some embodiments, an activation process can be performed to break the chemical bonds at the bonding surface, and the termination process can provide additional chemicals at the bonding surface, which improves the bonding energy during direct bonding. In some embodiments, activation and termination are provided in the same step (e.g., plasma activation and termination surfaces). In other embodiments, the bonding surface can be terminated in a separate process to provide additional substances for direct bonding. In various embodiments, the termination substance can include nitrogen. For example, in some embodiments, (one or more) bonding surfaces can be exposed to a nitrogen-containing plasma. In addition, in some embodiments, the bonding surface can be exposed to fluorine. For example, there may be one or more fluorine peaks near the layer and / or bonding interface. Thus, in a directly bonded structure, the bonding interface (e.g., bonding layer) between the two non-conductive materials may include a very smooth interface with a high nitrogen content and / or fluorine peak at the bonding interface. Additional examples of activation and / or termination treatments may be found in U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference in their entirety and for all purposes.

[0054] In various embodiments, the conductive contact pads of the first element may also be directly bonded to corresponding conductive contact pads of the second element. For example, hybrid bonding techniques may be used to provide conductor-to-conductor direct bonding along a bonding interface comprising covalently directly bonded non-conductive to non-conductive (e.g., dielectric to dielectric) surfaces prepared as described above. In various embodiments, direct bonding techniques disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988 may be used to form conductor-to-conductor (e.g., contact pad to contact pad) direct bonding and dielectric-to-dielectric hybrid bonding, the entire contents of each of which are incorporated by reference in their entirety and for all purposes.

[0055] For example, a non-conductive (e.g., dielectric) bonding surface (e.g., an inorganic dielectric surface) can be prepared and directly bonded to each other without an intermediate adhesive as explained above. Conductive contact features (e.g., contact pads that can be surrounded by a non-conductive dielectric field region within a bonding layer) can also be directly bonded to each other without an intermediate adhesive. In various embodiments, the conductive contact feature may include a discrete pad at least partially embedded in the non-conductive field region. In some embodiments, the conductive contact feature may include an exposed contact surface of a through-substrate via (TSV). In some embodiments, the corresponding contact pads 106a and 106b may be recessed below the outer (e.g., upper) surface of the dielectric field or non-conductive bonding layer, for example, the recess is less than 30nm, less than 20nm, less than 15nm, or less than 10nm, for example, the recess is in the range of 2nm to 20nm, or in the range of 4nm to 10nm. In various embodiments, before direct bonding, the size of the groove in the relative element can be designed so that the total gap between the relative contact pads is less than 15nm, or less than 10nm. In some embodiments, the non-conductive bonding layers can be directly bonded to each other at room temperature without an adhesive, and then the bonded structure can be annealed. Upon annealing, the contact pads can expand and contact each other to form a direct metal-to-metal bond. Advantageously, the non-conductive bonding layers can be directly bonded to each other without an adhesive at room temperature, and then the bonded structure can be annealed. Upon annealing, the contact pads can expand and contact each other to form a direct metal-to-metal bond. Advantageously, the non-conductive bonding layers can be directly bonded to each other using a bonding agent available from Xperi Corporation in San Jose, California. Commercially available direct bonding interconnect or DBI technology can enable high-density pads to be connected directly across the bonding interface (e.g., small pitch or fine pitch of regular stacking). In some embodiments, the pitch of the pads, or the pitch of the conductive traces in the bonding surface of one of the bonding elements embedded in the bonding element, can be less than 40 microns or less than 10 microns or even less than 2 microns. For some applications, the ratio of the pitch of the bonding pads 106a and 106b to one of the dimensions of the bonding pads (e.g., diameter) is less than 5, or less than 3, and sometimes desirably less than 2. In other applications, the width of the conductive traces in the bonding surface of one of the bonding elements embedded in the bonding element can be in the range of between 0.3 microns and 20 microns (e.g., in the range of 0.3 microns to 3 microns). In various embodiments, the contact pads and / or traces may include copper, but other metals may be suitable.

[0056] Therefore, in the direct bonding process, the first element can be directly bonded to the second element without an intermediate adhesive. In some arrangements, the first element may include a singulated element, such as a singulated integrated device die. In other arrangements, as shown, the first element may include a carrier or substrate (such as a wafer), which includes multiple (such as tens, hundreds or more) device regions, which form multiple integrated device dies when being singulated. Similarly, the second element 104 may include a singulated element, such as a singulated integrated device die. In other arrangements, the second element may include a carrier or substrate (such as a wafer). Therefore, the embodiments disclosed herein may be applied to wafer to wafer, die to die or die to wafer bonding processes. In wafer to wafer (W2W) processes, two or more wafers may be directly bonded to each other (such as directly hybrid bonding) and singulated using a suitable singulation process. After singulation, side edges of the singulated structures (eg, side edges of two bonded elements) may be substantially flush and may include markings indicative of the singulation process (eg, saw marks if a saw singulation process is used).

[0057] As explained herein, the first element and the second element can be directly bonded to each other without an adhesive, which is different from a deposition process. In one application, the width of the first element in the bonding structure is similar to the width of the second element. In some other embodiments, the width of the first element in the bonding structure is different from the width of the second element. Similarly, the width or area of ​​the larger element in the bonding structure can be greater than at least 10% of the width or area of ​​the smaller element. Therefore, the first element and the second element can include non-deposition elements. In addition, unlike the deposition layer, the structure of direct bonding can include a defective area along the bonding interface 118, in which there is a nanometer-scale void (nano void). The nano void may be formed due to the activation of the bonding surface (e.g., exposure to plasma). As explained above, the bonding interface may include material concentrations from activation and / or the last chemical treatment process. For example, in an embodiment activated by nitrogen plasma, a nitrogen peak can be formed at the bonding interface. The nitrogen peak can be detected using secondary ion mass spectrometry (SIMS) technology. In various embodiments, for example, nitrogen termination treatment (e.g., exposing the bonding surface to nitrogen-containing plasma) can be replaced with NH2 molecules to hydrolyze (OH-terminated) the OH group on the surface, producing a nitrogen-terminated surface. In embodiments where activation is performed using oxygen plasma, an oxygen peak may be formed at the bonding interface. In some embodiments, the bonding interface may include silicon oxynitride, silicon carbonitride or silicon carbonitride. As explained herein, direct bonds may include covalent bonds, which are stronger than van der Waals bonds. The bonding layers 108a and 108b may also include polished surfaces that are planarized to a high degree of smoothness.

[0058] In various embodiments, a metal-to-metal bond between bonding contact pads may be provided so that copper grains grow across each other across the bonding interface. In some embodiments, the copper may have grains oriented along 111 crystal planes to improve diffusion of copper across the bonding interface. The bonding interface may extend substantially completely to at least a portion of the bonding contact pads so that there is substantially no gap between the non-conductive bonding layers at or near the bonding contact pads. In some embodiments, a barrier layer (e.g., which may include copper) may be provided below the contact pads. However, in other embodiments, there may be no barrier layer below the contact pads, for example, as described in U.S. Patent No. 11,195,748, which is incorporated herein by reference in its entirety and for all purposes.

[0059] Advantageously, use of the hybrid soldering techniques described herein may allow for extremely fine pitches between adjacent contact pads and / or extremely small pad sizes. For example, in various embodiments, the pitch p (i.e., edge-to-edge or center-to-center distance between adjacent pads) may be in the range of 0.5 microns to 50 microns, in the range of 0.75 microns to 25 microns, in the range of 1 micron to 25 microns, in the range of 1 micron to 10 microns, or in the range of 1 micron to 5 microns. Additionally, the major lateral dimensions (e.g., pad diameters) may also be very small (e.g., in the range of 0.25 microns to 30 microns, in the range of 0.25 microns to 5 microns, or in the range of 0.5 microns to 5 microns).

[0060] Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprise", "comprising", "include", "including", etc. should be interpreted as including, rather than exclusive or exhaustive; that is, in the sense of "including, but not limited to". The word "coupled" as generally used herein refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Similarly, the word "connected" as generally used herein refers to two or more elements that can be directly connected or connected through one or more intermediate elements. In addition, when used in this application, the words "herein", "above", "below" and words of similar meaning shall refer to the entirety of this application, rather than to any particular part of this application. In addition, as used herein, when a first element is described as being "on" or "above" a second element, the first element can be directly on or above the second element, so that the first element and the second element are in direct contact, or the first element can be indirectly on or above the second element, so that one or more elements are between the first element and the second element. Where the context permits, words used in the singular or plural in the above detailed description may also include the plural or singular, respectively. The word "or," when referring to a list of two or more items, encompasses all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0061] In addition, conditional language used herein, such as "can", "could", "might", "may", "eg", "for example", "such as", etc., unless otherwise specifically stated or otherwise understood in the context of use, is generally intended to convey that some embodiments include, while other embodiments do not include, certain features, elements and / or states. Therefore, such conditional language is generally not intended to imply that one or more embodiments require the features, elements and / or states in any way.

[0062] Although some embodiments have been described, these embodiments are presented only by way of example and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein may be embodied in various other forms; in addition, various omissions, substitutions, and changes may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although the blocks are presented in a given arrangement, alternative embodiments may perform similar functionality with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and actions of the various embodiments described above may be combined to provide additional embodiments. The attached claims and their equivalents are intended to cover forms or modifications that will fall within the scope and spirit of the present disclosure.

Claims

1. A bonding structure comprising: Carrier; a first plurality of die stacks, each die stack comprising a plurality of dies, each die stack in the first plurality of die stacks being bonded to the carrier; a protective layer over at least a portion of the first plurality of die stacks; as well as a bridging layer, comprising a non-conductive bridge layer and a lateral conductive interconnect; Wherein the lateral conductive interconnect provides electrical communication between the first plurality of die stacks.

2. The bonding structure of claim 1 , further comprising a plurality of contact features at least partially embedded in the non-conductive bridge layer, Wherein the lateral conductive interconnect provides electrical communication between at least two contact features of the plurality of contact features. 3 . The bonded structure of claim 1 , further comprising at least one die stack directly bonded to the bridge layer without an adhesive. 4 . The bonded structure of claim 1 , further comprising a second plurality of die stacks bonded directly to the bridge layer and a bridge element bonded directly to the second plurality of die stacks. 5 . The bonded structure of claim 1 , further comprising at least one test pad at least partially embedded in the bridge layer, wherein the test pad is in electrical communication with the first plurality of stacks and the second plurality of stacks.

6. The joined structure of claim 1, further comprising a bridging element directly bonded to the bridging layer without an adhesive.

7. The joined structure of claim 6, further comprising a cavity between the first stack and the second stack. 8 . The bonded structure of claim 1 , wherein each stack of the first plurality of stacks comprises a first die bonded to a second die without an adhesive.

9. The bonded structure of claim 1 , wherein the first non-conductive bonding layer of at least one of the plurality of stacks is directly bonded to the second non-conductive bonding layer of the carrier without an intermediate adhesive, And wherein the first contact feature of at least one stack of the plurality of stacks is directly bonded to the second contact feature of the carrier without an intervening adhesive. 10 . The bonding structure according to claim 1 , wherein a material of the protection layer is the same as a material of the bridge layer.

11. A joining structure comprising: a first die stack comprising a first plurality of dies; a second die stack comprising a second plurality of dies; a protective layer disposed at least adjacent to lateral sides of the first die stack and the second die stack and between the first die stack and the second die stack; as well as A bridging layer is disposed over the first die stack, the second die stack and the protection layer, the bridging layer providing electrical communication between the first die stack and the second die stack. 12 . The bonded structure of claim 11 , wherein the first plurality of dies within the first die stack are direct hybrid bonded.

13. The bonded structure of claim 11, wherein the second plurality of dies within the second die stack are direct hybrid bonded. 14 . The bonded structure of claim 11 , wherein the first die stack and the second die stack are hybrid bonded directly to a carrier. 15 . The bonded structure of claim 11 , wherein the first die stack and the second die stack are hybrid bonded directly to a bridge element.

16. The joining structure according to claim 15, further comprising: a third die stack comprising a third plurality of dies, wherein the third die stack is hybrid bonded directly to the bridging layer, and a fourth die stack comprising a fourth plurality of dies, wherein the fourth die stack is hybrid bonded directly to the bridging layer. 17 . The bonded structure of claim 16 , further comprising a bridging element bonded to the third die stack and the fourth die stack. 18 . The bonding structure of claim 17 , further comprising at least one test pad embedded in the bridge layer, the test pad being configured to be in electrical communication with the first die stack, the second die stack, the third die stack, and the fourth die stack.

19. A method for forming a bonded structure, the method comprising: directly bonding a first plurality of stacks to a carrier, wherein each stack of the first plurality of stacks includes at least one die in contact with the carrier; providing a protective layer at least partially over at least a portion of the plurality of stacks; planarizing the protective material; as well as forming a non-conductive bridging layer including a non-conductive bridge layer and a lateral conductive interconnect, Wherein the lateral conductive interconnect provides electrical communication between the first plurality of die stacks.

20. The method of claim 19, further comprising forming a first plurality of contact features at least partially embedded in the non-conductive bridge layer, Wherein the lateral conductive interconnect provides electrical communication between at least two contact features of the first plurality of contact features.

21. The method of claim 19, wherein planarizing the protective material exposes the plurality of stacked contact features.

22. The method of claim 19, wherein each stack comprises at least a first die bonded to a second die.

23. The method of claim 19, further comprising bonding a second plurality of stacks to the non-conductive bridging layer.

24. The method of claim 23, wherein each stack in the second plurality of stacks is configured to be in electrical communication with each stack in the first plurality of stacks.

25. The method of claim 23, wherein a non-conductive bridging element is directly bonded to the second plurality of stacks.

26. The method of claim 19, wherein a bridging element is bonded directly to the non-conductive bridging layer.

27. The method of claim 19, wherein providing a protective layer further comprises forming a cavity between the first stack and the second stack.

28. The method of claim 19, wherein the non-conductive bridging layer further comprises a test pad configured to be in electrical communication with the first plurality of stacks.

29. A joining structure comprising: Carrier; a first die stack having a first top die and a first bottom die, the first bottom die of the first stack being bonded to the carrier; a bridging layer, comprising a non-conductive layer and a conductive interconnect, the bridging layer being disposed over the first top die of the first stack; as well as a second die stack having a second bottom die hybrid-bonded directly to an upper surface of the bridging layer, Wherein the conductive interconnect of the bridging layer provides electrical communication between the first die stack and the second die stack.

30. The bonded structure of claim 29, further comprising a third die stack bonded to the carrier, the bridging layer being disposed over a third top die of the third stack.

31. A joining structure comprising: a carrier having a non-conductive layer and a conductive feature at least partially embedded in the non-conductive layer; a first die stack having a first top die and a first bottom die, the first top die and the first bottom die of the first die stack each having a respective non-conductive layer and conductive features, the first bottom die of the first die stack being bonded to the carrier; a bridging layer, comprising a non-conductive layer and a conductive interconnect, the bridging layer being disposed over the first top die of the first stack; as well as a second die stack having a second bottom die hybrid-bonded directly to an upper surface of the bridging layer, Wherein the conductive interconnect of the bridging layer provides electrical communication between the first die stack and the second die stack.

32. The bonded structure of claim 31, further comprising a third die stack bonded to the carrier, the bridging layer being disposed over a third top die of the third stack.

33. The bonding structure of claim 31, wherein the conductive interconnects of the bridging layer comprise printed lines.

34. The bonded structure of claim 31 further comprising a wire bond connecting the first die stack and the second die stack.

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