Mute charge pump

Abstract

A mute charge pump includes a charge pump having a floating current source and a pre-filter. The floating current source includes a transistor. The pre-filter includes a capacitor and a resistor. In one aspect, the capacitor and resistor in the pre-filter act as a low pass filter on a gate-to-source voltage (VGS) and current to a charge pump input. At low clock frequencies, the pre-filter advantageously slowly responds the floating current source to the average demand of the charge pump. This slower response input of the charge pump reduces noise generated by the charge pump. At higher clock frequencies, the pre-filter is disengaged to allow the floating current source to provide a faster response input to the charge pump. A switch is provided to disengage the pre-filter to enable the charge pump to operate normally silently at higher clock frequencies using a Pi filter.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Provisional Patent Application No. 63 / 523,016 filed on June 23, 2023, and claims the benefit of Provisional Patent Application No. 63 / 384,001 filed on November 16, 2022, the disclosures of which are hereby incorporated by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a charge pump with reduced electrical noise emissions. Background Art

[0004] The charge pump will transfer charge on each clock edge to generate a DC voltage or current from the input voltage supply to the output voltage. The capacitor charged to the input supply is disconnected from the positive input supply when fully charged and connected across the negative output supply and then returned to the input voltage supply to form a charge pump.

[0005] However, a spectrum of switching current noise at the clock frequency and odd harmonics of the clock frequency is also generated, which is undesirable. This noise in the high frequency spectrum can be attenuated by filtering using a so-called Pi filter. Unfortunately, due to the configuration of its capacitors, Pi filters are mostly ineffective at lower frequencies, especially at reduced clock frequencies. Clock frequency reduction is common in devices when trying to save switching power under low load conditions. Therefore, it is desirable to provide a silent charge pump that provides silent load current over a wide spectrum of clock frequencies. Summary of the invention

[0006] According to one aspect of the present disclosure, a silent charge pump includes a charge pump having a floating current source and a prefilter. The floating current source includes a transistor, namely a metal oxide semiconductor transistor. The prefilter includes a capacitor and a resistor. In one aspect, the capacitor and resistor in the prefilter act as a low-pass filter on the gate-to-source voltage (VGS) and the current flowing to the charge pump input. The capacitor is coupled to the transistor from the gate to the source. The diode-connected resistor under direct current (DC) is also coupled from the gate to the drain. At low clock frequencies, the prefilter allows the VGS and current of the transistor in the floating current source to respond slowly to the average demand of the charge pump. This slower response input of the charge pump reduces the noise generated by the charge pump. At higher clock frequencies, the prefilter is disengaged (e.g., short-circuited) to allow the transistor in the floating current source to provide a faster response input to the charge pump. In one aspect, a switch across the drain-to-source voltage of the transistor is provided to disengage or short the pre-filter and thus enable the charge pump to operate normally quietly at higher clock frequencies at which the capacitor-resistor-capacitor circuit, i.e., the Pi filter, is effective. Disengaging the pre-filter at high clock frequencies at which the Pi filter is effective allows the charge pump to charge faster in its operating mode. Thus, the quiet charge pump performs more quietly with less noise at both low and high clock frequencies.

[0007] In one aspect, a charge pump is configured to generate an output voltage based on a variable frequency clock signal. A Pi filter is coupled to the charge pump and configured to filter an output of the charge pump that is higher than a first frequency of the variable clock signal. A current source is coupled to the charge pump and configured to provide current to the charge pump, wherein the current source includes a transistor having a gate, a source, and a drain, and wherein the current source is configured to provide current in response to a demand of the charge pump based on a VGS applied during each clock cycle of the clock signal. A pre-filter is coupled to the current source and configured to maintain VGS at a desired level when the variable frequency clock signal is lower than the first frequency. The pre-filter includes a capacitor coupled to the transistor from the gate to the source and a resistor coupled between the capacitor and the transistor from the gate to the drain.

[0008] On the other hand, a method of operating a charge pump is disclosed. An input voltage and a clock signal having a variable clock frequency are received. A gate-to-source voltage (VGS) is applied to a transistor and maintained via a capacitor coupled to the transistor from gate to source. The VGS applied to the transistor is maintained equal to the drain voltage of the transistor based on an average value of a drain-to-source voltage (VDS). An output is provided from the transistor based on the input voltage and a clock signal based on the applied VGS and current.

[0009] On the other hand, any of the aforementioned aspects, and / or various individual aspects and features as described herein, may be combined individually or together to obtain additional advantages. Unless otherwise indicated herein, any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements.

[0010] Those skilled in the art will understand the scope of the present disclosure and recognize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] Figure 1A An exemplary circuit for a silent charge pump according to an aspect of the present disclosure is shown.

[0013] Figure 1B An exemplary controller for a silent charge pump according to the present disclosure and how it is used with Figure 1A An exemplary circuit interface for a silent charge pump is shown in FIG.

[0014] Figure 2A and 2B The performance according to an embodiment of the present disclosure is shown as a solid line.

[0015] Figure 3 The performance of an embodiment according to the present disclosure is shown.

[0016] Figure 4 The performance of an embodiment according to the present disclosure is shown.

[0017] Figure 5 An exemplary current spike of a conventional charge pump that is addressed according to an aspect of the present disclosure is shown.

[0018] Figure 6 The effect of current spikes on an aspect of an exemplary silent charge pump and the performance of the silent charge pump according to the present disclosure is shown.

[0019] Figure 7 The present disclosure is used to operate Figure 1A and 1B An exemplary process flow for a charge pump.

[0020] Figure 8 Show that you can use Figure 1A and 1B An exemplary user component of a silent charge pump is shown in FIG. DETAILED DESCRIPTION

[0021] The embodiments set forth below represent information necessary to enable those skilled in the art to practice the embodiments and to illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will appreciate the applications of these concepts not specifically set forth herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0022] It will be appreciated that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish different elements. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items.

[0023] It should be understood that when an element such as a layer, region or substrate is referred to as "on another element" or "extending onto another element", it can be directly on another element or directly extend to another element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly on another element" or "directly extending onto another element", there is no intermediate element. Similarly, it should be understood that when an element such as a layer, region or substrate is referred to as "above another element" or "extending above another element", it can be directly above another element or directly extend above another element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly above another element" or "extending directly above another element", there is no intermediate element. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intermediate element. On the contrary, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0024] Relative terms such as "below" or "above" or "up" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0025] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a, an" and "the" are also intended to include the plural forms. It should also be understood that when used herein, the terms "comprises, comprising" and / or include, including specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or their groups.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined herein, the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0027] Embodiments are described herein with reference to schematic illustrations of embodiments of the present disclosure. In this way, the actual sizes of layers and elements may be different, and it is expected that they will be different from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. For example, a region illustrated or described as a square or rectangle may have circular or curved features, and a region shown as a straight line may have some irregularities. Therefore, the region illustrated in the drawings is schematic, and its shape is not intended to illustrate the precise shape of the region of the device, and is not intended to limit the scope of the present disclosure. In addition, for illustrative purposes, the size of a structure or region may be enlarged relative to other structures or regions, and therefore a structure or region is provided to illustrate the general structure of this theme, and may be drawn to scale or may not be drawn to scale. Common elements between the accompanying drawings may be shown in this article with common element numbers, and are not described subsequently.

[0028] According to one aspect of the present disclosure, a silent charge pump includes a charge pump having a floating current source and a prefilter. The floating current source includes a transistor, i.e., a metal oxide semiconductor transistor. The prefilter includes a capacitor and a resistor. In one aspect, the capacitor and resistor in the prefilter act as a low-pass filter on the gate-to-source voltage (VGS) and the current flowing to the charge pump input. The capacitor is coupled to the transistor from the gate to the source. The diode-connected resistor under DC is also coupled from the gate to the drain. At low clock frequencies, the prefilter enables the VGS and current of the transistor in the floating current source to respond slowly to the average demand of the charge pump. This slower response input of the charge pump reduces the noise generated by the charge pump. At higher clock frequencies, the prefilter is disengaged (e.g., short-circuited) to allow the transistor in the floating current source to provide a faster response input to the charge pump. In one aspect, a switch across the drain-to-source voltage of the transistor is provided to disengage or short-circuit the prefilter, and thus enable the charge pump to operate normally and quietly at higher clock frequencies, the higher clock frequency being the frequency at which the Pi filter is effective. Disengaging the pre-filter at high clock frequencies where the Pi filter is effective allows the charge pump to charge fastest in its operating mode. Thus, the silent charge pump performs more quietly with less noise over the spectrum of low and high clock frequencies.

[0029] As noted, charge pumps typically use a capacitor-resistor-capacitor or Pi filter to reduce the noise generated by the charge pump at the clock edges of its clock signal. However, Pi filters are ineffective at lower frequencies. Therefore, for devices with variable clock speeds that use lower clock frequencies under low load conditions, a charge pump with only a Pi filter is not sufficient.

[0030] in this regard, Figure 1A and 1B A circuit diagram of a silent charge pump 100 according to one aspect of the present disclosure is shown to achieve quieter operation with respect to spectral noise across low clock frequencies and high clock frequencies. As shown, in one aspect, the silent charge pump 100 includes a power supply voltage rail 102, a ground rail 104, an output 106, a power supply voltage filter 108, a capacitor ladder circuit 110 having, for example, a first stage 112 and a second stage 114, a switch 116, a floating current source 118, a level shifter 120, a pre-filter 122, and a controller 124. The silent charge pump 100 can be used in various applications, such as in a battery-powered device or a voltage multiplier. The silent charge pump 100 can be designed in various configurations, such as a voltage inverter or a voltage multiplier. In one aspect, the silent charge pump 100 can be a DC-DC voltage converter configured to generate a higher or lower DC voltage from an input voltage.

[0031] The silent charge pump 100 receives an input voltage from a power supply voltage rail 102 that supplies an input voltage Vdda. A ground rail 104 supplies a ground reference GND. An output terminal 106 provides an output voltage Vddo and an output current Iddo. The silent charge pump 100 is configured to provide a charge pump voltage Vddo and an output current Iddo. Figure 1B A controller 124 (described further) operates to charge and discharge a capacitor to control one or more elements within its circuitry.

[0032] refer to Figure 1A Unlike conventional charge pumps, the silent charge pump 100 utilizes a floating current source 118 and a pre-filter 122 to achieve silent operation with respect to undesired spectral emissions at low (e.g., below 1.5 MHz) and high (e.g., above 1.5 MHz) clock frequencies. The floating current source 118 includes a transistor M1. The transistor M1 can be a P-type metal oxide semiconductor transistor (PMOS) or an N-type metal oxide semiconductor (NMOS) transistor. It is worth noting that in conventional charge pumps, the transistor is typically a diode-connected gate to drain shorted to reduce the voltage (e.g., 0.7 volts). In one aspect, the transistor M1 is instead configured as a floating or constant current source. In addition, the pre-filter 122 is coupled to the transistor M1 in the floating current source 118 to enable the current demand of the silent charge pump 100 to be balanced, for example, from the power supply voltage rail 102.

[0033] Thus, in one aspect, the pre-filter 122 is a low pass filter configured to filter out undesirable high frequency components from the current flowing to the input of the silent charge pump 100. The filtering causes the gate-to-source voltage (i.e., VGS) and current of transistor M1 to advantageously respond slowly to the average demand of the silent charge pump 100 as indicated by the drain-to-source voltage (VDS). This slower response of the input by the floating current source 118 reduces the noise generated by the silent charge pump 100, for example, at low clock frequencies (e.g., less than 1.5 MHz). A description of various other supporting elements and their operation in the silent charge pump 100 will now be further described to explain the features and benefits of the floating current source 118 and the pre-filter 122 in the silent charge pump 100.

[0034] For illustrative purposes, Figure 1A Other components of the silent charge pump 100 are also shown. The components and exemplary operating functions will now be further described.

[0035] The supply voltage rail 102 supplies an input voltage Vdda from a power supply (not shown for simplicity) that provides power to the silent charge pump 100. The supply voltage rail 102 may provide a positive or negative input voltage Vdda relative to a common ground, i.e., a ground rail 104. Alternatively, the supply voltage rail 102 may provide a DC voltage referenced to another voltage level.

[0036] The ground rail 104 provides a reference GND and acts as a common return path for the current of the silent charge pump 100. Depending on the specific circuit design and application, the ground rail 104 can be implemented in various ways. For example, the ground rail 104 can be a conductive plane on a printed circuit board, a signal ground, or a chassis ground to provide a ground path and reduce noise in the silent charge pump 100. Alternatively, depending on the desired application of the silent charge pump 100, the silent charge pump 100 can utilize a negative voltage rail instead of a ground rail.

[0037] Output terminal 106 provides an output voltage Vddo and an output current Iddo generated by silent charge pump 100. Output voltage Vddo may be positive or negative depending on the specific design and application of silent charge pump 100. Output voltage Vddo may be used to provide, for example, Figure 8 The device may be used to power other devices such as user components shown in the figure, or may be used to generate a clock signal.

[0038] The supply voltage filter 108 is coupled across the supply voltage rail 102 and the ground rail 104 and, in one aspect, includes a resistor R1 connected in series with parallel capacitors C1 and C2. In this configuration, the supply voltage filter 108 acts as a filter that attenuates certain frequencies and noise that may be present in the supply voltage rail 102 and the input voltage Vdda.

[0039] The capacitor ladder circuit 110 is coupled to the power supply voltage filter 108 and includes a first stage 112 and a second stage 114. As shown, in one aspect, the capacitor ladder circuit 110 may include capacitors C3, C4, C5, and C6, which are connected in parallel across the power supply voltage rail 102 and the ground rail 104 in the first stage 112 and the second stage 114, respectively. For example, as shown, the ladder circuit 110 may include a first stage 112 of capacitors C3 and C4 and a second stage 114 of capacitors C5 and C6. The second stage 114 is controlled by a switch 116 including a resistor R2, an inverter I1, and a transistor M5 to control the charging and discharging sequence of capacitors C5 and C6. By grading the capacitors C3, C4, C5, and C6 in the first stage 112 and the second stage 114, the capacitor ladder circuit 110 can be gradually charged to a higher voltage, and a step-up voltage is selectively generated using the switch 116. As shown, the switch 116 includes a transistor M5 and an inverter I1 configured together as a switch.

[0040] In the floating current source 118, transistors M1, M2, M3, and M4 can be NMOS or PMOS transistors. In the pre-filter 122, the diode-connected resistor R3 and the diode D1 are coupled from the gate to the drain of the transistor M1, and the capacitor C7 is coupled from the gate to the source of the transistor M1. In one aspect, in the pre-filter 122, the diode-connected resistor R3 and the capacitor C7 are used as a low-pass filter to filter the voltage VGS to the transistor M1. That is, by implementing the diode-connected resistor R3 and the capacitor C7 as a low-pass filter with the transistor M1 as in the pre-filter 122, VGS and the transistor M1 respond slowly to the average demand of the quiet charge pump 100. This has the effect of reducing the ripple and noise of the charge pump 100 at the output 106, which can produce a quieter output voltage Vddo and output current Iddo.

[0041] In steady state, the output from transistor M1 integrates the sawtooth wave on capacitor C7 to supplement the output of transistor M1, for example, by (e.g., by converting reference Figure 1B The charge delivered at the clock edge of the clock signal (CS) is used by the controller 124 (described further). During high frequency operation, such as high performance operation or load transients, the silent charge pump 100 can be operated at higher frequencies and voltages to reduce output impedance and minimize voltage drops using transistor M4 as a switch across the drain-to-source voltage (VDS) of transistor M1 and inverters I2 and I3 in the level shifter 120 to achieve fast startup. Transistors M2 and M3 can be connected as a switch across resistor R3 to assist in initializing the VGS of transistor M1 before reducing the clock frequency and input voltage of the silent charge pump 100 for steady-state operation.

[0042] Because the VGS and drain-to-source current of transistor M1 vary slowly, proportional to the difference in VDS integrated over time, the current in transistor M1 follows the equation for an inductor, so that transistor M1 with a resistor-capacitor (RC) filter forms a synthetic inductor, where: L = Rgd*Cgs / GM1. The term Rgd is the gate-to-drain resistance of transistor M1. The term Cgs is the gate-to-source capacitance of the transistor, and the term GM1 is the transconductance of transistor M1. Therefore, the average VDS and VGS voltage drops across transistor M1 behave as if it were an active synthetic inductor.

[0043] In the level shifter 120, the inverters I2 and I3 are configured together to act as the level shifter 120 and operate by converting the voltage level from the second stage 114 (i.e., the voltage generated from the capacitors C5 and C6). As shown, the inverter I2 is coupled to the gates of M2 and M3 and produces an output signal to the inverter I3. The inverter I3 then inverts this output signal from I2 and provides an upward level shifted output, which is provided to the gate of the transistor M4. Therefore, by using the inverters I2 and I3 as the level shifter 120, the voltage from the second stage 114 of the capacitor ladder circuit 110 can be shifted from one voltage range to another voltage range as needed to fully drive the transistor M4.

[0044] Therefore, based on the circuit system of floating current source 118, silent charge pump 100 can use pre-filter 122 to pre-charge VGS to the turn-on voltage, and then transition to a low stable clock frequency, while operating silently at the start-up frequency and high frequency at the boost voltage and at the fast clock frequency with a reduced voltage. Therefore, silent charge pump 100 can be used in any system with a variable speed clock (e.g., Figure 8 ) in the user component shown in .

[0045] Figure 1B An exemplary controller 124 and how it can be used with the Figure 1A An exemplary circuit diagram of a silent charge pump 100 is shown in FIG. Figure 1A and 1B Common elements shown in FIG. 1 are shown with common element numbers. For the sake of brevity and clarity, any previous discussion of such common elements above also applies to FIG. Figure 1B The controller 124 and its components will now be described further.

[0046] The controller 124 controls the operation of the silent charge pump 100 and includes a control logic 126 and a Pi filter 128, for example, based on the requested voltage and the requested clock signal frequency of the silent charge pump 100. The control logic 126 includes various components to provide a clock source for a variable clock signal, or to provide an input to receive a variable clock signal and a charge pump. For example, the control logic 126 may include switches, capacitors, and diodes for the charge pump to transfer charge from one capacitor to another capacitor to produce a higher or lower voltage output. In one aspect, the control logic is configured to receive various input signals to control the operation of the silent charge pump 100. For example, the control logic 126 may receive input signals for enabling and speed selection. As an output, the control logic 126 may provide a voltage signal that is filtered or directly to Vneg, a timing control signal used by the silent charge pump 100 during its operation, a shorted VDS and or a shorted gate to drain voltage (VGD), or a signal to control the full filter operation, for example, by the pre-filter 122 without shorting.

[0047] The control logic 126 determines the timing and sequencing of the charge and discharge cycles between capacitors such as capacitors C1 and C2 in the silent charge pump 100. The control logic 126 is responsible for generating a clock signal that drives the silent charge pump 100 based on an input clock selection or trigger that may trigger a change in the variable clock frequency. In this regard, the control logic 126 includes various logic elements, such as oscillators and timers, which receive various signals, such as clock selection signals, command voltage level signals, and command voltage level change signals, and provide various outputs, such as Vneg. In one aspect, the control logic 126 is configured to ensure that capacitors C5 and C6 are charged and discharged in a controlled manner by providing a control signal (CS) based on the clock signal to the inverter I1 so that the output voltage Vddo remains stable and predictable during various operating modes, as will be further explained below. The control logic 126 may also include additional circuitry (for clarity, Figure 1B ), such as level shifters, additional oscillators, counters, additional timers, inverters, and logic elements, such as AND and OR gates, to ensure that the silent charge pump 100 operates correctly with the supply voltage rail 102 and the output voltage Vddo required by the silent charge pump 100.

[0048] As also shown, the controller 124 may include a Pi filter 128 having holding capacitors C8 and C9, and a plurality of diodes D2, D3, D4, and D5 having resistors R4, R5, R6, R7, R8, R9, and R10. Holding capacitors C8 and C9 maintain the charge of the control logic 126 between clock cycles and stabilize the voltage level within the control logic 126. Resistors R4, R5, R6, R7, R8, R9, and R10 are provided to filter the output current and set the desired voltage provided from the controller 124 at Vneg. Diodes D2, D3, D4, and D5 act as clamping diodes by limiting the amount of voltage that can be generated across any part of the controller 124. For example, if the voltage exceeds the threshold of any one of diodes D2, D3, D4, or D5. These diodes can enter their breakdown regions and limit the voltage, thereby protecting capacitors C8 and C9, as set during their manufacturing process.

[0049] Figure 2A and 2B The performance comparison of the embodiments before and according to the present disclosure is shown respectively. In particular, Figure 2B The performance of the silent charge pump 100 when operating at different sequencing clock frequencies is shown. As noted, the silent charge pump 100 can employ a clock signal having a variable clock frequency provided from the control logic 126 that constitutes the controller 124. For example, the clock signal can be relatively fast at a relatively high frequency at startup. Thus, the floating current source 118 can operate based on the increased voltage from capacitors C5 and C6, and the resistor R3 and capacitor C7 in the pre-filter are disengaged (e.g., shorted). The silent charge pump 100 can then be operated with a fast clock frequency at a reduced voltage from capacitors C5 and C6 using a pre-charge of VGS from capacitor C7 in the pre-filter 122. In steady state or desired low power operation, the silent charge pump 100 can transition to a lower turn-on voltage and then to a low stable clock frequency. These transitions are Figure 3 Shown in.

[0050] During operation of the silent charge pump, almost no disturbances appear at the regulated voltage input of the charge pump. Silencing the silent charge pump 100 can have one or more benefits. For example, the silent charge pump 100 can be silent to reduce or prevent interference with a regulator (not shown). The silent regulator connection to the silent charge pump 100 can also be shared by a low noise amplifier (LNA) (not shown) and one or more silent charge pumps without the need to add an external RC filter to the LNA power supply to further reduce the regulator output ripple, especially at low charge pump frequencies and their harmonics. Otherwise, the ripple can corrupt the LNA output through the regulator that supplies it.

[0051] Figure 3 and 4 The performance of the embodiment according to the present disclosure is shown. For example, Figure 3 The gate and source voltages during the timing phase of the charge pump operation are shown, along with the variable clock frequency being monitored below. Figure 4 Representation and Figure 3 Same operation, but noting the Vneg output from controller 124, and specifically noting below the time varying current drawn from the regulated input voltage, the logarithmic scale shows two orders of magnitude variation during mode sequencing, and the zoomed in linear scale shows a hundred times reduced regulator current ripple according to one aspect.

[0052] Figure 4 The performance of an embodiment according to the present disclosure is shown. In particular, the silent charge pump 100 can be implemented as an NMOS using transistor M1. The gate and source of transistor M1 and the pre-filter 122 are shown together with the charge pump clock signal from the controller 124. The performance of the silent charge pump 100 when driven by a divided or decoded control signal is shown, and the control signal is used to first control the power supply VDS that shorts the transistor M5 (as a PMOS) as a switch that is initially turned on to obtain a high voltage, and then only later releases the filter resistor parallel conductance to achieve the long time constant required for VGS filtering during low-frequency steady-state operation at lower voltages. During low-frequency operation, the gate and source of the current filtering NMOS M1 move together at a constant VGS, for example using the pre-filter 122.

[0053] With the prefilter 122 engaged, the gate signal of transistor M1 is bootstrapped above the supply as the clock frequency decreases because the oscillator on the same noisy supply draws a reduced average current at low frequencies. The excess current is integrated on the bypass capacitor of the charge pump in the control logic 126 to supply each clock edge. At each clock edge, some charge is transferred.

[0054] exist Figure 4 , the lower scale shows the clock frequency changing or transitioning from about 13 MHz at startup to about 10 MHz in the middle and then to about 0.6 MHz steady state. The floating current source 118 operates only at the 10 MHz intermediate state and the 0.6 MHz steady state. The 13 MHz clock noise has been fully filtered by the existing RC network, and each stage is 20 times more efficient than filtering the 0.6 MHz that just passed. As shown, a bottom zoomed-in linear scale is provided showing the remaining current ripple, which is about 100 times lower than the ripple in the original diode-connected circuit for the silent charge pump 100 by 0.3 μA. As shown, each time the charge pump dumps charge at its source, the noisy charge pump power supply, the diode-connected NMOS transistor M1 causes a high current spike in the regulated power supply.

[0055] Figure 5 shows the noise current performance and current spikes of a conventional charge pump, which is addressed by an aspect of the present disclosure, and Figure 6 Regulator performance prior to and in accordance with embodiments of the present disclosure is shown. For example, as shown, the spike peaks are 20 μA to 30 μA, depending on the process inflection point, and continue even when the charge pump stabilizes. The high frequency content of the spike at each edge causes a voltage spike at the output of the supply voltage filter 108, which is reduced or eliminated by techniques according to the present disclosure. Thus, even a ripple (e.g., 10 mV) on the shared power supply of the LNA may be partially passed to the output of the LNA and interfere with, for example, the fidelity of the received RF signal.

[0056] Figure 7 An exemplary process flow 700 for operating the silent charge pump 100 is shown. In a first step, an input voltage and a clock signal ( Figure 7 For example, the silent charge pump 100 may receive an input voltage from the power supply voltage rail 102. Additionally, the control logic 126 in the controller 124 may provide a variable frequency clock signal.

[0057] In the next step, VGS is applied to the transistor and VGS is maintained via a capacitor coupled to the transistor from gate to source ( Figure 7 10. In one aspect, capacitor C7 and diode-connected resistor R3 in pre-filter 122 act as a low pass filter on the VGS of transistor M1 in floating current source 118 and the current flowing to the charge pump input in control logic 126 of controller 124. Capacitor C7 is coupled to transistor M1 from gate to source and at DC. Diode-connected resistor R3 at DC is also coupled from gate to drain of transistor M1.

[0058] In the next step, the VGS applied to the transistor is adjusted to be equal to the drain voltage of the transistor based on the average value of VDS ( Figure 7118) to provide a more responsive input to the charge pump in the control logic 126. In one aspect, at low clock frequencies, the pre-filter 122 advantageously causes the VGS and current of transistor M1 in the floating current source 118 to respond slowly to the average demand of the charge pump. This slower response input to the charge pump in the control logic 126 reduces the noise generated by the charge pump 100. At higher clock frequencies, the pre-filter is disengaged (e.g., shorted) by the controller 124 to allow transistor M1 in the floating current source 118 to provide a more responsive input to the charge pump in the control logic 126. In one aspect, a switch across the drain-to-source voltage of transistor M1 is provided to disengage or short the pre-filter and, thus, enable the charge pump in the control logic 126 to operate normally quietly at higher clock frequencies at which the Pi filter 128 in the controller 124 is effective.

[0059] In the next step, an output 106 ( Figure 7 708 in FIG.

[0060] refer to Figure 8 , Figure 1A and 1B The silent charge pump 100 shown in and the concepts described above can be implemented in various types of user elements 800 such as mobile terminals, smart watches, tablet computers, computers, navigation devices, access points, and similar wireless communication devices that support wireless communications such as cellular, wireless local area network (WLAN), Bluetooth, and near field communication. The user unit 800 will generally include a control system 802, a baseband processor 804, a transmission circuit system 806, a receiving circuit system 808 including the silent charge pump 100, an antenna switching circuit system 810, a plurality of antennas 812A-812N, and a user interface circuit system 814. In a non-limiting example, as an example, the control system 802 can be a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). In this regard, the control system 802 can include at least a microprocessor, an embedded memory circuit, and a communication bus interface. The receiving circuit system 808 receives radio frequency signals from one or more base stations via antennas 812A-812N and through the antenna switching circuit system 810. The low noise amplifiers and filters of the receive circuitry 808 cooperate to amplify and remove broadband interference from the received signal for processing. Down-conversion and digitization circuitry (not shown) then down-converts the filtered received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter.

[0061] The baseband processor 804 processes the digitized received signal to extract the information or data bits transmitted in the received signal. Such processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 804 is typically implemented in one or more digital signal processors and ASICs.

[0062] To transmit, a baseband processor 804 receives digitized data from a control system 802 that may represent voice, data, or control information, and the baseband processor encodes the digitized data for transmission. The encoded data is output to a transmit circuit system 806, where a digital / analog converter converts the digital encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at one or more desired transmit frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission, and the modulated carrier signal is delivered to antennas 812A-812N via antenna switching circuit system 810. Multiple antennas 812A-812N and duplicate transmit circuit systems 806 and receive circuit systems 808 may provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0063] It is contemplated that any of the aforementioned aspects, and / or the various individual aspects and features described herein, may be combined to obtain additional advantages. Unless otherwise indicated herein, any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments.

[0064] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A circuit configured as a silent charge pump, the circuit comprising: an input configured to receive a variable frequency clock signal; a charge pump configured to provide an output voltage based on the variable frequency clock signal; a Pi filter coupled to the charge pump and configured to filter an output of the charge pump above a first frequency of the variable clock signal; a current source coupled to the charge pump and configured to provide current to the charge pump, wherein the current source comprises a transistor having a gate, a source, and a drain, and wherein the current source is configured to provide current in response to a demand of the charge pump based on a gate-to-source voltage (VGS) applied during each clock cycle of the clock signal; as well as a pre-filter coupled to the current source and configured to maintain the VGS at a desired level based on when the variable frequency clock signal is below the first frequency, wherein the pre-filter comprises: a capacitor coupled to the transistor from the gate to the source; as well as A resistor is coupled between the capacitor and the transistor from the gate to the drain.

2. The circuit of claim 1, wherein the transistor comprises a P-type metal oxide semiconductor transistor.

3. The circuit of claim 1, wherein the transistor comprises an N-type metal oxide semiconductor transistor. The circuit of claim 1 , wherein the pre-filter is configured as a low-pass filter.

5. The circuit of claim 4 wherein the pre-filter maintains the VGS equal to a drain voltage of the transistor based on an average value of a drain-to-source voltage.

6. The circuit of claim 1 further comprising a first switch across the drain to source of the transistor, the first switch being switched on based on a variable frequency of the clock signal to selectively disengage the pre-filter.

7. The circuit of claim 1, wherein the prefilter comprises a resistor, the resistor being a diode-connected resistor coupled to an input voltage.

8. The circuit of claim 7, wherein the pre-filter further comprises a second switch across the diode-connected resistor, the second switch configured to selectively short the diode-connected resistor based on a variable clock signal and the input voltage.

9. The circuit of claim 1, wherein the charge pump further comprises a controller configured to provide a requested voltage output.

10. The circuit of claim 9, wherein the controller is configured to provide the requested clock frequency.

11. A method for operating a charge pump based on a clock frequency, comprising: receiving an input voltage and a clock signal having a variable clock frequency; maintaining a gate-to-source voltage (VGS) applied to the transistor via a capacitor coupled to the transistor from gate to source; adjusting the VGS applied to the transistor to be equal to a drain voltage of the transistor based on an average value of a drain-to-source voltage (VDS); as well as An output is provided from the transistor to the charge pump based on the input voltage, the clock signal, and the VDS applied to the transistor.

12. The method of claim 11 , wherein receiving the input voltage comprises: Turning on the first switch; as well as The charge pump provides a first voltage when activated and transitions to a second voltage lower than the first voltage.

13. The method of claim 11, wherein regulating the VGS comprises providing current to the transistor via a diode-connected resistor connected to the input voltage.

14. The method according to claim 13, further comprising: Prior to transitioning to a lower turn-on voltage, a second switch across the diode-connected resistor is turned on, the second switch being configured to selectively short the diode-connected resistor based on a variable clock signal and the input voltage.

15. The method of claim 14, wherein receiving the input voltage comprises: providing a first voltage and a first clock frequency when the charge pump is started; transitioning to a second voltage after startup, wherein the second voltage is lower than the initial voltage and the clock frequency remains at the first clock frequency; as well as The clock frequency is changed to a second clock frequency that is lower than the first clock frequency.

16. A wireless communication device, comprising: a baseband processor configured to process a digitized version of a radio frequency (RF) signal to extract data bits conveyed in the received RF signal; as well as A receive circuit system is configured to receive the RF signal from at least one antenna, wherein the receive circuit system includes a quiet charge pump.

17. The wireless communication device of claim 16, wherein the silent charge pump comprises: an input configured to receive a variable frequency clock signal; a charge pump configured to provide an output voltage based on the variable frequency clock signal; a Pi filter coupled to the charge pump and configured to filter an output of the charge pump above a first frequency of the variable clock signal; a current source coupled to the charge pump and configured to provide current to the charge pump, wherein the current source comprises a transistor having a gate, a source, and a drain, and wherein the current source is configured to provide current in response to a demand of the charge pump based on a gate-to-source voltage (VGS) applied during each clock cycle of the clock signal; as well as a pre-filter coupled to the current source and configured to maintain the VGS at a desired level based on when the variable frequency clock signal is below the first frequency, wherein the pre-filter comprises: a capacitor coupled to the transistor from the gate to the source; as well as A resistor is coupled between the capacitor and the transistor from the gate to the drain.

18. The circuit of claim 17, wherein the transistor comprises a P-type metal oxide semiconductor transistor.

19. The circuit of claim 17, wherein the transistor comprises an N-type metal oxide semiconductor transistor.

20. The circuit of claim 17, wherein the pre-filter is configured as a low pass filter.

21. The circuit of claim 20, wherein the pre-filter maintains the VGS equal to a drain voltage of the transistor based on an average value of a drain-to-source voltage.

22. The circuit of claim 17, further comprising a first switch across the drain to source of the transistor, the first switch being switched on based on a variable frequency of the clock signal to selectively disengage the pre-filter.

23. The circuit of claim 17, wherein the prefilter comprises a resistor that is a diode-connected resistor coupled to an input voltage.

24. The circuit of claim 23, wherein the pre-filter further comprises a second switch across the diode-connected resistor, the second switch configured to selectively short the diode-connected resistor based on a variable clock signal and the input voltage.

25. The circuit of claim 17, wherein the charge pump further comprises a controller configured to provide the requested voltage output.

26. The circuit of claim 25, wherein the controller is configured to provide the requested clock frequency.

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