Providing low-inductance paths in wiring substrates used for capacitors, along with related electronic devices and manufacturing methods.

Abstract

This includes electronic devices with wiring substrates having lower inductance paths for capacitors and related manufacturing methods. In an exemplary aspect, to provide lower interconnect inductance for capacitors coupled to a power distribution network in the wiring substrate, an additional metal layer providing an additional second power plane is provided in a dielectric layer between adjacent metal layers in adjacent metallization layers. This additional second power plane is adjacent to a first power plane disposed in a first metal layer of one of these adjacent metallization layers. This placement of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first power plane and the second power plane coupled to the capacitor, which is part of the power distribution network. This reduced dielectric thickness between the first power plane and the second power plane coupled to the capacitor reduces the interconnect inductance for the capacitor.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Patent Application Serial No. 17 / 934,651, filed September 23, 2022, entitled “Providing a Lower Inductance Path in a Routing Substrate for a Capacitor, and Related Electronic Devices and Fabrication Methods,” the entire contents of which are incorporated herein by reference. background

[0003] I. Technical Field

[0004] The field of this disclosure relates to integrated circuit (IC) packages comprising one or more semiconductor dies supported by a packaging substrate, and more specifically to dies in which capacitors are coupled to the IC package to support signal processing and / or power integrity.

[0005] II. Background Technology

[0006] Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in IC packages (also known as “semiconductor packages” or “chip packages”). An IC package includes one or more semiconductor dies that are mounted on and electrically coupled to a package substrate to provide physical support and electrical interfaces for the dies. The IC package may be coupled to a printed circuit board (PCB) to connect the circuitry within the IC package to other electrical components coupled to the PCB. The IC package may also be coupled to power rails and ground rails within a power distribution network on the PCB to receive power for operation. For example, the PCB may include external interconnects configured to couple to a power source to receive power signals distributed in its power distribution network to be supplied to the IC package.

[0007] Capacitors are typically coupled to circuitry within an IC package. Capacitors can be coupled to circuitry within the IC package as part of a filtering circuitry for the die within the IC package. Capacitors can also be coupled to circuitry within the IC package to provide decoupling capacitance for the circuitry within the die of the IC package, shunting noise from one circuit (e.g., a power supply circuit) to another circuit (e.g., a powered circuit). For example, to provide decoupling capacitance for an IC package, a decoupling capacitor can be coupled to the package substrate of the IC package or the same PCB to which the IC package is coupled. The decoupling capacitor can be coupled to the outer surface of the package substrate or PCB such that it is electrically coupled to the power rails and ground rails of the power distribution network within the package substrate or PCB. For example, a decoupling capacitor can be coupled to the same side of the PCB to which the IC package is coupled (i.e., the package side). A decoupling capacitor can also be coupled to the opposite side of the PCB to which the IC package is coupled (i.e., the pad side). In the case of package-side capacitors or pad-side capacitors, it is desirable to minimize the signal routing path length between the die in the IC package and the capacitor. This is because the inductance in the connection path increases with the increased signal routing path length. Increased inductance can lead to performance degradation of the capacitor. If the capacitor cannot be mounted to a package substrate or PCB that is vertically aligned below the IC package (i.e., mounted to a package substrate or PCB laterally offset from the die), the signal routing path length between the capacitor and the die in the IC package can be further increased. Mounting the capacitor to a package substrate or PCB laterally offset from the die means that the signal routing path between the capacitor and the die will also include horizontal routing paths within the package substrate or PCB, thus contributing to the increased signal routing path length. Summary of the Invention

[0008] The aspects disclosed herein include providing low-inductance paths in wiring substrates used for capacitors. Related electronic devices and manufacturing methods are also disclosed. As an example, the wiring substrate may be a package substrate for an integrated circuit (IC) package. Alternatively, the wiring substrate may be a circuit board (e.g., a printed circuit board (PCB)) in which an IC chip or other IC package is coupled to provide electrical signal wiring between the PCB and the IC chip / IC package. The wiring substrate includes one or more metallization layers, each comprising a metal layer insulated by a dielectric layer. Capacitors are coupled to the wiring substrate and may be electrically coupled to planes (“power planes”) in the metallization layers of the wiring substrate to provide decoupling capacitance. The thickness of the dielectric layer between adjacent metallization layers affects the interconnect inductance of devices (e.g., capacitors) coupled to such adjacent metallization layers because magnetic flux loops are created between adjacent metallization layers when power signals are carried in the power planes in adjacent metallization layers. The greater the thickness of the dielectric layer between adjacent metallization layers, the greater the interconnect inductance between these adjacent metallization layers. For example, increased interconnect inductance can lead to performance degradation of capacitors coupled to such power planes. Therefore, in an exemplary aspect, to provide lower interconnect inductance in the power distribution network in the wiring substrate, an additional metal plane for providing a second power plane is provided in the dielectric layer between adjacent metal layers in adjacent metallization layers. The first power plane is provided in a metal layer within one of the adjacent metallization layers. Providing the second power plane in the dielectric layer between adjacent metal layers reduces the thickness of the dielectric material in the dielectric layer between the first and second power planes. This reduced dielectric thickness between the first and second power planes can reduce the interconnect inductance for capacitors coupled to the first and second power planes.

[0009] As an example, the additional metal plane serving as the additional second power plane can be a separate additional metal plane in the dielectric layer between adjacent metal layers in adjacent metallization layers. This reduces the thickness between the first power plane and the second power plane, thereby reducing the interconnect inductance between the first power plane and the second power plane. Alternatively, the additional metal plane serving as the additional second power plane can be disposed in one of the metal layers of adjacent metallization layers, and its thickness is increased to at least partially disposed in the dielectric layer between adjacent metal layers in adjacent metallization layers. In this example, this also reduces the thickness between the first power plane and the second power plane, thereby reducing the interconnect inductance between the first power plane and the second power plane.

[0010] When the signal routing path to the coupled capacitor requires a horizontal routing path in the wiring substrate, providing an additional metal plane in the metallization layer of the wiring substrate as an additional second power plane to reduce the thickness of the dielectric material between the first and second power planes can be particularly advantageous. This is because circuit board or package substrate manufacturing constraints may impose or require a minimum distance between metallization layers in the wiring substrate, which controls the minimum dielectric layer thickness between adjacent metallization layers. Providing an additional metal plane as an additional second power plane for the coupled capacitor to reduce the interconnect inductance to the capacitor allows for greater flexibility in placing the capacitor on the circuit board or package substrate. For example, the capacitor may be able to be placed on a circuit board or package substrate in an area where horizontal routing between the capacitor and an IC package or circuit would otherwise have increased interconnect inductance to the capacitor due to the longer signal routing path caused by horizontal routing. For example, placing the capacitor on a circuit board or package substrate that requires horizontal signal routing may be easier than placing the capacitor on a circuit board or package substrate that would allow vertical signal routing.

[0011] In one exemplary aspect, the wiring substrate is a circuit board (e.g., a printed circuit board (PCB)). In one example, the IC package includes one or more dies coupled to the circuit board, wherein the dies are indirectly electrically coupled to the circuit board. Alternatively, the dies may be directly coupled to the circuit board. A capacitor is also coupled to the circuit board and couples a first power plane in a first metal layer of a first metallization layer and an additional metal plane as an additional second power plane, with a reduced dielectric material thickness between them to provide decoupling capacitance to the IC package or die coupled to the circuit board. The capacitor may be a package-side capacitor coupled to the outer surface of the circuit board on the same side of the circuit board when the IC package or die is coupled. The capacitor may also be a pad-side capacitor (LSC) coupled to the outer surface of the circuit board on opposite sides of the circuit board when the IC package or die is coupled. The reduced interconnect inductance to the capacitor facilitated by the additional metal plane mitigates or offsets any increased inductance caused by providing a longer signal routing path to the capacitor. This provides additional flexibility in coupling the capacitor to the circuit board, utilizing available space and / or avoiding the need to increase the overall height of the IC package / die and the circuit board. Additional capacitors can also be coupled to circuit boards that are vertically aligned with IC packages or dies, requiring only a vertical signal routing path between the additional capacitor and the IC package or die.

[0012] In another exemplary aspect, the wiring substrate is a package substrate for an IC package. A capacitor is also coupled to the package substrate and to a first power plane in a first metal layer of a first metallization layer and an additional metal plane serving as an additional second power plane, with a reduced dielectric material thickness between them to provide decoupling capacitance to a die coupled to the package substrate. The capacitor may be a package-side capacitor coupled to an outer surface of the package substrate on the same side to which the die is coupled. The capacitor may also be an LSC coupled to an outer surface of the package substrate on the opposite side to which the die is coupled. The reduced interconnect inductance to the capacitor facilitated by the additional metal plane can mitigate or offset any increased inductance caused by providing a longer signal wiring path to the capacitor. This provides additional flexibility in coupling the capacitor to the package substrate, utilizing available space and / or avoiding the need to increase the overall height of the IC package. The additional capacitor may also be coupled to a package vertically aligned with the die, requiring only a vertical signal wiring path between the additional capacitor and the die.

[0013] In this regard, in one exemplary aspect, an electronic device is provided. The electronic device includes a wiring substrate comprising a plurality of metallization layers parallel to each other along a first direction. The plurality of metallization layers include a first metallization layer and a first dielectric layer adjacent to the first metallization layer, the first metallization layer including a first metal layer having a first metal plane. The plurality of metallization layers also include a second metallization layer adjacent to the first metallization layer. The second metallization layer includes a second metal layer and a second dielectric layer adjacent to the second metal layer. The wiring substrate also includes a second metal plane disposed in the first dielectric layer along the first direction between the first metal layer and the second metal layer. The electronic device also includes a capacitor coupled to the first metal plane and the second metal plane.

[0014] In another exemplary aspect, a method of manufacturing an electronic device is provided. The method includes forming a wiring substrate including a plurality of metallization layers parallel to each other along a first direction, including forming a first metallization layer and forming a second metallization layer. Forming the first metallization layer includes forming a first metal layer including a first metal plane and forming a first dielectric layer adjacent to the first metal layer. For the second metallization layer, the method includes forming a second metal layer and forming a second dielectric layer adjacent to the second metal layer. Forming the wiring substrate including the plurality of metallization layers further includes forming a second metal plane in the first dielectric layer of the first metallization layer. Forming the wiring substrate further includes coupling the second metallization layer to the first metallization layer such that the second metal plane is located between the first metal layer and the second metal layer along a second direction orthogonal to the first direction. The method further includes coupling a capacitor to the wiring substrate, including coupling the capacitor to the first metal plane and the second metal plane. Attached Figure Description

[0015] Figure 1 This is a side view of an electronic device, which includes an integrated circuit (IC) package coupled to a circuit board serving as a wiring substrate, and a capacitor coupled to the circuit board and electrically coupled to an adjacent metallization layer within the circuit board to provide decoupling capacitance.

[0016] Figure 2A and Figure 2B This is a side view of an exemplary electronic device, which includes an IC package coupled to a circuit board serving as a wiring substrate and a capacitor coupled to a first power plane disposed in a metal layer of a first metallization layer of the circuit board and coupled to an additional metal plane disposed in a dielectric layer of an adjacent second metallization layer as an additional power plane, in order to reduce the thickness of the dielectric material between the first power plane and the additional power plane coupled to the capacitor, thereby reducing the interconnect inductance for the capacitor.

[0017] Figures 3A to 3C This is a top view of an exemplary layout of the electronic device in Figure 2, illustrating an additional power plane provided by an additional metal plane in the dielectric layer of the metallization layer of the circuit board, and possible locations of capacitors coupled to the PCB and the power plane.

[0018] Figure 4 This is a side view of another exemplary electronic device, which includes an IC package coupled to a circuit board serving as a wiring substrate and a capacitor coupled to a first power plane disposed in a first metal layer of a first metallization layer of the circuit board, and coupled to an additional metal plane serving as an additional power plane disposed in a second metal layer of an adjacent second metallization layer and partially located in a dielectric layer between the adjacent first and second metal layers, in order to reduce the thickness of the dielectric material between the first power plane and the additional power plane coupled to the capacitor, thereby reducing the interconnect inductance for the capacitor;

[0019] Figure 5 This is a side view of another exemplary electronic device, which includes an IC package serving as a wiring substrate and a capacitor coupled to a first power plane in a metal layer of a first metallization layer of a circuit board and coupled to an additional metal plane serving as an additional power plane in a dielectric layer of an adjacent second metallization layer, in order to reduce the thickness of the dielectric material between the first power plane and the additional power plane coupled to the capacitor, thereby reducing the interconnect inductance for the capacitor.

[0020] Figure 6This is a flowchart illustrating an exemplary manufacturing process for manufacturing a wiring substrate for an electronic device, wherein the wiring substrate includes a metal layer serving as a first power plane in a first metallization layer of a circuit board, and an additional metal plane serving as a second additional power plane in a dielectric layer disposed in an adjacent second metallization layer, to reduce the thickness of the dielectric material between the first power plane and the additional power plane, thereby reducing interconnect inductance, including but not limited to... Figures 2A to 5 Wiring substrate in;

[0021] Figures 7A to 7C This is a flowchart illustrating another exemplary process for manufacturing a wiring substrate for an electronic device, wherein the wiring substrate includes a metal layer serving as a first power plane in a first metallization layer of a circuit board, and an additional metal plane serving as a second additional power plane in a dielectric layer disposed in an adjacent second metallization layer, to reduce the thickness of the dielectric material between the first power plane and the additional power plane, thereby reducing interconnect inductance, including but not limited to... Figures 2A to 5 Wiring substrate in;

[0022] Figures 8A to 8F It is based on Figures 7A to 7C An exemplary manufacturing stage during the manufacturing of a wiring substrate in an exemplary manufacturing process;

[0023] Figures 9A to 9C This is a flowchart illustrating another exemplary process for manufacturing a wiring substrate for an electronic device, wherein the wiring substrate includes a metal layer serving as a first power plane in a first metallization layer of a circuit board, and an additional metal plane serving as a second additional power plane in a dielectric layer disposed in an adjacent second metallization layer, to reduce the thickness of the dielectric material between the first power plane and the additional power plane, thereby reducing interconnect inductance, including but not limited to... Figures 2A to 5 Wiring substrate in;

[0024] Figures 10A to 10F It is based on Figures 9A to 9C An exemplary manufacturing stage during the manufacturing of a wiring substrate in an exemplary manufacturing process;

[0025] Figure 11 This is a block diagram of an exemplary wireless communication device including a radio frequency (RF) component. The RF component may include electronic devices and a capacitor. The electronic devices include a wiring substrate. The capacitor is coupled to a first power plane in a metal layer of a first metallization layer on a circuit board and to an additional metal surface in a dielectric layer of an adjacent second metallization layer, serving as a second additional power plane. This reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor, thereby reducing the interconnect inductance for the capacitor, including but not limited to... Figures 2A to 5 , Figures 8A to 8F and Figures 10A to 10FElectronic devices and wiring boards in, and according to, but not limited to Figures 6 to 8C and Figures 9A to 9C Any exemplary manufacturing process in the exemplary manufacturing process, and according to, but not limited to, the exemplary manufacturing process in the exemplary manufacturing process. Figures 6 to 8C Any exemplary manufacturing process in the exemplary manufacturing process; and and

[0026] Figure 12 This is a block diagram of an exemplary processor-based system including components, which may include electronic devices and capacitors. The electronic devices include a wiring substrate. The capacitor is coupled to a first power plane in a metal layer of a first metallization layer on a circuit board and to an additional metal surface in a dielectric layer of an adjacent second metallization layer, serving as a second additional power plane. This reduces the thickness of the dielectric material coupled to the capacitor between the first and second power planes, thereby reducing the interconnect inductance for the capacitor, including but not limited to... Figures 2A to 5 , Figures 8A to 8F and Figures 10A to 10F Electronic devices and wiring boards in, and according to, but not limited to Figures 6 to 8C and Figures 9A to 9C Any exemplary manufacturing process in the exemplary manufacturing process. Detailed Implementation

[0027] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0028] The aspects disclosed herein include providing low-inductance paths in wiring substrates used for capacitors. Related electronic devices and manufacturing methods are also disclosed. As an example, the wiring substrate may be a package substrate for an integrated circuit (IC) package. Alternatively, the wiring substrate may be a circuit board (e.g., a printed circuit board (PCB)) in which an IC chip or other IC package is coupled to provide electrical signal wiring between the PCB and the IC chip / IC package. The wiring substrate includes one or more metallization layers, each comprising a metal layer insulated by a dielectric layer. Capacitors are coupled to the wiring substrate and may be electrically coupled to planes (“power planes”) in the metallization layers of the wiring substrate to provide decoupling capacitance. The thickness of the dielectric layer between adjacent metallization layers affects the interconnect inductance of devices (e.g., capacitors) coupled to such adjacent metallization layers because magnetic flux loops are created between adjacent metallization layers when power signals are carried in the power planes in adjacent metallization layers. The greater the thickness of the dielectric layer between adjacent metallization layers, the greater the interconnect inductance between these adjacent metallization layers. For example, increased interconnect inductance can lead to performance degradation of capacitors coupled to such power planes. Therefore, in an exemplary aspect, to provide lower interconnect inductance in the power distribution network in the wiring substrate, an additional metal plane for providing a second power plane is provided in the dielectric layer between adjacent metal layers in adjacent metallization layers. The first power plane is provided in a metal layer within one of the adjacent metallization layers. Providing the second power plane in the dielectric layer between adjacent metal layers reduces the thickness of the dielectric material in the dielectric layer between the first and second power planes. This reduced dielectric thickness between the first and second power planes can reduce the interconnect inductance for capacitors coupled to the first and second power planes.

[0029] When the signal routing path to the coupled capacitor requires a horizontal routing path in the wiring substrate, providing an additional metal plane in the metallization layer of the wiring substrate as an additional second power plane to reduce the thickness of the dielectric material between the first and second power planes can be particularly advantageous. This is because circuit board or package substrate manufacturing constraints may impose or require a minimum distance between metallization layers in the wiring substrate, which controls the minimum dielectric layer thickness between adjacent metallization layers. Providing an additional metal plane as an additional second power plane for the coupled capacitor to reduce the interconnect inductance to the capacitor allows for greater flexibility in placing the capacitor on the circuit board or package substrate. For example, the capacitor may be able to be placed on a circuit board or package substrate in an area where horizontal routing between the capacitor and an IC package or circuit would otherwise have increased interconnect inductance to the capacitor due to the longer signal routing path caused by horizontal routing. For example, placing the capacitor on a circuit board or package substrate that requires horizontal signal routing may be easier than placing the capacitor on a circuit board or package substrate that would allow vertical signal routing.

[0030] Before discussing the example of an electronic device including a capacitor, which begins at Figure 2, let's first describe... Figure 1 In an electronic device 100, the capacitor is coupled to a first power plane in a first metallization layer of a wiring substrate and to an additional metal plane, which serves as an additional second power plane, disposed in a dielectric layer of an adjacent second metallization layer. This reduces the thickness of the dielectric material between the first and second power planes, thereby reducing the interconnect inductance for the capacitor. Alternatively, the electronic device 100 may exclude the additional power plane in the dielectric layer of an adjacent metallization layer to reduce the thickness of the dielectric material between the first and additional power planes, thereby reducing the interconnect inductance for the capacitor.

[0031] In this respect, Figure 1This is a side view of an electronic device 100. The electronic device 100 includes an integrated circuit (IC) package 102 coupled to a circuit board 104, which serves as a wiring substrate 106. In this example, the IC package 102 includes a first die 108 (1) coupled to a package substrate 109. For example, the first die 108 (1) may include a graphics processor chip 110. The IC package 102 also includes a second die 108 (2) stacked above and coupled to the first die 108 (1) along a first vertical direction (Z-axis direction). For example, the second die 108 (2) may include a central processing unit (CPU) chip 112. The first die 108 (1) and the second die 108 (2) are electrically coupled to the package substrate 109 via corresponding external interconnects 114 (1), 114 (2) (e.g., solder balls, ball grid array (BGA) interconnects). The package substrate 109 includes one or more metallization layers, which include metal lines interconnected to provide signal routing paths between the first die 108(1) and the second die 108(2) and external interconnects 115 (e.g., solder balls, BGA interconnects) of the package substrate 109. The IC package 102 is coupled to the circuit board 104 via the external interconnects 115.

[0032] Continue to refer to Figure 1 The circuit board 104 includes multiple metallization layers 116(1)-116(6), each of which includes a metal line that can provide a signal routing path within the circuit board 104. For example, an external interconnect 115 of the IC package 102 is coupled to the first metallization layer 116(1) of the circuit board 104 to electrically couple the IC package 102 and its first die 108(1) and second die 108(2) to the circuit board 104. The circuit board 104 in this example includes power planes configured to be coupled to power sources as part of a power distribution network, such that power can be tapped from these power planes to supply power to the IC package 102 and its first die 108(1) and second die 108(2) for operation. For example, as Figure 1 As shown, the second metallization layer 116(2) in circuit board 104 includes a second metal layer 118(2) which includes a first power plane 120(1) configured to be coupled to a ground connection for a power source. The third metallization layer 116(3) in circuit board 104 includes a third metal layer 118(3) which includes a second power plane 120(2) configured to be coupled to a power signal connection for a power source. Moreover, in this example, the fourth metallization layer 116(4) in circuit board 104 includes a fourth metal layer 118(4) which includes a third power plane 120(3) also configured to be coupled to a ground connection for a power source.

[0033] The first capacitor 122(1) and the second capacitor 122(2) are also coupled to Figure 1 The power planes 120(1)-120(3) of the circuit board 104 in the electronic device 100. For example, a first capacitor 122(1) may provide a decoupling capacitor or filter for the circuitry in the first die 108(1), and a second capacitor 122(2) may provide a decoupling capacitor or filter for the circuitry in the second die 108(2). The first capacitor 122(1) and the second capacitor 122(2) may provide capacitors as part of a filtering circuitry for the respective first die 108(1) and second die 108(2). In this example, the first capacitor 122(1) and the second capacitor 122(2) provide decoupling capacitors to shunt power from the first die 108(1) and the second die 108(2) and noise from other circuitry. The first capacitor 122(1) has a first terminal 124(1) coupled to the first power plane 120(1) and a second terminal 124(2) coupled to the second power plane 120(2). In this example, a first capacitor 122(1) and its first terminal 124(1) and second terminal 124(2) are electrically coupled to a circuit board 104 and a sixth metallization layer 116(6). Metal lines 126 in the sixth metal layer 118(6) of the sixth metallization layer 116(6) can be used for signal routing between the first capacitor 122(1) and the first power plane 120(1) and the second power plane 120(2). The second capacitor 122(2) has a first terminal 128(1) coupled to a third power plane 120(3) and a second terminal 128(2) coupled to the second power plane 120(2). In this example, the second capacitor 122(2) and its first terminal 128(1) and second terminal 128(2) are electrically coupled to a circuit board 104 and a sixth metallization layer 116(6). The metal line 126 in the sixth metal layer 118 (6) of the sixth metallization layer 116 (6) can be used for signal routing between the second capacitor 122 (2) and the second power plane 120 (2) and the third power plane 120 (3).

[0034] like Figure 1As shown, the first power plane 120(1) and the second power plane 120(2) are separated from each other along the first vertical direction (Z-axis direction) by the thickness of the third dielectric layer 130(3) of the third metallization layer 116(3) in the circuit board 104 at a first height H1 along the first vertical direction (Z-axis direction). The second power plane 120(2) and the third power plane 120(3) are separated from each other along the first vertical direction (Z-axis direction) by the thickness of the fourth dielectric layer 130(4) of the fourth metallization layer 116(4) in the circuit board 104 at a second height H2 along the first vertical direction (Z-axis direction). The thickness of the third dielectric layer 130(3) of the third metallization layer 116(3) in circuit board 104, as indicated by the first height H1 between the first power plane 120(1) and the second power plane 120(2) in the adjacent second metallization layer 116(2) and third metallization layer 116(3), affects the interconnect inductance of the first capacitor 122(1) coupled to the first power plane 120(1) and the second power plane 120(2). This is because when a power signal is carried in the first power plane 120(1) and the second power plane 120(2), a magnetic flux loop is generated between the first power plane 120(1) and the second power plane 120(2). Similarly, the thickness of the third dielectric layer 130(3) of the third metallization layer 116(3) in circuit board 104, as indicated by the second height H2 between the second power plane 120(2) and the third power plane 120(3) in adjacent third metallization layers 116(3) and fourth metallization layers 116(4), affects the interconnect inductance of the second capacitor 122(2) coupled to the second power plane 120(2) and the third power plane 120(3). This is also because when a power signal is carried in the second power plane 120(2) and the third power plane 120(3), a magnetic flux loop is generated between the second power plane 120(2) and the third power plane 120(3).

[0035] The greater the thickness of the dielectric layer between power planes, the greater the interconnect inductance between these power planes. The increased interconnect inductance can lead to a performance loss of the first capacitor 122(1) and the second capacitor 122(2) coupled to the respective first power plane 120(1) and second power plane 120(2), as well as the second power plane 120(2) and third power plane 120(3). This is not a problem for the first capacitor 122(1) because the first capacitor 122(1) is the signal wiring path to the IC package 102, not the second capacitor 122(2). The first capacitor 122(1) is coupled to the circuit board 104 below the IC package 102 along the first vertical direction (Z-axis direction), while the second capacitor 122(2) is coupled to the circuit board 104 which is laterally offset from the IC package 102 along the first vertical direction (Z-axis direction). Therefore, the signal routing path to the second capacitor 122(2) involves routing in the second power plane 120(2) and the third power plane 120(3), which extends horizontally in its respective third metal layer 118(3) and fourth metal layer 118(4) along a second horizontal direction orthogonal to the first vertical direction (Z-axis direction) (X-axis direction and / or Y-axis direction), thus increasing the signal routing path length between the IC package 102 and the second capacitor 122(2). This increased signal routing path length to the second capacitor 122(2) means that the second capacitor 122(2) can have a larger interconnect inductance than the first capacitor 122(1), because the increased signal routing distance can also lead to an increased interconnect inductance.

[0036] Due to the reduced signal routing path length between IC package 102 and the first capacitor 122(1), the interconnect inductance for the first capacitor 122(1) is within acceptable limits. However, due to the increased signal routing path length between IC package 102 and the second capacitor 122(2), the interconnect inductance for the second capacitor 122(2) is beyond acceptable limits. The second capacitor 122(2) can be coupled to different locations on the circuit board 104 to reduce the signal routing path length between IC package 102 and the second capacitor 122(2). However, this may be impossible or infeasible due to package area limitations and / or other limitations. For example, in Figure 1 In the electronic device 100, a first capacitor 122(1) occupies the space below the IC package 102. It is desirable to couple the capacitor to the die in the electronic device, which allows for lateral shift of the signal wiring path involving the capacitor and the die in the horizontal direction, but with reduced interconnect inductance.

[0037] In this respect, Figure 2A and Figure 2BThis is a side view of an exemplary electronic device 200, which includes an IC package 202 coupled to a circuit board 204 serving as a wiring substrate 206, wherein the interconnect inductance between the second capacitor 222(2) and the IC package 202 is reduced. In this regard, as described in more detail below and as... Figure 2A As shown, the second capacitor 222(2) is coupled to a first power plane 220(1) in the third metal layer 218(3) of the third metallization layer 216(3) of the circuit board 204 for a first power connection. The power plane is a metal line or plane disposed in the metallization layer. The first power plane 220(1) is configured to carry a first power signal of the power source. The second capacitor 222(2) is also coupled to an additional metal plane 232 (also referred to as "second power plane 220(2)") which serves as an additional second metal plane 220(2) and is disposed in the fourth dielectric layer 230(4) of the adjacent fourth metallization layer 216(4) to reduce the thickness of the dielectric material 234(4) between the first power plane 220(1) and the additional second power plane 220(2) coupled to the second capacitor 222(2). The second power plane 220(2) is disposed in the fourth dielectric layer 230(4) of the fourth metallization layer 216(4) adjacent to the third metallization layer 216(3) and between the third metallization layer 218(3) and the fourth metallization layer 218(4), along a first vertical direction (Z-axis direction) orthogonal to the second horizontal direction (X-axis direction and / or Y-axis direction) of the metallization layers 216(1)-216(6). This second horizontal direction is orthogonal to the first vertical direction. The second power plane 220(2) is configured to carry a second power signal (or return signal) of the power source. This has the effect of reducing the interconnect inductance to the second capacitor 222(2) because the first distance D1 between the first power plane 220(1) and the additional second power plane 220(2) is reduced compared to, for example, a third height H3 along the first vertical direction (Z-axis direction) between the first power plane 220(1) and the third power plane 220(3). Thus, when a power signal is carried in the first power plane 220(1) and the additional second power plane 220(2), the magnetic flux loop generated between the first power plane 220(1) and the additional second power plane 220(2) is smaller than the magnetic flux loop between the first power plane 220(1) and the third power plane 220(3).

[0038] In this example, providing an additional metal plane 232 in the fourth metallization layer 216(4) as an additional second power plane 220(2) reduces the thickness of the dielectric material 234(4) between the additional second power plane 220(2) and the first power plane 220(1), indicated by a first distance D1. This may be particularly advantageous for a second capacitor 222(2) having a horizontal wiring path in the circuit board 204. Providing the additional metal plane 232 in the fourth metallization layer 216(4) also causes the additional metal plane 232 to be located at a second distance D2 from the fourth metal layer 218(4) in the fourth metallization layer 216(4) that is less than the height H3 of the fourth dielectric layer 230(4). Figure 2B This is because the fabrication of circuit board 204 may impose or require a minimum distance (e.g., a sixth (60) micrometer (μm)) between adjacent metallization layers 216(1)-216(6), which controls the minimum dielectric layer thickness between adjacent metallization layers 216(1)-216(6). The additional second power plane 220(2) providing coupling to the second capacitor 222(2) to reduce the interconnect inductance to the second capacitor 222(2) allows for greater flexibility in placing the second capacitor 222(2) on circuit board 204. For example, as Figure 2A As shown, it may be easier to place and couple the second capacitor 222(2) on the first top surface 236(1) of the circuit board 204 than to couple the second capacitor 222(2) on the second bottom surface 236(2) of the circuit board 204, which then requires horizontal signal wiring in the circuit board 204 to the second capacitor 222(2).

[0039] refer to Figure 2BThe circuit board 204 includes a plurality of metallization layers 216(1)-216(6), each of which includes a metal layer 218(1)-218(6). These metal layers may include metal lines to provide signal routing paths within the circuit board 204. Each metallization layer 216(1)-216(6) also has a corresponding dielectric layer 230(1)-230(6) of dielectric material adjacent to its corresponding metal layer 218(1)-218(6) to insulate the metal layers 218(1)-218(6) from each other. The metallization layers 216(1)-216(6) are parallel to each other along a second horizontal direction (X-axis direction and / or Y-axis direction) orthogonal to a first vertical direction (Z-axis direction). For example, an external interconnect 217 of the IC package 202 is coupled to a first metallization layer 216(1) of the circuit board 204 to electrically couple the IC package 202 and its first die 208(1) and second die 208(2) to the circuit board 204. The circuit board 204 in this example includes power planes configured to be coupled to power sources as part of a power distribution network, such that power can be tapped from these power planes to supply power to the IC package 202 and its first die 208(1) and second die 208(2) for operation. For example, as... Figure 2B As shown, the second metallization layer 216(2) in circuit board 204 includes a second metal layer 218(2) which includes a fourth metal plane 220(4) (also referred to as "fourth power plane 220(4)") configured to be coupled to a ground connection for a power source. The third metallization layer 216(3) in circuit board 204 includes a third metal layer 218(3) which includes a first metal plane 220(1) (also referred to as "first power plane 220(1)") configured to be coupled to a power signal connection for a power source. The first power plane 220(1) is configured to carry a power signal of the power source. Moreover, in this example, the fourth metallization layer 216(4) in circuit board 204 includes a fourth metal layer 218(4) which includes a third metal plane 220(3) (also referred to as "third power plane 220(3)") also configured to be coupled to a ground connection for a power source.

[0040] Moreover, such as Figure 2BAs shown, the first capacitor 222(1) and the second capacitor 222(2) are also coupled to the first power plane 220(1) and the second power plane 220(2) of the circuit board 204. For example, the first capacitor 222(1) may provide a decoupling capacitor or filter for the circuitry in the first die 208(1), and the second capacitor 222(2) may provide a decoupling capacitor or filter for the circuitry in the second die 208(2). The first capacitor 222(1) and the second capacitor 222(2) may each provide a capacitor as part of a filtering circuitry for the respective first die 208(1) and second die 208(2). In this example, the first capacitor 222(1) and the second capacitor 222(2) provide decoupling capacitors to shunt power from the first die 208(1) and the second die 208(2) and noise from other circuitry. The first capacitor 222(1) has a first terminal 224(1) coupled to the fourth power plane 220(4) and a second terminal 224(2) coupled to the first power plane 220(1). In this example, the second capacitor 222(2) is coupled to the same first power plane 220(1) coupled to the first capacitor 222(1), but this is not necessary. For example, the second capacitor 222(2) may be coupled to a separate power plane coupled to the first power plane 220(1) in the same third metal layer 218(3) of the third metallization layer 216(3).

[0041] In this example, the first capacitor 222(1) and its first terminal 224(1) and second terminal 224(2) are electrically coupled to the circuit board 204 and the sixth metallization layer 216(6) via a first external interconnect 238(1) (e.g., solder ball, BGA interconnect). Metal lines 226(3)-226(6) in the third, fourth, fifth, and sixth metallization layers 216(3)-216(6) can be used for signal routing between the first capacitor 222(1) and the first power plane 220(1) and the fourth power plane 220(4). The second capacitor 222(2) has a first terminal 228(1) coupled to the third power plane 220(3) and a second terminal 228(2) coupled to the first power plane 220(1). In this example, the second capacitor 222(2) and its first terminal 228(1) and second terminal 228(2) are electrically coupled to the circuit board 204 and the first metallization layer 216(1) via a second external interconnect 238(2) (e.g., solder ball, BGA interconnect). The metal lines 226(1)-226(3) in the first, second and third metallization layers 216(1)-216(3) can be used for signal routing between the second capacitor 222(2) and the first power plane 220(1) and the second power plane 220(2).

[0042] Due to the reduced signal routing path length between the IC package 202 and the first capacitor 222(1), the first interconnect inductance for the first capacitor 222(1) is within acceptable limits. The first capacitor 222(1) is coupled to the circuit board 204 below the IC package 202 along a first vertical direction (Z-axis direction) such that the IC package 202 and the first capacitor 222(1) share a common vertical plane (e.g., plane P1) along the vertical direction (Y-axis direction and Z-axis direction). Therefore, in this example, no horizontal signal routing path is required between the first capacitor 222(1) and the IC package 202 in the circuit board 204. However, the second capacitor 222(2) is coupled to the circuit board 204 which is laterally offset from the IC package 202 along the first vertical direction (Z-axis direction) such that the second capacitor 222(2) and the IC package 202 do not share a common vertical plane along the first vertical direction (Y-axis direction and Z-axis direction). Therefore, the signal routing path to the second capacitor 222(2) involves horizontal routing in the first power plane 220(1) and the second power plane 220(2), which extends horizontally in its respective metal layers 218(3), 218(4) along a second horizontal direction (X-axis direction and / or Y-axis direction), thus increasing the signal routing path length between the IC package 202 and the second capacitor 222(2). This increased signal routing path length to the second capacitor 222(2) means that the second capacitor 222(2) can have a larger interconnect inductance than the first capacitor 222(1), because the increased signal routing distance can also lead to an increased interconnect inductance.

[0043] By providing an additional metal plane 232 to provide a reduced distance D1 to the second power plane 220(2) to the adjacent third metal layer 218(3) and its first power plane 220(1), the second interconnect inductance for the second capacitor 222(2) is also reduced. For example, the second interconnect inductance for the second capacitor 222(2) can be reduced to sixteen (16.0) pichenries (pH) or less (e.g., 15.1 pH or 2.5 pH). This reduced interconnect inductance can mitigate or offset the increased inductance due to the increased signal wiring path length between the IC package 202 and the second capacitor 222(2). The second interconnect inductance for the second capacitor 222(2) is smaller than the third interconnect inductance between the first power plane 220(1) and the third power plane 220(3). The third interconnect inductance between the first power plane 220(1) and the third power plane 220(3) can exceed 170 pH (e.g., 176 pH). This is because, compared to the reduced first distance D1 between the first power plane 220(1) and the second power plane 220(2) coupled to the second capacitor 222(2), there is an increased height H3 of the fourth dielectric layer 230(4) and its dielectric material 234(4) between the first power plane 220(1) and the third power plane 220(3). This may, for example, allow the second capacitor 222(2) to couple to a circuit board 204 that is laterally offset from the IC package 202 along a first vertical direction (Z-axis direction), and the second interconnect inductance of the second capacitor 222(2) remains within acceptable or desired limits.

[0044] For example, the third height H3 of the fourth dielectric layer 230(4) can be between fifty (50) μm and seventy (70) μm. The first distance D1 between the additional plane 232 in the fourth dielectric layer 230(4) providing the second power plane 220(2) and the third plane 218(3) in the adjacent third metallization layer 216(3) can be between 1.0 μm and 5.0 μm. The ratio of the third height H3 of the fourth dielectric layer 230(4) to the first distance D1 between the additional metal plane 232 in the fourth dielectric layer 230(4) and the third metal layer 218(3) in the third metallization layer 216(3) can be at least 10.0. For example, the ratio of the third interconnect inductance between the first power plane 220(1) and the third power plane 220(3) to the second interconnect inductance between the first power plane 220(1) and the second power plane 220(2) can be at least 10.0. It should be noted that the first capacitor 222(1) or any other capacitor is not required in the electronic device 200.

[0045] Figures 3A to 3C yes Figure 2A and Figure 2BA top view of an exemplary layout of an electronic device 200 illustrates an additional metal plane 232 provided by means of a dielectric layer disposed in the metallization layer of a circuit board 204, in order to provide an additional power plane for a second capacitor 222(2) to reduce interconnect inductance. Figure 3A As shown, it provides something similar to Figure 2A and Figure 2B Electronic device 200 (1). In Figure 3A In the electronic device 200(1), a plurality of second capacitors 222(2) are placed on the first top surface 204(1) of the circuit board 236. The second capacitors 222(2) are placed on the circuit board 204, which is laterally displaced from the IC package 202 along a second horizontal direction (X-axis direction and / or Y-axis direction). Figure 3A In this example, because a plurality of second capacitors 222(2) are provided around the IC package 202, an additional metal plane 232 is provided in a larger horizontal region along the second horizontal direction (X-axis direction and / or Y-axis direction) so that the second capacitors 222(2) can be coupled to the additional metal plane along the first vertical direction (Z-axis direction) via a signal wiring path.

[0046] like Figure 3B As shown, it provides something similar to Figure 2A and Figure 2B Another electronic device 200(2) is an electronic device 200 in the electronic device 200. In Figure 3B In the electronic device 200(2), a plurality of second capacitors 222(2) are placed on the first top surface 204(1) of the circuit board 236. The second capacitors 222(2) are placed on the circuit board 204, which is laterally displaced from the IC package 202 along a second horizontal direction (X-axis direction and / or Y-axis direction). Figure 3B In this example, because the second capacitor 222(2) disposed around the IC package 202 is more... Figure 3A Since there are fewer electronic devices 200(1) in the device, an additional metal plane 232 can be provided in the reduced horizontal region (along the X-axis and Y-axis directions) so that the second capacitor 222(2) can be coupled to the additional metal plane along the first vertical direction (Z-axis direction) through the signal wiring path.

[0047] like Figure 3C As shown, it provides something similar to Figure 2A and Figure 2B Another electronic device 200 (3) is an electronic device 200 in the electronic device 200. In Figure 3CIn the electronic device 200(3), two (2) second capacitors 222(2) are placed on the first top surface 204(1) of the circuit board 236. The second capacitors 222(2) are placed on the circuit board 204, which is laterally displaced from the IC package 202 along a second horizontal direction (X-axis direction and / or Y-axis direction). Figure 3C In this example, two (2) separate additional metal planes 232(1), 232(2) coupled to the respective second capacitors 222(2) are provided in circuit board 204. The additional metal planes 232(1), 232(2) may be arranged in a reduced horizontal region along a second horizontal direction (X-axis direction and Y-axis direction) such that the second capacitors 222(2) may be coupled to the additional metal planes along a first vertical direction (Z-axis direction) via signal wiring paths. In this example, the two (2) capacitors 222(2) may be coupled to their different corresponding power planes in different power domains. Therefore, using this example, the two (2) separate additional metal planes 232(1), 232(2) are arranged between different corresponding power planes in each power domain coupled to the respective capacitors 222(2).

[0048] Figure 4 This is a side view of another exemplary electronic device 400, which includes an IC package 402 coupled to a circuit board 404 serving as a wiring substrate 406, wherein the interconnect inductance between the capacitor 422 and the IC package 402 is reduced. Electronic device 400 is similar to... Figures 2A to 2B Electronic devices 200. Figure 2A and Figure 2B Electronic devices 200 and Figure 4 Common components among the electronic devices 400 are shown by common component numbers.

[0049] However, as discussed in more detail below, when set up Figure 4 In the electronic device 400, a thicker additional metal plane 432 is provided in the fourth dielectric layer 230(4) of the fourth metallization layer 216(4), and the thicker additional metal plane has a greater than 432 along the first vertical direction (Z-axis direction). Figures 2A to 2BThe additional metal plane 432 is increased by a fourth height H4. The additional metal plane 432 provides an additional second metal plane 420(2) (also referred to as "second power plane 420(2)") in the circuit board 404. In this example, the second power plane 420(2) is disposed in the third metal layer 218(3) of the third dielectric layer 216(3) and also partially disposed in the fourth dielectric layer 230(4) of the fourth metallization layer 216(4), which is the opposite of being disposed as a separate metal plane that is not at least partially disposed in the third metal layer 218(3). The second power plane 420(2) is configured to carry a second power signal (or return signal) of the power source. A capacitor 422 is coupled to a first metal plane 420(1) (also referred to as "first power plane 420(1)") disposed in the fourth metal layer 218(4) of the fourth metallization layer 216(4) of the circuit board 204 for a first power connection. The capacitor 422 is also coupled to an additional metal plane 432, which serves as a second power plane 420(2), disposed in the fourth dielectric layer 230(4) of the adjacent fourth metallization layer 216(4), to reduce the thickness of the dielectric material 234(4) between the first power plane 420(1) and the additional second power plane 420(2) coupled to the capacitor 422. The second power plane 420(2) is disposed in the fourth dielectric layer 230(4) of the fourth metallization layer 216(4) adjacent to the third metallization layer 216(3) and between the third metallization layer 218(3) and the fourth metallization layer 218(4) along a first vertical direction (Z-axis direction) orthogonal to the second horizontal direction (X-axis direction and / or Y-axis direction) of the metallization layers 216(1)-216(6), which is orthogonal to the first vertical direction (Z-axis direction).

[0050] The additional metal plane 432, serving as the second power plane 420(2), has the effect of reducing the interconnect inductance of the capacitor 422. This is because, for example, compared to the third height H3 along the first vertical direction (Z-axis direction) between the third metal layer 218(3) in the third metallization layer 216(3) and the first power plane 420(1) in the adjacent fourth metallization layer 216(4), the third distance D3 between the first power plane 420(1) and the additional second power plane 420(2) is reduced. Thus, when a power signal is carried in the first power plane 420(1) and the additional second power plane 420(2), the magnetic flux loop generated between the first power plane 420(1) and the additional second power plane 420(2) is smaller than the magnetic flux loop between the third metal layer 218(3) and the first power plane 420(1).

[0051] Providing an additional metal plane 432 in the fourth metallization layer 216(4) as an additional second power plane 420(2) reduces the thickness (third distance D3) of the dielectric material 234(4) between the additional second power plane 420(2) and the first power plane 420(1). This can be particularly advantageous for capacitors 422 having horizontal wiring paths in circuit board 404. This is because the fabrication of circuit board 404 may impose or require a minimum distance (e.g., sixty (60) micrometers (μm)) between adjacent metallization layers 216(1)-216(6), which controls the minimum dielectric layer thickness between adjacent metallization layers 216(1)-216(6). Providing an additional metal plane 432 coupled to capacitor 422 to reduce the interconnect inductance to capacitor 422 allows for greater flexibility in placing capacitor 422 on circuit board 404. For example, as Figure 4 As shown, it may be easier to place and couple capacitor 422 on the first top surface 436(1) of circuit board 404 than to couple capacitor 422 on the second bottom surface 436(1) of circuit board 404, which then requires horizontal signal wiring to capacitor 422 in circuit board 404.

[0052] Continue to refer to Figure 4 In this example, external interconnects 217 of IC package 402 are coupled to a first metallization layer 216(1) of circuit board 404 to electrically couple IC package 402 and its die 408 to circuit board 404. Circuit board 404 in this example includes power planes configured to couple to power sources as part of a power distribution network, such that power can be tapped from these power planes to supply power to IC package 402 and its die 408 for operation. For example, as... Figure 4 As shown, the fourth metallization layer 216(4) in circuit board 404 includes a fourth metal layer 218(4), which includes a first power plane 420(1) configured to be coupled to a ground signal connection for a power source. The first power plane 420(1) is configured to carry a power signal of the power source. Moreover, in this example, the fourth metallization layer 216(4) in circuit board 404 includes an additional second power plane 420(2), which is also configured to be coupled to a power signal connection for a power source.

[0053] Moreover, such as Figure 4As shown, capacitor 422 can provide capacitive decoupling or serve as a filter for circuitry within die 408. Capacitor 422 can serve as part of a filtering circuitry for die 408. In this example, capacitor 422 provides decoupling capacitance to shunt noise from power and other circuitry within die 408. Capacitor 422 has a first terminal 424(1) coupled to a first power plane 420(1) and a second terminal 424(2) coupled to a second power plane 420(2). The first terminal 424(1) and the second terminal 424(2) are electrically coupled to circuit board 404 and first metallization layer 216(1) via an external interconnect 438 (e.g., solder ball, BGA interconnect). Metal lines in the third, fourth, fifth and sixth metallization layers 216(3)-216(6) of the third, fourth, fifth and sixth metallization layers 216(3)-216(6) can be used for signal routing between the capacitor 422 and the first power plane 420(1) and the second power plane 420(2).

[0054] Capacitor 422 is coupled to circuit board 404, which is laterally offset from IC package 402 along a first vertical direction (Z-axis direction), such that capacitor 422 and IC package 402 do not share a common vertical plane along the first vertical direction (Y-axis and Z-axis directions). Therefore, the signal routing path to capacitor 422 involves horizontal routing in a first power plane 420(1) and a second power plane 420(2), which extends horizontally along a second horizontal direction (X-axis and / or Y-axis direction) orthogonal to the first vertical direction (Z-axis direction) in its respective third metallization layer 216(3) and fourth metallization layer 216(4), thus increasing the signal routing path length between IC package 402 and capacitor 422. This increased signal routing path length to capacitor 422 means that capacitor 422 can have a larger interconnect inductance than the first capacitor 122(1), as the increased signal routing distance also results in increased interconnect inductance. However, by providing an additional metal plane 432 to provide a reduced third distance D3 to the second power plane 420(2) to the adjacent fourth metal layer 218(4) and its first power plane 420(1), the interconnect inductance for capacitor 422 is reduced. For example, the interconnect inductance for capacitor 422 can be reduced to sixteen (16.0) pichenries (pH) or less (e.g., 15.1 pH or 2.5 pH). This reduced interconnect inductance can mitigate or offset the increased inductance due to the increased signal wiring path length between IC package 402 and capacitor 422. The interconnect inductance for capacitor 422 is less than the interconnect inductance between the third metal layer 218(3) and the first power plane 420(1). The interconnect inductance between the third metal layer 218(3) and the first power plane 420(1) can exceed 170 pH (e.g., 176 pH). This is because, compared to the reduced third distance D3 between the first power plane 420(1) and the second power plane 420(2) coupled to capacitor 422, there is an increased height H3 of the fourth dielectric layer 230(4) and its dielectric material 234(4) between the third metal layer 218(3) and the first power plane 420(1). This, for example, allows capacitor 422 to be coupled to a circuit board 204 that is laterally offset from IC package 402 along a first vertical direction (Z-axis direction), and the second interconnect inductance of the second capacitor 222(2) remains within acceptable or desired limits.

[0055] For example, the third height H3 of the fourth dielectric layer 230(4) can be between fifty (50) μm and seventy (70) μm. The third distance D3 between the additional plane 432 in the fourth dielectric layer 230(4) providing the second power plane 420(2) and the adjacent fourth metal layer 418(4) can be between 1.0 μm and 5.0 μm. The ratio of the third height H3 of the fourth dielectric layer 230(4) to the third distance D3 between the additional metal plane 432 in the fourth dielectric layer 230(4) and the fourth metal layer 218(4) in the fourth metallization layer 216(4) can be at least 10.0. For example, the ratio of the interconnect inductance between the third metal layer 218(3) and the first power plane 420(1) to the interconnect inductance between the first power plane 420(1) and the second power plane 420(2) can be at least ten (10.0). Note that the additional capacitor can be coupled to Figure 4 The circuit board 404 and its power planes 420(1)-420(3) are shown in the figure.

[0056] It should be noted that, although Figure 4 The wiring substrate 406 in the electronic device 400 has an additional second metal plane 420(2) with increased thickness. This additional second metal plane is also part of the third metal layer 218(3) in the third metallization layer 216(3), but this is not necessary. For example, the additional second metal plane 420(2) with increased thickness can be completely disposed outside the third metal layer 218(3) and completely disposed within the fourth dielectric layer 230(4) of the fourth metallization layer 216(4), similar to Figure 2A and Figure 2B The second metal plane 220(2) in the electronic device 200. However, when an additional second metal plane 420(2) with increased thickness is disposed within the fourth dielectric layer 230(4) of the fourth metallization layer 216(4), the second metal plane 420(2) can be configured to reduce the distance between the second metal plane 420(2) and the adjacent third metal layer 218(3) and fourth metal layer 218(4). Therefore, the power plane connection between the capacitor 422 and the metal planes of either the second metal plane 420(2) or the adjacent third metal layer 218(3) and fourth metal layer 218(4) can still provide reduced interconnect inductance.

[0057] Figure 5 This is a side view of another exemplary electronic device 500, which includes an IC package 502 having a package substrate 504 as a wiring substrate 506, wherein the interconnect inductance between a capacitor 522 and a die 508 is reduced. As described in more detail below and as... Figure 5As shown, capacitor 522 is coupled to a first metal plane 520(1) (also referred to as "first power plane 520(1)") disposed in the third metal layer 518(3) of the third metallization layer 516(3) of the package substrate 504 for a first power connection. The first power plane 520(1) is configured to carry a first power signal of a power source. Capacitor 522 is also coupled to an additional metal plane 532 (also referred to as "second power plane 520(2)") which serves as an additional second metal plane 520(2) disposed in the fourth dielectric layer 530(4) adjacent to the fourth metallization layer 516(4) to reduce the thickness of the dielectric material 534(4) between the first power plane 520(1) and the additional second power plane 520(2) coupled to capacitor 522. The second power plane 520(2) is disposed in the fourth dielectric layer 530(4) of the fourth metallization layer 516(4) adjacent to the third metallization layer 516(3) and between the third metallization layer 518(3) and the fourth metallization layer 518(4), along a first vertical direction (Z-axis direction) orthogonal to the second horizontal direction (X-axis direction) and / or the Y-axis direction, which is orthogonal to the first vertical direction (Z-axis direction). The second power plane 520(2) is configured to carry a second power signal (or return signal) of the power source. This has the effect of reducing the interconnect inductance to the capacitor 522 because the fourth distance D4 between the first power plane 520(1) and the additional second power plane 520(2) is reduced compared to, for example, a fifth height H5 along the first vertical direction (Z-axis direction) between the first power plane 520(1) and the second power plane 520(2). Thus, when a power signal is carried in the first power plane 520(1) and the additional second power plane 520(2), the magnetic flux loop generated between the first power plane 520(1) and the additional second power plane 520(2) is smaller than the magnetic flux loop between the first power plane 520(1) and the third metal plane 520(3) (also referred to as "third power plane 520(3)") in the adjacent fourth metal layer 518(4) of the fourth metallization layer 516(4).

[0058] In this example, providing an additional metal plane 532 in the fourth metallization layer 516(4) as an additional second power plane 520(2) reduces the thickness of the dielectric material 534(4) between the second power plane 520(2) and the first power plane 520(1), indicated by a fourth distance D4. This may be particularly advantageous for capacitors 522 having horizontal wiring paths in the package substrate 504. Providing the additional metal plane 532 in the fourth metallization layer 516(4) also results in the additional metal plane 532 being located at a fifth distance D5 from the fourth metal layer 518(4) in the fourth metallization layer 516(4) at a fifth height H5 less than that of the fourth dielectric layer 530(4). This is because the fabrication of the package substrate 504 may impose or require a minimum distance between adjacent metallization layers 516(1)-516(6) that controls the minimum dielectric layer thickness between adjacent metallization layers 516(1)-516(6). The additional second power plane 520(2) coupled to capacitor 522 to reduce the interconnect inductance to capacitor 522 allows for greater flexibility in placing capacitor 522 on package substrate 504. For example, as Figure 5 As shown, it may be easier to place and couple capacitor 522 on the first top surface 536(1) of package substrate 504 than to couple capacitor 522 on the second bottom surface 536(1) of package substrate 504, which then requires horizontal signal wiring in package substrate 504 to capacitor 522.

[0059] refer to Figure 5 The package substrate 504 includes a plurality of metallization layers 516(1)-516(6), each of which includes a metal layer 518(1)-518(6). These metal layers may include metal lines to provide signal wiring paths within the package substrate 504. Each metallization layer 516(1)-516(6) also has a corresponding dielectric layer 530(1)-530(6) of dielectric material adjacent to its corresponding metal layer 518(1)-518(6) to insulate the metal layers 518(1)-518(6) from each other. The metallization layers 516(1)-516(6) are parallel to each other along a first horizontal direction (X-axis direction and / or Y-axis direction). For example, an external interconnect 517 is coupled between the die 508 and the first metallization layer 516(1) of the package substrate 504 to electrically couple the die 508 to the package substrate 504. In this example, the package substrate 504 includes power planes configured to be coupled to power sources as part of a power distribution network, such that power can be tapped from these power planes to supply power to the package substrate 504 and die 508 (1) for operation. For example, as Figure 5As shown, the third metallization layer 516(3) in the package substrate 504 includes a third metal layer 518(3), which includes a first power plane 520(1) configured to be coupled to a ground connection for a power source. The fourth metallization layer 516(4) in the package substrate 504 includes a second power plane 520(2) provided by an additional metal plane 532 and configured to be coupled to a power signal connection for a power source. Moreover, in this example, the fourth metallization layer 516(4) in the circuit board 204 includes a fourth metal layer 518(4), which includes a third power plane 520(3) also configured to be coupled to a ground connection for a power source.

[0060] Moreover, such as Figure 5 As shown, die 508 is also coupled to a first power plane 520(1) and a second power plane 520(2) in package substrate 504. Capacitor 522 may provide decoupling capacitance or a filter for circuitry in die 508. Capacitor 522 may provide a capacitor as part of a filtering circuitry for die 508. In this example, capacitor 522 provides decoupling capacitance to shunt noise from power and other circuitry in die 508. Capacitor 522 has a first terminal 524(1) coupled to the first power plane 520(1) and a second terminal 524(2) coupled to an additional second power plane 520(2). In this example, for example, capacitor 522 may be a deep trench capacitor (DTC). Capacitor 522 and its first terminal 524(1) and second terminal 524(2) are electrically coupled to package substrate 504 and first metallization layer 516(1) via external interconnect 538 (e.g., solder ball, BGA interconnect). Metal lines in the first, second, third and fourth metal layers 518(1)-518(4) of the first, second, third and fourth metallization layers 516(1)-516(4) can be used for signal routing between the capacitor 522 and the first power plane 520(1) and the second power plane 520(2).

[0061] Continue to refer to Figure 5Capacitor 522 is coupled to package substrate 504, which is laterally offset from die 508 along a first vertical direction (Z-axis direction), such that capacitor 522 and die 508 do not share a common vertical plane along the first vertical direction (Y-axis and Z-axis directions). Therefore, the signal routing path to capacitor 522 involves horizontal routing in the first power plane 520(1) and the second power plane 520(2), which extends horizontally along a second horizontal direction (X-axis and / or Y-axis direction) in their respective third metal layer 518(3) and fourth metal layer 518(4), thus increasing the signal routing path length between die 508 and capacitor 522. This increased signal routing path length to capacitor 522 means that capacitor 522 can have a larger interconnect inductance, as the increased signal routing distance can also lead to increased interconnect inductance.

[0062] By providing an additional metal plane 532 to provide a reduced fourth distance D4 to the second power plane 520(2) to the adjacent third metal layer 518(3) and its first power plane 520(1), the interconnect inductance for capacitor 522 is also reduced. For example, the interconnect inductance for capacitor 522 can be reduced to sixteen (16.0) pichenries (pH) or less (e.g., 15.1 pH or 2.5 pH). This reduced interconnect inductance can mitigate or offset the increased inductance due to the increased signal wiring path length between die 508 and capacitor 522. The interconnect inductance for capacitor 522 is less than the interconnect inductance between the second power plane 520(2) and the third power plane 520(3). The interconnect inductance between the second power plane 520(2) and the third power plane 520(3) can exceed 170 pH (e.g., 176 pH). This is because, compared to the reduced fourth distance D4 between the first power plane 520(1) and the second power plane 520(2) coupled to the capacitor 522, there is an increased fifth height H5 of the fourth dielectric layer 530(4) and its dielectric material 534(4) between the second power plane 520(2) and the third power plane 520(3). This, for example, allows the capacitor 522 to be coupled to the package substrate 504, which is laterally offset from the die 508 along the first vertical direction (Z-axis direction), and the interconnect inductance of the capacitor 522 remains within acceptable or desired limits.

[0063] For example, the fifth height H5 of the fourth dielectric layer 530(4) can be between fifty (50) μm and seventy (70) μm. The fourth distance D4 between the additional plane 532 in the fourth dielectric layer 530(4) providing the second power plane 520(2) and the third plane 518(3) in the adjacent third metallization layer 516(3) can be between 1.0 μm and 5.0 μm. The ratio of the fifth height H5 of the fourth dielectric layer 530(4) to the fourth distance D4 between the additional metal plane 532 in the fourth dielectric layer 530(4) and the third metal layer 518(3) in the third metallization layer 516(3) can be at least 10.0. For example, the ratio of the interconnect inductance between the second power plane 520(2) and the third power plane 520(3) to the interconnect inductance between the first power plane 520(2) and the second power plane 520(4) can be at least ten (10.0).

[0064] Electronic devices and their wiring substrates can be manufactured using a manufacturing process, wherein the wiring substrate includes a metal layer serving as a first power plane in a first metallization layer of a circuit board, and an additional metal plane serving as an additional power plane in a dielectric layer disposed in an adjacent second metallization layer, to reduce the thickness of the dielectric material between the first power plane and the additional power plane, thereby reducing interconnect inductance, including but not limited to... Figures 2A to 5 The electronic devices 200, 200(1)-200(3), 400, 500 and the wiring substrates 206, 406, 506 are included. In this respect, Figure 6 This is a flowchart illustrating an exemplary manufacturing process 600 for manufacturing an electronic device including a wiring substrate, wherein the wiring substrate includes a metal layer serving as a first power plane in a first metallization layer of a circuit board, and an additional metal plane serving as an additional power plane in a dielectric layer disposed in an adjacent second metallization layer, to reduce the thickness of the dielectric material between the first power plane and the additional power plane, thereby reducing interconnect inductance, including but not limited to... Figures 2A to 5 The electronic devices 200, 200(1)-200(3), 400, 500 and the wiring substrates 206, 406, 506 are included. Figure 6 The manufacturing process in 600 Figure 2A and Figure 2B The electronic device 200 and wiring board 206 in the process are discussed, but it should be noted that the manufacturing process 700 is not limited to manufacturing. Figure 2A and Figure 2B The electronic device 200 and the wiring board 206 are included.

[0065] In this respect, such as Figure 6As shown, in this example, the first step in the manufacturing process 600 of manufacturing electronic device 200 may include forming a wiring substrate 206, which includes a plurality of metallization layers 216(1)-216(6) parallel to each other along a first direction (X-axis direction and / or Y-axis direction). Figure 6 (See box 602). The next step in the manufacturing process 600 that forms the wiring substrate 206 may include forming a first metallization layer as a fourth metallization layer 216 (4). Figure 6 (See box 604 in the text). Forming the fourth metallization layer 216 (4) may include forming a first metal layer as a fourth metal layer 220 (4) including a third metal plane 218 (3) and forming a first dielectric layer as a fourth dielectric layer 218 (4) adjacent to the fourth metal layer 230 (4). The next step in the fabrication process 600 that forms the wiring substrate 206 may include forming a second metallization layer as the third metallization layer 216 (3). Figure 6 (in box 606). Forming the third metallization layer 216 (3) may include forming a second metal layer as the third metal layer 218 (3) and forming a second dielectric layer as the third dielectric layer 230 (3) adjacent to the third metal layer 218 (3). A first metal plane 220 (1) may be formed in the third metallization layer 216 (3). The next step in the manufacturing process 600 of forming the wiring substrate 206 may include forming a second metal plane 220 (2) in the fourth dielectric layer 230 (4) of the fourth metallization layer 216 (4). Figure 6 (See box 608 in the text). The next step in the manufacturing process 600 to form the wiring substrate 206 may include coupling a third metallization layer 216 (3) to a fourth metallization layer 216 (4) such that a second metal plane 220 (2) is located between a fourth metal layer 218 (4) in the fourth metallization layer 216 (4) and a third metal layer 218 (3) in the third metallization layer 216 (3). Figure 6 (Box 610 in the middle). The next step in the manufacturing process 600 of manufacturing the electronic device 200 may include coupling the second capacitor 222 (2) to the wiring substrate 206 (in the middle). Figure 6 (See box 612). Coupling the second capacitor 222(2) may include the steps of coupling the second capacitor 222(2) to one of the first metal plane 220(3) and the first metal plane 220(1) and coupling the second capacitor 222(2) to the second metal plane 220(2). The next step in the manufacturing process 600 of manufacturing the electronic device 200 may include coupling the first die 208(1) and the second die 208(2) to the first metal plane 220(3) and the second metal plane 220(4). Figure 6 (Box 614 in the middle).

[0066] Other manufacturing processes can be used to manufacture electronic devices and their wiring substrates, wherein the wiring substrate includes a metal layer serving as a first power plane in a first metallization layer of a circuit board, and an additional metal plane serving as an additional second power plane in a dielectric layer disposed in an adjacent second metallization layer, to reduce the thickness of the dielectric material between the first power plane and the additional power plane, thereby reducing interconnect inductance, including but not limited to... Figures 2A to 5 The electronic devices 200, 200(1)-200(3), 400, 500 and the wiring substrates 206, 406, 506 are included.

[0067] In this respect, Figures 7A to 7C This is a flowchart illustrating another exemplary manufacturing process 700 for a wiring substrate used in an electronic device, wherein the wiring substrate includes a metal layer serving as a first power plane in a first metallization layer of a circuit board, and an additional metal plane serving as an additional second power plane in a dielectric layer disposed in an adjacent second metallization layer, to reduce the thickness of the dielectric material between the first power plane and the additional second power plane, thereby reducing interconnect inductance, including but not limited to... Figures 2A to 5 The electronic devices 200, 200(1)-200(3), 400, 500 and the wiring substrates 206, 406, 506 are included. Figures 8A to 8F It is based on Figures 7A to 7C The exemplary manufacturing stages 800A-800F during the manufacturing process 700 of the wiring substrate are shown. Figures 7A to 7C In the manufacturing process 700, an additional metal plane with a reduced distance from the adjacent metallization layer is formed in the upper portion of the dielectric layer so that the distance between the additional metal plane and the adjacent metal layer above it is closer in the vertical direction (Z-axis direction).

[0068] In this respect, such as Figure 8A As shown in manufacturing stage 800A, the first step in manufacturing process 700 is to form a core substrate 802 and a first metal layer 804(1) and a second metal layer 804(2) (e.g., copper layer) located on the corresponding outer surfaces 806(1), 806(2) of the core substrate 802. Figure 7A (See box 702 in the image). In this example, the wiring substrate to be formed includes a core substrate 802 as an inner layer. Furthermore, as... Figure 8AAs shown in manufacturing stage 800A, openings 808(1) and 808(2) are formed in corresponding metal layers 804(1) and 804(2) to form individual metal layers 810(1)-810(6). The first metal layer 804(1) and the second metal layer 804(2) will be used as metal layers for additional metallization layers to be formed. Metal planes 810(1) and 810(4) are coupled to each other through a first metal via 812(1) formed in the core substrate 802. Metal planes 810(3) and 810(6) are coupled to each other through a second metal via 812(2) formed in the core substrate 802.

[0069] Then, as Figure 8B As shown in manufacturing stage 800B, the next step in manufacturing process 700 is to form a first dielectric layer 814(1) and a second dielectric layer 814(2) of dielectric material on the corresponding first metal layer 804(1) and second metal layer 804(2) to insulate the corresponding metal planes 810(1)-810(6) formed on the outer surfaces 806(1) and 806(2) of the core substrate 802. Figure 7A (See box 704 in the image). For example, the first dielectric layer 814(1) and the second dielectric layer 814(2) can be laminated onto the metal layers 804(1) and 804(2). Then, as shown in the image... Figure 8B As shown in manufacturing stage 800B, a third metal layer 804(3) and a fourth metal layer 804(4) (e.g., copper layer) are then formed on the outer surfaces 816(1), 816(2) of the first dielectric layer 814(1) and the second dielectric layer 814(2). Figure 7A (Box 704 in the middle).

[0070] Then, as Figure 8C As shown in manufacturing stage 800C, the next step in manufacturing process 700 is to pattern and remove a portion of the fourth metal layer 804 (4) to form an additional metal plate 810 (7) as the ground plane in this example. Figure 7A (See box 706 in the example). In this example, metal plane 810(7) is an additional metal plane that will be disposed in the subsequently formed dielectric layer to provide a power plane having a reduced distance to the adjacent metal plane to be formed on the dielectric layer, thereby reducing the interconnect inductance to the additional metal plane 810(7). In this respect, as Figure 8D As shown in manufacturing stage 800D, the next step is to form a third dielectric layer 814(3) on the additional metal plane 814(7) and the second dielectric layer 810(2), and to form a fifth dielectric layer 804(5) on the third dielectric layer 814(3). Figure 7B (Box 708 in the middle). Figure 8DAs shown, the distance D6 between the fifth metal layer 804(5) and the metal plane 810(5) is less than the height H6 of the second dielectric layer 814(2) and the third dielectric layer 814(3) between the second metal layer 804(2) and the fifth metal layer 804(5). Therefore, if a component such as a capacitor is coupled to the additional metal plane 810(7) and the metal plane formed in the fifth metal layer 804(5) as a power plane, the interconnect inductance resulting from such connection will be less than if the component is coupled to the metal plane formed in the fifth metal layer 804(5) and the metal planes 804(4)-810(6) in the second metal layer 810(2) as power planes.

[0071] Then, as Figure 8E As shown in manufacturing stage 800E, the next step in manufacturing process 700 is to pattern the third metal layer 804(3) and the fifth metal layer 804(5) to form metal vias 812(3)-812(4) and metal vias 812(5)-812(6) coupled to the corresponding metal planes 810(1), 810(3) and metal planes 810(4), 810(6). Figure 7B (Box 710 in the middle). Also, for example... Figure 8E As shown in manufacturing stage 800E, the corresponding third metal layer 804(3) and fourth metal layer 804(4) are patterned, and metal lines or metal layers 810(8)-810(13) are formed in the third metal layer 804(3) and fourth metal layer 804(4). Metal planes 810(8), 810(10) are formed to contact metal vias 812(3), 812(4). Metal planes 810(11), 810(13) are formed to contact metal vias 812(5), 812(6). Then, as Figure 8F As shown in manufacturing stage 800F, the next step in manufacturing process 700 is to form additional dielectric layers 814(4), 814(5) on the corresponding third metal layer 810(3) and fourth metal layer 804(4) to make metal layers 804(8)-810(13) insulating. Figure 7C (Box 712 in the text). Also, for example... Figure 8F As shown in manufacturing stage 800F, additional dielectric layers 814(4), 814(5) are patterned, and openings are formed therein to form metal vias 812(7), 812(8) coupled to the corresponding metal planes 810(9), 810(11). Figure 7C (Box 712 in the middle). Then, additional metal layers 804(6) and 804(7) are formed on the additional dielectric layers 804(4) and 814(5) and patterned to form additional metal planes 810(14)-810(19) in the corresponding metal layers 814(6) and 804(7). Figure 7C(in box 712). Metal planes 810(15), 810(18) are coupled to corresponding metal vias 812(7), 812(8) to couple metal planes 810(15), 810(18) to corresponding metal planes 810(7), 810(12).

[0072] Figures 9A to 9C This is a flowchart illustrating another exemplary manufacturing process 900 for a wiring substrate used in an electronic device, wherein the wiring substrate includes a metal layer serving as a first power plane in a first metallization layer of a circuit board, and an additional metal plane serving as an additional second power plane in a dielectric layer disposed in an adjacent second metallization layer, to reduce the thickness of the dielectric material between the first power plane and the second power plane, thereby reducing interconnect inductance, including but not limited to... Figures 2A to 5 The electronic devices 200, 200(1)-200(3), 400, 500 and the wiring substrates 206, 406, 506 are included. Figures 10A to 10F It is based on Figures 9A to 9C Exemplary manufacturing stages 1000A-1000F during the manufacturing process 900 of the wiring substrate. Figures 9A to 9C In the manufacturing process 900, an additional metal plane is formed in the lower portion of the dielectric layer, reducing the distance to the adjacent metallization layer, so that the distance to the adjacent metal layer below the additional metal plane is closer in the vertical direction (Z-axis direction).

[0073] In this respect, such as Figure 10A As shown in manufacturing stage 1000A, the first step in manufacturing process 900 is to form a core substrate 1002 and a first metal layer 1004(1) and a second metal layer 1004(2) (e.g., copper layer) on the corresponding outer surfaces 1006(1), 1006(2) of the core substrate 1002. Figure 9A (See box 902 in the image). In this example, the wiring substrate to be formed includes a core substrate 1002 as an inner layer. Furthermore, as... Figure 10A As shown in manufacturing stage 1000A, openings 1008(1) and 1008(2) are formed in corresponding first metal layer 1004(1) and second metal layer 1004(2) to form separate metal layers 1010(1)-1010(6). The first metal layer 1004(1) and the second metal layer 1004(2) will be used as metal layers for additional metallization layers to be formed. Metal planes 1010(1) and 1010(4) are coupled to each other through a first metal via 1012(1) formed in the core substrate 1002. Metal planes 1010(3) and 1010(6) are coupled to each other through a second metal via 1012(2) formed in the core substrate 1002.

[0074] Then, as Figure 10BAs shown in manufacturing stage 1000B, the next step in manufacturing process 900 is to form a thin resin layer as a first dielectric layer 1014(1) on the second metal layer 1004(2) and to form a third metal layer 1014(3) on the first dielectric layer 1004(1). Figure 9A (See box 904 in the image). The first dielectric layer 1014(1) provides an additional metal plane formed in the third metal layer 1004(3), the additional metal plane having a reduced distance to the second metal layer 1004(2), such that components coupled to the additional metal plane formed in the third metal layer 1004(3) have reduced interconnect inductance. In this respect, as... Figure 10C As shown in manufacturing stage 1000C, the next step in manufacturing process 900 is to pattern and remove a portion of the third metal layer 1004 (3) to form an additional metal plate 1010 (7) as the ground plane in this example. Figure 9A (See box 906 in the example). In this example, metal plane 1010 (7) is an additional metal plane that will be disposed in the subsequently formed dielectric layer to provide a power plane with a reduced distance to the adjacent metal plane to be formed on the dielectric layer, thereby reducing the interconnect inductance to the additional metal plane 1010 (7).

[0075] Then, as Figure 10D As shown in manufacturing stage 1000D, the next step in manufacturing process 900 is to form a second dielectric layer 1014(2) and a third dielectric layer 1014(3) on the corresponding first metal layer 1014(1) and first dielectric layer 1014(1), and subsequently form an additional fourth metal layer 1004(4) and a fifth metal layer 1004(5) on the corresponding second dielectric layer 1004(2) and third dielectric layer 1014(3). Figure 9B (See box 908 in the image). The second dielectric layer 1014(2) and the third dielectric layer 1014(3) insulate the first metal layer 1004(1) and the second metal layer 1004(2) from the fourth metal layer 1004(4) and the fifth metal layer 1004(5). Figure 10D As shown, the distance D7 between the second metal layer 1004(2) and the additional metal plane 1010(7) is less than the height H7 of the third dielectric layer 1014(3) between the second metal layer 1004(2) and the fifth metal layer 1004(5). Therefore, if a component such as a capacitor is coupled to the additional metal plane 1010(7) and the metal plane formed in the second metal layer 1004(4) as a power plane, the interconnect inductance resulting from such a connection will be less than if the component is coupled to the metal plane formed in the second metal layer 1004(2) and the metal plane formed in the fifth metal layer 1004(5) as a power plane.

[0076] Then, as Figure 10E As shown in manufacturing stage 1000E, the next step in manufacturing process 900 is to pattern the fourth metal layer 1004(4) and the fifth metal layer 1004(5) to form metal vias 1012(3)-1012(4) coupled to the corresponding metal planes 1010(1), 1010(3) and metal vias 1012(5)-1012(6) coupled to the metal planes 1010(4), 1010(6). Figure 9B (Box 910 in the middle). Also, for example... Figure 10E As shown in manufacturing stage 1000E, the corresponding fourth metal layer 1004(4) and fifth metal layer 1004(5) are patterned, and metal lines or metal layers 1010(8)-1010(13) are formed. Metal planes 1010(8), 1010(10) are formed to contact metal vias 1012(3), 1012(4). Metal planes 1010(11), 1010(13) are formed to contact metal vias 1012(5), 1012(6). Then, as Figure 10F As shown in manufacturing stage 1000F, the next step in manufacturing process 900 is to form additional dielectric layers 1014(4), 1014(5) on the corresponding fourth metal layer 1004(4) and fifth metal layer 1004(5) to make metal layers 1010(8)-1010(13) insulating. Figure 9C (Box 912 in the example). Also, as in this example... Figure 10F As shown in manufacturing stage 1000F, an additional dielectric layer 1014(4) is patterned, and openings are formed therein to form metal vias 1012(7), 1012(8) coupled to the corresponding metal planes 1010(8), 1010(9). Figure 9C (in box 912). Then, additional metal layers 1004(6) and 1004(7) are formed on the corresponding additional dielectric layers 1004(4) and 1014(5), and patterned to form additional metal planes 810(14)-812(19) in the corresponding metal layers 1014(6) and 1004(7). Figure 9C (in box 912). Metal planes 1010(14), 1010(15) are coupled to the corresponding metal vias 1012(7), 1012(8) to couple metal planes 1010(14), 1010(15) to the corresponding metal planes 1010(8), 1010(9).

[0077] It should be noted that the term "metal plane" refers to a metal structure that can be arranged in a plane along two or more directional axes. The term "power plane" is a metal plane configured to couple to a power source to conduct power signals. The terms "top" and "bottom" are relative terms and are not necessarily limited to components described as "top" or "bottom" being above or below another component relative to ground / ground. It should also be noted that components described herein as "located in" (such as being located in a layer, package substrate, or circuit board) are not limited to such components being entirely located in such a layer, package substrate, or circuit board. It should also be noted that the term "external" as used with reference to a particular component or structure (including, but not limited to, package substrates, circuit boards, dies, and capacitors) refers to a component that is wholly or partially exposed from the outer surface of such a component or structure.

[0078] Electronic devices including wiring substrates include a metal layer that serves as a first power plane in a first metallization layer of a circuit board and an additional metal plane that serves as an additional second power plane in a dielectric layer disposed in an adjacent second metallization layer, to reduce the thickness of the dielectric material between the first power plane and the second power plane, thereby reducing interconnect inductance, including but not limited to... Figures 2A to 5 , Figures 8A to 8F and Figures 10A to 10F The electronic devices 200, 200(1)-200(3), 400, 500 and wiring substrates 206, 406, 506, and according to, but not limited to Figures 6 to 8C and Figures 9A to 9C Any exemplary manufacturing process described herein, and which, according to any aspect disclosed herein, may be set in or integrated into any processor-based device. Examples not intended to be limiting include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, motor vehicles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0079] Figure 11An exemplary wireless communication device 1100 is illustrated, comprising a radio frequency (RF) component formed by one or more ICs 1102, wherein any of the ICs 1102 may be included in an electronic device 1103. The electronic device 1103 may include a wiring substrate comprising a metal layer serving as a first power plane in a first metallization layer of a circuit board and an additional metal plane serving as an additional second power plane in a dielectric layer disposed in an adjacent second metallization layer, to reduce the thickness of the dielectric material between the first power plane and the second power plane, thereby reducing interconnect inductance, including but not limited to... Figures 2A to 5 , Figures 8A to 8F and Figures 10A to 10F The electronic devices 200, 200(1)-200(3), 400, 500 and wiring substrates 206, 406, 506, and according to, but not limited to Figures 6 to 8C and Figures 9A to 9C This refers to any exemplary manufacturing process within the exemplary manufacturing process described herein, and in accordance with any aspect disclosed herein. As an example, wireless communication device 1100 may include or be incorporated into any of the devices mentioned above. Figure 11 As shown, the wireless communication device 1100 includes a transceiver 1104 and a data processor 1106. The data processor 1106 may include memory for storing data and program code. The transceiver 1104 includes a transmitter 1108 and a receiver 1110 supporting bidirectional communication. Generally, the wireless communication device 1100 may include any number of transmitters 1108 and / or receivers 1110 for any number of communication systems and frequency bands. All or part of the transceiver 1104 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0080] The transmitter 1108 or receiver 1110 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband; for example, for receiver 1110, it is converted from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can utilize different circuit blocks and / or have different requirements. Figure 11 In the wireless communication device 1100, the transmitter 1108 and the receiver 1110 are implemented using a direct frequency conversion architecture.

[0081] In the transmission path, data processor 1106 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1108. In the exemplary wireless communication device 1100, data processor 1106 includes digital-to-analog converters (DACs) 1111(1) and 1112(2) to convert digital signals generated by data processor 1106 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0082] Within transmitter 1108, low-pass filters 1114(1) and 1214(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the preceding digital-to-analog conversion. Amplifiers (AMPs) 1116(1) and 1116(2) amplify the signals from low-pass filters 1114(1) and 1114(2), respectively, and provide I and Q baseband signals. Upconverter 1118 upconverts the I and Q baseband signals using the I and Q TX LO signals from transmit (TX) local oscillator (LO) signal generator 1122 via mixers 1120(1) and 1120(2) to provide upconverted signal 1124. Filter 1126 filters upconverted signal 1124 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1128 amplifies the up-converted signal 1124 from filter 1126 to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is wired through duplexer or switch 1130 and transmitted via antenna 1132.

[0083] In the receiving path, antenna 1132 receives signals transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1130 and provided to low-noise amplifier (LNA) 1134. Duplexer or switch 1130 is designed to operate using specific receive (RX) and TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1134 and filtered by filter 1136 to obtain the desired RF input signal. Downconversion mixers 1138(1) and 1138(2) mix the output of filter 1136 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1140 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1142(1) and 1142(2) and further filtered by low-pass filters 1144(1) and 1144(2) to obtain I and Q analog input signals, which are provided to data processor 1106. In this example, data processor 1106 includes analog-to-digital converters (ADCs) 1146(1) and 1146(2) to convert the analog input signals into digital signals to be further processed by data processor 1106.

[0084] exist Figure 11 In the wireless communication device 1100, a TX LO signal generator 1122 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1140 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1148 receives timing information from a data processor 1106 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1122. Similarly, an RX PLL circuit 1150 receives timing information from a data processor 1106 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1140.

[0085] In this respect, Figure 12 An example of a processor-based system 1200 is illustrated, which includes circuitry that may be provided in one or more electronic devices 1202(1)-1202(7). The electronic devices 1202(1)-1202(7) may include a wiring substrate comprising a metal layer serving as a first power plane in a first metallization layer of a circuit board and an additional metal plane serving as an additional second power plane in a dielectric layer disposed in an adjacent second metallization layer, to reduce the thickness of the dielectric material between the first and second power planes, thereby reducing interconnect inductance, including but not limited to... Figures 2A to 5 , Figures 8A to 8Fand Figures 10A to 10F The electronic devices 200, 200(1)-200(3), 400, 500 and wiring substrates 206, 406, 506, and according to, but not limited to Figures 6 to 8C and Figures 9A to 9C This refers to any exemplary manufacturing process in the exemplary manufacturing process described herein, and in accordance with any aspect disclosed herein. In this example, the processor-based system 1200 may be formed as IC 1204 in electronic device 1202 and as System-on-Chip (SoC) 1206. The processor-based system 1200 includes a central processing unit (CPU) 1208, which includes one or more processors 1210, which may also be referred to as CPU cores or processor cores. The CPU 1208 may have a cache memory 1212 coupled to the CPU 1208 for fast access to temporarily stored data. The CPU 1208 is coupled to a system bus 1214 and may be coupled to master and slave devices included in the processor-based system 1200. As is well known, the CPU 1208 communicates with these other devices by exchanging address, control, and data information on the system bus 1214. For example, the CPU 1208 may communicate a bus transaction request to a memory controller 1216, which is an example of a slave device. Figure 12 Not illustrated, but multiple system buses 1214 may be provided, each of which constitutes a different structure.

[0086] Other master and slave devices can be connected to system bus 1214. For example... Figure 12As illustrated, by way of example, these devices may include a memory system 1220 (which includes a memory controller 1216 and a memory array 1218), one or more input devices 1222, one or more output devices 1224, one or more network interface devices 1226, and one or more display controllers 1228. Each of the memory system 1220, one or more input devices 1222, one or more output devices 1224, one or more network interface devices 1226, and one or more display controllers 1228 may be provided in the same or different electronic devices 1202(2)-1202(7). Input devices 1222 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 1224 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 1226 may be any device configured to allow data exchange to and from network 1230. Network 1230 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and Bluetooth. TM Networks and the Internet. The network interface device 1226 can be configured to support any type of communication protocol desired.

[0087] CPU 1208 can also be configured to access display controller 1228 via system bus 1214 to control information transmitted to one or more displays 1232. Display controller 1228 transmits information to be displayed to display 1232 via one or more video processors 1234, which process the information to be displayed into a format suitable for display 1232. As an example, display controller 1228 and video processor 1234 can be included as ICs in the same or different electronic devices 1202(2), 1202(3), and in the same or different electronic devices 1202 containing CPU 1208. Display 1232 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0088] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0089] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic component, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0090] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0091] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different technologies and processes may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0092] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0093] Specific implementation examples are described in the following numbered clauses:

[0094] 1. An electronic device, the electronic device comprising:

[0095] A wiring substrate, the wiring substrate including a plurality of metallization layers parallel to each other along a first direction, the plurality of metallization layers including:

[0096] A first metallization layer, the first metallization layer comprising:

[0097] A first metal layer, the first metal layer including a first metal plane;

[0098] and

[0099] A first dielectric layer, wherein the first dielectric layer is adjacent to the first metal layer;

[0100] A second metallization layer, adjacent to the first metallization layer, the second metallization layer comprising:

[0101] Second metal layer; and

[0102] A second dielectric layer, the second dielectric layer being adjacent to the second metal layer; and

[0103] A second metal plane is disposed in the first dielectric layer between the first metal layer and the second metal layer along the first direction; and

[0104] A capacitor coupled to the first metal plane and the second metal plane.

[0105] 2. The electronic device according to Clause 1, wherein:

[0106] The first metal plane and the second metal layer are configured to generate a first interconnect inductance in response to a voltage difference between the first metal plane and the second metal layer; and

[0107] The first metal plane and the second metal plane are configured to generate a second interconnect inductance smaller than the first interconnect inductance in response to the voltage difference between the first metal plane and the second metal plane.

[0108] 3. The electronic device according to Clause 2, wherein the ratio of the first interconnect inductor to the second interconnect inductor is at least 10.0.

[0109] 4. The electronic device according to any one of clauses 1 to 3, wherein the second metal plane is coupled to a third metal plane in the second metal layer.

[0110] 5. The electronic device according to Clause 4, wherein:

[0111] The first metal plane is configured to couple to a first power signal from a power source to carry the first power signal; and

[0112] The second metal plane is configured to couple to the power source to carry the second power signal.

[0113] 6. The electronic device according to any one of clauses 1 to 5, wherein:

[0114] The first dielectric layer between the first metal layer and the second metal layer has a first height along a second direction orthogonal to the first direction; and

[0115] The second metal plane is disposed at a first distance from the second metal layer along the second direction.

[0116] The first distance is less than the first height.

[0117] 7. The electronic device according to Clause 6, wherein the second metal plane is disposed at a second distance from the first metal layer along the second direction.

[0118] The first distance is less than the second distance.

[0119] 8. The electronic device according to clause 6 or 7, wherein:

[0120] The first height is between fifty (50) micrometers (μm) and seventy (70) μm; and

[0121] The first distance is between 1.0 μm and 5.0 μm.

[0122] 9. The electronic device according to any one of Clauses 6 to 8, wherein the ratio between the first height and the first distance is at least 10.0.

[0123] 10. The electronic device according to any one of clauses 1 to 5, wherein:

[0124] The first dielectric layer between the first metal layer and the second metal layer has a first height; and

[0125] The second metal plane is set at a first distance from the first metal layer, and the first distance is less than the first height.

[0126] 11. The electronic device according to Clause 10, wherein the second metal plane is disposed at a second distance from the second metal layer along a second direction orthogonal to the first direction.

[0127] The first distance is less than the second distance.

[0128] 12. The electronic device according to clause 10 or 11, wherein:

[0129] The first height is between fifty (50) micrometers (μm) and seventy (70) μm; and

[0130] The first distance is between 1.0 μm and 5.0 μm.

[0131] 13. The electronic device according to any one of clauses 10 to 12, wherein the ratio between the first height and the first distance is at least 10.0.

[0132] 14. The electronic device according to any one of clauses 1 to 13, further comprising: an IC package;

[0133] in:

[0134] The wiring substrate includes a circuit board;

[0135] The IC package is coupled to the circuit board; and

[0136] The IC package includes a packaging substrate, the packaging substrate including a first metal line coupled to the first metal plane and a second metal line coupled to the second metal plane; and

[0137] The IC package also includes a die coupled to the first metal line and the second metal line.

[0138] 15. The electronic device according to Clause 14, wherein:

[0139] The plurality of metallization layers are disposed in the first plane; and

[0140] The packaging substrate and the capacitor do not share a common second plane orthogonal to the first plane.

[0141] 16. An electronic device according to any one of clauses 1 to 13, the electronic device comprising an IC package, the IC package comprising:

[0142] Packaging substrate, the packaging substrate including the wiring substrate; and

[0143] A die, which is electrically coupled to the first metal plane and the second metal plane of the packaging substrate.

[0144] 17. The electronic device according to Clause 16, wherein:

[0145] The plurality of metallization layers are disposed in the first plane; and

[0146] The die and the capacitor do not share a common second plane orthogonal to the first plane.

[0147] 18. An electronic device according to any one of clauses 1 to 17, wherein said capacitor includes a deep trench capacitor (DTC).

[0148] 19. The electronic device according to any one of clauses 1 to 18, wherein:

[0149] The plurality of metallization layers are disposed in the first plane; and

[0150] The electronic device also includes:

[0151] A second capacitor is coupled to the wiring substrate;

[0152] The die is electrically coupled to the first metal plane and the second metal plane of the wiring substrate; and

[0153] The die and the second capacitor share a common second plane orthogonal to the first plane.

[0154] 20. The electronic device according to any one of clauses 1 to 19, wherein the IC package is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video discs (DVDs).

[0155] Media players; portable digital video players; automobiles; vehicle components; avionics systems; drones; and multi-rotor aircraft.

[0156] 21. A method of manufacturing an electronic device, the method comprising:

[0157] A wiring substrate is formed, the wiring substrate comprising multiple components parallel to each other along a first direction.

[0158] A metallization layer, including:

[0159] Forming a first metallization layer, wherein forming the first metallization layer includes:

[0160] A first metal layer is formed, the first metal layer including a first metal plane; and

[0161] A first dielectric layer is formed, which is adjacent to the first metal layer;

[0162] Forming a second metallization layer, wherein forming the second metallization layer includes:

[0163] Forming a second metal layer; and

[0164] A second dielectric layer is formed, which is adjacent to the second metal layer;

[0165] A second metal plane is formed in the first dielectric layer of the first metallization layer; and

[0166] Couple the second metallization layer to the first metallization layer such that the second metal plane is located between the first metallization layer and the second metallization layer along a second direction orthogonal to the first direction; and

[0167] Coupling a capacitor to the wiring substrate includes:

[0168] The capacitor is coupled to the first metal plane and the second metal plane.

[0169] 22. The method according to Clause 21, the method further comprising coupling the second metal plane to a third metal plane in the second metal layer.

[0170] 23. The method described according to Clause 21 or 22, wherein:

[0171] The first dielectric layer between the first metal layer and the second metal layer has a first height along the second direction; and

[0172] Forming the second metal plane further includes forming the second metal plane along the second direction at a first distance from the second metal layer, and

[0173] The first distance is less than the first height.

[0174] 24. The method according to clause 23, wherein forming the second metal plane further comprises forming the second metal plane along the second direction at a second distance from the first metal layer, and

[0175] The first distance is less than the second distance.

[0176] 25. The method described according to Clause 21 or 22, wherein:

[0177] The first dielectric layer between the first metal layer and the second metal layer has a first height; and

[0178] Forming the second metal plane further includes forming the second metal plane at a first distance from the first metal layer, and

[0179] The first distance is less than the first height.

[0180] 26. The method according to clause 25, wherein forming the second metal plane further comprises forming the second metal plane at a second distance from the second metal layer along the second direction, and

[0181] The first distance is less than the second distance.

[0182] 27. The method according to any one of clauses 21 to 26, the method further comprising coupling the die to the first metal plane and the second metal plane.

[0183] 28. The method described according to Clause 27, wherein:

[0184] The plurality of metallization layers are disposed in the first plane; and

[0185] The die and the capacitor do not share a common second plane orthogonal to the first plane.

Claims

1. An electronic device, the electronic device comprising: a wiring substrate comprising a plurality of metallization layers parallel to each other along a first direction, the plurality of metallization layers comprising: a first metallization layer comprising: a first metal layer comprising a first metal plane; and a first dielectric layer adjacent to the first metal layer; a second metallization layer adjacent to the first metallization layer, the second metallization layer comprising: a second metal layer; and a second dielectric layer adjacent to the second metal layer, the second dielectric layer located between the first metal layer and the second metal layer along a second direction orthogonal to the first direction; and a second metal plane disposed in the second dielectric layer, the second metal plane located between the first metal layer and the second metal layer along the second direction; and a capacitor coupled to the first metal plane and the second metal plane; wherein: the second metal plane is disposed a first distance from the first metal layer along the second direction; the second metal plane is disposed a second distance from the second metal layer along the second direction; and the first distance is less than the second distance.

2. The electronic device of claim 1, wherein: the first metal plane and the second metal layer are configured to produce a first interconnect inductance in response to a voltage difference between the first metal plane and the second metal layer; and the first metal plane and the second metal plane are configured to produce a second interconnect inductance less than the first interconnect inductance in response to a voltage difference between the first metal plane and the second metal plane.

3. The electronic device of claim 2, wherein a ratio of the first interconnect inductance to the second interconnect inductance is at least 10.

0.

4. The electronic device of claim 1, wherein the second metal plane is coupled to a third metal plane in the second metal layer.

5. The electronic device of claim 4, wherein: the first metal plane is configured to be coupled to a first power signal of a power source to carry the first power signal; and the second metal plane is configured to be coupled to a second power signal of the power source to carry the second power signal.

6. The electronic device of claim 1, wherein: the second dielectric layer has a first height along the second direction; and the first distance is less than the first height.

7. The electronic device of claim 6, wherein: the first height is between fifty (50) micrometers (pm) and seventy (70) pm; and the first distance is between 1.0 pm and 5.0 pm.

8. The electronic device of claim 6, wherein a ratio between the first height and the first distance is at least 10.

0.

9. The electronic device of claim 1, wherein: the second metal plane has a second height along the second direction; and the second distance is less than the second height.

10. The electronic device of claim 9, wherein: the second height is between fifty (50) micrometers (pm) and seventy (70) pm; and the second distance is between 1.0 pm and 5.0 pm. the second distance is between 1.0 pm and 5.0 pm.

11. The electronic device of claim 9, wherein a ratio between the second height and the second distance is at least 10.

0.

12. The electronic device of claim 1, further comprising: an integrated circuit (IC) package; wherein: the wiring substrate comprises a circuit board; the IC package is coupled to the circuit board; and the IC package comprises a package substrate comprising a first metal line coupled to the first metal plane and a second metal line coupled to the second metal plane; and the IC package further comprises a die coupled to the first metal line and the second metal line.

13. The electronic device of claim 12, wherein: the plurality of metallization layers are disposed in a first plane; and the package substrate and the capacitor do not share a common second plane that is orthogonal to the first plane.

14. The electronic device of claim 1, comprising an integrated circuit (IC) package, the integrated circuit (IC) package comprising: a package substrate, the package substrate comprising the wiring substrate; and a die electrically coupled to the first metal plane and the second metal plane of the package substrate.

15. The electronic device of claim 14, wherein: the plurality of metallization layers are disposed in a first plane; and the die and the capacitor do not share a common second plane that is orthogonal to the first plane.

16. The electronic device of claim 1, wherein the capacitor comprises a deep trench capacitor (DTC).

17. The electronic device of claim 1, wherein: the plurality of metallization layers are disposed in a first plane; and the electronic device further comprises: a second capacitor coupled to the wiring substrate; a die electrically coupled to the first metal plane and the second metal plane of the wiring substrate; and the die and the second capacitor share a common second plane that is orthogonal to the first plane.

18. The electronic device of claim 1, integrated into a device selected from a group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a transportation component; avionics; a drone; and a multicopter.

19. A method of manufacturing an electronic device, the method comprising: forming a wiring substrate, the wiring substrate comprising a plurality of metallization layers parallel to each other along a first direction, comprising: forming a first metallization layer, comprising: forming a first metal layer, the first metal layer comprising a first metal plane; and forming a first dielectric layer adjacent to the first metal layer; forming a second metallization layer, comprising: forming a second metal layer; and forming a second dielectric layer adjacent to the second metal layer, the second dielectric layer being between the first metal layer and the second metal layer along a second direction orthogonal to the first direction; forming a second metal plane in the second dielectric layer of the second metallization layer; and coupling the second metallization layer to the first metallization layer such that the second metal plane is between the first metal layer and the second metal layer along the second direction; and coupling a capacitor to the wiring substrate, comprising: coupling the capacitor to the first metal plane and the second metal plane; wherein: the second metal plane is disposed a first distance from the first metal layer along the second direction; the second metal plane is disposed a second distance from the second metal layer along the second direction; and the first distance is less than the second distance.

20. The method of claim 19, further comprising coupling the second metal plane to a third metal plane in the second metal layer.

21. The method of claim 19, wherein: the second dielectric layer has a first height along the second direction; and the first distance is less than the first height.

22. The method of claim 19, wherein: the second metal plane has a second height along the second direction; and the second distance is less than the second height.

23. The method of claim 19, further comprising coupling a die to the first metal plane and the second metal plane.

24. The method of claim 23, wherein: the plurality of metallization layers are disposed in a first plane; and the die and the capacitor do not share a common second plane orthogonal to the first plane.

25. The method of claim 21, wherein: the first height is between fifty (50) micrometers (pm) and seventy (70) pm; and the first distance is between 1.0 pm and 5.0 pm.

26. The method of claim 21, wherein a ratio between the first height and the first distance is at least 10.

0.

27. The method of claim 22, wherein: the second height is between fifty (50) micrometers (pm) and seventy (70) pm; and the second distance is between 1.0 pm and 5.0 pm.

28. The method of claim 22, wherein a ratio between the second height and the second distance is at least 10.0.

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