Sorting control method and apparatus for chip testing

Abstract

The application discloses a sorting control method and device for chip testing, and relates to the technical field of article sorting, and comprises the following steps: setting a carrier for chip testing; placing a plurality of to-be-tested chips on a plurality of test sites on the carrier, the pins of each to-be-tested chip comprising a scan register and a test access port; connecting a chip testing system, reading a test script corresponding to the plurality of to-be-tested chips; controlling a boundary scan tester to perform boundary scan testing according to the test script, and outputting chip response data; analyzing the chip response data, identifying abnormal chips and test sites of the abnormal chips, and controlling a sorting mechanism to perform abnormal sorting according to the test sites of the abnormal chips. The application solves the technical problems that the existing technology has slow sorting speed, unreasonable sorting line planning, and insufficient combination degree of chip testing and sorting control, and achieves the technical effects of improving the sorting speed, reasonably planning the sorting line, and improving the combination degree of chip testing and sorting control.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of article sorting, in particular to a sorting control method and device for chip testing. BACKGROUND

[0002] With the rapid development of the semiconductor industry, chip testing technology has been widely used in electronic manufacturing industry. The existing chip testing and sorting method has realized a certain degree of automation, which can play an important role in improving efficiency and reducing human error. However, with the continuous expansion of production scale and the increasing complexity of process flow, there are still problems in the sorting and management of normal chips and abnormal chips in the chip testing process, such as slow sorting speed, unreasonable sorting line planning, and insufficient combination of chip testing and sorting control. SUMMARY

[0003] The present application provides a sorting control method and device for chip testing, which is used to solve the technical problems of slow sorting speed, unreasonable sorting line planning, and insufficient combination of chip testing and sorting control in the prior art.

[0004] In view of the above problems, the present application provides a sorting control method and device for chip testing.

[0005] In a first aspect of the present application, a sorting control method for chip testing is provided, which comprises:

[0006] A carrier for chip testing is set, and the carrier is provided with a plurality of test sites; a plurality of to-be-tested chips are placed in the plurality of test sites on the carrier, wherein the pins of each to-be-tested chip include a scan register and a test access port, and the test single-path scan chains corresponding to each to-be-tested chip are connected to each other; a chip testing system is connected, and a test script corresponding to the plurality of to-be-tested chips is read; a boundary scan tester is controlled according to the test script to perform boundary scan testing on the plurality of to-be-tested chips, and chip response data is output; the chip response data is analyzed to identify abnormal chips and test sites of the abnormal chips, and an abnormal sorting is performed by a sorting mechanism according to the test sites of the abnormal chips.

[0007] In a second aspect of the present application, a sorting control device for chip testing is provided, which comprises:

[0008] The carrier setting unit sets a carrier for chip testing, and the carrier is provided with a plurality of test sites; the chip placing unit places a plurality of chips to be tested in the plurality of test sites on the carrier, wherein the pins of each chip to be tested include scan registers and test access ports, and the test single scan chains corresponding to each chip to be tested are connected with each other; the script reading unit is connected with a chip testing system and reads test scripts corresponding to the plurality of chips to be tested; the boundary scan testing unit controls a boundary scan tester to perform boundary scan testing on the plurality of chips to be tested according to the test scripts, and outputs chip response data; and the abnormal sorting unit analyzes the chip response data, identifies abnormal chips and test sites of the abnormal chips, and controls a sorting mechanism to perform abnormal sorting according to the test sites of the abnormal chips.

[0009] The one or more technical solutions provided in the present application have at least the following technical effects or advantages:

[0010] The carrier setting unit sets a carrier for chip testing, and the carrier is provided with a plurality of test sites; the chip placing unit places a plurality of chips to be tested in the plurality of test sites on the carrier, wherein the pins of each chip to be tested include scan registers and test access ports, and the test single scan chains corresponding to each chip to be tested are connected with each other; the script reading unit is connected with a chip testing system and reads test scripts corresponding to the plurality of chips to be tested; the boundary scan testing unit controls a boundary scan tester to perform boundary scan testing on the plurality of chips to be tested according to the test scripts, and outputs chip response data; and the abnormal sorting unit analyzes the chip response data, identifies abnormal chips and test sites of the abnormal chips, and controls a sorting mechanism to perform abnormal sorting according to the test sites of the abnormal chips. The present application solves the technical problems of the prior art, such as slow sorting speed, unreasonable sorting line planning, and insufficient combination degree of chip testing and sorting control, and achieves the technical effects of improving the sorting speed, reasonably planning the sorting line, and improving the combination degree of chip testing and sorting control, by integrating path planning algorithms, conflict detection algorithms and real-time optimization techniques. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0012] Figure 1 The sorting control method flowchart for chip testing provided in the embodiments of the present application is shown in the figure.

[0013] Figure 2A structure diagram of a sorting control device for chip testing is provided in the embodiments of the present application.

[0014] The reference signs are explained as follows: a carrier setting unit 11, a chip to be tested placing unit 12, a script reading unit 13, a boundary scan test unit 14, and an abnormal sorting unit 15. DETAILED DESCRIPTION

[0015] The present application provides a sorting control method and device for chip testing, which solves the technical problems of slow sorting speed, unreasonable sorting line planning, and insufficient combination of chip testing and sorting control in the prior art, by integrating path planning algorithms, conflict detection algorithms, and real-time optimization techniques, thereby achieving the technical effects of improving sorting speed, reasonably planning sorting lines, and improving the combination of chip testing and sorting control.

[0016] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0017] It should be noted that any variation of the terms "comprise" and "have" is intended to cover non-exclusive inclusion, for example, a process, method, device, product, or server comprising a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or modules that are not clearly listed or inherent to the process, method, product, or device.

[0018] Embodiment one, as shown in the present application provides a sorting control method for chip testing, which comprises: Figure 1

[0019] Step S100: setting a carrier for chip testing, wherein a plurality of test sites are arranged on the carrier.

[0020] In the embodiments of the present application, during the chip testing process, first, a carrier for chip testing is set, and when the carrier is set, the size, shape, and pin layout of the chip to be tested are compared with the preset carrier structure, and a carrier matching the size, shape, and pin layout of the chip to be tested is selected as the carrier for chip testing. The carrier is a specially designed physical device for fixing and accommodating a plurality of chips to be tested. A plurality of test sites are arranged on the carrier, and each test site is a predefined position for placing and fixing the chip to be tested. The test site includes a needle bed or a slot, which is precisely connected with the pins of the chip, thereby realizing stable transmission of signals.

[0021] ​Step S200: Place multiple chips to be tested in multiple test sites on the carrier, wherein the pins of each chip to be tested include scan registers and test access ports, and the test single-chain scan chains of each chip to be tested are connected to each other.

[0022] In the embodiments of the present application, the placement of chips to be tested is performed by an automated chip placement system. The automated chip placement system includes a mechanical arm and a vision recognition system. The mechanical arm picks up a chip to be tested from a chip tray and uses the vision recognition system to locate the pin positions of the chip. The mechanical arm accurately places the chip in a test site on the carrier, ensuring that the pins of the chip are aligned with the connection points on the test site. These connection points are designed to correspond to the scan registers and test access ports of the chip. The scan registers are used to store and transmit test data, while the test access ports are a standardized interface for external test equipment to communicate with the chip. After each chip is placed in a test site, the placement of other chips to be tested continues, and the placement process of each chip follows the same steps, i.e., picking up the chip from the tray, accurate positioning, and placing it in the test site.

[0023] When placing the chip in the test site, the pins of each chip are accurately connected to the connection points on the carrier. These connection points electrically connect the chip to the test system, allowing test signals to be transmitted to the chip and returned to the test system. Furthermore, the test single-chain scan chains of each chip to be tested are connected to each other to form a continuous test chain. The test single-chain scan chain refers to a path for transmitting test signals, which starts from the output of the test system, enters the chip through the input pin of the chip, passes through the scan register, and then exits from the output pin to the next chip. In this way, the scan chain of each chip is connected to the scan chain of the adjacent chip to form a long test link.

[0024] Through the above process, multiple chips to be tested are placed in multiple test sites on the carrier, and the pins of each chip, including scan registers and test access ports, are connected to the carrier while being connected to each other to form test single-chain scan chains.

[0025] Step S300: Connect the chip test system and read the test scripts corresponding to the multiple chips to be tested.

[0026] In the embodiments of the present application, the carrier is first physically connected to the chip testing system. The chip testing system is a specially designed device for performing complex chip testing tasks. It includes multiple interfaces and connection points that match the test sites on the carrier to ensure seamless signal transmission. Once the physical connection is complete, the chip testing system communicates with each chip through the test access port. The test access port is a standardized interface that allows external testing equipment to access the testing functions inside the chip. Through the TAP, the testing system sends commands to the chip and receives the response signals of the chip. After establishing the communication connection, the chip testing system begins to read the test scripts stored in the system. The test script is a set of predefined instruction set that guides the testing system on how to test each chip. These scripts include various test patterns, signal transmission paths, expected response data, and error handling mechanisms.

[0027] Step S400: According to the test script, control the boundary scan tester to perform boundary scan test on the plurality of chips to be tested, and output chip response data.

[0028] In the embodiments of the present application, first, the chip testing system configures the boundary scan tester according to the instructions in the test script, including setting the initial state of the scan register, determining the sequence and frequency of the test signal, and specifying the order of the test steps. These configuration parameters are transmitted to the boundary scan tester through a high-speed serial interface, such as JTAG. After the configuration is completed, the chip testing system issues a start instruction, and the boundary scan tester begins to perform the test. The tester sends test signals to the input pins of each chip through the test access port. These signals are sent in a predetermined sequence and frequency to ensure that all functions and connections of the chip are covered. After the test signal enters the chip, it is transmitted through the internal scan register. The signal is transmitted inside the chip along the predetermined path, passing through various functional modules and connections between pins, and finally returns to the boundary scan tester from the output pin. The boundary scan tester transmits the received response signal data back to the chip testing system. Through the above process, the chip response data is obtained.

[0029] Step S500: Analyze the chip response data, identify abnormal chips and test sites of the abnormal chips, and control the sorting mechanism to perform abnormal sorting according to the test sites of the abnormal chips.

[0030] In the embodiments of the present application, first, the chip testing system uses data analysis software to analyze the chip response data collected from the boundary scan tester in detail, compares the actual response data with the expected response mode, and finds any abnormal conditions such as signal loss, delay or incorrect connection. Through this comparative analysis, it is identified which chips show abnormality in the test, and the specific test sites of these abnormal chips are determined.

[0031] Once the abnormal chip and its test site are identified, the chip testing system controls the sorting mechanism to perform abnormal sorting. The sorting mechanism is composed of multiple mechanical arms equipped with precise movement and grabbing devices. After receiving the sorting instruction, the mechanical arms move to the test site of the identified abnormal chip according to the predetermined path, accurately grab the abnormal chip, and complete the abnormal sorting.

[0032] Further, the method provided by the application embodiment further comprises the following steps:

[0033] The position information and layout structure information of the plurality of test sites are acquired, and single-path scan chain planning is performed according to the layout structure information until a preset scan chain planning index is met, and the single-path scan chain of the carrier is output, including a single-path scan chain starting point, a single-path scan chain ending point and intermediate nodes; the boundary scan tester performs boundary scan testing on the plurality of chips to be tested through the single-path scan chain.

[0034] In the application embodiment, first, the position information and layout structure information of the plurality of test sites are acquired through a design document. The test site is a predefined position on the carrier for fixing and connecting the chip to be tested; the layout structure information includes the arrangement mode of the test site on the carrier and the connection relationship therebetween. Next, single-path scan chain planning is performed according to the position information and layout structure information. The single-path scan chain is a path for transmitting test signals and must pass through all test sites of the chips to be tested on the carrier. The planning process adopts a path optimization algorithm, such as a shortest path algorithm or Dijkstra algorithm in graph theory, to ensure that the length and complexity of the scan chain meet the preset scan chain planning index. The preset index includes the shortest path, the least number of intermediate nodes and the maximum test coverage. In the planning process, the EDA software is used to determine the starting point and the ending point of the single-path scan chain. The starting point is the first chip position where the test signal enters, and the ending point is the last position where the signal leaves after passing through all the chips. The intermediate nodes are other test sites passed through by the single-path scan chain, which are arranged in the best order calculated by the optimization algorithm. Through repeated iteration and optimization, the path of the single-path scan chain is gradually adjusted by using optimization methods such as Monte Carlo simulation, until all the preset planning indexes are met. Once the planning is completed, the single-path scan chain of the carrier is output, and the starting point, the ending point and the positions and orders of all the intermediate nodes of the link are specified in detail.

[0035] After the single-path scan chain planning is completed, the boundary scan tester performs boundary scan testing on the plurality of chips to be tested through the planned single-path scan chain. The boundary scan tester sends a test signal to the starting point of the scan chain through a test access port, and the signal sequentially passes through each intermediate node and finally reaches the ending point. Each node is a test site, and the signal is processed and transmitted by the scan register inside the chip at these nodes.

[0036] Further, the method provided by the application embodiment further comprises:

[0037] initializing a single-path scan chain, evaluating the initialized single-path scan chain, the evaluation indexes including test site coverage, length of the scan chain and transfer nodes in the scan chain, obtaining scan chain planning indexes according to the test site coverage, the length of the single-path scan chain and the transfer nodes in the scan chain, comparing the scan chain planning indexes with preset scan chain planning indexes, optimizing the initialized single-path scan chain, and outputting the single-path scan chain of the carrier.

[0038] In the application embodiment, first, the single-path scan chain is initialized by using an electronic design automation software, and a preliminary scan chain path is generated by reading position information and layout structure information of test sites on the carrier. The initial path planning adopts a standard path generation algorithm, such as a shortest path algorithm, to ensure that all test sites are included in the link. Next, the initialized single-path scan chain is evaluated, and the evaluation indexes include test site coverage, length of the scan chain and transfer nodes in the scan chain. The test site coverage evaluation is completed by using a coverage algorithm, which calculates whether the scan chain covers all test sites. The length of the scan chain is calculated by using a geometric distance algorithm to count the total length of all path segments in the link. The number of transfer nodes is counted by using a simple counting algorithm to calculate all transfer points in the signal transmission process.

[0039] After the evaluation is completed, the test site coverage, the length of the single-path scan chain and the transfer nodes in the scan chain are used as scan chain planning indexes. The scan chain planning indexes are compared with preset scan planning indexes. The preset indexes are standard values set according to best practices and specific test requirements, including minimum path length, highest coverage and least transfer nodes. In the comparison process, the actual evaluation results and the preset standards are compared item by item to determine which indexes need to be optimized.

[0040] In order to optimize the single-path scan chain, a high-level optimization algorithm, such as a genetic algorithm or a Monte Carlo simulation, is used to adjust the link path. The optimization process is iterated repeatedly, and the link indexes are recalculated and evaluated after each adjustment, gradually approaching the preset standard. By this method, the path length is shortened, the coverage is improved and the number of transfer nodes is reduced. Finally, after multiple iterations and optimization, the single-path scan chain of the carrier is output.

[0041] Further, the method provided by the application embodiment further comprises:

[0042] The carrier further has multiple-path scan chains planned therein, wherein the multiple-path scan chains correspond to the multiple test sites; and the multiple-path scan chains are used to perform independent boundary scan tests on the multiple chips to be tested.

[0043] In the embodiments of the present application, first, the electronic design automation software is used to plan multiple scan chains. By reading the position information and layout structure information of all test sites on the carrier, a preliminary multiple scan chain layout is generated. Each scan chain corresponds to a group of test sites, ensuring that all chips under test can accept independent boundary scan testing through these links.

[0044] After planning, each scan chain starts from a starting point, passes through a series of intermediate nodes, and finally reaches the termination point. The design of multiple scan chains enables each link to work independently without interference. According to the planned multiple scan chains, independent boundary scan testing is performed on multiple chips under test. During the testing process, signal transmission and data acquisition of each scan chain are performed independently. The tester records the response data of each chip and transmits these data back to the chip testing system. Through the planning and use of multiple scan chains, the impact of single-point failures is reduced. If a scan chain fails, other links can still continue to work, ensuring the reliability and stability of the overall testing process.

[0045] Further, the method provided by the embodiments of the application comprises:

[0046] The chip testing system further comprises a mode switching control module; wherein the mode switching control module is provided with a chip response health sample; the mode switching control module performs abnormality identification on the chip response data according to the chip response health sample, activates a mode switching instruction if the chip response data is abnormal, wherein the chip response data is obtained through single scan chain mode testing; according to the mode switching instruction, the mode of single scan chain is switched to the mode of multiple scan chains, multiple chip response data are obtained, and abnormal chips are identified according to the multiple chip response data.

[0047] In the embodiments of the present application, in the chip testing system, in addition to the conventional test module, a mode switching control module is also included. The design purpose of this module is to enhance the flexibility of the testing system and the ability to cope with abnormal situations. The mode switching control module is provided with a chip response health sample for comparison and identification of abnormal situations that may occur during chip testing. The chip response health sample refers to pre-determined response data representing the normal working state of the chip.

[0048] When identifying anomalies in chip response data based on healthy chip response samples, statistical anomaly detection algorithms are used to calculate the difference between the chip response data and the healthy samples. For example, the Z-score is calculated for each test point to measure its deviation from the mean of the healthy samples. Based on the calculated difference index, it is determined whether the chip response data is abnormal. Specifically, technical experts first set a threshold, such as an absolute value of the Z-score exceeding 3, and then compare the calculated difference index with the threshold. If the difference index exceeds the threshold, the chip response data is considered abnormal.

[0049] When an anomaly is detected, the mode switching control module sends a mode switching command via the system bus. Upon receiving the command, the chip testing system initiates a multi-scan chain mode, where the boundary scan tester simultaneously uses multiple independent scan chains to perform parallel testing on the chip under test. The testing system acquires the response data of each chip through each independent scan chain, and the test data is transmitted to the testing system via a parallel interface.

[0050] After parallel testing, data fusion techniques are used to integrate response data from different scan chains for comprehensive evaluation. First, data fusion techniques, such as Kalman filtering or Bayesian inference, are used to integrate response data from multiple scan chains to form a comprehensive dataset. Then, statistical analysis tools are used to evaluate the comprehensive dataset to determine the specific location and cause of anomalies. Specifically, based on healthy chip response samples, a statistical model under normal operating conditions is constructed, including calculating the mean and standard deviation. Next, Z-scores are used to calculate the difference between each test point in the comprehensive dataset and the healthy sample. The calculated difference index is compared with a preset threshold to determine which test points are abnormal. Through this process, abnormal chips are identified, qualified chips are distinguished, and the test positions of each chip are recorded.

[0051] Furthermore, in the method provided in the application embodiments, the abnormal chip is sorted according to the test bit control sorting mechanism, including:

[0052] The sorting mechanism includes a first sorting arm and a second sorting arm; the first sorting arm sorts the abnormal chips according to their test positions and places them in a non-conforming container, while the second sorting arm sorts the remaining test chips into a conforming container.

[0053] In this embodiment of the application, the sorting mechanism includes a first sorting arm and a second sorting arm. The first sorting arm is responsible for sorting abnormal chips, and the second sorting arm is responsible for sorting qualified chips.

[0054] The first sorting arm moves to the test site where the abnormal chip is located through a pre-planned path, the mechanical arm uses a vacuum chuck or a mechanical clamp to pick up the abnormal chip from the test site, and then the first sorting arm moves the picked-up abnormal chip to the unqualified container and places it at a specified position.

[0055] The second sorting arm also moves to the test site where the qualified chip is located along a pre-planned path, and the mechanical arm also uses a vacuum chuck or a mechanical clamp to pick up the qualified chip from the test site. Then the second sorting arm moves the picked-up qualified chip to the qualified container and places it at a specified position.

[0056] Further, the method provided by the application embodiment comprises the following steps:

[0057] The sorting route of the first sorting arm is planned, the sorting route of the second sorting arm is planned, collision prediction is performed on the sorting route of the first sorting arm and the sorting route of the second sorting arm to obtain a collision index, the sorting route of the first sorting arm and the sorting route of the second sorting arm are respectively optimized according to the collision index, and the optimized sorting route of the first sorting arm and the optimized sorting route of the second sorting arm are output.

[0058] In the application embodiment, for the first sorting arm, the optimal path is planned by reading the information of the chip test site and combining the current position of the sorting arm, and the A* algorithm is used to determine the sorting route of the first sorting arm. Similarly, for the second sorting arm, the same path planning algorithm is used to plan the optimal path by reading the test site information of the qualified chip and combining the current position of the sorting arm, and the sorting route of the second sorting arm is determined.

[0059] After the initial sorting route is planned, collision prediction is performed on the sorting route of the first sorting arm and the sorting route of the second sorting arm, and a collision detection algorithm such as the RRT algorithm is used for collision prediction. The RRT algorithm identifies the positions and times where collisions are likely to occur by simulating the motion trajectories of the two mechanical arms, and generates a collision index.

[0060] Once the conflict indicators are obtained, the sorting lines of the first sorting arm and the second sorting arm are optimized according to the conflict indicators. Specifically, first, a priority scheduling algorithm is used to rearrange the task order of the mechanical arms. The priority scheduling algorithm assigns priorities according to the importance and urgency of each mechanical arm task, and arranges the execution order of the tasks. By adjusting the movement order, the mechanical arms are prevented from occupying the same space at the same time. In the present application, the priority of the first sorting arm is higher than that of the second sorting arm. If the movement order adjustment cannot completely avoid the conflict, a path optimization algorithm is used to recalculate the path of the mechanical arms. On the basis of adjusting the path and the movement order, a speed planning algorithm is used to optimize the movement speed of the mechanical arms. Gradient descent method iteratively optimizes the speed curve, so that the mechanical arms are staggered in time, thereby avoiding conflicts.

[0061] Through the above process, the optimization of the sorting lines of the first sorting arm and the sorting lines of the second sorting arm is completed, and the optimized sorting lines of the first sorting arm and the optimized sorting lines of the second sorting arm are output.

[0062] In the embodiments of the present application, as described above, the embodiments of the present application have at least the following technical effects:

[0063] The present application sets a carrier for chip testing, and the carrier is provided with a plurality of test sites; a plurality of to-be-tested chips are placed in the plurality of test sites on the carrier, wherein the pins of each to-be-tested chip include scan registers and test access ports, and the test single-path scan chains corresponding to each to-be-tested chip are connected to each other; a chip testing system is connected, and a test script corresponding to the plurality of to-be-tested chips is read; a boundary scan tester is controlled according to the test script to perform boundary scan testing on the plurality of to-be-tested chips, and chip response data is output; the chip response data is analyzed, abnormal chips and test sites of the abnormal chips are identified, and a sorting mechanism is controlled according to the test sites of the abnormal chips to perform abnormal sorting. The present application solves the technical problems of the prior art, such as slow sorting speed, unreasonable sorting line planning, and insufficient combination degree of chip testing and sorting control, and achieves the technical effects of improving the sorting speed, reasonably planning the sorting line, and improving the combination degree of chip testing and sorting control by integrating path planning algorithms, conflict detection algorithms, and real-time optimization technologies.

[0064] In the embodiments of the present application, as described above, the embodiments of the present application have at least the following technical effects: Figure 2 As shown in the foregoing embodiments, the present application provides a sorting control device for chip testing, and the device and method embodiments in the present application are based on the same inventive concept. The device includes:

[0065] The device comprises a carrier setting unit 11, a chip placing unit 12, a script reading unit 13, a boundary scan testing unit 14 and an abnormal sorting unit 15.

[0066] Further, the device is further used to realize the following functions:

[0067] The device is further used to realize the following functions:

[0068] Further, the device is further used to realize the following functions:

[0069] The device is further used to realize the following functions:

[0070] Further, the device is further used to realize the following functions:

[0071] The device is further used to realize the following functions:

[0072] Further, the device is further used to realize the following functions:

[0073] The chip test system further comprises a mode switching control module; wherein the mode switching control module is provided with a chip response health sample; the mode switching control module performs abnormality identification on the chip response data according to the chip response health sample, activates a mode switching instruction if the chip response data is abnormal, wherein the chip response data is acquired through single-path scan chain mode test; the mode of the single-path scan chain is switched to the mode of the multi-path scan chain according to the mode switching instruction, a plurality of chip response data is acquired, and an abnormal chip is identified according to the plurality of chip response data.

[0074] Further, the device is further used to realize the following functions:

[0075] Wherein, the sorting mechanism comprises a first sorting arm and a second sorting arm; the first sorting arm performs abnormal sorting according to the test position of the abnormal chip and is placed in an unqualified container, and the second sorting arm sorts the remaining test chips into a qualified container.

[0076] Further, the device is further used to realize the following functions:

[0077] Planning a sorting route of the first sorting arm; planning a sorting route of the second sorting arm; performing conflict prediction on the sorting route of the first sorting arm and the sorting route of the second sorting arm to obtain a conflict index; respectively optimizing the sorting route of the first sorting arm and the sorting route of the second sorting arm according to the conflict index, and outputting the optimized sorting route of the first sorting arm and the optimized sorting route of the second sorting arm.

[0078] It should be noted that the above-mentioned sequence of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. The above describes a specific embodiment of the present application. The processes depicted in the drawings do not necessarily require the specific order and continuous order shown to achieve the desired results. In some embodiments, multi-task processing and parallel processing are possible or can be advantageous.

[0079] The above only describes the preferred embodiments of the present application and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0080] The present specification and drawings are only exemplary descriptions of the present application, and are considered to cover any and all modifications, changes, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art can make various modifications and changes to the present application without departing from the scope of the present application. Thus, if these modifications and changes of the present application belong to the scope of the present application and its equivalents, the present application intends to include these modifications and changes.

Claims

1. A method of controlling sorting for chip testing, characterized by, The method comprises: A carrier for chip testing is arranged, and a plurality of test sites are arranged on the carrier; A plurality of to-be-tested chips are placed in the plurality of test sites on the carrier, wherein the pins of each to-be-tested chip comprise scan registers and test access ports, and the corresponding test single scan chains of each to-be-tested chip are connected to each other; A chip testing system is connected, and test scripts corresponding to the plurality of to-be-tested chips are read; Boundary scan testing of the plurality of to-be-tested chips is controlled according to the test scripts by a boundary scan tester, and chip response data is output; The chip response data is analyzed, and an abnormal chip and a test site of the abnormal chip are identified, and the sorting mechanism is controlled according to the test site of the abnormal chip to perform abnormal sorting; The single scan chain is planned in the carrier, and the planning of the single scan chain comprises: Position information and layout structure information of the plurality of test sites are acquired; The single scan chain is planned according to the layout structure information until a preset scan chain planning index is met, and the single scan chain of the carrier is output, including a single scan chain starting point, an end point and intermediate nodes; The boundary scan tester performs boundary scan testing on the plurality of to-be-tested chips through the single scan chain; The plurality of test sites correspond to a plurality of scan chains which are also planned in the carrier; The plurality of to-be-tested chips are independently subjected to boundary scan testing according to the plurality of scan chains; The chip testing system further comprises a mode switching control module; The mode switching control module is provided with a chip response health sample; The mode switching control module identifies abnormalities in the chip response data according to the chip response health sample, and activates a mode switching instruction if the chip response data is abnormal, wherein the chip response data is obtained through mode testing of the single scan chain; According to the mode switching instruction, the mode of the single scan chain is switched to the mode of the multiple scan chains, a plurality of chip response data is obtained, and an abnormal chip is identified according to the plurality of chip response data.

2. The method of claim 1, wherein, The method for planning the single scan chain according to the layout structure information comprises: The single scan chain is initialized, and the initialized single scan chain is evaluated, and the evaluation index comprises test site coverage, length of the scan chain and scan chain transfer nodes; The scan chain planning index is obtained according to the test site coverage, the length of the single scan chain and the scan chain transfer nodes; The scan chain planning index is compared with a preset scan chain planning index, the initialized single scan chain is optimized, and the single scan chain of the carrier is output.

3. The method of claim 1, wherein, The method for controlling the sorting mechanism to perform abnormal sorting according to the test site of the abnormal chip comprises: The sorting mechanism comprises a first sorting arm and a second sorting arm; The first sorting arm performs abnormal sorting according to the test site of the abnormal chip and is placed in an unqualified container, and the second sorting arm sorts the remaining test chips into a qualified container. The method for controlling the sorting mechanism to perform abnormal sorting according to the test site of the abnormal chip further comprises:

4. The method of claim 3, wherein, A sorting line of the first sorting arm is planned; A sorting line of the second sorting arm is planned; ​ The sorting lines of the first sorting arm and the second sorting arm are subjected to conflict prediction to obtain a conflict index; The sorting lines of the first sorting arm and the second sorting arm are respectively optimized according to the conflict index, and the optimized sorting lines of the first sorting arm and the second sorting arm are output.

5. A handler control device for testing of chips, characterized in that The device is used to perform the sorting control method for chip testing as claimed in any one of claims 1-4, and the device comprises: A carrier setting unit is configured to set a carrier for chip testing, and the carrier is provided with a plurality of test sites; A to-be-tested chip placing unit is configured to place a plurality of to-be-tested chips in the plurality of test sites on the carrier, wherein the pins of each to-be-tested chip comprise scan registers and test access ports, and the test single-path scan chains corresponding to each to-be-tested chip are connected to each other; A script reading unit is connected to a chip testing system and reads test scripts corresponding to the plurality of to-be-tested chips; A boundary scan test unit is configured to control a boundary scan tester to perform boundary scan testing on the plurality of to-be-tested chips according to the test scripts and output chip response data; An abnormal sorting unit is configured to analyze the chip response data, identify abnormal chips and test sites of the abnormal chips, and control a sorting mechanism to perform abnormal sorting according to the test sites of the abnormal chips.

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