Ground penetrating radar echo signal collecting and processing device and method

Abstract

The invention provides a ground penetrating radar echo signal acquisition and processing device and method, and relates to the field of ground penetrating radars, and the device comprises an echo conditioning circuit, an ADC module, an FPGA module, an STM32 module, and an upper computer. An echo conditioning circuit is used for receiving an echo signal during detection of the ground penetrating radar and conditioning the echo signal; analog-to-digital conversion is carried out on the echo signals through an ADC module, and parallel high-speed data streams are obtained; the acquisition process of the ADC module and the gain of the echo conditioning circuit are controlled through the FPGA module; the FPGA module is used for receiving the high-speed data flow and carrying out data processing, and sending the data to the STM32 module; and the processed high-speed data stream is transmitted to the upper computer through the STM32 module for visual display. According to the technical scheme, the method can adapt to complex and changeable geological exploration environments and has high exploration precision.

Description

Technical Field

[0001] The present application relates to the field of ground penetrating radar, and in particular to a device and method for collecting and processing ground penetrating radar echo signals. Background Art

[0002] Ground penetrating radar (GPR) equipment transmits electromagnetic waves underground, and uses the characteristics of different reflected signals generated when encountering media with different dielectric constants during the propagation of electromagnetic waves to identify the distribution of underground media. By receiving reflected pulses caused by discontinuities, it can detect underground structures and objects. It is widely used in road inspection, archaeological detection and mineral exploration to find underground defects, ancient sites, mineral resources and obstacles.

[0003] Ground penetrating radar uses electromagnetic waves as information carriers. Since electromagnetic waves decay quickly during propagation, the detection accuracy of underground cavities is related to the center frequency of the electromagnetic waves. The higher the center frequency of the electromagnetic waves, the higher the detection accuracy, but the faster the decay. It is suitable for high-precision detection of shallow layers, and vice versa for deep detection. Therefore, a high-power high-frequency signal is usually generated, which is transmitted underground through the antenna, and then the echo signal is received by the antenna for analysis and processing to achieve the detection of underground conditions.

[0004] The echo signal received by the antenna cannot be directly collected using ADC, so a front-end conditioning circuit is designed to amplify or attenuate the signal to a suitable range according to the needs. In the face of high-frequency echo signals, a high-speed data acquisition system is designed. A high-speed data acquisition circuit is designed based on FPGA and two domestic high-speed ADCs. At the same time, a set of ADC control and high-speed LVDS data stream receiving solutions are designed using FPGA. A high-speed acquisition system with program-controllable sampling rate is realized to adapt to the working conditions of different electromagnetic wave frequencies and select the appropriate sampling rate to collect signals.

[0005] Due to the working characteristics of ground penetrating radar, various clutter and noise will be received in actual detection work, including electromagnetic interference caused by mobile phones, wires, etc. Therefore, it is very necessary to study reliable ground penetrating radar echo signal processing methods and noise filtering. Summary of the invention

[0006] The purpose of the present invention is to provide a ground penetrating radar echo signal acquisition and processing device and method in order to solve the problem that the existing signal filtering technology cannot effectively filter the electromagnetic interference in the echo signal.

[0007] The above-mentioned purpose of the present application is achieved through the following technical solutions:

[0008] The device comprises: an echo conditioning circuit, an ADC module, an FPGA module, an STM32 module and a host computer;

[0009] The echo conditioning circuit is connected to the ADC module; the echo conditioning circuit is connected to the FPGA module; the ADC module is connected to the FPGA module; the FPGA module is connected to the STM32 module;

[0010] The echo conditioning circuit is used to receive and condition the echo signal during ground penetrating radar detection;

[0011] The ADC module is used to perform analog-to-digital conversion on the conditioned echo signal to obtain a parallel high-speed data stream;

[0012] The FPGA module is used to control the analog-to-digital conversion process of the ADC module;

[0013] The FPGA module is also used to receive the parallel high-speed data stream and perform data processing to obtain the first data stream and send it to the STM32 module;

[0014] The STM32 module is used to receive and process the first data stream, and issue a reverse control gain instruction to the FPGA module;

[0015] The FPGA module is also used to control the gain of the echo conditioning circuit through reverse control gain instructions, so as to realize program-controlled amplification or attenuation of the echo signal;

[0016] The host computer is used to visualize the processed first data stream.

[0017] Optionally, the echo conditioning circuit includes: a radio frequency transformer, a radio frequency amplifier with variable gain, and a fully differential amplifier;

[0018] The radio frequency transformer, the radio frequency amplifier with variable gain and the fully differential amplifier are connected in sequence;

[0019] A variable gain RF amplifier is connected to the FPGA module; a fully differential amplifier is connected to the ADC module;

[0020] The radio frequency transformer is used to transform the received radio frequency signal;

[0021] The variable gain RF amplifier is used to programmatically amplify or programmatically attenuate the voltage-converted echo signal before inputting it into the fully differential amplifier;

[0022] The model of the radio frequency transformer is T3002NL;

[0023] The model of the variable gain RF amplifier is ADL5201ACPZ-R7;

[0024] The model of the fully differential amplifier is LMH6554.

[0025] Optionally, the ADC module uses two analog-to-digital converters to alternately sample the conditioned echo signal; the model of the analog-to-digital converter is MXT2001; the two analog-to-digital converters are connected in parallel;

[0026] The ADC module samples the conditioned echo signal through the DES double-edge sampling mode combined with the double edges of the sampling clock provided by the FPGA module to obtain a parallel high-speed data stream;

[0027] The ADC module also sends parallel high-speed data streams to the FPGA module through LVDS low-voltage differential transmission.

[0028] Optionally, the FPGA chip model of the FPGA module is 10CL055YF484C6G.

[0029] Optionally, the FPGA module includes: a high-speed data receiving unit, a pulse control unit, a data cache unit, a data superposition unit and a control gain unit;

[0030] The high-speed data receiving unit is connected to the data buffer unit; the data buffer unit is connected to the data superposition unit; the data superposition unit is connected to the STM32 module; the control gain unit is connected to the STM32 module; the control gain unit is connected to the echo conditioning circuit;

[0031] The data buffer unit is used to cache the received parallel high-speed data streams, and reassemble the parallel high-speed data streams into serial data, and input them into the data superposition unit for data processing;

[0032] The data superposition unit is used to perform zero-time correction and superposition noise reduction processing on the spliced ​​high-speed data stream to obtain the first data stream and send it to the STM32 module;

[0033] The control gain unit is used to adjust the gain of the echo conditioning circuit;

[0034] The pulse control unit is used to control the signal source and transmit the pulse signal to the underground through the transmitting antenna.

[0035] Optionally, the FPGA module obtains two sampling clocks with a phase difference of 90° through PLL phase-locked loop frequency multiplication and phase shift processing;

[0036] The high-speed data receiving unit is used to input sampling clocks with the same frequency and different phases into the ADC module;

[0037] The high-speed data receiving unit is also used to receive parallel high-speed data streams.

[0038] Optionally, the data processing of the FPGA module includes: zero-time correction and superposition noise reduction processing;

[0039] The specific steps of zero-time correction include: using the relative position between the fixed transmitting antenna and the receiving antenna and taking the arrival time of the direct wave as a reference to correct the time difference;

[0040] The specific steps of the superposition noise reduction process include: using an average superposition noise reduction algorithm to process the high-speed data stream.

[0041] A method for collecting and processing ground penetrating radar echo signals, characterized in that the method comprises:

[0042] S1: Fix the relative positions of the transmitting antenna and the receiving antenna; transmit radar signals through the transmitting antenna; receive echo signals during ground penetrating radar detection through the receiving antenna;

[0043] S2: Condition the echo signal;

[0044] S3: by performing parallel high-speed sampling on the conditioned echo signal to obtain a parallel high-speed data stream;

[0045] S4: performing splicing, zero-time correction, average superposition noise reduction processing and calculation on the parallel high-speed data streams to obtain a first data stream and a gain control signal;

[0046] Update the conditioning parameters of the echo signal through the gain control signal;

[0047] S5: Complete the detection of underground cavities by processing and visualizing the first data stream.

[0048] The beneficial effects of the technical solution provided by this application are:

[0049] 1. The echo signal is conditioned at the front end by the echo conditioning circuit, and then 3.6GSPS high-speed data acquisition is realized by using FPGA and two ADCs, and finally the received data is subjected to real-time high-speed superposition, averaging, superposition and noise reduction processing, with high detection accuracy. The echo conditioning circuit of the present invention can be well applied to various complex and changeable ground exploration environments, and has high practicality.

[0050] 2. In order to reduce the impact of noise, a real-time superposition average noise reduction is designed. At the same time, the collected echo signal is corrected at zero time for the jitter of the signal source. When the ground penetrating radar is working, the FPGA will perform real-time high-speed superposition average filtering on the received echo signal data. After reaching a certain number of times, the filtered data will be sent to the host computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The present application will be further described below with reference to the accompanying drawings and embodiments, in which:

[0052] Figure 1 is a structural diagram in an embodiment of the present application;

[0053] Figure 2 It is a circuit diagram of the FPGA controlling the single-chip ADC in the embodiment of the present application;

[0054] Figure 3 It is a logic block diagram of the FPGA controlling the single-chip MXT2001 acquisition and transmission in the embodiment of the present application;

[0055] Figure 4 It is a high-speed data stream receiving diagram in an embodiment of the present application;

[0056] Figure 5 This is a schematic diagram of the alternating sampling principle of two ADCs in an embodiment of the present application;

[0057] Figure 6 It is a structural diagram of data sampling in an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to have a clearer understanding of the technical features, purposes and effects of the present application, the specific implementation methods of the present application are now described in detail with reference to the accompanying drawings.

[0059] An embodiment of the present application provides a ground penetrating radar echo signal acquisition and processing device.

[0060] Please refer to Figure 1 , Figure 1 It is a structural diagram of a ground penetrating radar echo signal acquisition and processing device in an embodiment of the present application, including: the device includes: an echo conditioning circuit, an ADC module, an FPGA module, an STM32 module and a host computer;

[0061] The echo conditioning circuit is connected to the ADC module; the echo conditioning circuit is connected to the FPGA module; the ADC module is connected to the FPGA module; the FPGA module is connected to the STM32 module;

[0062] The echo conditioning circuit is used to receive and condition the echo signal during ground penetrating radar detection;

[0063] The ADC module is used to perform analog-to-digital conversion on the conditioned echo signal to obtain a parallel high-speed data stream;

[0064] The FPGA module is used to control the analog-to-digital conversion process of the ADC module;

[0065] The FPGA module is also used to receive the parallel high-speed data stream and perform data processing to obtain the first data stream and send it to the STM32 module;

[0066] The STM32 module is used to receive and process the first data stream, and issue a reverse control gain instruction to the FPGA module;

[0067] The FPGA module is also used to control the gain of the echo conditioning circuit through reverse control gain instructions, so as to realize program-controlled amplification or attenuation of the echo signal;

[0068] The host computer is used to visualize the processed first data stream.

[0069] The echo conditioning circuit includes: a radio frequency transformer, a radio frequency amplifier with variable gain, and a fully differential amplifier;

[0070] The radio frequency transformer, the radio frequency amplifier with variable gain and the fully differential amplifier are connected in sequence;

[0071] A variable gain RF amplifier is connected to the FPGA module; a fully differential amplifier is connected to the ADC module;

[0072] The radio frequency transformer is used to transform the received radio frequency signal;

[0073] The variable gain RF amplifier is used to programmatically amplify or programmatically attenuate the voltage-converted echo signal before inputting it into the fully differential amplifier;

[0074] The model of the radio frequency transformer is T3002NL;

[0075] The model of the variable gain RF amplifier is ADL5201ACPZ-R7;

[0076] The model of the fully differential amplifier is LMH6554.

[0077] As an embodiment, the echo conditioning circuit first passes the echo signal through an RF transformer to complete the electrical isolation of the signal. After that, due to the limited input amplitude of the high-performance ADC, it is necessary to pass through a variable gain RF amplifier to implement program-controlled amplification or attenuation of the input signal through FPGA. The input signal finally needs to pass through a fully differential amplifier to offset the interference of the common-mode signal, and then the signal differential is input into the ADC; in the design of the echo conditioning circuit, stable signal transmission is achieved through impedance matching. After passing through the RF transformer model T3002NL, the echo signal is input into the variable gain amplifier model ADL5201ACPZ-R7, and after program-controlled amplification or attenuation, it is input into the LMH6554 fully differential amplifier to provide low-distortion amplification for broadband differential signals.

[0078] The ADC module uses two analog-to-digital converters to alternately sample the conditioned echo signal; the model of the analog-to-digital converter is MXT2001; the two analog-to-digital converters are connected in parallel;

[0079] The ADC module samples the conditioned echo signal through the DES double-edge sampling mode combined with the double edges of the sampling clock provided by the FPGA module to obtain a parallel high-speed data stream;

[0080] The ADC module also sends parallel high-speed data streams to the FPGA module through LVDS low-voltage differential transmission.

[0081] As an embodiment, the core device ADC adopts the model of MXT2001, which is a dual-channel, high-performance ADC with a sampling accuracy of 8 bits and a variety of program-controllable acquisition and data-side transmission methods. Under dual-channel working conditions, each channel can reach a maximum of 1.0GSPS. It supports time-interleaved mode sampling, and can reach a maximum of 2.0GSPS under bilateral sampling. The chip integrates two channels of ADC, and uses TIADC technology to shift the phase of the sampling clock so that the two ADCs are sampled alternately, doubling the real-time sampling rate. The converted data adopts LVDS parallel transmission mode, and with the data synchronization clock, the data is sent to the FPGA in parallel at a speed of up to 500MHz. The main structure of the FPGA-controlled single-chip ADC working circuit, such as Figure 2 As shown in Figure 1, the monolithic ADC has four parallel high-speed data streams.

[0082] As an example, in order to achieve higher resolution sampling, two ADCs are used to alternately sample to achieve 3.6 GSPS. The design principle is as follows: Figure 5 shown.

[0083] As an embodiment, a sampling clock with the same frequency but different phases is used to control multiple ADCs to work together. The sampling clock is phase-shifted and then distributed to each sub-ADC as the sampling clock of each sub-ADC, so that the same signal can be collected at different phases. The collected data is then processed and rearranged to finally restore the original signal.

[0084] The phase corresponding to the kth ADC is: Finally, if N ADC chips are integrated within one sampling clock cycle, the sampling rate is f = Nf clk

[0085] In PCB design, the transmission lines from the input signal to the two ADCs are strictly controlled to be equal in length, the clock lines of the two ADCs are equal in length, and the data lines from the two ADCs to the FPGA are equal in length. The sampling clock is phase-shifted 90° inside the FPGA and then input to the two ADCs to achieve alternating sampling. After that, the data is alternately spliced ​​inside the FPGA. The design structure diagram is as follows: Figure 6 shown.

[0086] The FPGA chip model of the FPGA module is 10CL055YF484C6G.

[0087] As an example, the main design of the single-chip MXT2001 acquisition is concentrated on the logic of the FPGA. From a functional analysis, it mainly includes: PLL module, data storage module, data reordering module, SPI communication module and FPGA timing constraints. The logic block diagram of FPGA controlling the single-chip MXT2001 acquisition transmission is as follows: Figure 3 shown.

[0088] The FPGA module includes: a high-speed data receiving unit, a pulse control unit, a data buffer unit, a data superposition unit and a control gain unit;

[0089] The high-speed data receiving unit is connected to the data buffer unit; the data buffer unit is connected to the data superposition unit; the data superposition unit is connected to the STM32 module; the control gain unit is connected to the STM32 module; the control gain unit is connected to the echo conditioning circuit;

[0090] The data buffer unit is used to cache the received parallel high-speed data streams, and reassemble the parallel high-speed data streams into serial data, and input them into the data superposition unit for data processing;

[0091] The data superposition unit is used to perform zero-time correction and superposition noise reduction processing on the spliced ​​high-speed data stream to obtain the first data stream and send it to the STM32 module;

[0092] The control gain unit is used to adjust the gain of the echo conditioning circuit;

[0093] The pulse control unit is used to control the signal source and transmit the pulse signal to the underground through the transmitting antenna.

[0094] The FPGA module obtains two sampling clocks with a phase difference of 90° through PLL phase-locked loop frequency multiplication and phase shift processing;

[0095] The high-speed data receiving unit is used to input sampling clocks with the same frequency and different phases into the ADC module;

[0096] The high-speed data receiving unit is also used to receive parallel high-speed data streams.

[0097] As an embodiment, the sampling and transmission of MXT2001 each have two modes, and the FPGA high-speed data stream receiving method is designed according to the mode used. In the sampling mode of MXT2001, the double-sided sampling mode (DES) samples on both edges of the sampling clock provided by the FPGA, and the sampling frequency is twice the clock frequency. In this mode, all sub-ADCs under the two channels sample one of the channels. In terms of data transmission, the single data rate transmission (SDR) only transmits on a single edge of the data clock DCLK, and both data of the I channel and the Q channel are output in parallel.

[0098] As an embodiment, in the bilateral sampling mode, the designed FPGA high-speed data stream receiving solution is as follows: Figure 4 In this design, the FPGA multiplies the 50MHz clock to 900MHz and outputs it to the ADC as a sampling clock. The single-chip ADC works in DES mode to achieve a sampling rate of 1.8GSPS (Gigabit Samples Per Second) and sends the high-speed data stream to the FPGA via low voltage differential transmission (LVDS).

[0099] As an embodiment, in the internal design of the FPGA, the phase difference between the two sampling clocks is 90° through PLL phase-locked loop frequency multiplication, and they are sent to two ADCs respectively. Then, the parallel 450MHz data streams of the two ADCs are buffered and received, and then spliced ​​and sent to the host computer.

[0100] The data processing of the FPGA module includes: zero-time correction and superposition noise reduction processing;

[0101] The specific steps of zero-time correction include: using the relative position between the fixed transmitting antenna and the receiving antenna and taking the arrival time of the direct wave as a reference to correct the time difference;

[0102] The specific steps of the superposition noise reduction process include: using an average superposition noise reduction algorithm to process the high-speed data stream.

[0103] As an embodiment, data processing is designed inside the FPGA. The FPGA chip temporarily stores the parallel high-speed sampling data stream in the ROM read-only memory, and then reads it out serially through a high-speed clock to restore the normal serial sampling data. Then, a group of data is corrected at zero time inside the FPGA, and real-time superposition and average noise reduction are performed. This is repeated continuously. After a certain noise reduction effect is achieved, the processed data is forwarded to the STM32 chip, and the STM32 acts as a relay to send the data to the host computer.

[0104] As an embodiment, when the device is working, there are often various interferences and noises, and due to the consistency of the device and the influence of temperature on the analog circuit, the delay between the final output of the signal and the trigger signal may fluctuate. In order to reduce the impact of noise interference on detection accuracy and stability, it is necessary to perform zero-time correction and superposition noise reduction processing on the data and send it to the STM32 module, and then transmit it to the host computer. The STM32 module mainly plays the role of function control and data interaction.

[0105] As an example, for zero-time correction, the device uses the idea of ​​fixing the relative position between the transmitting and receiving antennas and using the arrival time of the direct wave as a reference to correct the time difference. For random noise in the environment, the device uses an average superposition noise reduction algorithm to highlight the effective information of the reflected waveform and improve the signal-to-noise ratio.

[0106] The device integrates zero-time correction and noise reduction into a module, which includes a superposition operator, a traversal search module, a data selector, a shift divider, and a dual-port data cache module generated by the M9K memory resources inside the FPGA. The processed data is sent to the STM32, which temporarily stores the data and reversely controls the gain. Finally, during actual detection, the designed host computer can observe that the high-speed acquisition and processing of the echo signal are completed normally.

[0107] A method for collecting and processing ground penetrating radar echo signals, the method comprising:

[0108] S1: Fix the relative positions of the transmitting antenna and the receiving antenna; transmit radar signals through the transmitting antenna; receive echo signals during ground penetrating radar detection through the receiving antenna;

[0109] S2: Condition the echo signal;

[0110] S3: by performing parallel high-speed sampling on the conditioned echo signal to obtain a parallel high-speed data stream;

[0111] S4: performing splicing, zero-time correction, average superposition noise reduction processing and calculation on the parallel high-speed data streams to obtain a first data stream and a gain control signal;

[0112] Update the conditioning parameters of the echo signal through the gain control signal;

[0113] S5: Complete the detection of underground cavities by processing and visualizing the first data stream.

[0114] The above are only exemplary embodiments of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure.

[0115] This application is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the art not described in the present disclosure. The description and examples are to be regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

Claims

1. A ground penetrating radar echo signal acquisition and processing device, characterized in that: The device comprises: an echo conditioning circuit, an ADC module, an FPGA module, an STM32 module and a host computer; The echo conditioning circuit is connected to the ADC module; the echo conditioning circuit is connected to the FPGA module; the ADC module is connected to the FPGA module; the FPGA module is connected to the STM32 module; The echo conditioning circuit is used to receive and condition the echo signal during ground penetrating radar detection; The ADC module is used to perform analog-to-digital conversion on the conditioned echo signal to obtain a parallel high-speed data stream; The FPGA module is used to control the analog-to-digital conversion process of the ADC module; The FPGA module is also used to receive the parallel high-speed data stream and perform data processing to obtain the first data stream and send it to the STM32 module; The STM32 module is used to receive and process the first data stream, and issue a reverse control gain instruction to the FPGA module; The FPGA module is also used to control the gain of the echo conditioning circuit through reverse control gain instructions, so as to realize program-controlled amplification or attenuation of the echo signal; The host computer is used to visualize the processed first data stream.

2. A ground penetrating radar echo signal acquisition and processing device as claimed in claim 1, characterized in that: The echo conditioning circuit includes: a radio frequency transformer, a radio frequency amplifier with variable gain, and a fully differential amplifier; The radio frequency transformer, the radio frequency amplifier with variable gain and the fully differential amplifier are connected in sequence; A variable gain RF amplifier is connected to the FPGA module; a fully differential amplifier is connected to the ADC module; The radio frequency transformer is used to transform the received radio frequency signal; The variable gain RF amplifier is used to programmatically amplify or programmatically attenuate the voltage-converted echo signal before inputting it into the fully differential amplifier; The model of the radio frequency transformer is T3002NL; The model of the variable gain RF amplifier is ADL5201ACPZ-R7; The model of the fully differential amplifier is LMH6554.

3. The ground penetrating radar echo signal acquisition and processing device according to claim 1, characterized in that: The ADC module uses two analog-to-digital converters to alternately sample the conditioned echo signal; the model of the analog-to-digital converter is MXT2001; the two analog-to-digital converters are connected in parallel; The ADC module samples the conditioned echo signal through the DES double-edge sampling mode combined with the double edges of the sampling clock provided by the FPGA module to obtain a parallel high-speed data stream; The ADC module also sends parallel high-speed data streams to the FPGA module through LVDS low-voltage differential transmission.

4. The ground penetrating radar echo signal acquisition and processing device according to claim 1, characterized in that: The FPGA chip model of the FPGA module is 10CL055YF484C6G.

5. The ground penetrating radar echo signal acquisition and processing device according to claim 1, characterized in that: The FPGA module includes: a high-speed data receiving unit, a pulse control unit, a data buffer unit, a data superposition unit and a control gain unit; The high-speed data receiving unit is connected to the data buffer unit; the data buffer unit is connected to the data superposition unit; the data superposition unit is connected to the STM32 module; the control gain unit is connected to the STM32 module; the control gain unit is connected to the echo conditioning circuit; The data buffer unit is used to cache the received parallel high-speed data streams, and reassemble the parallel high-speed data streams into serial data, and input them into the data superposition unit for data processing; The data superposition unit is used to perform zero-time correction and superposition noise reduction processing on the spliced ​​high-speed data stream to obtain the first data stream and send it to the STM32 module; The control gain unit is used to adjust the gain of the echo conditioning circuit; The pulse control unit is used to control the signal source and transmit the pulse signal to the underground through the transmitting antenna.

6. A ground penetrating radar echo signal acquisition and processing device as claimed in claim 5, characterized in that: The FPGA module obtains two sampling clocks with a phase difference of 90° through PLL phase-locked loop frequency multiplication and phase shift processing; The high-speed data receiving unit is used to input sampling clocks with the same frequency and different phases into the ADC module; The high-speed data receiving unit is also used to receive parallel high-speed data streams.

7. The ground penetrating radar echo signal acquisition and processing device according to claim 1, characterized in that: The data processing of the FPGA module includes: zero-time correction and superposition noise reduction processing; The specific steps of zero-time correction include: using the relative position between the fixed transmitting antenna and the receiving antenna and taking the arrival time of the direct wave as a reference to correct the time difference; The specific steps of the superposition noise reduction process include: using an average superposition noise reduction algorithm to process the high-speed data stream.

8. A method for collecting and processing ground penetrating radar echo signals, implemented based on a ground penetrating radar echo signal collection and processing device according to any one of claims 1 to 7, characterized in that: The method comprises: S1: Fix the relative positions of the transmitting antenna and the receiving antenna; transmit radar signals through the transmitting antenna; receive echo signals during ground penetrating radar detection through the receiving antenna; S2: Condition the echo signal; S3: by performing parallel high-speed sampling on the conditioned echo signal to obtain a parallel high-speed data stream; S4: performing splicing, zero-time correction, average superposition noise reduction processing and calculation on the parallel high-speed data streams to obtain a first data stream and a gain control signal; Update the conditioning parameters of the echo signal through the gain control signal; S5: Complete the detection of underground cavities by processing and visualizing the first data stream.

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