FPGA-based AD sampling system internal and external phase synchronization method and system, and electronic equipment

Abstract

The invention discloses an FPGA-based AD sampling system internal and external phase synchronization method and system and electronic equipment, and the method comprises the steps: periodically sending test data in an AD sampling system, dynamically adjusting the phase relation of all modules in the AD sampling system until the test data can be stably collected, and completing the phase synchronization in the AD sampling system; any AD sampling system is selected as a master system, the other AD sampling systems are selected as slave systems, the master system periodically sends synchronous pulses to the slave systems, the slave systems collect the synchronous pulses and generate synchronous signals according to pulse widths, and external phase synchronization of the AD sampling systems is completed; and each AD sampling system performs data resetting, reading and writing according to the synchronizing signal, and starts data down-conversion processing. The invention provides an efficient synchronization method which can simultaneously solve the problem of phase synchronization in the modules and between the modules and has adaptive adjustment capability and an exception handling mechanism so as to meet the requirements of a modern complex electronic system on high-precision and high-reliability synchronization.

Description

Technical Field

[0001] The present invention relates to the technical field of signal synchronization, and in particular to an internal and external phase synchronization method, system and electronic equipment of an AD sampling system based on FPGA. Background Art

[0002] As the complexity of modern electronic systems continues to increase, modular design is widely used in various scenarios due to its high scalability and flexibility, especially in the fields of communication, radar, measurement and control, etc. In these complex systems, FPGA-based high-speed AD sampling systems play a key role. However, the resulting phase synchronization problem has become a technical bottleneck that seriously restricts system performance.

[0003] In a system with multiple modules working together, phase synchronization faces two major challenges: intra-module phase synchronization and inter-module phase synchronization. For intra-module phase synchronization, traditional methods mainly rely on manually adjusting the clock delay line or using dedicated phase adjustment devices. These methods are not only complex to operate and difficult to debug, but also difficult to adapt to dynamic changes in system operation. For example, when using high-speed AD sampling chips (such as AD9680, etc.), it is common to estimate the phase relationship between data and clock during the design stage and configure the sampling timing in a fixed manner. However, due to factors such as temperature drift and power supply fluctuations, this static configuration method often leads to sampling window offset, resulting in data sampling errors.

[0004] For phase synchronization between modules, the existing technologies mainly include the following methods: 1. Unified clock distribution scheme: The same clock source is distributed to all modules to achieve synchronization. However, this method will cause phase deviation due to the difference in clock line transmission delay when the physical distance is far or the number of modules is large, and it is susceptible to electromagnetic interference.

[0005] 2. Synchronization solution based on PTP / IEEE1588: Although it has high accuracy, it is complex to implement, has high requirements on network bandwidth, and is difficult to meet microsecond-level synchronization requirements.

[0006] 3. External trigger signal synchronization: Although this method is simple and direct, it lacks a mechanism to judge the signal quality. Problems such as noise and metastable state during signal transmission may lead to synchronization failure or missynchronization.

[0007] In addition, existing synchronization methods generally lack effective exception handling mechanisms. When synchronization fails, the system often falls into a waiting or abnormal state, affecting the reliability and continuous operation of the system. Especially in real-time signal processing systems, synchronization failure may cause the entire system data processing link to crash, resulting in serious consequences. Summary of the invention

[0008] In order to address the deficiencies in the above-mentioned prior art, the present invention aims to provide an efficient synchronization method which can simultaneously solve the intra-module and inter-module phase synchronization problems and has adaptive adjustment capabilities and exception handling mechanisms, so as to meet the requirements of modern complex electronic systems for high-precision and high-reliability synchronization.

[0009] In order to achieve the above-mentioned invention object, the technical solution provided by the present invention includes: The internal and external phase synchronization method of the AD sampling system based on FPGA includes the following steps: S1. Periodically sending test data in the AD sampling system, dynamically adjusting the phase relationship between the modules in the AD sampling system, until the test data can be stably collected, and the phase synchronization within the AD sampling system is completed; S2. Select any AD sampling system as the master system and the other AD sampling systems as slave systems. The master system periodically sends synchronization pulses to the slave systems. Each slave system collects the synchronization pulses and generates a synchronization signal according to the pulse width to complete the phase synchronization outside the AD sampling system. S4. Each AD sampling system performs data reset and reading and writing according to the synchronization signal, and starts data down-conversion processing.

[0010] Preferably, the method for dynamically adjusting the phase relationship of each module in the AD sampling system in step S1 includes: S11, adjusting the sampling timing position through FPGA primitives, collecting test data, and initializing the position adjustment counter and the data stability counter; S12, when the position adjustment count exceeds the preset maximum number threshold, adjust the phase of the clock and data through the phase-locked loop, record the adjustment direction and number, and return to step S11; S13, when the position adjustment count is within the preset maximum number threshold range and the data stability count reaches the preset value, continue to adjust the phase relationship between the clock and the data along the current direction until the sampled data deviates, and record the clock phase adjustment count at this time as the boundary number; S14, determining the optimal phase adjustment range according to the boundary number, and centering the sampling window by reversely adjusting the phase relationship between the clock and the data; S15, locking the obtained optimal phase relationship, and completing the phase synchronization in the AD sampling system.

[0011] Preferably, the method for determining the optimal phase adjustment range according to the boundary number in step S14 includes: When the boundary number is less than the first preset number, the phase relationship between the clock and the data is adjusted in the opposite direction until the sampled data deviates, and a new boundary number is recorded; When the boundary number is greater than or equal to the first preset number, the phase relationship between the clock and the data is adjusted in the reverse direction until the reverse adjustment number is equal to half of the boundary number, so as to realize the centering of the sampling window.

[0012] Preferably, the sum of the high level duration and the low level duration of the synchronization pulse in step S2 is an integer multiple of the data period.

[0013] Preferably, it also includes: Step S3. A timeout mechanism is set based on the duration of the synchronization pulse transmission. When the synchronization is not completed within the timeout period, the AD sampling system enters a normal working mode.

[0014] Preferably, the timeout mechanism in step S3 includes: S31 obtains the high level standard duration H and the low level standard duration I of the synchronization pulse; each slave device first samples and determines the pulse with a high level duration of H+1 and a low level duration of I-1, and sets a first timeout period; S321. If the synchronization pulse is correctly sampled within the first timeout period, the synchronization signal is pulled high; S322. If the sampling is not completed within the first timeout period, the pulse with a high level duration of H and a low level duration of I is sampled and judged, and a second timeout period is set; if the synchronization pulse is correctly sampled within the second timeout period, the synchronization signal is pulled high; S323. If the sampling is not completed within the second timeout period, directly pull up the synchronization signal and make the system enter the normal working mode.

[0015] The present invention also provides an internal and external phase synchronization system of an AD sampling system based on FPGA, and the system is used to implement the internal and external phase synchronization method of the AD sampling system based on FPGA.

[0016] The present invention also provides a storage medium, which includes a stored program, wherein the program executes the above-mentioned FPGA-based AD sampling system internal and external phase synchronization method when running.

[0017] The present invention also provides an electronic device, characterized in that the electronic device is used to run a program, wherein the program executes the above-mentioned FPGA-based AD sampling system internal and external phase synchronization method when running.

[0018] Beneficial Effects The present invention effectively solves the problem of internal and external phase synchronization of AD sampling systems in the prior art, and significantly improves the accuracy and reliability of AD data acquisition. Through the master-slave device architecture and specially designed synchronization pulses, the present invention can accurately identify synchronization signals in the presence of noise and metastable states. A timeout fault-tolerant mechanism is designed to ensure the robustness of the system while ensuring high-precision synchronization. Even if synchronization fails under extreme conditions, the system can automatically switch to a normal working mode, avoiding the system lock problem that may occur in traditional synchronization methods, and greatly improving the availability of the system. Taking full advantage of the programmable characteristics of FPGA, the complex phase synchronization function is integrated into the FPGA for implementation, without the need for additional hardware circuits and dedicated chips, significantly reducing the complexity and cost of system design. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic flow chart of an internal and external phase synchronization method of an AD sampling system based on FPGA provided in a preferred embodiment of the present invention; Figure 2 A schematic diagram of four possible situations that may occur when a 400M clock is used to latch a 100M clock, taking the adjustment of the clock phase by a phase-locked loop circuit as an example, provided in a preferred embodiment of the present invention; Figure 3 A schematic diagram of two situations in which a synchronization pulse generates a sudden change during the transmission of a synchronization signal provided in a preferred embodiment of the present invention; Figure 4 A schematic flow chart of an internal and external phase synchronization method of an AD sampling system based on FPGA provided in another preferred embodiment of the present invention; Figure 5 A schematic diagram of a timeout mechanism flow chart provided in another preferred embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention is further described below in conjunction with the accompanying drawings. In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present invention.

[0021] like Figure 1 As shown, this embodiment provides an internal and external phase synchronization method of an AD sampling system based on FPGA, comprising the steps of: S1. Periodically send test data in the AD sampling system, and dynamically adjust the phase relationship of each module in the AD sampling system until the test data can be stably collected and the phase synchronization in the AD sampling system is completed.

[0022] AD sampling system (Analog-to-Digital Sampling System) refers to an electronic system that converts continuous analog signals into discrete digital signals, and its core component is an AD converter (Analog-to-Digital Converter). In the present invention, AD sampling system specifically refers to a data acquisition and processing unit composed of a high-speed AD sampling chip (such as AD9680, etc.) and an FPGA, which is responsible for accurately converting external analog signals into digital signals for subsequent processing. Such systems usually operate at sampling rates up to hundreds of MHz or even GHz, and have extremely high requirements for sampling timing accuracy, and are widely used in radar signal processing, broadband communication, high-precision measurement and other fields. The performance of the AD sampling system directly affects the accuracy and reliability of the entire signal processing link, and the phase synchronization problem is one of the key factors affecting its performance.

[0023] FPGA (Field-Programmable Gate Array) is an integrated circuit whose logic functions can be configured by the user through programming after manufacturing. In the present invention, FPGA is the core processing platform for realizing the entire synchronization method. It is not only responsible for the collection and processing of AD data, but also undertakes key functions such as dynamic adjustment of phase relationship, generation and detection of synchronization pulses. The advantages of FPGA lie in its high parallelism and reconfigurability, which can realize precise timing control at the nanosecond level, and can modify the functional logic at any time according to actual needs. The present invention makes full use of the primitive resources of FPGA (such as IDELAY, ODELAY, BUFGCE, etc.) and hardware phase-locked loop (PLL / MMCM) to realize high-precision phase adjustment. Compared with traditional ASIC or microprocessor, FPGA has significant advantages in processing high-speed data streams and realizing precise timing control, and is an ideal implementation platform for the technical solution of the present invention.

[0024] Test data refers to the known data pattern periodically sent by the AD sampling chip in a specific test mode during the phase synchronization process in the AD sampling system. These test data are usually fixed bit patterns (such as "AABB", which is represented by "1010101010111011" in binary). Its characteristics are that the pattern is determined and repeated periodically, which is convenient for FPGA performs pattern matching and phase relationship verification. By comparing the actual sampled data with the expected test data, the system can determine whether the current sampling timing is accurate.

[0025] Those skilled in the art should know that the dynamic adjustment of the phase relationship refers to the process of finding the best sampling point by real-time monitoring and adjusting the phase difference between the clock and data signals. Traditional phase adjustment methods commonly used in this field (such as phase-locked loop circuit adjustment of clock phase, time synchronization protocol, satellite signal as a common time reference, etc.) are mostly static configurations, which are difficult to deal with phase drift caused by factors such as temperature changes and power supply fluctuations, and require dedicated hardware support and complex software stacks, which consumes a lot of resources. Taking the phase-locked loop circuit adjustment of the clock phase as an example, Figure 2 As shown, when a 400M clock is used to latch a 100M clock, four situations may occur as shown in the figure, among which the data phase difference between the first and fourth situations is 90 degrees, so in the actual process, the phase of the data between different channels may be unstable.

[0026] To this end, in some preferred embodiments, a dynamic phase relationship adjustment method based on FPGA primitives and a phase-locked loop is provided, which specifically includes: S11, adjusting the sampling timing position through FPGA primitives, collecting test data, and initializing the position adjustment counter and data stability counter. The position adjustment count is used to determine whether the phase relationship between the clock and the data is correct.

[0027] Among them, FPGA primitives refer to the basic functional units or hardware modules built into the FPGA chip and cannot be decomposed. These components are directly implemented by FPGA manufacturers at the silicon level and have optimal performance and reliability. This embodiment can adjust the delay based on hardware primitives without restarting or reconfiguring the FPGA, and the adjustment accuracy is high, and the adjustment process has little impact on other functions of the system.

[0028] S12. When the position adjustment count exceeds a preset maximum number threshold, the phase of the clock and data is adjusted through a phase-locked loop, the adjustment direction and number are recorded, and the process returns to step S11.

[0029] It should be understood that when the value of the position adjustment counter exceeds the preset maximum threshold (typical value is 30-40 steps), it indicates that a stable sampling window cannot be found under the current clock phase. At this time, the system will adjust the phase of the sampling clock through the built-in phase-locked loop (PLL) of the FPGA. The phase step of each adjustment is usually 45 degrees or less, and the right adjustment is recorded as R and the left adjustment is recorded as L. After completing the PLL phase adjustment, return to step S11 for sampling. The preset maximum number threshold is set according to the sampling position step size and the test data bit width each time.

[0030] S13. When the position adjustment count is within the preset maximum number threshold and the data stability count reaches the preset value, continue to adjust the phase relationship between the clock and the data in the current direction until the sampled data deviates, and record the clock phase adjustment count at this time as the boundary number. The correctness of the sampled data is checked after each adjustment until the continuously collected data begins to have errors, indicating that the boundary of the stable sampling window has been reached. At this time, the number of adjustment steps required from the stable point to the boundary is recorded, and this value is called the "boundary number". This boundary number is a key parameter for determining the optimal sampling point and an important indicator for evaluating the system timing margin.

[0031] S14, determining an optimal phase adjustment range according to the boundary number, and centering the sampling window by reversely adjusting the phase relationship between the clock and the data.

[0032] It should be understood that the determination of the optimal phase adjustment range is the core optimization step to achieve the optimal sampling point positioning. The specific adjustment method can be to set a fixed clock delay according to the recommended value in the hardware manual, or to find the working range by traversing all possible clock phases. In some preferred embodiments, it is considered to make full use of the characteristics of the programmable delay unit in the FPGA, control the hardware resources through software algorithms, and accurately position the sampling point in the center of the window without adding external components, which can maximize the timing margin, have strong anti-interference ability and low error rate. Specifically including: When the boundary times are less than the first preset times, the phase relationship between the clock and the data is adjusted in the reverse direction until the sampled data deviates, and the new boundary times are recorded. This step is mainly aimed at the complex situation where the initial sampling point may be close to the edge of the sampling window. When the boundary times (such as 2-3 steps) obtained by the initial detection are less than the first preset times (usually set to 5-10 steps), it means that the current sampling point is close to one side of the boundary. At this time, centering adjustment based only on the unilateral boundary information may cause deviations, and then the dual boundary detection mechanism is started. When the sampled data begins to be wrong during the reverse adjustment process, the system reaches the other side of the sampling window, and the number of steps of this reverse adjustment is recorded as the new boundary times. Compared with the unidirectional detection method, fixed offset method or prediction method based on statistical model in the prior art, this bidirectional detection strategy has higher accuracy and adaptability, and is particularly suitable for complex systems with impaired signal integrity or asynchronous timing relationships.

[0033] When the number of boundary times is greater than or equal to the first preset number, the phase relationship between the clock and the data is adjusted in the reverse direction until the number of reverse adjustments is equal to half of the number of boundary times, so as to realize the centering of the sampling window. When the number of boundary times exceeds the preset threshold (typically 5-10 steps), it indicates that the current sampling point is already in a good position in the sampling window, and there is a considerable margin from the known boundary. At this time, a simplified centering strategy is adopted: the system directly calculates half of the number of boundary times (usually the integer is lower for non-integer results), and then reversely adjusts this number of steps. This method is based on a reasonable assumption: when the distance from the initial sampling point to one side of the boundary is large enough, the sampling window is likely to be approximately symmetrical, and the sampling point can be brought closer to the center of the window by reversely adjusting half of the number of boundary times. For example, if the number of boundary times is 8, the system will reversely adjust 4 steps to move the sampling point to a position farther from the boundary. This fast path strategy has the advantages of simple calculation and efficient implementation, avoids unnecessary complete bidirectional scanning, and reduces system initialization time. From the perspective of hardware resource utilization, this method significantly reduces the complexity of the state machine and FPGA resource occupation, and is particularly suitable for large-scale data acquisition systems that require multi-channel parallel optimization.

[0034] S15, locking the obtained optimal phase relationship, and completing the phase synchronization in the AD sampling system.

[0035] S2. Select any AD sampling system as the master system and the other AD sampling systems as slave systems. The master system periodically sends synchronization pulses to the slave systems. Each slave system collects the synchronization pulses and generates a synchronization signal according to the pulse width to complete the external phase synchronization of the AD sampling system.

[0036] External phase synchronization of the AD sampling system refers to establishing and maintaining a unified timing relationship between multiple physically independent AD sampling systems, so that their sampling clocks maintain precise consistency or fixed deviation in phase, which is essentially different from the phase synchronization between FPGA-AD channels within a single system (internal phase synchronization). The master-slave architecture of this step can achieve a high sampling synchronization accuracy between systems and provide time consistency guarantee for subsequent multi-source data fusion. From the perspective of system integration, this master-slave synchronization architecture supports flexible expansion and reconstruction of the system. The newly added sampling system only needs to be connected to the synchronization pulse distribution network to be quickly incorporated into the overall system, which has significant engineering practical value. In some preferred embodiments, in order to reduce path delay, when selecting the master system, it should be ensured that the path to the slave system is basically consistent.

[0037] Those skilled in the art can know that the synchronization pulse refers to a special timing signal generated by the main system FPGA through a dedicated synchronization output pin, which has precise time characteristics and level change rules. Unlike ordinary clock signals, the synchronization pulse contains synchronization instruction information encoded in its pulse width. The implementation of generating a synchronization signal according to the pulse width involves precise time measurement and decoding logic inside the slave system. The slave system measures the duration of the received synchronization pulse through a high-precision counter or time-to-digital converter (TDC) technology, and compares the measurement result with a preset threshold to identify the pulse type. The specific implementation method can be specifically set by those skilled in the art based on the prior art, and the present invention does not make further limitations.

[0038] In the application scenario of the multi-sampling system, the burrs generated by the noise cause misjudgment of the synchronization pulse, and in the periodic data sampling, it is ensured that the sampling of the synchronization pulse at different times does not affect the phase relationship between the modules. In some preferred embodiments, this problem is solved by setting the sum of the high-level duration and the low-level duration of the synchronization pulse to an integer multiple of the data period, so that each slave system can detect and respond to the synchronization event at the same exact relative time, ensuring that the edge of the synchronization pulse always appears at a specific data sampling point, eliminating timing uncertainty. The specific implementation method can be realized by a high-precision digital timing circuit in the master system. The data period refers to the basic time unit required for the AD sampling system to perform a complete data sampling, that is, the period of the sampling clock.

[0039] S4. Each AD sampling system performs data reset and reading and writing according to the synchronization signal, and starts data down-conversion processing.

[0040] Digital Down-Conversion (DDC) is a core signal processing technology in RF signal acquisition systems, used to digitally convert high-frequency RF signals (such as in the IF or RF band) into low-frequency signals close to baseband. The above steps together constitute a complete processing pipeline: data reset establishes the processing starting point, read and write operations control data acquisition, and down-conversion processing is the first-level algorithm conversion of acquired data. The synchronization signal plays the role of general commander in this pipeline, not only accurately defining the starting point of the data flow, but also ensuring that the parameters of the down-conversion processing (such as the initial phase of the NCO) remain consistent across multiple systems.

[0041] Those skilled in the art will know that in complex electromagnetic environments or long-distance transmission scenarios, the synchronization signal may be lost or delayed due to interference, attenuation or equipment failure, and the system waiting for synchronization may be always in a suspended state, causing the entire data acquisition link to be paralyzed. From the perspective of resource utilization efficiency, AD sampling systems are usually equipped with cache and processing resources. Excessive synchronization waiting will cause these valuable resources to be idle and wasted, affecting the overall performance of the system. Therefore, in some preferred embodiments, consider adding a timeout mechanism after completing the synchronization inside and outside the system, such as Figure 4 As shown, specifically including: Step S3. A timeout mechanism is set based on the duration of the synchronization pulse transmission. When the synchronization is not completed within the timeout period, the AD sampling system enters a normal working mode.

[0042] Those skilled in the art can know that the timeout mechanism commonly used in this field is mainly a fixed time timeout, that is, a fixed time threshold (such as 100ms) is simply set. If the synchronization is not completed within this time, the timeout processing is triggered. This method is simple to implement but lacks flexibility and is difficult to adapt to complex and changeable working environments. In this embodiment, the timeout threshold is dynamically determined based on the characteristics of the synchronization pulse itself (such as pulse period, expected number of pulses), so that the timeout determination is closely related to the actual synchronization process. When the synchronization is not completed by timeout, the AD sampling system enters the fault-tolerant model. At this time, each AD sampling system works independently, does not rely on the central synchronization signal, and collects data according to its own clock. Although the precise time alignment of data between multiple systems cannot be guaranteed in this state, the basic data collection function is ensured to be uninterrupted. For some applications (such as scenarios that only focus on signal amplitude rather than phase), the data in this degraded mode is still of considerable value. In engineering practice, a system warning or error log should also be generated after the timeout is triggered to record detailed information of the timeout event (such as the number of synchronization pulses received, signal quality indicators, etc.), providing a basis for subsequent fault analysis and system optimization. In other preferred embodiments, a mechanism may be provided to periodically attempt to re-establish synchronization in the normal working mode, so as to automatically switch back to the high-precision synchronization working mode after the synchronization condition is restored, thereby maximizing the system availability and data quality.

[0043] Those skilled in the art will know that during the transmission of the synchronization signal, due to link instability or contention risk, the synchronization pulse will mutate, resulting in the following situation: Figure 3There are two situations shown. In the first situation, in the process of data changing from 0 to 1, due to the metastable state, 1 is judged as 0; in the process of data changing from 1 to 0, 0 is judged as 1; in this case, if the slave devices all judge H as a high level and I as a low level, it may cause the data phase between modules to differ by 90 degrees. In the second situation, in the process of data changing from 0 to 1, 1 can be correctly judged; in the process of data changing from 1 to 0, 0 is judged as 1; in this case, if the slave devices all judge H+1 as a high level and I-1 as a low level, there will be no deviation in the data phase between modules. At this time, the external phase synchronization process of the AD sampling system considering the timeout mechanism is as follows: Figure 5 As shown, including: S31. Obtain the high level standard duration H and low level standard duration I of the synchronization pulse; make each slave device first sample and judge the pulse with high level duration H+1 and low level duration I-1, and set the first timeout period. The setting of the first timeout period represents the expected waiting time for high-quality synchronization. This time length is usually determined according to the maximum tolerable delay of the system and the actual application scenario.

[0044] S321. If the synchronization pulse is correctly sampled within the first timeout period, the synchronization signal is pulled high. When the system successfully samples the synchronization pulse that meets the H+1 / I-1 standard within the first timeout period, the synchronization signal is immediately pulled high, indicating that the optimal synchronization state has been reached. In this state, the data phase difference between different modules will be minimized. This step is the first level judgment.

[0045] S322. If the sampling is not completed within the first timeout period, the pulse with a high level duration of H and a low level duration of I is sampled and judged, and a second timeout period is set; if the synchronization pulse is correctly sampled within the second timeout period, the synchronization signal is pulled high. When the first level judgment times out, the second level judgment is transferred to, which reflects the design concept of flexibility, that is, when the optimal state cannot be achieved, the system is still ensured to operate with acceptable performance as much as possible. At this time, there is a certain phase difference between the AD sampling systems, but in an environment with relatively poor signal quality, this compromise is necessary. The second timeout period is usually set shorter than the first timeout period, because the system has been waiting for a considerable time at this time, and a quick decision is needed to avoid delaying data acquisition. After successfully sampling a synchronization pulse that meets the standard at this stage, the system also pulls up the synchronization signal, but records a mark internally, indicating that the current synchronization quality is at the "suboptimal" level.

[0046] S323. If the sampling is not completed within the second timeout period, the synchronization signal is directly pulled high and the system enters the normal working mode. This step represents the ultimate safety guarantee of the timeout mechanism. When both levels of judgment have timed out, the system will no longer wait for the synchronization pulse, but will directly pull up the synchronization signal and enter the normal working mode. This design ensures that under the worst conditions (such as the complete loss of the synchronization signal), the system can still operate autonomously and maintain basic data acquisition functions. In this state, although the data between different modules may lack precise phase alignment, these data are still of practical value for some application scenarios with higher tolerance (such as amplitude measurement). More importantly, this automatic degradation mechanism avoids the risk of the system shutting down completely due to waiting for synchronization, significantly improving the reliability and continuous operation time of the system.

[0047] Compared with the traditional single standard synchronization judgment, the dual-stage timeout judgment mechanism of the present invention can maximize the phase consistency between modules while ensuring the reliability of the system. This design is particularly suitable for distributed multi-channel acquisition systems, high-speed coherent radar systems, and precision scientific instruments. It can significantly improve the synchronization accuracy and stability of the system without increasing the complexity of the hardware. At the same time, the adaptive characteristics of this mechanism also enable the system to intelligently adjust the working mode in transmission environments of different qualities, providing great flexibility and reliability for practical engineering applications.

[0048] The above shows and describes the basic principles, main features and advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. An internal and external phase synchronization method of an AD sampling system based on FPGA, characterized in that: Includes steps: S1. Periodically sending test data in the AD sampling system, dynamically adjusting the phase relationship between the modules in the AD sampling system, until the test data can be stably collected, and the phase synchronization within the AD sampling system is completed; S2. Select any AD sampling system as the master system and the other AD sampling systems as slave systems. The master system periodically sends synchronization pulses to the slave systems. Each slave system collects the synchronization pulses and generates a synchronization signal according to the pulse width to complete the phase synchronization outside the AD sampling system. S4. Each AD sampling system performs data reset and reading and writing according to the synchronization signal, and starts data down-conversion processing.

2. The internal and external phase synchronization method of the AD sampling system based on FPGA as claimed in claim 1, characterized in that: The method for dynamically adjusting the phase relationship of each module in the AD sampling system in step S1 includes: S11, adjusting the sampling timing position through FPGA primitives, collecting test data, and initializing the position adjustment counter, data stability counter and clock phase adjustment counter; S12, when the position adjustment count exceeds the preset maximum number threshold, adjust the phase of the clock and data through the phase-locked loop, record the adjustment direction and number, and return to step S11; S13, when the position adjustment count is within the preset maximum number threshold range and the data stability count reaches the preset value, continue to adjust the phase relationship between the clock and the data along the current direction until the sampled data deviates, and record the clock phase adjustment count at this time as the boundary number; S14, determining the optimal phase adjustment range according to the boundary number, and centering the sampling window by reversely adjusting the phase relationship between the clock and the data; S15, locking the obtained optimal phase relationship, and completing the phase synchronization in the AD sampling system.

3. The internal and external phase synchronization method of the AD sampling system based on FPGA as claimed in claim 2, characterized in that: The method for determining the optimal phase adjustment range according to the boundary times in step S14 includes: When the boundary number is less than the first preset number, the phase relationship between the clock and the data is adjusted in the opposite direction until the sampled data deviates, and a new boundary number is recorded; When the boundary number is greater than or equal to the first preset number, the phase relationship between the clock and the data is adjusted in the reverse direction until the reverse adjustment number is equal to half of the boundary number, so as to realize the centering of the sampling window.

4. The internal and external phase synchronization method of the AD sampling system based on FPGA as claimed in claim 1, characterized in that: The sum of the high level duration and the low level duration of the synchronization pulse in step S2 is an integer multiple of the data cycle.

5. The internal and external phase synchronization method of the AD sampling system based on FPGA as claimed in claim 1 or 4, characterized in that: Also includes: Step S3: A timeout mechanism is set based on the duration of the synchronization pulse transmission. When the synchronization is not completed within the timeout period, the AD sampling system enters a normal working mode.

6. The internal and external phase synchronization method of the AD sampling system based on FPGA as claimed in claim 5, characterized in that: The timeout mechanism in step S3 includes: S31 obtains the high level standard duration H and the low level standard duration I of the synchronization pulse; each slave device first samples and determines the pulse with a high level duration of H+1 and a low level duration of I-1, and sets a first timeout period; S321. If the synchronization pulse is correctly sampled within the first timeout period, the synchronization signal is pulled high; S322. If the sampling is not completed within the first timeout period, the pulse with a high level duration of H and a low level duration of I is sampled and judged, and a second timeout period is set; if the synchronization pulse is correctly sampled within the second timeout period, the synchronization signal is pulled high; S323. If the sampling is not completed within the second timeout period, directly pull up the synchronization signal and make the system enter the normal working mode.

7. The internal and external phase synchronization system of the AD sampling system based on FPGA is characterized by: The system is used to implement the internal and external phase synchronization method of the AD sampling system based on FPGA according to any one of claims 1 to 6.

8. A storage medium, characterized in that: The storage medium includes a stored program, wherein the program, when running, executes the internal and external phase synchronization method of the AD sampling system based on FPGA according to any one of claims 1 to 6.

9. An electronic device, characterized in that: The electronic device is used to run a program, wherein the program, when running, executes the internal and external phase synchronization method of an AD sampling system based on FPGA according to any one of claims 1 to 6.

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