FPGA-Based Internal and External Phase Synchronization Method, System and Electronic Device for AD Sampling System

Abstract

The present invention discloses a method, a system and an electronic device for internal and external phase synchronization of an AD sampling system based on FPGA. The method includes: periodically sending test data within the AD sampling system, dynamically adjusting the phase relationship of each module within the AD sampling system until the test data can be stably acquired, thereby completing the internal phase synchronization of the AD sampling system; selecting any one of the AD sampling systems as the master system and the remaining AD sampling systems as slave systems, and the master system periodically sends synchronization pulses to the slave systems. Each slave system acquires the synchronization pulses and generates synchronization signals according to the pulse width, thereby completing the external phase synchronization of the AD sampling system; each AD sampling system performs data reset and read / write according to the synchronization signals and starts data down-conversion processing. The present invention provides an efficient synchronization method that can simultaneously solve the phase synchronization problems within and between modules, has an adaptive adjustment ability and an exception handling mechanism, so as to meet the requirements of modern complex electronic systems for high-precision and high-reliability synchronization.

Description

Technical Field

[0001] The present invention relates to the technical field of signal synchronization, and particularly to an internal and external phase synchronization method, system, and electronic device for an AD sampling system based on FPGA. Background Art

[0002] With the continuous improvement of the complexity of modern electronic systems, modular design has been widely applied to various scenarios due to its high scalability and flexibility, especially in the fields of communication, radar, measurement and control, etc. In these complex systems, a high-speed AD sampling system based on FPGA plays a key role. However, the subsequent phase synchronization problem has become a technical bottleneck severely restricting the system performance.

[0003] In a system where multiple modules work together, phase synchronization mainly faces two major challenges: in-module phase synchronization and inter-module phase synchronization. For in-module phase synchronization, traditional methods mainly rely on manually adjusting the clock delay line or using dedicated phase adjustment devices. These methods are not only complex to operate and difficult to debug, but also difficult to adapt to the dynamic changes during system operation. For example, when using a high-speed AD sampling chip (such as AD9680, etc.), a common practice is to estimate the phase relationship between data and clock during the design stage and fix the configuration of the sampling timing. However, due to factors such as temperature drift and power supply fluctuations, this static configuration method often leads to the offset of the sampling window, resulting in data sampling errors.

[0004] For inter-module phase synchronization, the existing technologies mainly include the following methods:

[0005] 1. Unified clock distribution scheme: Synchronization is achieved by allocating the same clock source to all modules. However, in the case of a long physical distance or a large number of modules, phase deviation will occur due to the difference in clock line transmission delay, and it is easily affected by electromagnetic interference.

[0006] 2. Synchronization scheme based on PTP / IEEE1588: Although it has high precision, it is complex to implement, has high requirements for network bandwidth, and is difficult to meet the microsecond-level synchronization requirements.

[0007] 3. External trigger signal synchronization: This method is simple and direct, but it lacks a mechanism for judging the signal quality. Problems such as noise and metastability during signal transmission may lead to synchronization failure or mis-synchronization.

[0008] In addition, the existing synchronization methods generally lack an effective exception handling mechanism. When synchronization fails, the system often falls into a waiting or abnormal state, affecting the reliability and continuous operation ability of the system. Especially in a real-time signal processing system, synchronization failure may lead to the collapse of the entire system data processing link, causing serious consequences. Summary of the Invention

[0009] To address the deficiencies of the above-mentioned existing technologies, the present invention aims to provide an efficient synchronization method that can simultaneously solve the phase synchronization problems within and between modules, has an adaptive adjustment ability and an exception handling mechanism, in order to meet the requirements of modern complex electronic systems for high-precision and high-reliability synchronization.

[0010] To achieve the above-mentioned invention objective, the technical solution provided by the present invention includes:

[0011] A method for internal and external phase synchronization of an AD sampling system based on FPGA, comprising the steps of:

[0012] S1. Periodically send test data within the AD sampling system, dynamically adjust the phase relationship of each module within the AD sampling system until test data can be stably collected, and complete the internal phase synchronization of the AD sampling system;

[0013] S2. Select any one AD sampling system as the master system, and the remaining AD sampling systems as slave systems. The master system periodically sends synchronization pulses to the slave systems, and each slave system collects the synchronization pulses and generates synchronization signals according to the pulse width to complete the external phase synchronization of the AD sampling system;

[0014] S4. Each AD sampling system performs data reset and read / write according to the synchronization signal, and starts data down-conversion processing.

[0015] Preferably, the method for dynamically adjusting the phase relationship of each module within the AD sampling system in step S1 includes:

[0016] S11. Adjust the sampling timing position through FPGA primitives, collect test data, and initialize the position adjustment counter and the data stability counter;

[0017] S12. When the position adjustment count exceeds the preset maximum number threshold, adjust the phase of the clock and data through a phase-locked loop, record the adjustment direction and number of times, and return to step S11;

[0018] S13. When the position adjustment count is within the preset maximum number threshold range and the data stability count reaches the preset value, continue to adjust the phase relationship of the clock and data in the current direction until the sampled data deviates, and record the clock phase adjustment count at this time as the boundary number;

[0019] S14. Determine the optimal phase adjustment range according to the boundary number, and achieve the centering of the sampling window by reversely adjusting the phase relationship of the clock and data;

[0020] S15. Lock the obtained optimal phase relationship to complete the internal phase synchronization of the AD sampling system.

[0021] Preferably, the method for determining the optimal phase adjustment range according to the number of boundaries in step S14 includes:

[0022] When the number of boundaries is less than the first preset number, adjust the phase relationship between the clock and the data in the reverse direction until the sampled data deviates, and record the new number of boundaries;

[0023] When the number of boundaries is greater than or equal to the first preset number, adjust the phase relationship between the clock and the data in the reverse direction until the number of reverse adjustments is equal to half of the number of boundaries, so as to center the sampling window.

[0024] Preferably, in step S2, the sum of the high-level duration and the low-level duration of the synchronization pulse is an integer multiple of the data period.

[0025] Preferably, it further includes:

[0026] Step S3. Set a timeout mechanism based on the transmission duration of the synchronization pulse. When the synchronization is not completed within the timeout, the AD sampling system enters the normal working mode.

[0027] Preferably, the timeout mechanism in step S3 includes:

[0028] S31. Obtain the high-level standard duration H and the low-level standard duration I of the synchronization pulse; make each slave device first sample and judge the pulse with a high-level duration of H + 1 and a low-level duration of I - 1, and set the first timeout period;

[0029] S321. If the synchronization pulse is correctly sampled within the first timeout period, pull up the synchronization signal;

[0030] S322. If the sampling is not completed within the first timeout period, sample and judge the pulse with a high-level duration of H and a low-level duration of I, and set the second timeout period; if the synchronization pulse is correctly sampled within the second timeout period, pull up the synchronization signal;

[0031] S323. If the sampling is not completed within the second timeout period, directly pull up the synchronization signal and make the system enter the normal working mode.

[0032] The present invention also provides an internal and external phase synchronization system for an AD sampling system based on FPGA, and the system is used to implement the above-mentioned internal and external phase synchronization method for an AD sampling system based on FPGA.

[0033] The present invention also provides a storage medium, and the storage medium includes a stored program, wherein the program executes the above-mentioned internal and external phase synchronization method for an AD sampling system based on FPGA when running.

[0034] The present invention also provides an electronic device, characterized in that the electronic device is used to run a program, and when the program runs, it executes the above-mentioned method for internal and external phase synchronization of the AD sampling system based on FPGA.

[0035] Beneficial effects

[0036] The present invention effectively solves the problem of internal and external phase synchronization of the AD sampling system in the prior art, and significantly improves the accuracy and reliability of AD data acquisition. Through the master-slave device architecture and specially designed synchronization pulses, the present invention can accurately identify synchronization signals in the presence of noise and metastability. A timeout fault tolerance mechanism is designed to ensure the robustness of the system while guaranteeing high-precision synchronization. Even if the synchronization fails under extreme conditions, the system can automatically switch to the normal working mode, avoiding the system lock-up problem that may occur in traditional synchronization methods, and greatly improving the usability of the system. By making full use of the programmable characteristics of FPGA, the complex phase synchronization function is integrated inside the FPGA without the need for additional hardware circuits and dedicated chips, significantly reducing the system design complexity and cost. Description of the drawings

[0037] Figure 1 It is a schematic flow chart of the method for internal and external phase synchronization of the AD sampling system based on FPGA provided in a preferred embodiment of the present invention;

[0038] Figure 2 It is a schematic diagram of four possible situations that may occur when using a 400M clock to latch a 100M clock by taking the phase-locked loop circuit to adjust the clock phase as an example in a preferred embodiment of the present invention;

[0039] Figure 3 It is a schematic diagram of two situations where the synchronization pulse mutates during the transmission of the synchronization signal provided in a preferred embodiment of the present invention;

[0040] Figure 4 It is a schematic flow chart of the method for internal and external phase synchronization of the AD sampling system based on FPGA provided in another preferred embodiment of the present invention;

[0041] Figure 5 It is a schematic flow chart of the timeout mechanism provided in another preferred embodiment of the present invention. Detailed implementation manners

[0042] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described below with reference to the accompanying drawings. In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0043] As Figure 1 shown, this embodiment provides a method for internal and external phase synchronization of an AD sampling system based on FPGA, including the steps:

[0044] S1. Periodically send test data within the AD sampling system, and dynamically adjust the phase relationships of the various modules within the AD sampling system until the test data can be stably acquired, thereby completing the internal phase synchronization of the AD sampling system.

[0045] An AD sampling system (Analog-to-Digital Sampling System) refers to an electronic system that converts continuous analog signals into discrete digital signals, and its core component is an AD converter (Analog-to-Digital Converter). In the present invention, the AD sampling system specifically refers to a data acquisition and processing unit composed of a high-speed AD sampling chip (such as AD9680, etc.) and an FPGA, which is responsible for accurately converting external analog signals into digital signals for subsequent processing. Such systems usually operate at sampling rates of up to several hundred MHz or even GHz, and have extremely high requirements for the accuracy of sampling timing. They are widely used in fields such as radar signal processing, broadband communication, and high-precision measurement. The performance of the AD sampling system directly affects the accuracy and reliability of the entire signal processing link, and the phase synchronization problem is one of the key factors affecting its performance.

[0046] FPGA (Field-Programmable Gate Array) is an integrated circuit whose logic functions can be configured by users through programming after manufacturing. In the present invention, the FPGA is the core processing platform for implementing the entire synchronization method, responsible not only for the acquisition and processing of AD data, but also undertaking key functions such as dynamic adjustment of phase relationships, generation and detection of synchronization pulses. The advantages of FPGA lie in its high parallelism and reconfigurability, enabling precise timing control at the nanosecond level and allowing the modification of functional logic according to actual requirements at any time. The present invention makes full use of the primitive resources of FPGA (such as IDELAY, ODELAY, BUFGCE, etc.) and hardware phase-locked loops (PLL / MMCM) to achieve high-precision phase adjustment. Compared with traditional ASICs or microprocessors, FPGA has significant advantages in processing high-speed data streams and achieving precise timing control, and is an ideal implementation platform for the technical solution of the present invention.

[0047] Test data refers to the known data patterns periodically sent by the AD sampling chip in a specific test mode during the phase synchronization process in the AD sampling system. These test data are usually fixed bit patterns (such as "AABB", which is "1010101010111011" in binary representation). Its characteristics are that the pattern is determined and periodically repeated, facilitating

[0048] the FPGA to perform pattern matching and phase relationship verification. By comparing whether the actually sampled data is consistent with the expected test data, the system can determine whether the current sampling timing is accurate.

[0049] Those skilled in the art should be aware that the dynamic adjustment of the phase relationship refers to the process of finding the optimal sampling point by real-time monitoring and adjusting the phase difference between the clock and data signals. The traditional phase adjustment methods commonly used in this field (such as adjusting the clock phase by a phase-locked loop circuit, time synchronization protocol, satellite signals as a common time reference, etc.) are mostly static configurations, difficult to cope with phase drifts caused by factors such as temperature changes and power fluctuations, and require dedicated hardware support and complex software stacks, with large resource occupancy. Taking the adjustment of the clock phase by a phase-locked loop circuit as an example, as Figure 2 shown, when using a 400M clock to latch a 100M clock, there may be 4 situations as shown in the figure. The phase difference of the data in the first situation and the fourth situation is 90 degrees. Therefore, in the actual process, the phase of the data between different channels may be unstable.

[0050] Therefore, in some preferred embodiments, a dynamic phase relationship adjustment method based on FPGA primitives and phase-locked loops is provided, specifically including:

[0051] S11. Adjust the sampling timing position through FPGA primitives, collect test data, and initialize the position adjustment counter and the data stability counter. Among them, the position adjustment count is used to determine whether the phase relationship between the clock and the data is correct.

[0052] Among them, the FPGA primitive refers to the built-in, indecomposable basic functional unit or hardware module of the FPGA chip. These components are directly implemented by the FPGA manufacturer at the silicon wafer level and have optimal performance and reliability. In this embodiment, through the delay adjustment based on hardware primitives, it is possible to adjust without restarting or reconfiguring the FPGA, with high adjustment accuracy and little impact on other functions of the system during the adjustment process.

[0053] S12. When the position adjustment count exceeds the preset maximum number threshold, adjust the phase of the clock and the data through the phase-locked loop, record the adjustment direction and the number of times, and return to step S11.

[0054] It should be understood that when the value of the position adjustment counter exceeds the preset maximum threshold (the typical value is 30 - 40 steps), it indicates that a stable sampling window cannot be found at the current clock phase. At this time, the system will adjust the phase of the sampling clock through the phase-locked loop (PLL) built in the FPGA. The phase step of each adjustment is usually 45 degrees or less. Adjusting to the right is recorded as R, and adjusting to the left is recorded as L. After completing the PLL phase adjustment, return to step S11 for sampling. The preset maximum number threshold is set according to the step size of each sampling position adjustment and the bit width of the test data.

[0055] S13. When the position adjustment count is within the preset maximum number threshold and the data stability count reaches the preset value, continue to adjust the phase relationship between the clock and the data in the current direction until the sampled data deviates. Record the clock phase adjustment count at this time as the boundary number. The correctness of the sampled data is checked after each adjustment until the continuously collected data starts to show errors, indicating that the boundary of the stable sampling window has been reached. At this time, record the number of adjustment steps required from the stable point to the boundary. This value is called the "boundary number". This boundary number is the key parameter for determining the optimal sampling point and an important indicator for evaluating the system timing margin.

[0056] S14. Determine the optimal phase adjustment range according to the boundary number, and center the sampling window by reversely adjusting the phase relationship between the clock and the data.

[0057] It should be understood that the determination of the optimal phase adjustment range is the core optimization step for achieving the optimal sampling point positioning. The specific adjustment method can be to set a fixed clock delay according to the recommended value in the hardware manual, or to find the working range by traversing all possible clock phases. In some preferred embodiments, considering making full use of the characteristics of the programmable delay units in the FPGA, the sampling point is accurately positioned at the center of the window by controlling the hardware resources through a software algorithm without adding external components, which can maximize the timing margin, have strong anti-interference ability and low error rate. Specifically, it includes:

[0058] When the number of boundary steps is less than the first preset number of steps, adjust the phase relationship between the clock and the data in the reverse direction until the sampled data deviates, and record the new number of boundary steps. This step mainly aims at the complex situation where the initial sampling point may be close to the edge of the sampling window. When the number of boundary steps obtained from the initial detection (such as in steps 2 - 3) is less than the first preset number of steps (usually set to 5 - 10 steps), it indicates that the current sampling point is close to one side boundary. At this time, relying only on the unilateral boundary information for centering adjustment may lead to deviation, and then the double-boundary detection mechanism is activated. When the sampled data starts to show errors during the reverse adjustment process, the system reaches the other side boundary of the sampling window, and record the number of steps of this reverse adjustment as the new number of boundary steps. Compared with the unidirectional detection method, fixed offset method or prediction method based on statistical models in the prior art, this two-way detection strategy has higher accuracy and adaptability, especially suitable for complex systems with impaired signal integrity or asynchronous timing relationships.

[0059] When the number of boundary steps is greater than or equal to the first preset number of steps, adjust the phase relationship between the clock and the data in the reverse direction until the number of reverse adjustment steps is equal to half of the number of boundary steps, so as to center the sampling window. When the number of boundary steps exceeds the preset threshold (typical value is 5 - 10 steps), it indicates that the current sampling point is already in a good position within the sampling window and has a considerable margin from the known boundary. At this time, a simplified centering strategy is adopted: the system directly calculates half of the number of boundary steps (usually taking the floor value for non-integer results), and then adjusts this number of steps in the reverse direction. This method is based on a reasonable assumption: when the distance from the initial sampling point to one side boundary is large enough, the sampling window is likely to be approximately symmetric, and the sampling point can be made closer to the window center by adjusting half of the number of boundary steps in the reverse direction. For example, if the number of boundary steps is 8, the system will adjust 4 steps in the reverse direction to move the sampling point to a position farther from the boundary. This fast-path strategy has the advantages of simple calculation and high implementation efficiency, avoiding unnecessary full two-way scans and reducing the system initialization time. From the perspective of hardware resource utilization, this method significantly reduces the complexity of the state machine and the FPGA resource occupancy, and is especially suitable for large-scale data acquisition systems that require multi-channel parallel optimization.

[0060] S15. Lock the obtained optimal phase relationship to complete the phase synchronization within the AD sampling system.

[0061] S2. Select any one of the AD sampling systems as the master system, and the remaining AD sampling systems as slave systems. The master system periodically sends synchronization pulses to the slave systems. Each slave system collects the synchronization pulses and generates synchronization signals according to the pulse widths to complete the phase synchronization outside the AD sampling system.

[0062] The phase synchronization outside the AD sampling system refers to establishing and maintaining a unified timing relationship among multiple physically independent AD sampling systems, so that their sampling clocks are exactly the same or have a fixed deviation in phase. This is essentially different from the phase synchronization (internal phase synchronization) between the FPGA-AD channels within a single system. The master-slave architecture of this step can achieve a high sampling synchronization accuracy between systems, providing a time consistency guarantee for subsequent multi-source data fusion. From the perspective of system integration, this master-slave synchronization architecture supports the flexible expansion and reconstruction of the system. The newly added sampling system can be quickly incorporated into the overall system by simply connecting to the synchronization pulse distribution network, which has significant engineering practical value. In some preferred embodiments, in order to reduce the path delay, when selecting the master system, it should be ensured that the paths to the slave systems are basically the same.

[0063] Those skilled in the art can know that the synchronization pulse refers to a special timing signal generated by the master system FPGA through a dedicated synchronous output pin, which has precise time characteristics and level change rules. Different from ordinary clock signals, the synchronization pulse contains synchronization instruction information encoded in its pulse width. The implementation of generating synchronization signals according to the pulse width involves precise time measurement and decoding logic inside the slave system. The slave system measures the duration of the received synchronization pulse through a high-precision counter or time-to-digital converter (TDC) technology, and compares the measurement result with a preset threshold to identify the pulse type. Its specific implementation manner can be specifically set by those skilled in the art according to the existing technology, and the present invention does not make further limitations.

[0064] In the application scenario of a multi-sampling system, the glitches generated by noise misjudge the synchronization pulses, and ensuring sampling synchronization pulses at different times in periodic data sampling does not affect the phase relationship between modules. In some preferred embodiments, this problem is solved by setting the sum of the high-level duration and the low-level duration of the synchronization pulse to an integer multiple of the data period, so that each slave system can detect and respond to synchronization events at exactly the same relative moment, ensuring that the edges of the synchronization pulses always appear at specific data sampling points, eliminating timing uncertainties. The specific implementation manner can be realized by a high-precision digital timing circuit in the master system. The data period refers to the basic time unit required for the AD sampling system to perform a complete data sampling, that is, the period of the sampling clock.

[0065] S4. Each AD sampling system resets and reads / writes data according to the synchronization signal, and initiates data down-conversion processing.

[0066] Data down-conversion processing (Digital Down-Conversion, DDC) is the core signal processing technology in a radio frequency signal acquisition system, which is used to digitally convert a high-frequency RF signal (such as in the IF or RF band) into a low-frequency signal close to the baseband. The above steps together constitute a complete processing pipeline: data reset determines the starting point of processing, read / write operations control data acquisition, and down-conversion processing is the first-level algorithm conversion of the acquired data. The synchronization signal plays the role of a general commander in this pipeline, not only precisely defining the starting point of the data stream, but also ensuring that the parameters of the down-conversion processing (such as the initial phase of the NCO) are consistent among multiple systems.

[0067] Those skilled in the art can know that in a complex electromagnetic environment or a long-distance transmission scenario, the synchronization signal may be lost or delayed due to interference, attenuation, or equipment failure. The systems waiting for synchronization may be in a suspended state forever, resulting in the paralysis of the entire data acquisition link. From the perspective of resource utilization efficiency, AD sampling systems are usually equipped with high-speed caches and processing resources. Prolonged synchronization waiting will cause these valuable resources to be idle and wasted, affecting the overall performance of the system. Therefore, in some preferred embodiments, it is considered to add a timeout mechanism after completing the synchronization inside and outside the system, such as Figure 4 as shown, specifically including:

[0068] Step S3. Set a timeout mechanism based on the transmission duration of the synchronization pulse. When the synchronization is not completed within the timeout, the AD sampling system enters the normal working mode.

[0069] Those skilled in the art can be aware that the commonly used timeout mechanism in this field is mainly fixed-time timeout, that is, simply set a fixed time threshold (such as 100 ms). If the synchronization is not completed within this time, the timeout process will be triggered. This method is simple to implement but lacks flexibility and is difficult to adapt to complex and changeable working environments. In this embodiment, the timeout threshold is dynamically determined based on the characteristics of the synchronization pulse itself (such as pulse period, expected number of pulses), so that the timeout determination is closely related to the actual synchronization process. When the synchronization is not completed within the timeout, the AD sampling system enters the fault tolerance model. At this time, each AD sampling system works independently, does not rely on the central synchronization signal, and collects data according to its own clock. Although the precise time alignment of data between multiple systems cannot be guaranteed in this state, the basic data acquisition function is ensured not to be interrupted. For some applications (such as scenarios where only the signal amplitude rather than the phase is concerned), the data in this degraded mode still has considerable value. In engineering practice, a system warning or error log should also be generated after the timeout is triggered, recording the detailed information of the timeout event (such as the number of received synchronization pulses, signal quality indicators, etc.), providing a basis for subsequent fault analysis and system optimization. In some other preferred embodiments, a mechanism for periodically attempting to re-establish synchronization in the normal working mode can also be set, so as to automatically switch back to the high-precision synchronization working mode after the synchronization condition is restored, maximizing the availability and data quality of the system.

[0070] Those skilled in the art can be aware that during the transmission of the synchronization signal, due to unstable links or race hazards, the synchronization pulse will mutate, resulting in the two situations shown in Figure 3 . In the first situation, during the process of data changing from 0 to 1, due to metastability, 1 is judged as 0; during the process of data changing from 1 to 0, 0 is judged as 1. In this case, if the slave devices all judge the high level of H and the low level of I, it may cause a 90-degree phase difference in the data between modules. In the second situation, during the process of data changing from 0 to 1, 1 can be correctly judged; during the process of data changing from 1 to 0, 0 is judged as 1. In this case, if the slave devices all judge the high level of H + 1 and the low level of I - 1, there will be no deviation in the data phase between modules. At this time, the external phase synchronization process of the AD sampling system considering the timeout mechanism is as shown in Figure 5 and includes:

[0071] S31. Obtain the standard high-level duration H and the standard low-level duration I of the synchronization pulse; enable each slave device to first sample and judge the pulse with a high-level duration of H + 1 and a low-level duration of I - 1, and set the first timeout period. The setting of the first timeout period represents the expected waiting time for high-quality synchronization. This time length is usually determined according to the maximum tolerable delay of the system and the actual application scenario.

[0072] S321. If a synchronization pulse is correctly sampled within the first timeout period, the synchronization signal is pulled high. When the system successfully samples a synchronization pulse that meets the H+1 / I-1 standard within the first timeout period, the synchronization signal is immediately pulled high, indicating that the optimal synchronization state has been reached. In this state, the data phase difference between different modules will be minimized. This step is the first-level judgment.

[0073] S322. If the sampling is not completed within the first timeout period, sample and judge a pulse with a high-level duration of H and a low-level duration of I, and set a second timeout period; if a synchronization pulse is correctly sampled within the second timeout period, the synchronization signal is pulled high. When the first-level judgment times out, it transfers to the second-level judgment, which reflects the flexible design concept, that is, when the optimal state cannot be achieved, the system still tries to ensure that it operates with acceptable performance as much as possible. At this time, there is a certain phase difference between each AD sampling system, but in an environment with relatively poor signal quality, this compromise is necessary. The second timeout period is usually set shorter than the first timeout period because the system has already waited for a long time and needs to make a quick decision to avoid delaying data acquisition. After successfully sampling a synchronization pulse that meets the standard at this stage, the system also pulls high the synchronization signal, but records a mark internally, indicating that the current synchronization quality is at the "sub-optimal" level.

[0074] S323. If the sampling is not completed within the second timeout period, directly pull high the synchronization signal and make the system enter the normal working mode. This step represents the ultimate safety guarantee of the timeout mechanism. When both levels of judgment time out, the system will no longer wait for the synchronization pulse, but directly pull high the synchronization signal and enter the normal working mode. This design ensures that under the worst conditions (such as the complete loss of the synchronization signal), the system can still operate independently and maintain the basic data acquisition function. In this state, although the data between different modules may lack precise phase alignment, for some application scenarios with higher tolerance (such as amplitude measurement), these data still have practical value. More importantly, this automatic degradation mechanism avoids the risk of the system completely stopping due to waiting for synchronization, significantly improving the reliability and continuous operation time of the system.

[0075] Compared with the traditional single-standard synchronization judgment, the dual-level timeout judgment mechanism of the present invention can pursue the phase consistency between modules to the greatest extent while ensuring the reliability of the system. This design is particularly suitable for fields such as distributed multi-channel acquisition systems, high-speed coherent radar systems, and precision scientific instruments, and can significantly improve the synchronization accuracy and stability of the system without increasing the hardware complexity. At the same time, the adaptive characteristics of this mechanism also enable the system to intelligently adjust the working mode in different quality transmission environments, providing great flexibility and reliability guarantee for practical engineering applications.

[0076] The foregoing has shown and described the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments, and what is described in the above embodiments and the specification only illustrates the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements fall within the scope of the present invention claimed. The scope of protection claimed for the present invention is defined by the appended claims and their equivalents.

Claims

1. An internal and external phase synchronization method for an AD sampling system based on FPGA, characterized in that Including the steps: S1. Periodically send test data within the AD sampling system, dynamically adjust the phase relationship of each module within the AD sampling system until stable acquisition of test data is achieved, and complete in-phase synchronization within the AD sampling system; S2. Select any one of the AD sampling systems as the master system, and the remaining AD sampling systems as slave systems. The master system periodically sends synchronization pulses to the slave systems. Each slave system acquires the synchronization pulses and generates synchronization signals according to the pulse width, and completes out-of-phase synchronization outside the AD sampling system; S4. Each AD sampling system performs data reset and read / write according to the synchronization signal, and starts data down-conversion processing; The method for dynamically adjusting the phase relationship of each module within the AD sampling system in step S1 includes: S11. Adjust the sampling timing position through FPGA primitives, acquire test data, and initialize the position adjustment counter, data stability counter, and clock phase adjustment counter; S12. When the position adjustment count exceeds the preset maximum number threshold, adjust the phase of the clock and data through a phase-locked loop, record the adjustment direction and number of times, and return to step S11; S13. When the position adjustment count is within the preset maximum number threshold and the data stability count reaches the preset value, continue to adjust the phase relationship of the clock and data in the current direction until the sampled data deviates, and record the clock phase adjustment count at this time as the boundary number; S14. Determine the optimal phase adjustment range according to the boundary number, and center the sampling window by reversely adjusting the phase relationship of the clock and data; S15. Lock the obtained optimal phase relationship and complete in-phase synchronization within the AD sampling system.

2. The method for internal and external phase synchronization of the AD sampling system based on FPGA according to claim 1, characterized in that, The method for determining the optimal phase adjustment range according to the boundary number in step S14 includes: When the boundary number is less than the first preset number, reversely adjust the phase relationship of the clock and data until the sampled data deviates, and record the new boundary number; When the boundary number is greater than or equal to the first preset number, reversely adjust the phase relationship of the clock and data until the reverse adjustment number is equal to half of the boundary number to center the sampling window.

3. The method for internal and external phase synchronization of the AD sampling system based on FPGA according to claim 1, characterized in that: In step S2, the sum of the high-level duration and the low-level duration of the synchronization pulse is an integer multiple of the data period.

4. The method for internal and external phase synchronization of the FPGA-based AD sampling system according to claim 1 or 3, characterized in that It also includes: Step S3. Set a timeout mechanism based on the synchronization pulse transmission duration. When synchronization is not completed within the timeout, the AD sampling system enters the normal working mode.

5. The method for internal and external phase synchronization of the AD sampling system based on FPGA according to claim 4, characterized in that, The timeout mechanism in step S3 includes: S31. Obtain the high-level standard duration H and low-level standard duration I of the synchronization pulse; enable each slave device to first sample and judge the pulse with a high-level duration of H + 1 and a low-level duration of I - 1, and set the first timeout period; S321. If the synchronization pulse is correctly sampled within the first timeout period, raise the synchronization signal; S322. If sampling is not completed within the first timeout period, sample and judge the pulse with a high-level duration of H and a low-level duration of I, and set the second timeout period; if the synchronization pulse is correctly sampled within the second timeout period, raise the synchronization signal; S323. If the sampling is not completed within the second timeout period, directly raise the synchronization signal and make the system enter the normal working mode.

6. An internal and external phase synchronization system for an AD sampling system based on FPGA, characterized in that, The system is used to implement the internal and external phase synchronization method of the FPGA-based AD sampling system described in any one of claims 1 to 5.

7. A storage medium, characterized in that, The storage medium includes a stored program, wherein the program, when running, executes the internal and external phase synchronization method of the FPGA-based AD sampling system described in any one of claims 1 to 5.

8. An electronic device, characterized in that, The electronic device is used to run a program, wherein the program, when running, executes the internal and external phase synchronization method of the FPGA-based AD sampling system described in any one of claims 1 to 5.

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