Memory system, operating method thereof, and computer readable storage medium

Abstract

The embodiment of the invention discloses a memory system, an operation method thereof and a computer readable storage medium. The memory system comprises a memory, and the physical space of the memory is divided into a user space and a hidden space; a memory controller coupled to the memory, the memory controller being configured to: set a first memory block of the user space as a write-in acceleration cache region; wherein the first storage block is in a first-level storage unit mode; the write-in acceleration cache region is configured to cache data; setting a free storage block of the hidden space as a write-in acceleration cache region; wherein the free storage block is in a first-level storage unit mode.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and relate to but are not limited to a memory system and an operating method thereof, and a computer-readable storage medium. Background Art

[0002] Memory controllers and memories can be integrated into various types of storage devices, such as Solid State Drives (SSDs), Universal Flash Storage (UFS), and embedded Multi-Media Cards (eMMCs). The memory controller can control the operation of the memory, such as read, write, or erase operations.

[0003] As memory integration and bit density increase, more data can be stored in the memory. However, there is still much room for improvement in terms of improving memory performance, especially writing performance. Summary of the invention

[0004] The present disclosure provides a memory system and an operating method thereof, and a computer-readable storage medium.

[0005] According to a first aspect of an embodiment of the present disclosure, there is provided a memory system, including:

[0006] A memory, wherein a physical space of the memory is divided into a user space and a hidden space;

[0007] A memory controller is coupled to the memory, and the memory controller is configured to:

[0008] Setting the first storage block of the user space as a write acceleration cache area; wherein the first storage block is a first-level storage unit mode; and the write acceleration cache area is configured to cache data;

[0009] The free storage blocks of the hidden space are set as the write acceleration cache area; wherein the free storage blocks are the first-level storage unit mode.

[0010] In some embodiments, the hidden space includes a reserved subspace, and the reserved subspace is used for garbage collection; the memory controller is specifically configured to:

[0011] The free storage blocks of the reserved subspace are set as the write acceleration cache area.

[0012] In some embodiments, the memory controller is further configured to:

[0013] When the hidden space needs to use the free storage blocks of the reserved subspace, the free storage blocks occupied by the write acceleration cache area are returned to the reserved subspace.

[0014] In some embodiments, the memory controller is specifically configured to:

[0015] Writing the data cached in the free storage block occupied by the write acceleration cache area into the second storage block of the user space; wherein the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode;

[0016] After the data cached in the free storage block is written into the second storage block, the free storage block is erased so that the free storage block is returned to the reserved sub-space.

[0017] In some embodiments, the situation where the hidden space needs to use the free storage block of the reserved subspace includes at least one of the following: the available capacity of the hidden space is less than or equal to the preset capacity, and garbage collection.

[0018] In some embodiments, the memory controller is further configured to:

[0019] When the number of erasure and writing times of the free storage blocks in the hidden space is greater than or equal to a preset value, stop setting the free storage blocks in the hidden space as the write acceleration cache area.

[0020] In some embodiments, the memory controller is further configured to:

[0021] When the number of erasing and writing times of the free storage block in the hidden space is greater than or equal to a preset value, the data to be cached in the free storage block is cached in the first storage block.

[0022] In some embodiments, the memory controller is specifically configured to:

[0023] The physical address of the free memory block and the physical address of the first memory block are exchanged.

[0024] In some embodiments, the memory controller is further configured to:

[0025] Writing the data cached in the first storage block to a second storage block in the user space; wherein the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode;

[0026] After writing the data cached in the first storage block into the second storage block, erasing the first storage block.

[0027] In some embodiments, the memory controller is further configured to:

[0028] Setting the first storage block of the user space to the first-level storage unit mode;

[0029] Setting the storage block of the hidden space to the first-level storage unit mode;

[0030] The second storage block of the user space is set to a second-level storage unit mode; wherein the second storage block is configured to store the data.

[0031] In some embodiments, the memory system includes: a solid state drive, an embedded multimedia card, and a universal flash memory storage.

[0032] According to a second aspect of an embodiment of the present disclosure, there is provided an operating method of a memory system, the memory system comprising a memory and a memory controller coupled to the memory, wherein a physical space of the memory is divided into a user space and a hidden space; the operating method comprises:

[0033] Setting the first storage block of the user space as a write acceleration cache area; wherein the first storage block is a first-level storage unit mode; and the write acceleration cache area is configured to cache data;

[0034] The free storage blocks of the hidden space are set as the write acceleration cache area; wherein the free storage blocks are the first-level storage unit mode.

[0035] In some embodiments, the hidden space includes a reserved subspace, and the reserved subspace is used for garbage collection;

[0036] The step of setting the free storage blocks of the hidden space as the write acceleration cache area comprises:

[0037] The free storage blocks of the reserved subspace are set as the write acceleration cache area.

[0038] In some embodiments, the operating method further includes:

[0039] When the hidden space needs to use the free storage blocks of the reserved subspace, the free storage blocks occupied by the write acceleration cache area are returned to the reserved subspace.

[0040] In some embodiments, returning the free storage blocks occupied by the write acceleration cache area to the reserved subspace includes:

[0041] Writing the data cached in the free storage block occupied by the write acceleration cache area into the second storage block of the user space; wherein the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode;

[0042] After the data cached in the free storage block is written into the second storage block, the free storage block is erased so that the free storage block is returned to the reserved sub-space.

[0043] In some embodiments, the operating method further includes:

[0044] When the number of erasure and writing times of the free storage blocks in the hidden space is greater than or equal to a preset value, stop setting the free storage blocks in the hidden space as the write acceleration cache area.

[0045] In some embodiments, the operating method further includes:

[0046] When the number of erasing and writing times of the free storage block in the hidden space is greater than or equal to a preset value, the data to be cached in the free storage block is cached in the first storage block.

[0047] In some embodiments, caching the data to be cached in the free storage block in the first storage block includes:

[0048] The physical address of the free memory block and the physical address of the first memory block are exchanged.

[0049] In some embodiments, the operating method further includes:

[0050] Setting the first storage block of the user space to the first-level storage unit mode;

[0051] Setting the storage block of the hidden space to the first-level storage unit mode;

[0052] The second storage block of the user space is set to a second-level storage unit mode; wherein the second storage block is configured to store the data.

[0053] According to a third aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which instructions are stored. When the instructions are executed, the operating method as described in any embodiment of the second aspect of the present disclosure is implemented.

[0054] In the disclosed embodiment, the write speed can be increased by setting the first storage block of the user space as a write acceleration cache area; the capacity of the write acceleration cache area can be increased by setting the free storage block of the hidden space as the write acceleration cache area; and even in a dirty scenario, the write acceleration cache area can still use the free storage block of the hidden space, which is conducive to improving the write performance in dirty scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0056] Figure 1 is a schematic diagram of a system according to an embodiment of the present disclosure;

[0057] Figure 2a is a schematic diagram of a memory card according to an embodiment of the present disclosure;

[0058] Figure 2b is a schematic diagram of a solid state hard disk according to an embodiment of the present disclosure;

[0059] Figure 3 A physical space diagram of a memory according to an embodiment of the present disclosure is shown in FIG. Figure 1 ;

[0060] Figure 4 is a second schematic diagram of a physical space of a memory according to an embodiment of the present disclosure;

[0061] Figure 5 The flowchart of a method for operating a memory system according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0062] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0063] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0064] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0065] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0066] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0067] Figure 1 1 is a schematic diagram of a system 100 according to an embodiment of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory 104 or receive data from the memory 104.

[0068] The memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital Memory Card (SD Card), a Compact Flash Card (CF Card), a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded MultiMedia Card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0069] The memory controller 106 may be configured to control the operation of the memory 104, such as read, write, and erase operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with a host (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCIE) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced System Device Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0070] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in , the memory controller 106 and the single memory 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (Smart Media, SM) card, a memory stick, a Multi Media Card (Multi Media Card, MMC), a Reduced-Size MMC (RS-MMC), a Micro Multi Media Card (Multi Media Card Micro, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a Universal Flash Storage (Univeral Flash Storage, UFS), etc. The memory card 202 may also include a method for connecting the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memories 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 The memory 104 may include an SSD connector 208 coupled to the host 108 in the memory card 202. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202. The memory 104 may include a volatile memory and a non-volatile memory, such as a NAND flash memory, a dynamic random access memory, a ferroelectric random access memory, a magnetic random access memory, a phase change random access memory, a resistive random access memory, a nano random access memory, etc.

[0071] Figure 3 A physical space diagram of a memory 300 according to an embodiment of the present disclosure is shown in FIG. Figure 1 . Reference Figure 3 As shown, the physical space of the memory 300 can be divided into a user space 310 and a hidden space 320; wherein the user space 310 is used to store data, and the hidden space 320 is used to store parameter information or status information of the user space 310. Both the user space 310 and the hidden space 320 need to reserve a certain number of storage blocks for garbage collection operations. The space composed of the reserved storage blocks is called the reserved subspace (Over Provisioning, OP). For example, Figure 3310 and the reserved subspace 321 of the hidden space 320. Here, the number of storage blocks in the reserved subspace can be one or more, and the present disclosure has no special restrictions on this. In practical applications, the capacity of the reserved subspace is generally calculated and cannot be changed at will. For example, the capacity of the reserved subspace 321 of the hidden space 320 can be reduced to increase the capacity of the reserved subspace 311 of the user space 310.

[0072] In order to improve the write performance of the storage device, some storage blocks of the user space 310 can be set as write booster cache areas 330. For example, the storage units of some storage blocks of the user space 310 are configured as single-level cell mode and used to cache data. The capacity of the write booster cache area 330 is closely related to the write performance. The larger the capacity of the write booster cache area 330 that a manufacturer's product can provide, the more competitive it will undoubtedly be in the entire market.

[0073] However, the capacity of the write acceleration cache area 330 is limited by the capacity of the user space 310. The capacity of the write acceleration cache area 330 will decrease as the available capacity of the user space 310 decreases. Specifically, the capacity of the write acceleration cache area 330 comes from the user space 310. In order to prevent the write acceleration cache area 330 from consuming the storage blocks in the SLC mode too quickly, a threshold line is usually set, such as Figure 3 As shown by the dashed line in the middle. When the write acceleration cache area 330 is in a dirty scenario, for example, after the available storage blocks of the write acceleration cache area 330 drop to the threshold line, the capacity of the write acceleration cache area 330 will become zero, and the storage blocks used thereafter will be a multi-level storage unit mode, for example, a three-level storage unit mode (Triple-Level Cell). At this time, the write speed will be significantly slowed down and the write performance will be reduced. Therefore, how to increase the capacity of the write acceleration cache area to improve the write performance has become a technical problem that needs to be solved urgently.

[0074] Based on this, in order to solve one or more of the above technical problems, an embodiment of the present disclosure provides a memory system.

[0075] Figure 4 This is a second physical space diagram of a memory 400 according to an embodiment of the present disclosure. Figure 4 The memory system provided by the embodiment of the present disclosure is described. Figure 4 As shown, the memory system includes:

[0076] A memory 400, wherein the physical space of the memory 400 is divided into a user space 410 and a hidden space 420;

[0077] A memory controller is coupled to the memory 400, and the memory controller is configured as follows:

[0078] The first storage block of the user space 410 is set as the write acceleration cache area 430; wherein the first storage block is a first-level storage unit mode; the write acceleration cache area 430 is configured to cache data;

[0079] The free storage blocks of the hidden space 420 are set as the write acceleration cache area 430; wherein the free storage blocks are in the first-level storage unit mode.

[0080] The memory system includes a solid state drive, a universal flash memory storage, and an embedded multimedia card. Here, the specific structure and composition of the memory system can be referred to in the above Figure 1 , Figure 2a , Figure 2b The other details about the memory system are similar to those mentioned above and will not be described here for the sake of brevity.

[0081] The memory 400 includes an SLC memory, an MLC (Multi-Level Cell) memory, a TLC (Trinary-Level Cell) memory, or a QLC (Quad-Level Cell) memory, etc.; wherein one storage cell of the SLC memory stores one bit, one storage cell of the MLC memory stores two bits, one storage cell of the TLC memory stores three bits, and one storage cell of the QLC memory stores four bits. For ease of understanding, the TLC memory will be used as an example for explanation in the present disclosure.

[0082] The memory 400 includes a plurality of memory blocks, each memory block includes a plurality of memory pages, and each memory page includes a plurality of memory cells. Taking NAND memory as an example, the minimum unit for performing an erase operation on the NAND memory is a memory block, and the minimum unit for performing a write operation on the NAND memory is a memory page. In practical applications, the plurality of memory blocks of the memory may be partitioned. Specifically, the physical space corresponding to the plurality of memory blocks may be divided into a user space 410 and a hidden space 420. The user space 410 is used to store data, and the hidden space 420 is used to store parameter information or status information of the user space 410.

[0083] The memory controller is coupled to the memory 400 and can control the memory 400. More specifically, the memory controller may include a processor for controlling the overall operation of the memory controller, and the processor may drive firmware to control the overall operation of the memory controller to implement various functions of the memory controller, such as bad block management, garbage collection, logical to physical address conversion, wear leveling, data error correction, etc. The processor may also manage and maintain multiple storage blocks in the memory 400. For example, the firmware manages free storage blocks by means of an array or a block bitmap. In this example, the firmware may be stored in the memory controller or the memory, and when the firmware is stored in the memory, the firmware may be loaded into the memory controller at power-on.

[0084] The memory controller sets the first storage block of the user space 410 as the write acceleration cache area 430, and sets the free storage block of the hidden space 420 as the write acceleration cache area 430. The first storage block and the free storage block are both first-level storage unit modes. In this way, the capacity of the write acceleration cache area 430 can be increased. Here, the first-level storage unit mode includes SLC mode, MLC mode or TLC mode, etc. Exemplarily, when the memory 400 is a TLC memory, the first-level storage unit mode can be SLC mode or MLC mode. In this example, at least part of the first storage block of the reserved subspace 411 of the user space 410 can be set as the write acceleration cache area 430.

[0085] It should be noted that the first storage block and the free storage block can be set as the write acceleration cache area 430 at the same time, or can be set as the write acceleration cache area 430 one after another, and the present disclosure has no special restrictions on this. The number of free storage blocks set as the write acceleration cache area 430 in the hidden space 420 can be one or more. In practical applications, the number of free storage blocks set as the write acceleration cache area 430 can be dynamically adjusted according to the capacity size of the current write acceleration cache area 430 and / or the size of the data currently to be written to the user space 410.

[0086] In a specific embodiment, the first-level storage unit mode is the SLC mode, and the write acceleration cache area 430 is the SLC cache area. The SLC cache area is used to cache data temporarily or permanently. By setting part of the storage blocks of the memory as the SLC cache area, write requests can be processed with lower latency, the write speed can be increased, and the overall write performance can be improved. In actual applications, the data cached in the SLC cache area can be refreshed to the data storage area of ​​the user space through the command of the host or when the firmware is idle, for example, the space in the user space other than the write acceleration cache area 430.

[0087] In the disclosed embodiment, the write speed can be increased by setting the first storage block of the user space as a write acceleration cache area; the capacity of the write acceleration cache area can be increased by setting the free storage block of the hidden space as the write acceleration cache area; and even in a dirty scenario, the write acceleration cache area can still use the free storage block of the hidden space, which is conducive to improving the write performance in dirty scenarios.

[0088] In some embodiments, the processor may include a partition module, and the partition module has functions such as creating partitions, deleting partitions, merging partitions, and extending partitions. Through the combination of functions related to the partition module, multiple storage blocks of the memory 400 can be partitioned. It should be noted that the processor may also include other functional modules known in the art, and each module of the processor may be a software module running on a processor that is a part of the processor (e.g., a microcontroller unit (MCU)), or may be a hardware module of a finite state machine (FSM) (e.g., an integrated circuit (IC, such as an application specific IC (ASIC), a field programmable gate array (FPGA)), etc.), or may be a combination of software modules and hardware modules.

[0089] In some embodiments, the hidden space 420 includes a reserved subspace 421 , and the reserved subspace 421 is used for garbage collection; the memory controller is specifically configured to: set the free storage blocks of the reserved subspace 421 as the write acceleration cache area 430 .

[0090] Exemplarily, when the capacity of the write acceleration cache area 430 is small or the available capacity is insufficient, the free storage blocks of the reserved subspace 421 can be set as the write acceleration cache area 430. For example, some free storage blocks are divided from the reserved subspace 421 and included in the scope of the write acceleration cache area 430, thereby expanding the capacity of the write acceleration cache area 430. It should be noted that the free storage blocks divided and included in the write acceleration cache area 430 still belong to the hidden space 420 in terms of ownership.

[0091] In other embodiments, when there are unoccupied free storage blocks in the hidden space 420 except the reserved subspace 421, some of the free storage blocks in the space may be set as the write acceleration cache area 430, and the present disclosure has no special limitation on this.

[0092] In some embodiments, the memory controller is further configured to: when the hidden space 420 needs to use the free storage blocks of the reserved subspace 421, return the free storage blocks occupied by the write acceleration cache area 430 to the reserved subspace 421. Here, the situation where the hidden space 420 needs to use the free storage blocks of the reserved subspace 421 includes at least one of the following: the available capacity of the hidden space 420 is less than or equal to the preset capacity, and garbage collection. It can be understood that when the hidden space 420 needs to use the free storage blocks of the reserved subspace, the write acceleration cache area 430 needs to return the occupied free storage blocks in a timely manner.

[0093] In one example, when the available capacity of the hidden space 420 is less than or equal to the preset capacity, the free storage blocks occupied by the write acceleration cache area 430 can be returned to the reserved subspace 421 for use by the hidden space 420. Here, the preset capacity can be reasonably set according to the actual memory capacity, and the present disclosure has no special restrictions on this. In a specific embodiment, the preset capacity is less than the capacity of the hidden space 420.

[0094] In another example, when the hidden space 420 needs garbage collection, the free storage blocks occupied by the write acceleration cache area 430 can be returned to the reserved subspace 421, so as to provide garbage collection for the hidden space 420. The garbage collection operation refers to transferring valid data on one or more storage blocks to a free storage block and erasing the one or more storage blocks, so that the erased storage blocks can be used to write new data.

[0095] In some embodiments, the memory controller is specifically configured to:

[0096] Writing the data cached in the free storage block occupied by the write acceleration cache area 430 to the second storage block of the user space 410; wherein the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode;

[0097] After the data cached in the free storage block is written into the second storage block, the free storage block is erased so that the free storage block is returned to the reserved subspace 421 .

[0098] Exemplarily, the data cached in the free storage block is written to the data storage area of ​​the user space, and the free storage block is erased. Since the free storage block still belongs to the hidden space 420, the erased free storage block does not need to be repartitioned and is returned to the reserved subspace 421. In this example, the data storage area includes one or more second storage blocks, and the second-level storage unit mode includes MLC mode, TLC mode or QLC mode, etc. When the memory 400 is a TLC memory, the second-level storage unit mode can be a TLC mode.

[0099] In some embodiments, the memory controller is further configured to stop setting the free storage blocks of the hidden space 420 as the write acceleration cache area 430 when the number of erasure times of the free storage blocks of the hidden space 420 is greater than or equal to a preset value.

[0100] Since the write acceleration cache area 430 uses the free storage blocks of the hidden space 420, the wear of the hidden space 420 may be accelerated. In order to make the user space 410 and the hidden space 420 wear evenly as much as possible, when the erase count (EC) of the free storage blocks of the hidden space 420 is greater than or equal to the preset value, the free storage blocks of the hidden space 420 can be stopped from being set as the write acceleration cache area 430, so that the wear balance of the user space 410 and the hidden space 420 can be guaranteed. Here, those skilled in the art can reasonably set the preset value according to the characteristics of the storage unit in the actual memory, and the present disclosure is not limited here.

[0101] In some embodiments, the memory controller is further configured to: when the number of erasures and writes of the free storage blocks of the hidden space 420 is greater than or equal to a preset value, cache the data to be cached in the free storage blocks to the first storage block. By caching the data to be cached in the free storage blocks to the first storage block, the positions of the storage blocks of the hidden space 420 and the user space 410 can be exchanged, that is, the storage blocks in the user space that do not store data are re-divided into the hidden space 420, and the free storage blocks in the hidden space 420 that are more severely worn are re-divided into the user space 410, thereby ensuring the wear balance of the user space 410 and the hidden space 420.

[0102] In some embodiments, the memory controller is specifically configured to: exchange the physical address of the free storage block and the physical address of the first storage block. In this example, the free storage block to be exchanged may be a storage block with serious wear of the hidden space 420, and the first storage block to be exchanged may be a storage block in which no data is stored in the user space. By exchanging the physical address of the free storage block and the physical address of the first storage block, the position of the free storage block and the first storage block can be interchanged.

[0103] In some embodiments, the memory controller is further configured to:

[0104] Writing the data cached in the first storage block to a second storage block in the user space 410; wherein the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode;

[0105] After the data cached in the first storage block is written into the second storage block, the first storage block is erased.

[0106] Exemplarily, the data cached in the first storage block is written into the data storage area of ​​the user space, and the first storage block is erased; the erased first storage block can be swapped with the free storage block of the hidden space. The second-level storage unit mode includes an MLC mode, a TLC mode, or a QLC mode. When the memory 400 is a TLC memory, the second-level storage unit mode can be a TLC mode.

[0107] In some embodiments, the memory controller is further configured to:

[0108] Setting the first storage block of the user space 410 to a first-level storage unit mode;

[0109] Setting the storage blocks of the hidden space 420 to a first-level storage unit mode;

[0110] The second storage block of the user space 410 is set to a second-level storage unit mode; wherein the second storage block is configured to store data.

[0111] Exemplarily, the memory controller sets the first storage block of the user space 410 to the SLC mode, sets the second storage block of the user space 410 to the TLC mode, and sets the storage block of the hidden space 420 to the SLC mode; wherein, the first storage block of the user space 410 is used to cache data, and one or more data cached by the first storage block can be refreshed to the second storage block of the user space 410; some storage blocks of the hidden space 420 set to the SLC mode are used to store parameter information or status information of the user space 410, and some free storage blocks of the hidden space 420 set to the SLC mode can be dynamically included in the range of the write acceleration cache area 430.

[0112] In the disclosed embodiment, by setting the first storage block of the user space to the first-level storage unit mode, the first storage block can be set as a write-acceleration cache area to improve the write speed; by setting the storage block of the hidden space to the first-level storage unit mode, the free storage block of the hidden space can be set as a write-acceleration cache area, thereby increasing the capacity of the write-acceleration cache area, which is beneficial to improving the write performance.

[0113] Based on the above memory system, an embodiment of the present disclosure further provides an operating method of the memory system.

[0114] Figure 5 1 is a flowchart of an operation method of a memory system according to an embodiment of the present disclosure, wherein the memory system includes a memory and a memory controller coupled to the memory, and the physical space of the memory is divided into a user space and a hidden space. Figure 5 As shown, the operation method includes:

[0115] S510: Setting a first storage block in the user space as a write acceleration cache area; wherein the first storage block is in a first-level storage unit mode; and the write acceleration cache area is configured to cache data;

[0116] S520: Setting the free storage blocks of the hidden space as the write acceleration cache area; wherein the free storage blocks are in the first-level storage unit mode.

[0117] In some embodiments, the hidden space includes a reserved subspace, and the reserved subspace is used for garbage collection; the above step S520 includes: setting the free storage blocks of the reserved subspace as the write acceleration cache area.

[0118] In some embodiments, the above operation method further includes: when the hidden space needs to use the free storage blocks of the reserved subspace, returning the free storage blocks occupied by the write acceleration cache area to the reserved subspace.

[0119] In some embodiments, returning the free storage blocks occupied by the write acceleration cache area to the reserved subspace includes:

[0120] Writing the data cached in the free storage block occupied by the write acceleration cache area to the second storage block of the user space; wherein the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode;

[0121] After the data cached in the free storage block is written into the second storage block, the free storage block is erased so that the free storage block is returned to the reserved sub-space.

[0122] In some embodiments, the above operation method further includes: when the number of erasure times of the free storage blocks in the hidden space is greater than or equal to a preset value, stopping setting the free storage blocks in the hidden space as the write acceleration cache area.

[0123] In some embodiments, the above operation method further includes: when the number of erasure and write times of the free storage block in the hidden space is greater than or equal to a preset value, caching the data to be cached in the free storage block in the first storage block.

[0124] In some embodiments, caching the data to be cached in the free storage block in the first storage block includes: exchanging the physical address of the free storage block and the physical address of the first storage block.

[0125] In some embodiments, the above operation method further includes:

[0126] Setting the first storage block of the user space to a first-level storage unit mode;

[0127] Setting the storage block of the hidden space to the first-level storage unit mode;

[0128] The second storage block of the user space is set to a second-level storage unit mode; wherein the second storage block is configured to store data.

[0129] The above operation method has been introduced in detail on the memory system side, and will not be repeated here for the sake of brevity.

[0130] The embodiments of the present disclosure further provide a computer-readable storage medium, on which instructions are stored, and when the instructions are executed, an operation method as in any of the above embodiments is implemented.

[0131] Here, all or part of the processes in the above-mentioned embodiment method can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk (HDD) or a solid state drive, etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0132] An embodiment of the present disclosure further provides an electronic device, including: a memory system as described in any of the above embodiments.

[0133] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0134] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0135] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0136] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0137] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory system, characterized in that: include: A memory, wherein a physical space of the memory is divided into a user space and a hidden space; A memory controller is coupled to the memory, and the memory controller is configured to: Setting the first storage block of the user space as a write acceleration cache area; wherein the first storage block is a first-level storage unit mode; and the write acceleration cache area is configured to cache data; The free storage blocks of the hidden space are set as the write acceleration cache area; wherein the free storage blocks are the first-level storage unit mode.

2. The memory system according to claim 1, wherein: The hidden space includes a reserved subspace, and the reserved subspace is used for garbage collection; The memory controller is specifically configured as follows: The free storage blocks of the reserved subspace are set as the write acceleration cache area.

3. The memory system according to claim 2, wherein: The memory controller is further configured to: When the hidden space needs to use the free storage blocks of the reserved subspace, the free storage blocks occupied by the write acceleration cache area are returned to the reserved subspace.

4. The memory system according to claim 3, characterized in that: The memory controller is specifically configured as follows: Writing the data cached in the free storage block occupied by the write acceleration cache area into the second storage block of the user space; wherein the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode; After the data cached in the free storage block is written into the second storage block, the free storage block is erased so that the free storage block is returned to the reserved sub-space.

5. The memory system according to claim 2, wherein: The situation where the hidden space needs to use the free storage block of the reserved subspace includes at least one of the following: the available capacity of the hidden space is less than or equal to the preset capacity, and garbage collection.

6. The memory system according to claim 1, wherein: The memory controller is further configured to: When the number of erasure and writing times of the free storage blocks in the hidden space is greater than or equal to a preset value, stop setting the free storage blocks in the hidden space as the write acceleration cache area.

7. The memory system according to claim 1, wherein: The memory controller is further configured to: When the number of erasing and writing times of the free storage block in the hidden space is greater than or equal to a preset value, the data to be cached in the free storage block is cached in the first storage block.

8. The memory system according to claim 7, characterized in that: The memory controller is specifically configured as follows: The physical address of the free memory block and the physical address of the first memory block are exchanged.

9. The memory system according to claim 7, wherein: The memory controller is further configured to: Writing the data cached in the first storage block to a second storage block in the user space; wherein the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode; After writing the data cached in the first storage block into the second storage block, erasing the first storage block.

10. The memory system according to claim 1, wherein: The memory controller is further configured to: Setting the first storage block of the user space to the first-level storage unit mode; Setting the storage block of the hidden space to the first-level storage unit mode; The second storage block of the user space is set to a second-level storage unit mode; wherein the second storage block is configured to store the data.

11. The memory system according to claim 1, wherein: The memory system includes: a solid state hard disk, an embedded multimedia card, and a universal flash memory storage.

12. A method for operating a memory system, characterized in that: The memory system includes a memory and a memory controller coupled to the memory, wherein a physical space of the memory is divided into a user space and a hidden space; The operation method comprises: Setting the first storage block of the user space as a write acceleration cache area; wherein the first storage block is a first-level storage unit mode; and the write acceleration cache area is configured to cache data; The free storage blocks of the hidden space are set as the write acceleration cache area; wherein the free storage blocks are the first-level storage unit mode.

13. The operating method according to claim 12, characterized in that: The hidden space includes a reserved subspace, and the reserved subspace is used for garbage collection; The step of setting the free storage blocks of the hidden space as the write acceleration cache area comprises: The free storage blocks of the reserved subspace are set as the write acceleration cache area.

14. The operating method according to claim 13, characterized in that: The operation method also includes: When the hidden space needs to use the free storage blocks of the reserved subspace, the free storage blocks occupied by the write acceleration cache area are returned to the reserved subspace.

15. The operating method according to claim 14, characterized in that: The step of returning the free storage blocks occupied by the write acceleration cache area to the reserved subspace includes: Writing the data cached in the free storage block occupied by the write acceleration cache area into the second storage block of the user space; wherein the second storage block is a second-level storage unit mode, and the number of bits stored in the storage unit of the second-level storage unit mode is greater than the number of bits stored in the storage unit of the first-level storage unit mode; After the data cached in the free storage block is written into the second storage block, the free storage block is erased so that the free storage block is returned to the reserved sub-space.

16. The operating method according to claim 12, characterized in that: The operation method also includes: When the number of erasure and writing times of the free storage blocks in the hidden space is greater than or equal to a preset value, stop setting the free storage blocks in the hidden space as the write acceleration cache area.

17. The operating method according to claim 12, characterized in that: The operation method also includes: When the number of erasing and writing times of the free storage block in the hidden space is greater than or equal to a preset value, the data to be cached in the free storage block is cached in the first storage block.

18. The operating method according to claim 17, characterized in that: The step of caching the data to be cached in the free storage block in the first storage block comprises: The physical address of the free memory block and the physical address of the first memory block are exchanged.

19. The operating method according to claim 12, characterized in that: The operation method also includes: Setting the first storage block of the user space to the first-level storage unit mode; Setting the storage block of the hidden space to the first-level storage unit mode; The second storage block of the user space is set to a second-level storage unit mode; wherein the second storage block is configured to store the data.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed, the operating method according to any one of claims 12 to 19 is implemented.

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