Extended CORDIC algorithm-based cubic root solving method and solving device

Abstract

The invention discloses a cubic root solving method and solving device based on an extended CORDIC algorithm, which considers the characteristics of digital signal processing in a super-large-scale integrated circuit, and divides the structure of cubic root calculation into three steps: solving a natural logarithm ln (R), where R is an input digital signal and represents the amplitude of a signal to be processed, and R is an output digital signal and represents the amplitude of the signal to be processed; in the step, the signal is converted into a logarithmic form, and a natural logarithmic signal is obtained. The step is realized by expanding a vector mode of the CORDIC algorithm in a hyperbolic coordinate system. And further processing the natural logarithm signal, obtaining ln (R) / 3 by a solving method, and obtaining a division result signal. The step is realized by expanding a vector mode of the CORDIC algorithm in a linear coordinate system. And an e index is solved, and index processing is carried out on the division result signal. The device comprises a natural logarithm calculation module, a division calculation module and an e index calculation module. According to the method, a plurality of calculation stages are processed in parallel, the delay is reduced, and the requirements of real-time processing and high-performance calculation are met.

Description

Technical Field

[0001] The invention relates to the field of digital signal processing of very large scale integrated circuits, and in particular to a cube root solving method and a solving device based on an extended CORDIC algorithm. Background Art

[0002] As an important basic mathematical operation, cube root calculation is widely used in modern digital signal processing, image processing, high-performance computing and other fields. For example, in 3D image rendering, cube root operation can be used to calculate spatial distance or volume parameters in ray tracing algorithms; in machine learning and data science, cube root is often used for standardization and data transformation; in communication systems, it can help solve problems such as power calculation and modulation and demodulation.

[0003] At present, there are mainly the following methods for solving cube roots: numerical iteration method (such as Newton iteration method), lookup table method and interpolation method based on polynomial approximation. These methods have certain flexibility in software implementation, but face great challenges in hardware implementation. Numerical iteration method usually requires a large number of multiplication operations, resulting in large consumption of hardware resources; although the lookup table method is faster, the storage requirements of the table will increase rapidly with the improvement of input accuracy, which is difficult to meet the requirements of resource-constrained embedded systems; and the polynomial interpolation method is easily affected by the complexity of high-order polynomials in hardware implementation, thereby increasing the delay and power consumption of the circuit. Therefore, the existing methods have a trade-off problem between efficiency, resource occupation and accuracy in hardware implementation, and it is difficult to meet the requirements of high efficiency, low power consumption and high accuracy at the same time.

[0004] The expression for cube root calculation can be converted equivalently, that is, It can be seen that the equivalent expression combines three functions, natural logarithm, division and e-exponent, and the complexity of directly designing the hardware calculation circuit is relatively high. The CORDIC (Coordinate Rotation Digital Computer) algorithm is a method that can realize complex calculations such as trigonometric functions, logarithms, exponents, square roots, etc. by relying only on shift and addition operations. It is very suitable for application in hardware circuits. The CORDIC algorithm provides an effective technical approach to construct the above-mentioned cube root solving device.

[0005] The standard CORDIC algorithm can be operated in three coordinate systems: circular coordinate system, linear coordinate system and hyperbolic coordinate system. Each coordinate system has two working modes: rotation and vector. The iterative process of the standard CORDIC algorithm in the hyperbolic coordinate system is shown as follows:

[0006]

[0007] It contains three processing links, x, y, and z. The iteration coefficient i is an integer starting from 1. x and y represent vector coordinates on the two-dimensional coordinate plane. z represents the angle accumulator, which accumulates the angle of each iteration to track the overall rotation angle. In vector mode and rotation mode, the sign function sign is used to calculate d i The positive and negative value of d i =sign(y i ) and di = sign(z i ), used to determine the rotation direction of this iteration; tanh -1 (2 -i ) represents the fixed angle for each iteration, which can be calculated in advance based on the iteration coefficient.

[0008] In addition, in the hyperbolic coordinate system, when the iteration coefficient satisfies i=3n+1 (n is a positive integer), that is, i=4, 7, 10, ..., the iterative calculation needs to be repeated once to ensure the result converges. Finally, the result needs to be multiplied by the scaling factor 1 / K determined by the total number of iterations n. n ,Right now:

[0009]

[0010] When the hardware circuit is implemented, the fixed rotation angle and the scaling factor are generally calculated in advance and set as fixed parameters and stored in a ROM table.

[0011] The iterative process of the vector mode of the standard CORDIC algorithm in the linear coordinate system is shown as follows:

[0012]

[0013] Where i is an integer starting from 0, d i =-sign(y i ), through sign(y i ) determines the rotation direction of this iteration.

[0014] From the equivalent expression of the cube root calculation, it can be seen that from the inner layer to the outer layer of the expression, the CORDIC algorithm module needs to be called three times in the specific implementation. First, the vector mode of the CORDIC algorithm in the hyperbolic coordinate system is used to calculate ln(R), then the vector mode of the CORDIC algorithm in the linear coordinate system is used to calculate ln(R) / 3, and finally the rotation mode of the CORDIC algorithm in the hyperbolic coordinate system is used to calculate The final calculation result is obtained. Although this implementation method based on the standard CORDIC algorithm can realize cube root calculation, its calculation range is limited. In the actual application scenarios of digital systems, the values ​​required for calculation often exceed the support range of the cube root solution method. At the same time, in order to meet the needs of real-time processing and high-performance computing in the actual application of digital systems, the solution device can be designed with a pipeline architecture to process multiple calculation stages in parallel to improve the calculation throughput. Summary of the invention

[0015] The purpose of the present invention is to propose a high-efficiency, low-power, high-precision cube root solution method based on the extended CORDIC algorithm, and further provide a cube root solution device suitable for the field of digital signal processing of very large-scale integrated circuits. In particular, the method overcomes the trade-off problem between efficiency, resource occupation and accuracy in the hardware implementation of the traditional method by extending the CORDIC algorithm and designing a full pipeline architecture, and can effectively meet the computing requirements of the real-time digital signal processing system.

[0016] The present invention provides a method for solving cube roots based on an extended CORDIC algorithm, especially for related calculation problems in the field of digital signal processing, and the specific steps are as follows:

[0017] First, for a positive real number R (in digital signal processing, R can represent the amplitude, power value, etc. of the signal), the calculation of the cube root can be equivalent to:

[0018]

[0019] Specifically, the application of cube root calculation in digital signal processing can include the following aspects:

[0020] 1. Gain adjustment of audio signal: R can represent the amplitude or strength of the audio signal. It can smooth the dynamic range of audio to avoid distortion caused by over-amplification during sound playback.

[0021] 2. Lighting adjustment in image processing: Assuming that R represents the light intensity or pixel brightness value in the scene, by calculating its cube root, we can ensure that the brightness or contrast of the image remains in an appropriate range and improve the image effect.

[0022] 3. Calculation of signal power: In wireless communication, R can represent the amplitude of the received signal. For example, in modulation and demodulation technology, by calculating the cube root of the signal strength R, the system can adjust the transmission power, optimize the signal quality, and avoid excessive interference.

[0023] 4. Data standardization and preprocessing: In data science, R can represent data values ​​that need to be standardized or normalized. For example, when processing large amounts of data, using cube root calculations can help compress the data into a more appropriate range and reduce the impact of extreme values ​​on model training.

[0024] According to the above equation, considering the characteristics of digital signal processing in VLSI, the structure of cube root calculation can be divided into three steps:

[0025] Step 1: Solve the natural logarithm ln(R), where R is the input digital signal, which represents the amplitude of the signal to be processed. This step converts the signal into its logarithmic form to obtain the natural logarithmic signal. This step is achieved by extending the vector mode of the CORDIC algorithm in the hyperbolic coordinate system.

[0026] Step 2: Further process the natural logarithmic signal, find the division method to get ln(R) / 3, and get the division result signal. This step is achieved by extending the vector mode of the CORDIC algorithm in the linear coordinate system.

[0027] Step 3: Solve the e exponent and perform exponential processing on the division result signal to obtain This is the desired cube root

[0028] The technical solution adopted by the device of the present invention is: a cube root solving device based on the extended CORDIC algorithm, including a natural logarithm calculation module, a division calculation module and an e-exponent calculation module, which are specially designed for the processing and calculation of digital signals to meet the high efficiency and low power consumption requirements of ultra-large-scale integrated circuit applications.

[0029] Step 1: Natural logarithm calculation module

[0030] In the natural logarithm calculation, the extended CORDIC algorithm vector mode based on the hyperbolic coordinate system is used to implement it. The specific extension method is to expand the range of the iteration coefficient from i=0,1,2,…,n to i=m,m+1,…,0,1,2,…,n. The specific iteration formula is as follows:

[0031] When i≤0, the iteration formula is as follows:

[0032]

[0033] When i>0, the iteration formula remains consistent with the standard CORDIC iteration formula:

[0034]

[0035] In the above formula, the specific meanings of the parameters are as follows: d i =-sign(yi ), this parameter determines the rotation direction of each iteration; x i ,y i Represents the vector coordinates in the current iteration and stores the intermediate results after each iteration; z i Represents the current angle, which gradually approaches the target value through iterative rotation; With tanh -1 (2 -i ) represents the fixed angle value of the iteration.

[0036] After expansion, the scaling factor K n It can be calculated in advance according to the number of iterations and set as a constant to adjust the final calculation result. The calculation formula is as follows:

[0037]

[0038] In the specific natural logarithm module design, the input signal R is initialized: x0 = R + 1, y0 = R + 1, z0 = 0. After n iterations, it can be calculated. Then, By shifting left by one bit, the natural logarithm value ln(R) for R can be obtained, and the natural logarithm calculation result signal is transmitted to the division calculation module.

[0039] Step 2: Division Calculation Module

[0040] In the division calculation module, the vector mode of the extended CORDIC algorithm based on the linear coordinate system is used to implement it. The specific extension method is to expand the range of iteration coefficients from i=0,1,2,…,n to i=m,m+1,…,0,1,2,…,n, and keep the iteration formula of the standard CORDIC unchanged:

[0041]

[0042] In the above formula, the specific meanings of the parameters are as follows: d i =-sign(y i ), this parameter determines the rotation direction of each iteration; x i ,y i Represents the vector coordinates in the current iteration and stores the intermediate results after each iteration; z i Represents the current angle, which gradually approaches the target value through iterative rotation; (2 -i ) represents the fixed angle value of the iteration.

[0043] In the specific division calculation module design, the input is initialized to x0=3, y0=ln(R), z0=0. After iterative calculation, the calculation result ln(R) / 3 with the dividend as ln(R) and the divisor as 3 can be obtained, and the division calculation result signal is passed to the exponential calculation module.

[0044] Step 3: Index calculation module

[0045] For step 3, the extended CORDIC algorithm rotation mode based on the hyperbolic coordinate system can be used to implement it. The specific extension method is to expand the range of iteration coefficients from i=0,1,2,…,n to i=m,m+1,…,0,1,2,…,n: The specific iteration formula is as follows:

[0046] When i≤0, the iteration formula is as follows:

[0047]

[0048] When i>0, the iteration formula is consistent with the standard CORDIC algorithm:

[0049]

[0050] In the above formula, the specific meanings of the parameters are as follows: d i =sign(z i ), this parameter determines the rotation direction of each iteration; x i ,y i Represents the vector coordinates in the current iteration and stores the intermediate results after each iteration; z i Represents the current angle, which gradually approaches the target value through iterative rotation; With tanh -1 (2 -i ) represents the fixed angle value of the iteration.

[0051] In the design of the specific e-index calculation module, the input is initialized as After iterative calculation, we can get Adding the two together gives the exponential calculation result with e as the base and ln(R) / 3 as the exponent That is the cube root calculation result, which is finally output to the cube root calculation result signal.

[0052] Convergence constraints:

[0053] In the specific implementation process, convergence constraints are crucial to the real-time effectiveness. Specifically:

[0054] 1. Convergence conditions of natural logarithm calculation module: Requirements

[0055]

[0056] 2. Convergence conditions of the division calculation module: meet

[0057]

[0058] 3. Convergence conditions of index calculation module: meet

[0059] |z0|≤θ max

[0060] By adding a finite number of iterations, based on convergence constraints, efficient and accurate cube root calculations can be ensured in hardware implementation, and the scope of application in digital signal processing is greatly expanded.

[0061] Calculation range:

[0062] According to the convergence constraints of the extended CORDIC algorithm, when the value of m is 1, we can get:

[0063]

[0064] It can be concluded that the calculation range of R is: [4.840×10 -4 ,2.067×10 3 ] is much larger than the range supported by the standard CORDIC algorithm. Furthermore, when the value of m is 2, the calculation range of the designed cube root calculation implementation method can reach [9.468×10 -7 ,1.056×10 6 In summary, the cube root solution method based on the extended CORDIC algorithm provided by the present invention can significantly expand the calculation range and basically meet the actual application requirements of digital systems.

[0065] The natural logarithm calculation module includes the following key parts:

[0066] System input / startup control module: This module is responsible for external signal interaction and operation status management. It provides a unified timing reference by receiving the system clock signal (CLK); clears registers and status signals through the reset signal (RESET) to ensure that the system enters the initial state; and triggers the start of the natural logarithm calculation process through the start signal (start).

[0067] Initialization module: This module clears registers and status signals when the reset signal is valid; after the start signal is activated, it receives the input real number R and uses it to initialize the initial values ​​of x, y, and z according to the input settings, providing accurate initial conditions for the iterative calculation process.

[0068] Timing control module: This module delays the sampling of the start signal through multi-stage D triggers, generates timing control signals for each stage, and ensures that each stage of the pipeline is executed in strict time sequence; through the cascade design of multi-stage triggers, the timing control module realizes efficient pipeline control of the core iteration module, and generates control signals in the final stage to enter the result output stage.

[0069] Parameter definition module: This module defines the fixed iteration angle parameters (atanh_1 to atanh_18) required for natural logarithm calculation and stores them in hardware registers through fixed-point processing for direct call. The predefined parameters significantly reduce dynamic operations and support adjustment of parameter accuracy to meet different application requirements.

[0070] Core iteration module: This module completes the step-by-step calculation of the natural logarithm value through 24 iteration stages. The module dynamically selects the calculation formula: when the iteration coefficient is -1 or 0, the extended CORDIC algorithm is used; when the iteration coefficient is positive, the standard CORDIC algorithm is used, and the iteration is repeated at specific stages (such as i=4,7,10...) to improve the accuracy. The iteration trigger and result transmission are realized through the control signals of each level generated by the timing control module.

[0071] Result output module: This module processes the final calculation results of the core iteration module, generates a calculation completion flag signal (finish) when the final stage is detected, completes the final processing by shifting one bit left, and pulls up the finish signal to indicate that the calculation process is completed. The result is output to the ln signal, and the calculation result ln(R) is passed to the division calculation module.

[0072] The division calculation module includes the following key parts:

[0073] System input / startup control module: This module is responsible for the interaction with external signals and the management of the operating status. By receiving the system clock signal (CLK), it provides a unified timing reference for each computing unit; through the reset signal (RESET), it clears the registers and status signals to ensure that the system enters the initial state; through the start signal (start), it triggers the start of the division calculation process.

[0074] Initialization module: When the reset signal is valid, all registers and status signals are cleared; after the start signal is activated, it receives the input ln(R) and initializes the values ​​of x, y, and z according to the input settings to provide accurate initial conditions for the iterative calculation process.

[0075] Timing control module: This module delays the sampling of the start signal through multi-stage D flip-flops, generates timing control signals for each stage, and ensures that each step of the division calculation is executed in strict time sequence. The timing control module efficiently manages the calculation pipeline of each stage through the design of multi-stage flip-flops, and finally generates control signals to enter the final result output stage.

[0076] Parameter definition module: This module defines the fixed iteration angle parameters (atan_1 to atan_18) required for the division operation and stores them in hardware registers through fixed-point processing for direct call. The predefined parameters significantly reduce dynamic operations and support the adjustment of parameter accuracy to meet different application requirements.

[0077] Core iteration module: This module completes the division operation with a divisor of 3 through 19 iteration stages, and realizes iteration triggering and result transmission through various levels of control signals generated by the timing control module.

[0078] Result output module: This module processes the final result of the division operation. When the final stage is detected, it generates a calculation completion flag signal (finish), passes the calculation result to the final output signal (div), and passes the calculation result ln(R) / 3 to the e exponent calculation module.

[0079] The e-index calculation module includes the following key parts:

[0080] System input / startup control module: This module is responsible for external signal interaction and operation status management. It provides a unified timing reference by receiving the system clock signal (CLK); clears registers and status signals through the reset signal (RESET) to ensure that the system enters the initial state; and triggers the start of the e-index calculation process through the start signal (start).

[0081] Initialization module: This module clears registers and status signals when the reset signal is valid; after the start signal is pulled high, it receives the input ln(R) / 3 and uses it to initialize the initial values ​​of x, y, and z according to the input settings, providing accurate initial conditions for the iterative calculation process.

[0082] Timing control module: This module delays the sampling of the start signal through multi-stage D triggers, generates timing control signals for each stage, and ensures that each stage of the pipeline is executed in strict time sequence; through the cascade design of multi-stage triggers, the timing control module realizes efficient pipeline control of the core iteration module, and generates control signals in the final stage to enter the result output stage.

[0083] Parameter definition module: This module defines the fixed iteration angle parameters (atanh_1 to atanh_18) required for natural logarithm calculation and stores them in hardware registers through fixed-point processing for direct call. The predefined parameters significantly reduce dynamic operations and support adjustment of parameter accuracy to meet different application requirements.

[0084] Core iteration module: This module completes the step-by-step calculation of the natural logarithm value through 24 iteration stages. The module dynamically selects the calculation formula: when the iteration coefficient is -1 or 0, the iteration formula of the extended CORDIC algorithm is used; when the iteration coefficient is positive, the standard CORDIC algorithm is used, and the iteration is repeated at specific stages (such as i=4,7,10...) to improve the accuracy. The iteration trigger and result transmission are realized through the control signals of each level generated by the timing control module.

[0085] Result output module: This module processes the final calculation results of the core iteration module, generates a calculation completion flag signal (finish) when the final stage is detected, and adds the x link and y link results of the last iteration calculation to the exp signal to obtain the final calculation result. This is the cube root calculation result.

[0086] Features of the present invention

[0087] The present invention provides a cube root solving method and solving device based on an extended CORDIC algorithm, which mainly include the following features: the present invention divides the cube root calculation into three independent steps, respectively calculating the natural logarithm, division and exponential function, respectively based on the vector mode of the extended CORDIC algorithm in a hyperbolic coordinate system, the vector mode of the extended CORDIC algorithm in a linear coordinate system, and the rotation mode of the extended CORDIC algorithm in a hyperbolic coordinate system, the extended CORDIC algorithm significantly improves the support range of the calculation method, and the solution accuracy can reach the order of 10^-4, which basically meets the application requirements of actual digital systems; the present invention divides the hardware circuit implementation of the solving device into three modules: a natural logarithm calculation module, a division calculation module, and an exponential calculation module, each module supports efficient full-pipeline calculation, each iterative calculation stage is triggered by a control signal strictly according to the timing, so that multiple calculation stages are processed in parallel, delay is reduced, and the requirements of real-time processing and high-performance calculation are met, and the maximum operating frequency can reach above 300MHz. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] Figure 1 It is the overall flow chart of the method of the present invention;

[0089] Figure 2 It is the internal pipeline diagram of the natural logarithm calculation module of the present invention;

[0090] Figure 3It is the internal flow chart of the division calculation module of the present invention;

[0091] Figure 4 It is the internal flow chart of the e-index calculation module of the present invention;

[0092] Figure 5 It is the calculation accuracy simulation realized by the present invention on the hardware circuit;

[0093] Figure 6 It is the comprehensive result performance analysis realized by the present invention on the hardware circuit. DETAILED DESCRIPTION

[0094] The following is a detailed description of the implementation examples of the present invention in conjunction with the accompanying drawings:

[0095] The embodiment of the present invention specifically provides a method and device for solving cube roots based on an extended CORDIC algorithm. The calculation method involved includes the following steps:

[0096] First, make the following equivalent transformation on the expression of cube root calculation:

[0097]

[0098] Then, the converted cube root calculation expression is decomposed. According to the converted cube root calculation expression, its calculation can be decomposed into the following three parts, namely, natural logarithm calculation ln(R), division calculation ln(R) / 3, and e exponent calculation Among them, ln(R) can be calculated using the extended CORDIC algorithm vector mode based on the hyperbolic coordinate system; ln(R) / 3 can be calculated using the extended CORDIC algorithm vector mode based on the linear coordinate system; The calculation can be performed using the extended CORDIC algorithm rotation mode based on the hyperbolic coordinate system. The specific extension method is as follows:

[0099] (1) ln(R) is calculated based on the extended CORDIC algorithm vector mode in the hyperbolic coordinate system. In this mode, the input is initialized to x0=R+1, y0=R+1, z0=0. When i≤0, the iterative formula of the CORDIC algorithm is:

[0100]

[0101] Among them, d i =-sign(y i ). When i>0, the iteration formula of the CORDIC algorithm is:

[0102]

[0103] After the above improvements, the final iterative output z of the extended CORDIC algorithm vector mode in the hyperbolic coordinate system is n After the left shift operation, the final result of the natural logarithm calculation is obtained.

[0104] (2) Calculate ln(R) / 3 based on the vector mode of the CORDIC algorithm in the linear coordinate system. In this mode, the input is initialized to x0=3, y0=ln(R), z0=0. At this time, the iterative formula of the CORDIC algorithm is not affected by the value of i and is the standard CORDIC iterative formula:

[0105]

[0106] Among them, d i =-sign(y i ); The final iterative output z of the extended CORDIC algorithm vector mode based on the linear coordinate system n , which is the result of the division calculation.

[0107] (3) Calculation based on the extended CORDIC algorithm rotation mode in the hyperbolic coordinate system In this mode, the input is initialized to When i≤0, the iteration formula of the CORDIC algorithm is:

[0108]

[0109] Among them, d i =sign(z i ). When i>0, the iteration formula of the CORDIC algorithm is:

[0110]

[0111] After the above improvements, the final iterative output x is obtained based on the rotation mode of the extended CORDIC algorithm in the hyperbolic coordinate system n and n , and the final result of e index calculation is obtained by adding the two.

[0112] The overall architecture of the cube root solving device based on the extended CORDIC algorithm of the present invention is shown in FIG. Figure 1 As shown, it includes a natural logarithm calculation module, a division calculation module and an e exponent calculation module. The three modules are cascaded in sequence to form a complete cube root solving device. In this embodiment, the input data is (1,2 8 ), set the iteration coefficient to start from -1, and the maximum iteration coefficient of the natural logarithm calculation module, e exponential calculation module, and division calculation module is set to 16.

[0113] like Figure 2As shown in FIG. 1 , the pipeline iteration architecture diagram of the natural logarithm calculation module designed based on the extended CORDIC algorithm vector mode in the hyperbolic coordinate system proposed by the present invention mainly includes two different iteration units when i≤0 and i>0, and each iteration unit only includes addition, subtraction and shift operations; the rotation direction of each iteration is based on y i The specific positive and negative judgment of the iteration angles are calculated in advance as fixed parameters and can be used directly; in particular, when the iteration coefficient satisfies i = 3n + 1 (n is a positive integer), that is, i = 4, 7, 10..., the current iteration architecture needs to be reused once; the input of the designed natural logarithm calculation module is initialized to x0 = R + 1, y0 = R + 1, z0 = 0, and after iteration z n The final value of is shifted left by 1 bit to obtain the natural logarithm calculation value ln(R), which is the output of the module.

[0114] like Figure 3 As shown in FIG. 1 , the pipeline iteration architecture diagram of the division calculation module designed based on the extended CORDIC algorithm vector mode in the linear coordinate system proposed by the present invention is shown. In different iteration stages, the internal structure of the iteration unit remains consistent, and the iteration unit only includes addition, subtraction and shift operations; the rotation direction of each iteration is based on y i The specific positive and negative judgments of the iterations are calculated in advance as fixed parameters and can be used directly. The input of the designed division calculation module is initialized as x0=3, y0=ln(R), z0=0. After iterative calculation, z n The final value is the final result of the division calculation and is assigned to the output port div.

[0115] like Figure 4 As shown in FIG. 1 , the pipeline iteration architecture diagram of the e-index calculation module designed based on the extended CORDIC algorithm rotation mode in the hyperbolic coordinate system proposed by the present invention mainly includes two different iteration units when i≤0 and i>0, and each iteration unit only includes addition, subtraction and shift operations; the rotation direction of each iteration is based on z i The specific positive and negative judgments of the iterations and the specific angles of the iterations are calculated in advance as fixed parameters and can be used directly; in particular, when the iteration coefficient satisfies i = 3n + 1 (n is a positive integer), that is, i = 4, 7, 10, etc., the current iteration architecture needs to be reused once; the input of the designed e-index calculation module is initialized as Among them, K n is the scaling factor, which can be calculated in advance according to the number of iterations and set as a fixed parameter, so x0 can be initialized to a fixed value; after iterative calculation, x n and nAfter the addition operation, the e exponential calculation result can be obtained and assigned to the output port exp, thus obtaining the cube root calculation result.

[0116] The hardware circuit implementation of the device of the present invention is based on the logic described above and is written in Verilog language. The solution device provided by the present invention can be deployed on FPGA. The input of the solution device is the real number R to be solved represented by a fixed-point number. The specific implementation is implemented using fixed-point numbers, and the data bit width uses a 32-bit signed number, that is, 1 sign bit, 15 integer bits, and 16 decimal places; by flexibly setting the number of iterative calculations and the iteration coefficient, the needs of different precisions and different calculation ranges can be met. The natural logarithm calculation module, the division calculation module, and the e-exponent calculation module all implement a full-pipeline iterative architecture, and its key path is a combination of adder and shift operations; the above logic is functionally verified and comprehensively analyzed in Vivado2017.4, and the device selected is XC7Z100FFG990-2. Compared with the MATLAB standard library function cbrt, the results of the calculation accuracy simulation are as follows Figure 5 As shown in the figure, it can be seen that the method of the present invention can achieve a calculation accuracy of 10^-4 while greatly expanding the calculation range, achieving a relatively high calculation accuracy.

[0117] In addition, if Figure 6 As shown, the hardware circuit of the present invention can achieve a maximum operating frequency of 316MHz under a clock operating frequency cycle of 200MHz, which meets the actual application scenarios of most high-speed digital systems. At the same time, since the computing modules designed by the present invention are all implemented using a full-pipeline architecture, they can be fully integrated and reused in embedded platforms with limited computing resources such as FPGA, and have great application potential.

Claims

1. A cube root solving method based on an extended CORDIC algorithm, characterized in that: For relevant computational problems in the field of digital signal processing, the specific steps are as follows: First, for a positive real number R, in digital signal processing, R represents the amplitude, power value, etc. of the signal, and the calculation of the cube root is equivalent to: The structure of the cube root calculation is divided into three steps: Step 1: Solve the natural logarithm ln(R), where R is the input digital signal, which represents the amplitude of the signal to be processed. This step converts the signal into its logarithmic form to obtain the natural logarithmic signal; this is achieved by extending the vector mode of the CORDIC algorithm in the hyperbolic coordinate system; Step 2: Further process the natural logarithmic signal, solve the division method to get ln(R) / 3, and get the division result signal; this step is achieved by extending the vector mode of the CORDIC algorithm in the linear coordinate system; Step 3: Solve the e exponent and perform exponential processing on the division result signal to obtain This is the desired cube root 2. A cube root solving device based on an extended CORDIC algorithm for implementing the method as claimed in claim 1, characterized in that: It includes natural logarithm calculation module, division calculation module and e-exponent calculation module, which are designed for digital signal processing and calculation to meet the high efficiency and low power consumption requirements of VLSI applications; In the natural logarithm calculation module, the extended CORDIC algorithm vector mode based on the hyperbolic coordinate system is used to implement it. The specific extension method is to expand the range of the iteration coefficient from i=0,1,2,…,n to i=m,m+1,…,0,1,2,…,n. The specific iteration formula is as follows: When i≤0, the iteration formula is as follows: When i>0, the iteration formula remains consistent with the standard CORDIC iteration formula: In the above formula, the specific meanings of the parameters are as follows: d i =-sign(y i ); x i ,y i Represents the vector coordinates in the current iteration and stores the intermediate results after each iteration; z i Represents the current angle, which gradually approaches the target value through iterative rotation; tanh -1 (1-2 -2-i+1 ) and tanh -1 (2 -i ) represents the fixed angle value of iteration; After expansion, the scaling factor K n According to the number of iterations, it is calculated in advance and set as a constant to adjust the final calculation result. The calculation formula is as follows: In the natural logarithm module, the input signal R is initialized: x0 = R + 1, y0 = R + 1, z0 = 0. After n iterations, the calculated The value of Shift left by one bit to obtain the natural logarithm value ln(R) for R, and pass the natural logarithm calculation result signal to the division calculation module; In the division calculation module, the vector mode of the extended CORDIC algorithm based on the linear coordinate system is used to implement it. The specific extension method is to expand the range of iteration coefficients from i=0,1,2,…,n to i=m,m+1,…,0,1,2,…,n, and keep the iteration formula of the standard CORDIC unchanged: In the above formula, the specific meanings of the parameters are as follows: d i =-sign(y i ), this parameter determines the rotation direction of each iteration; x i ,y i Represents the vector coordinates in the current iteration and stores the intermediate results after each iteration; z i Represents the current angle, which gradually approaches the target value through iterative rotation; 2 -i Indicates the fixed angle value of the iteration; The input is initialized to x0=3, y0=ln(R), z0=0. After iterative calculation, the dividend is ln(R) and the divisor is 3, and the calculation result is ln(R) / 3. The division calculation result signal is passed to the exponential calculation module. The exponential calculation module is implemented using the extended CORDIC algorithm rotation mode based on the hyperbolic coordinate system. The specific extension method is to expand the range of the iteration coefficient from i=0,1,2,…,n to i=m,m+1,…,0,1,2,…,n: The specific iteration formula is as follows: When i≤0, the iteration formula is as follows: When i>0, the iteration formula is consistent with the standard CORDIC algorithm: The specific meanings of the parameters are as follows: i =sign(z i ), this parameter determines the rotation direction of each iteration; x i ,y i Represents the vector coordinates in the current iteration and stores the intermediate results after each iteration; zi represents the current angle, which gradually approaches the target value through iterative rotation; tanh -1 (1-2 -2-i+1 ) and tanh -1 (2 -i ) represents the fixed angle value of iteration; In the design of the specific e-index calculation module, the input is initialized as y0=0, After iterative calculation, we get Adding the two together gives the exponential calculation result with e as the base and ln(R) / 3 as the exponent That is the cube root calculation result, which is finally output to the cube root calculation result signal.

3. The cube root solving device based on the extended CORDIC algorithm according to claim 2, characterized in that: According to the convergence constraints of the extended CORDIC algorithm, when the value of m is 1, we get: It can be concluded that the calculation range of R is: [4.840×10 -4 ,2.067×10 3 ].

4. The device for solving cube root based on extended CORDIC algorithm according to claim 2, characterized in that: The natural logarithm calculation module includes the following key parts: System input / startup control module: This module is responsible for external signal interaction and operation status management. It provides a unified timing reference by receiving the system clock signal. It clears registers and status signals through reset signals to ensure that the system enters the initial state. The start signal is used to trigger the start of the natural logarithm calculation process; Initialization module: This module clears registers and status signals when the reset signal is valid; after the start signal is activated, it receives the input real number R and uses it to initialize the initial values ​​of x, y, and z according to the input settings, providing accurate initial conditions for the iterative calculation process; Timing control module: This module delays the sampling of the start signal through a multi-stage D flip-flop, generates timing control signals for each stage, and ensures that each stage of the pipeline is executed in strict time sequence; Through the cascade design of multi-stage triggers, the timing control module realizes efficient pipeline control of the core iteration module and generates control signals in the final stage to enter the result output stage; Parameter definition module: This module defines the fixed iteration angle parameters required for natural logarithm calculation and stores them in hardware registers through fixed-point processing for direct call; predefined parameters reduce dynamic operations and support adjustment of parameter accuracy to meet different application requirements; Core iteration module: This module completes the step-by-step calculation of the natural logarithm value through 24 iteration stages; the module dynamically selects the calculation formula: when the iteration coefficient is -1 or 0, the extended CORDIC algorithm is used; when the iteration coefficient is positive, the standard CORDIC algorithm is used, and the iteration is repeated at a specific stage to improve the accuracy; the iteration trigger and result transmission are realized through the control signals of each level generated by the timing control module; Result output module: This module processes the final calculation result of the core iteration module, generates a calculation completion flag signal when the final stage is detected, completes the final processing by shifting one bit left, and pulls up the flag signal to indicate that the calculation process is completed. The result is output to the ln signal, and the calculation result ln(R) is passed to the division calculation module.

5. The device for solving cube root based on extended CORDIC algorithm according to claim 2, characterized in that: The division calculation module includes the following key parts: System input / startup control module: This module is responsible for the interaction with external signals and the management of the operating status. By receiving the system clock signal CLK, it provides a unified timing reference for each computing unit. Through the reset signal, it clears the register and status signal to ensure that the system enters the initial state. The start signal is used to trigger the start of the division calculation process; Initialization module: when the reset signal is valid, clear all registers and status signals; After the start signal is activated, it receives the input ln(R) and initializes the values ​​of x, y, and z according to the input settings to provide accurate initial conditions for the iterative calculation process; Timing control module: This module delays the sampling of the start signal through multi-stage D flip-flops and generates timing control signals for each stage to ensure that each step of the division calculation is executed in strict time sequence; The timing control module efficiently manages the calculation pipeline of each stage through the design of multi-level triggers, and finally generates a control signal to enter the final result output stage; Parameter definition module: This module defines the fixed iteration angle parameters required for the division operation and stores them in hardware registers through fixed-point processing for direct call; the predefined parameters significantly reduce dynamic operations and support the adjustment of parameter accuracy to meet different application requirements; Core iteration module: This module completes the division operation with a divisor of 3 through 19 iteration stages, and realizes iteration triggering and result transmission through various levels of control signals generated by the timing control module; Result output module: This module processes the final result of the division operation; when the final stage is detected, it generates a calculation completion flag signal, passes the calculation result to the final output signal, and passes the calculation result ln(R) / 3 to the e exponent calculation module.

6. The device for solving cube root based on extended CORDIC algorithm according to claim 2, characterized in that: The e-index calculation module includes the following key parts: System input / startup control module: This module is responsible for external signal interaction and operation status management. It provides a unified timing reference by receiving the system clock signal. It clears registers and status signals through reset signals to ensure that the system enters the initial state. The e-index calculation process is triggered by the start signal; Initialization module: This module clears registers and status signals when the reset signal is valid; after the start signal is pulled high, it receives the input ln(R) / 3 and uses it to initialize the initial values ​​of x, y, and z according to the input settings, providing accurate initial conditions for the iterative calculation process; Timing control module: This module delays the sampling of the start signal through a multi-stage D flip-flop, generates timing control signals for each stage, and ensures that each stage of the pipeline is executed in strict time sequence; Through the cascade design of multi-stage triggers, the timing control module realizes efficient pipeline control of the core iteration module and generates control signals in the final stage to enter the result output stage; Parameter definition module: This module defines the fixed iteration angle parameters required for natural logarithm calculation and stores them in hardware registers through fixed-point processing for direct call; predefined parameters significantly reduce dynamic operations and support adjustment of parameter accuracy to meet different application requirements; Core iteration module: This module completes the step-by-step calculation of the natural logarithm value through 24 iteration stages; the module dynamically selects the calculation formula: when the iteration coefficient is -1 or 0, the iteration formula of the extended CORDIC algorithm is used; when the iteration coefficient is positive, the standard CORDIC algorithm is used, and the iteration is repeated at a specific stage to improve the accuracy; the iteration trigger and result transmission are realized through the control signals of each level generated by the timing control module; Result output module: This module processes the final calculation results of the core iteration module, generates a calculation completion flag signal when the final stage is detected, and adds the x-link and y-link results of the last iteration calculation to the exp signal to obtain the final calculation result. This is the cube root calculation result.

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