Data processing method, readable storage medium, program product and electronic equipment

Abstract

The invention relates to the technical field of computers, in particular to a data processing method, a readable storage medium, a program product and electronic equipment. The data processing method is applied to the electronic equipment, the electronic equipment comprises a register file and N first arithmetic units, a reading port in the register file can be divided into N sub-ports, and an operand in a register can be divided into N sub-data parts. When the electronic equipment runs a vector instruction of an index mode, N sub-ports on a reading port can read N first sub-data parts according to a register address and a part of index identification, and each first sub-data part comprises a first sub-operand indicated by an index value. Moreover, the N sub-ports can send the first sub-data parts read by the N sub-ports to the corresponding first operation units, and the first operation units can determine first sub-operands from the first sub-data parts according to the other part of index identifiers, and carry out the operation of the vector instruction of the index mode according to the first sub-operands.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data processing method, a readable storage medium, a program product, and an electronic device. Background Art

[0002] The operation process of vector instructions can operate on multiple data elements at the same time, thereby significantly improving computing efficiency. Therefore, vector instructions are often used in high-performance computing, digital signal processing, image processing, etc.

[0003] In order to further improve the operating speed of the electronic device, multiple data elements of the vector instruction can be distributed to multiple computing units for execution. In this way, the operation process of each data element can be performed synchronously in multiple computing units, thereby achieving the effect of improving the operating speed of the electronic device.

[0004] However, for some vector instructions (for example, index mode vector instructions), when one computing unit is executing part of the data elements of the vector instruction, another part of the required data elements may be allocated to other computing units. Therefore, the electronic device needs to allocate the corresponding data elements from other computing units to the computing unit. This process will increase the complexity of the control circuit and the data transmission circuit between the additional computing units, resulting in increased circuit delay and increased coupling between computing units. Summary of the invention

[0005] Embodiments of the present application provide a data processing method, a readable storage medium, a program product, and an electronic device.

[0006] In a first aspect, an embodiment of the present application provides a data processing method, which is applied to an electronic device, wherein the processor of the electronic device includes a register stack and N first operation units; wherein the register stack includes multiple registers and multiple read ports, each read port includes N sub-ports, and one sub-port is used to read one sub-data portion of the N sub-data portions of the operand stored in the register, where N is an integer greater than 1; the method includes: the processor detects a first instruction for performing a first operation in the N first operation units, and the first instruction includes an index identifier; wherein the first operation includes operations between each sub-operand in the first operand and the first sub-operand indicated by the index identifier in the second operand, respectively, and the first operand is an operand in a first register of multiple registers, and the sub-operand in the first operand is an operand in a second operand. The second operand is an operand in a second register among the multiple registers; the processor obtains N sub-data parts of the first operand from the first register through N sub-ports of the first read port among the multiple read ports, and sends the N sub-data parts to the N first operation units respectively, and obtains the first sub-data part of the second operand from the second register through N sub-ports of the second read port among the multiple read ports, and sends the first sub-data part to the N first operation units, the first sub-data part is the sub-data part where the first sub-operand is located in the N sub-data parts of the second operand; the processor obtains the operation results between the sub-data part of the first operand allocated to each first operation unit and the first sub-operand through each first operation unit.

[0007] Exemplarily, in some embodiments of the present application, a read port of a register stack of an electronic device may be divided into N subports, one subport may correspond to a first operation unit, and one subport may read a corresponding sub-data portion from the register according to the address of the register. For example, a subport of the first read port may determine the first register according to the address of the first register, and then read a sub-data portion of the first operand from the first register, and then the N subports of the first read port respectively send the read sub-data portion to the corresponding first operation unit. A subport of the second read port may determine the second register according to the address of the second register, and read the first sub-data portion of the second operand including the first sub-operand from the second register according to the first index identification portion, and the N subports of the second read port respectively send the read first sub-data portion to the N first operation units.

[0008] It can be understood that when a subport of a read port does not receive the first index identification part, it can read each sub-data part in the register respectively, that is, the sub-data part read by a subport in the register is preset, and N subports read N sub-data parts respectively. If a subport receives the first index identification part, the subport can read the corresponding first sub-data part according to the first index identification part, that is, N subports can read the first sub-data part at the same time.

[0009] Through the sub-port of the second read port, the first sub-data portion including the first sub-operand can be read, and then the corresponding sub-data portion is sent to the corresponding first operation unit, so each first operation unit can obtain the first sub-data portion including the first sub-operand. When performing an operation, the first operation unit can select the first sub-operand from the first sub-data portion, and perform an operation based on the first sub-operand and each sub-operand in the obtained sub-data portion of the first operand. In other words, the various first operation units do not need to be interconnected through lines, and the various first operation units do not need to transmit data, thereby reducing the delay of the processor, improving the efficiency of the processor, and reducing the complexity of the circuit.

[0010] In a possible implementation of the first aspect above, the first instruction includes a first register address of a first register; according to N sub-ports of a first read port among multiple read ports, N sub-data parts of the first operation data are respectively obtained from the first register, including: based on the first register address, determining from multiple registers that the first operand is located in the first register, and, based on the N sub-ports of the first read port, obtaining the N sub-data parts from the first register; wherein the N sub-ports of the first read port respectively correspond to the N sub-data parts in the first register.

[0011] In some embodiments of the present application, after the processor of the electronic device obtains the first instruction, it can decode the first instruction based on the decoder to obtain the first register address of the first operand and the second register address of the second operand corresponding to the first instruction. Then the processor can send the first register address to the first read port, and after the N sub-ports in the first read port receive the first register address, the first register can be determined, and then the N sub-ports read the N sub-data parts of the first operand from the first register respectively.

[0012] In a possible implementation of the first aspect above, the first instruction also includes a second register address of a second register, and the index identifier includes a first index identifier part; according to N sub-ports of a second read port among multiple read ports, the first sub-data parts where N first sub-operands are located are obtained from the second register respectively, including: based on the second register address, determining from multiple registers that the second operand is located in the second register; based on the first index identifier part, determining that the first sub-operand is located in the first sub-data part; according to the N sub-ports of the second read port, the first sub-data parts where N first sub-operands are located are obtained from the second register respectively.

[0013] In some embodiments of the present application, after the processor parses the second register address and index identifier of the second operand of the first instruction, the second register address and the first index identifier part of the index identifier can be sent to the second read port, and the N sub-ports of the second read port determine the second register according to the second register address, and then determine the first sub-data part to be read according to the first index identifier part, and the N sub-ports of the second read port can simultaneously read the first sub-data part from the second register based on the first index identifier part.

[0014] In a possible implementation of the first aspect above, the above-mentioned index identifier includes a second index identifier part in addition to the first index identifier part, and the method also includes: determining the first sub-data from the first sub-data part according to the second index identifier part, and, according to each first operation unit, performing a first operation on each sub-operand of the sub-data part of the first operand received by each first operation unit and the first sub-operand.

[0015] In some embodiments of the present application, after parsing the index identifier of the first instruction, the decoder of the processor can send the first index identifier part to the register stack, then associate the second index identifier part with the operation code of the first instruction, and send the operation code and the second index identifier part of the first instruction to N first operation units. After receiving a sub-data part of the first operand and the first sub-data part of the second operand, a first operation unit can determine the first sub-operand from the first sub-data part according to the second index identifier part, and then the first operation unit can perform a first operation on the first sub-operand and each sub-operand corresponding to the received sub-data part of the first operand.

[0016] It can be understood that the above-mentioned first operation unit does not need to obtain data from other operation units during the process of performing the first operation. Therefore, the first operation units do not need to be connected by lines, thereby reducing the coupling between the first operation units and reducing the complexity of the circuit. In addition, the first operation units do not need to transmit data to each other, which can also reduce the delay of the processor in executing the first instruction.

[0017] In a possible implementation of the first aspect above, the N sub-ports of the above-mentioned second read port include a first sub-port, the N first operation units include a first sub-operation unit associated with the first sub-port, and the first sub-port is used to allocate the acquired first sub-data portion to the first sub-operation unit.

[0018] In some embodiments of the present application, a first subport among the N subports of the second read port may be associated with a first suboperation unit among the N first operation units, and then the read data is fixedly sent to the first suboperation unit. That is, one subport is associated with one first operation unit, so that the subport sends the read data to the corresponding first operation unit.

[0019] In a possible implementation of the first aspect above, the number of bits of the above index identifier is determined according to the number of sub-operands in the second operand; the first index identifier part is the first m bits of the index identifier, m=log2(N), and N is an exponent of 2.

[0020] In some embodiments of the present application, the number of bits of the index identifier is related to the number of sub-operands of the second operand. For example, if the index identifier has a total of K bits of data, the number of sub-operands of the second operand is less than or equal to 2. K so that the index identifier can indicate any sub-operand in the second operand. The first index identifier part in the index identifier.

[0021] In a possible implementation of the first aspect, the sub-data portion includes at least one sub-operand.

[0022] In a possible implementation of the first aspect, the first instruction is a vector instruction in index mode.

[0023] In a second aspect, the present application provides an electronic device, comprising: a memory for storing instructions; and at least one processor for executing instructions so that the device implements the first aspect and any possible implementation method of the first aspect. The beneficial effects that can be achieved in the second aspect can refer to the beneficial effects of the method provided in any implementation of the first aspect, and will not be repeated here.

[0024] In a third aspect, the present application provides a computer-readable storage medium, in which instructions are stored, and when the instructions are executed by a device, the computer implements the method provided in the first aspect and any possible implementation of the first aspect. The beneficial effects that can be achieved in the third aspect can refer to the beneficial effects of the method provided in any implementation of the first aspect, and will not be repeated here.

[0025] In a fourth aspect, the present application provides a computer program product, which, when running on a device, enables the device to implement the method provided in the first aspect and any possible implementation of the first aspect. The beneficial effects that can be achieved in the fourth aspect can refer to the beneficial effects of the method provided in any implementation of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A A vector instruction is shown;

[0027] Figure 1B The operation process of a vector instruction is shown;

[0028] Figure 2A A vector instruction in index mode is shown;

[0029] Figure 2B The operation process of a vector instruction in an index mode is shown;

[0030] Figure 3A A process of executing vector instructions based on pipeline is shown;

[0031] Figure 3B A process of executing vector instructions in an indexed mode based on a pipeline is shown;

[0032] Figure 4A According to some embodiments of the present application, a schematic diagram of a micro-architecture is shown;

[0033] Figure 4B A schematic diagram of a register file is shown according to some embodiments of the present application;

[0034] Figure 5 According to an embodiment of the present application, a flowchart of an implementation method of a data processing method is shown;

[0035] Figure 6 According to some embodiments of the present application, a schematic structural diagram of an electronic device 100 is shown. DETAILED DESCRIPTION

[0036] The illustrative embodiments of the present application include, but are not limited to, a data processing method, a readable storage medium, a program product, and an electronic device.

[0037] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0038] As shown in the background technology, if part of the data elements of a vector instruction are allocated to other operation units during the execution of one operation unit, the other part of the data elements required are allocated to other operation units, and the electronic device needs to allocate the corresponding data elements from other operation units to the operation unit. This process will increase the complexity of the control circuit and the data transmission circuit between the additional operation units, resulting in increased circuit delay and increased coupling between the operation units.

[0039] To facilitate understanding, some of the terms and related technologies involved in this application are explained below.

[0040] 1. Instruction execution pipeline (core pipeline)

[0041] The instruction execution pipeline can, for example, divide the instruction execution process into multiple stages, including instruction fetch (IF), decoding (ID), execution (EX), memory access (MM) and write back (WB).

[0042] Each stage has a dedicated hardware unit responsible for processing. When an instruction enters the pipeline, its different stages will occupy different hardware units in turn, forming a pipeline process.

[0043] By processing various stages of instructions in parallel, the pipeline of a processor (such as a central processing unit (CPU), graphics processing unit (GPU), microprocessor (MCU), neural-network processing unit (NPU), or vector processing unit (VPU)) can complete more computing tasks in the same clock cycle, thereby improving computing efficiency.

[0044] 2. Vector instruction

[0045] The basic operation object of vector instructions is vector, that is, a group of numbers arranged in order. When the instruction is a vector operation, the instruction determines the address of the vector source vector (such as the main memory start address or the vector register number), and directly or implicitly specifies other vector parameters such as increment and vector length. Vector instructions process all components in the vector in the same operation, which can effectively improve the computer's computing speed.

[0046] Next, the operation process of vector instructions is introduced.

[0047] For example, Figure 1A A vector instruction is shown.

[0048] like Figure 1A In the 32-bit vector instruction shown, the 5th to 9th bits are the register address corresponding to the first source vector Zn, the 16th to 20th bits are the register address corresponding to the second source vector Zm, size represents the bit width of the elements in the source vector, the 0th to 4th bits are the register address corresponding to the operation result vector Zd, and the data other than size, the register address of the first source vector Zn, the register address of the second source vector Zd, and the register address of the result vector Zm can represent the operation code of the 32-bit vector instruction. The operation code is used to indicate the calculation mode of the vector instruction, such as multiplication, addition, subtraction, etc. The operation code of the vector instruction is used to indicate that the vector instruction performs corresponding operations (for example, multiplication, addition, subtraction, etc.) on Zn and Zm, the operation result is Zd, and the operation result is stored in the register pointed to by the register address from 0th to 4th bits.

[0049] Figure 1B The operation process of a vector instruction is shown.

[0050] It can be understood that the operation process of the vector instruction is to operate on the one-to-one corresponding elements in two vectors. Figure 1B As shown, in the process of operating the source vector Zn and the source vector Zm, it is necessary to operate each data element in the source vector Zn with each corresponding data element in the source vector Zm, and then use the operation results as each data element in the vector Zd.

[0051] For example, refer to Figure 1B , the source vector Zn has 4 elements, namely: Zn_elmt[0], Zn_elmt[1], Zn_elmt[2] and Zn_elmt[3]. The source vector Zm has 4 elements, namely: Zm_elmt[0], Zm_elmt[1], Zm_elmt[2] and Zm_elmt[3].

[0052] The operation process of the source vector Zn and the source vector Zm is, for example: the first data element Zn_elmt[0] in the source vector Zn is operated with the first element Zm_elmt[0] in the source vector Zm, thereby obtaining the first element Zd_elmt[0] in the vector Zd. Similarly, the second data element Zn_elmt[1] in the source vector Zn is operated with the second element Zm_elmt[1] in the source vector Zm, thereby obtaining the second element Zd_elmt[1] in the vector Zd. After the four elements in the source vector Zn are operated one by one with the four elements in the source vector Zm, the four elements of the vector Zd can be obtained: Zd_elmt[0], Zd_elmt[1], Zd_elmt[2] and Zd_elmt[3].

[0053] 3. Index mode vector instructions

[0054] Index mode is often used to access a specific element in an array or vector by index. And the specific element is compared with the elements in another array or vector. In index mode, the instruction can contain an index value, which is used to select a specific data element from a vector or array for operation.

[0055] For example, in the operation process of the source vector Zn and the source vector Zm, the index value indicates the x-th element in the source vector Zm, and the operation process is to operate each element in the source vector Zn with the x-th element in the source vector Zm.

[0056] For example, Figure 2A A vector instruction in index mode is shown.

[0057] like Figure 2AIn the vector instruction of the index mode shown, the data from the 5th to the 9th bit is the register address corresponding to the first source vector Zn, the data from the 16th to the 18th bit is the register address corresponding to the second source vector Zm, the data from the 0th to the 4th bit is the register address of the result vector Zf, i3h represents the high part of the index value, and i3l represents the low part of the index value. In the vector instruction of the 32-bit index mode, the data other than i3h, i3l, the register address of the source vector Zn, the register address of the source vector Zm, and the register address of the result vector Zf can represent the operation code of the 32-bit vector instruction. The operation code of the vector instruction is used to indicate that the index vector instruction is to operate each element in the source vector Zn with the elements indicated by i3h and i3l in the source vector Zm (for example, to perform multiplication, addition, subtraction, etc.), and the operation result is Zf and Zf is stored in the register indicated by the register address corresponding to the data from the 0th to the 4th bit of the instruction. In some embodiments, the index value can be stored separately. For example, in this embodiment, the index value can be divided into two parts, the first part of the index value is i3h at bit 22, and the second part of the index value is i3l at bits 19 and 20. The data element in the source vector Zn that is operated with the source vector Zm can be determined through the index value.

[0058] For example, Figure 2B The operation process of a vector instruction in an index mode is shown.

[0059] like Figure 2B As shown, in the process of operating the source vector Zn and the source vector Zm, it is necessary to determine the data element in the source vector Zm that operates with the source vector Zn according to the index value. Then the data element is operated with each data element in the source vector Zn, and the operation results are used as each data element in the vector Zf.

[0060] For example, refer to Figure 2B, the data element determined from the source vector Zm based on the index value is Zm_elmt[1], that is, the second element in the source vector Zm. During the operation, the first data element Zn_elmt[0] in the source vector Zn is selected to operate with the second element Zm_elmt[1] in the source vector Zm, thereby obtaining the first element Zf_elmt[0] in the vector Zf. Similarly, the second data element Zn_elmt[1] in the source vector Zn is operated with the second element Zm_elmt[1] in the source vector Zm to obtain the second element Zf_elmt[1] in the vector Zf, the third data element Zn_elmt[2] in the source vector Zn is operated with the second element Zm_elmt[1] in the source vector Zm to obtain the third element Zf_elmt[2] in the vector Zf, the fourth data element Zn_elmt[3] in the source vector Zn is operated with the second element Zm_elmt[1] in the source vector Zm to obtain the fourth element Zf_elmt[3] in the vector Zf.

[0061] In some embodiments of the present application, the above-mentioned vector instructions or index mode vector instructions can be executed in the pipeline of the processor.

[0062] The following describes the operation process of vector instructions in the pipeline.

[0063] For example, Figure 3A A process of executing vector instructions based on pipeline is shown.

[0064] like Figure 3A As shown, in some embodiments, the operation of the pipeline can be implemented through the microarchitecture (arch) of the CPU (also called microsystem or microprocessor system). The microarchitecture is used to describe how the processor actually implements the instruction set, including the components of the processor such as the decoder, register file, and operation unit and the connection between them.

[0065] The instruction set is also called instruction set architecture or instruction set system. The instruction set includes basic data types, instruction queues, registers, addressing modes, storage systems, interrupts, exception handling, and external input / output. The instruction set architecture can be regarded as a standard or specification to guide the work of developers.

[0066] The decoder is used to decode the instructions read from the instruction queue and convert them into control signals that the processor can understand and execute. These control signals are then used to instruct other components in the processor on how to operate. The decoding process involves parsing out the operation code (opcode) and possible address code (address) in the instruction and generating corresponding control signals based on this information.

[0067] For example, the decoder can identify different types of instructions (such as arithmetic operations, logical operations, data transfer, etc.) and generate corresponding control signals based on the type and operand of the instruction. These signals are then sent to the operation unit and other related components to perform the operations specified by the instruction.

[0068] The register file is a place in the processor for storing temporary data. It usually consists of multiple registers. These registers include general registers, special registers (such as status registers, program counters, etc.). The main function of the register file is to provide fast data access speed to support the processor's fast calculation and data transmission requirements.

[0069] The register file also includes a data port. For example, the register file is usually designed with multiple read ports to read operands from multiple registers at the same time.

[0070] Exemplarily, each port has an address interface and a value interface. The address interface is used to receive the address of a register to be read, while the value interface is used to output the value stored in the register.

[0071] For example, when the processor needs to read the value of a register, it sends the address of the register to the corresponding read port. The register file retrieves the corresponding value from the internal storage according to the received address and outputs it to the operation unit through the value interface. For example, the register file can send the data read from the register to the operation unit through the internal data bus or data path.

[0072] In addition to the read port, a register file usually has one or more write ports. The write port is used to receive the value to be written to the register and the address of the new register.

[0073] The arithmetic unit is the part of the processor's microarchitecture that is responsible for executing instructions. It receives control signals from the decoder and performs corresponding operations or operations based on these signals. The arithmetic unit usually includes multiple functional units, such as arithmetic logic unit, floating point unit, etc., to support different types of instruction execution requirements.

[0074] Arithmetic logic unit: responsible for performing basic arithmetic operations (such as addition, subtraction, multiplication, division, etc.) and logical operations (such as AND, OR, NOT, XOR, etc.). The arithmetic logic unit is one of the most important functional units in the processor, which supports the arithmetic and logical processing capabilities of the processor.

[0075] Floating-point unit: Specialized for performing floating-point operations such as floating-point addition, subtraction, multiplication, and division. FPU plays an important role in processing scientific computing, graphics processing, and other applications.

[0076] The arithmetic unit also usually includes some additional functions, such as branch prediction, instruction pipelining, etc., to improve the performance and efficiency of the processor.

[0077] For example, in an embodiment of the present application, the operation unit may include an operation unit A and an operation unit B.

[0078] It is understandable that in other embodiments, the micro-architecture of the processor may include more or fewer modules, and the embodiments of the present application do not limit the specific structure of the micro-architecture.

[0079] Next, we will introduce the process of executing pipeline based on the processor microarchitecture.

[0080] In the instruction fetching stage, some modules (such as the front-end module) in the micro-architecture of the processor can obtain the address of the next instruction from the program counter, and then obtain the instruction from the memory or cache according to the address of the instruction, and store the instruction in the instruction queue. For example, in some embodiments of the present application, the front-end module can obtain a vector instruction from the memory or cache and store the instruction in the instruction queue.

[0081] In the decoding stage, the decoder can obtain the vector instruction from the instruction queue and decode the vector instruction, thereby obtaining the register address and operation code of the source vector that performs the vector operation in the vector instruction. For example, there are 32 registers in the register stack that can be used to store the source vector, and each register can store 128 bits of vector data. Therefore, the register address can be 5-bit data, and the decoder can determine the register address of the first source vector Zn of the vector instruction and the register address of the second source vector Zm after decoding the vector instruction. Then the decoder sends the register address of the source vector to the register stack, and the register stack reads the source vector from the corresponding register through the register address of the source vector, and then sends the corresponding source vector to the corresponding operation unit based on the corresponding data path. The data path may include, for example, a transmission queue and a transmission module. The transmission queue is used to temporarily store instructions and wait for the data of the instruction to be prepared. For example, after the decoder completes the decoding of the vector instruction, the operation code of the vector instruction can be sent to the transmission queue for temporary storage. After the register stack obtains the source vector based on the address of the source vector, the source vector can be sent to the emission queue. After the relevant data of the vector instruction in the emission queue (such as the source vector and operation code data) is prepared, the emission module can send the source vector and operation code of the vector instruction to the corresponding execution unit respectively.

[0082] For example, in some embodiments of the present application,

[0083] The source vectors for performing vector operations include source vector Zn and source vector Zm. Source vector Zn is stored in register 1, and source vector Zm is stored in register 2. The decoder sends the register address (e.g., the address of register 1 and register 2) to the register file. After receiving the register addresses of source vector Zn and source vector Zm, the data port of the register file can read source vector Zn and source vector Zm from register 1 and register 2. Then, source vector Zn and source vector Zm are distributed to the corresponding operation units through the data path of the register file and the operation unit.

[0084] For example, in an embodiment of the present application, the operation unit includes an operation unit A and an operation unit B. The operation unit A and the operation unit B can complete the instruction operation in parallel. Therefore, the register file can send a part of the data in the source vector Zn and the corresponding data in the source vector Zm to the operation unit A through the data path, and then send another part of the data in the source vector Zn and the corresponding another part of the data in the source vector Zm to the operation unit B through the data path. For example, there are 32 registers in the register file that can store 128-bit vector data, and the two read ports in the register file each determine register 1 and register 2 from the 32 registers according to the received register address. Each read port can read 128-bit data from the corresponding register, and send the high 64 bits of the 128-bit data to the operation unit A for operation, and send the low 64 bits of the 128-bit data to the operation unit B for operation. In other words, the data read out by a read port of the register file needs to be distributed to multiple operation units for operation.

[0085] It can be understood that the number of bits of data that can be operated by an operation unit in the micro-architecture is fixed, and the number of bits of data of the source vector corresponding to the instruction that can be operated by the micro-architecture is also corresponding to the corresponding operation unit in the micro-architecture. For example, the vector width supported by the operation unit A and the operation unit B of the parallel operation in the micro-architecture can be 64 bits, for example, then the vector width of the source vector Zn and the source vector Zm is 128 bits, that is, the source vector Zn and the source vector Zm can just be allocated to the operation unit A and the operation unit B for operation. It can be understood that in the 128-bit data, the size of each element can be 32 bits. That is to say, a 128-bit vector can include 4 32-bit elements. In other embodiments, each element in a 128-bit vector can also be 16 bits, that is, the 128-bit vector includes 8 16-bit elements. Therefore, in an embodiment of the present application, the register stack can determine through the data path that 128 bits of data can be allocated to the two operation units respectively. For example, the register file distributes the first 64 bits of data of source vector Zn and the first 64 bits of data of source vector Zm to operation unit A through the data path, and distributes the last 64 bits of data of source vector Zn and the last 64 bits of data of source vector Zm to operation unit B.

[0086] For example, the source vector Zn includes 4 elements, namely: Zn_elmt[0], Zn_elmt[1], Zn_elmt[2] and Zn_elmt[3]. The source vector Zm includes 4 elements, namely: Zm_elmt[0], Zm_elmt[1], Zm_elmt[2] and Zm_elmt[3]. Among them, part of the elements n0 in the source vector Zn: Zn_elmt[0], Zn_elmt[1], and part of the elements m0 in the source vector Zm: Zm_elmt[0], Zm_elmt[1] are allocated to the operation unit A. Another part of the elements n1 in the source vector Zn: Zn_elmt[2], Zn_elmt[3] and another part of the elements m1 in the source vector Zm: Zm_elmt[2], Zm_elmt[3] are allocated to the operation unit B.

[0087] In the execution phase, operation unit A and operation unit B can perform corresponding operations on the obtained source vector according to the operation code. For example, in operation unit A, the first data element Zn_elmt[0] in source vector Zn is operated with the first element Zm_elmt[0] in source vector Zm, so as to obtain the first element Zd_elmt[0] in vector Zd. Similarly, the second data element Zn_elmt[1] in source vector Zn is operated with the second element Zm_elmt[1] in source vector Zm, so as to obtain the second element Zd_elmt[1] in vector Zd. After the four elements in source vector Zn are operated in one-to-one correspondence with the four elements in source vector Zm, the four elements of the operation result vector Zd can be obtained: Zd_elmt[0], Zd_elmt[1], Zd_elmt[2] and Zd_elmt[3]. Among them, some elements d1p0: Zd_elmt[0], Zd_elmt[1] of the vector Zd are output by the operation unit A, and the other elements d2p1: Zd_elmt[2] and Zd_elmt[3] are output by the operation unit B.

[0088] It can be understood that by running the above vector instructions through two pipelines, the two pipelines can operate in parallel to improve the operation efficiency.

[0089] However, for indexed vector instructions, the operation process is to operate each data element in a source vector with the data element specified by the index value in another source vector. Therefore, when the register file distributes the data elements in the source vector to multiple pipelines through the data path, only one pipeline can be allocated to the data element specified by the index value. Therefore, it is necessary to add additional circuits to distribute the data elements specified by the index value to multiple pipelines to complete the operation of the instruction.

[0090] The following describes the operation process of index mode vector instructions in the pipeline.

[0091] For example, Figure 3B A process of executing vector instructions in an index mode based on a pipeline is shown.

[0092] For example, in some embodiments of the present application, a multiplexer (MUX) may be provided in the computing unit of the micro-architecture. A multiplexer is a circuit or logic unit that can select an output signal from one or more input signals. In this embodiment, the multiplexer can select the correct data element to perform the corresponding operation according to the index value.

[0093] In the embodiment of the present application, the multiplexers in the various computing units capable of parallel computing are connected via lines, and data can be transmitted to each other. Figure 3B As shown, the multiplexers in the operation unit A and the operation unit B can be coupled through lines, so that the data in the multiplexers in each operation unit can be transmitted to each other. For example, the multiplexer in the operation unit A can select data from the multiplexer in the operation unit B to obtain data, and similarly, the multiplexer in the operation unit B can also obtain data from the operation unit A.

[0094] Next, the operation process of the vector instruction in index mode is introduced.

[0095] For example, in an embodiment of the present application, the index value indicates that the second data element (i.e., Zm_elmt[1]) in the source vector Zm is operated with each data element in the source vector Zn. In the process of the register stack issuing the source vector to the operation unit A and the operation unit B through the data path, a part of the elements n0: Zn_elmt[0], Zn_elmt[1] in the source vector Zn, and the first part of the elements m0: Zm_elmt[0], Zm_elmt[1] in the source vector Zm can be allocated to the operation unit A. Another part of the elements n1: Zn_elmt[2], Zn_elmt[3] in the source vector Zn, and another part of the elements m1: Zm_elmt[2], Zm_elmt[3] in the source vector Zm are allocated to the operation unit B.

[0096] In the execution phase, operation unit A and operation unit B can perform corresponding operations on the acquired source vector. For example, in operation unit A, a part of the elements m0 in the source vector Zm: Zm_elmt[0], Zm_elmt[1] are input into the multiplexer of operation unit A. In addition, the multiplexer in operation unit A can obtain another part of the elements m1 in operation unit B: Zm_elmt[2], Zm_elmt[3] through the line. The multiplexer can select the element Zm_elmt[1] from Zm_elmt[0], Zm_elmt[1] and Zm_elmt[2], Zm_elmt[3] according to the index value and perform operations with a part of the elements n0 in the source vector Zn: Zn_elmt[0], Zn_elmt[1], so as to obtain the first element Zf_elmt[0] and the second element Zm_elmt[1] in the vector Zf. In operation unit B, another part of the elements m1 in source vector Zm: Zm_elmt[0], Zm_elmt[1] are input to the multiplexer of operation unit B. In addition, the multiplexer in operation unit B can obtain a part of the elements m0 in operation unit A: Zm_elmt[0], Zm_elmt[1] through the line. The multiplexer can select the element Zm_elmt[1] from Zm_elmt[0], Zm_elmt[1] and Zm_elmt[2], Zm_elmt[3] according to the index value and perform operations with another part of the elements a1p1 in source vector Zn: Zn_elmt[2], Zn_elmt[3], so as to obtain the third element Zf_elmt[2] and the fourth element Zf_elmt[3] in vector Zf. Among them, some elements f0 of vector Zf: Zf_elmt[0], Zf_elmt[1] are output by operation unit A, and another part of elements f1: Zf_elmt[0], Zf_elmt[1] are output by operation unit B.

[0097] However, after the above scheme couples multiple computing units together through lines, the control process of the operation becomes more complicated, the coupling of each computing unit is high, and the delay in the data transmission process will also become higher, thereby increasing the delay of the processor.

[0098] In summary, when an electronic device uses multiple computing units to operate on each data element of a vector instruction in an index mode, it is necessary to send the element data corresponding to the index value to the corresponding computing unit through an additional circuit, thereby increasing the processor delay.

[0099] In some embodiments of the present application, the processor of the electronic device includes N first operation units executed in parallel, and a read port of a register file in the processor can be configured as N sub-ports corresponding to the N first operation units. It can be understood that the bit width of the data that can be read by each sub-port also becomes 1 / N of the bit width of the read port.

[0100] And the operands in each register in the register file can be divided into N sub-data parts, the data bit width of a sub-data part accounts for 1 / N of the bit width of the entire source vector, each sub-port can read one sub-data part of the N sub-data parts in one access, and a sub-data part can include at least one sub-operand, that is, for instructions with vector operands, a sub-data part contains at least one vector element, and the sub-data parts read by different sub-ports can be the same or different. In addition, the data read out by a sub-port is sent to a corresponding operation unit, that is, the data read out by the sub-port will not be distributed to different operation units.

[0101] In some embodiments, each sub-data portion includes the same number of sub-operands (eg, the same number of vector elements).

[0102] In order to solve the above problems, the present application proposes a data processing method, which is applied to an electronic device, wherein the processor of the electronic device includes a register file and N first operation units. The register file includes multiple registers and multiple read ports, and a read port can read data from any one of the multiple registers, and each read port of the register file includes N sub-ports, and the operand in the register is divided into N sub-data parts. The method includes:

[0103] The register file obtains a first instruction to be operated in the N first operation units, the first instruction includes an index identifier, and the first instruction instructs to execute a first operation in the first operation unit, the first operation includes operations between each sub-operand in the first operand of the first register and the first sub-operand indicated by the index identifier in the second operand of the second register;

[0104] The register file obtains N sub-data parts of the first operation data from the first register through the N sub-ports in the first read port, and distributes the respectively read N sub-data parts to the N first operation units through the data path, and obtains the first sub-data part where the first sub-operand is located from the second register through the N sub-ports in the second read port, and distributes the first sub-data part to the N first operation units through the data path;

[0105] Each first operation unit performs a first operation on each sub-operand in the sub-data part of the received first operation data and the first sub-operand to obtain a result of the operation of the first instruction.

[0106] In some embodiments, the first operation unit in the processor may be, for example, the aforementioned arithmetic logic unit, floating point operation unit, or integer multiplication unit, integer division unit, etc.

[0107] In some embodiments, the index identifier may include a first index identifier portion and a second index identifier portion, the first index identifier portion indicating the first sub-data portion where the first sub-operand is located, and the second index identifier portion indicating the position of the first sub-operand in the first sub-data portion. The N sub-ports of the second read port of the register file may read the N first sub-data portions from the second register based on the first index identifier portion; and each first pipeline unit may obtain the first sub-operand from the first sub-data portion based on the second index identifier portion.

[0108] Among them, the first sub-data part corresponding to the first sub-operand is the x-th sub-data part in the second sub-operand, and the x-th sub-data part in the second sub-operand is determined according to a part of data identified by the index; 0<x≤N, N is an integer greater than 1.

[0109] Through the above scheme, the register file can determine that the first sub-operand to be operated with each sub-operand of the first operand is in the first sub-data part according to the first index identification part of the index identification, and the N sub-ports in the second read port of the register file can read the first sub-data part in the second operand from the second register at the same time. Then the register file can distribute the N first sub-data parts to the N first operation units running in parallel through the corresponding data path. In this way, each first operation unit includes the first sub-data part, so that each first operation unit can perform operations based on the first sub-operand of the first sub-data part and each sub-operand in the first operand. In the above process, each first operation unit does not need to be coupled together, nor does it need to add additional circuits on the data path between the register file and each first operation unit, so the process of the electronic device performing operations can reduce delays.

[0110] In some embodiments of the present application, the first instruction is a vector instruction in an index mode. The first instruction may be, for example, an instruction in technologies such as image processing, audio processing, or natural language processing. Through the vector instruction in the index mode, efficient data processing capabilities may be provided for the above-mentioned various technologies.

[0111] In some embodiments of the present application, the number of bits of data that can be operated in each first operation unit in a micro-architecture of a processor is fixed, and the number of bits of data that can be calculated by the N first operation units corresponds to the number of bits of the operand.

[0112] For example, the number of bits of data that can be calculated by an operation unit is 64 bits, and the micro-architecture corresponding to the processor of the electronic device includes two first operation units, then the two first operation units can simultaneously run a vector instruction, and the vector instruction includes a first operation of two 128-bit source vectors (as an example of operands). Exemplarily, in other embodiments, the number of bits of data that can be calculated by a first operation unit can also be other bits, such as 16 bits, 32 bits, etc. The embodiments of the present application do not limit the number of bits of data that can be calculated by a first operation unit.

[0113] It can be understood that the number of elements in a source vector is related to the number of bits of an element (as an example of a sub-operand) in the source vector. For example, if the number of bits of a source vector is 128 bits and the number of bits of a corresponding element is 32 bits, then a source vector includes 4 elements. Or if the number of bits of a corresponding element is 16 bits, then a 128-bit source vector includes 8 elements.

[0114] In some embodiments of the present application, the index identifier can be represented by an M-bit binary number, where the size of M is related to the number K of elements in the source vector. M ≥ K. For example, if there are 8 data in the source vector, then K = 8, M = 3, that is, the bit width of the index identifier is 3.

[0115] In some embodiments of the present application, the number N of sub-data parts in the register is related to the number of first operation units, so the source vector in the register can be divided into N sub-data parts. The number of bits m of the first index identification part of the index identification can be determined according to N, where m=log2(N), that is, the first index identification part can be the first m bits of data from left to right of the index identification, and the second index identification part is the data after the index identification is divided by m bits of data.

[0116] It can be understood that since the number of bits of data that can be calculated by the N first operation units corresponds to the number of bits of the source vector, that is, the total number of bits of data that can be calculated by the N first operation units is the same as the total number of bits of data of the two source vectors corresponding to the vector instruction or the vector instruction of the index mode. For example, a source vector of a vector instruction of an index mode has a total of 128 bits of data. The number of bits of data that can be calculated by a first operation unit is 32 bits, then the vector instruction can be assigned to a micro-architecture with 4 first operation units that can calculate 32 bits for calculation. Or it can be assigned to a micro-architecture with 2 first operation units that can calculate 64 bits for calculation. It can be understood that the number of bits of the source vector is generally an exponent of 2. Therefore, m can be an integer greater than or equal to 1.

[0117] Exemplarily, in some embodiments, the number of first operation units N=2, and a source vector includes 4 elements, that is, the index identifier is two-bit data. Correspondingly, the source vector in the register is divided into two sub-data parts, and the first sub-data part includes the first element and the second element in the source vector. The second sub-data part includes the third element and the fourth element in the source vector. Among them, the first sub-operand is the second element in the second source vector, then the index identifier is 01, the first sub-data part is the second sub-data part in the second source vector, and the first sub-operand is the second element in the first data part.

[0118] The number of bits of the first index identification part m=log2(2)=1, and the first index identification part is the first bit of the index identification from left to right, that is, the first index identification part is 0. Then, according to the first index identification part being 0, it can be determined that the first sub-operand is located in the first sub-data part of the second source vector. The data of the second index identification part is 1, indicating that the first sub-operand is at the second bit in the first sub-data part.

[0119] Exemplarily, in some other embodiments, the number of first operation units N=4, and the second source vector includes 8 sub-source vectors, that is, the index identifier is three-bit data. Correspondingly, the source vector in the second register is divided into 4 sub-data parts, each sub-data part includes two elements. Among them, the first sub-operand is the 6th element in the second source vector. Then the index identifier is 101, the first sub-data part is the third sub-data part in the second source vector, and the first sub-operand is the second element in the first data part.

[0120] The number of bits of the first index identification part m=log2(4)=2, and the first index identification part is the first two bits of the index identification from left to right, that is, the first index identification part is 10, then according to the first index identification part being 10, it can be determined that the first sub-operand is located in the third sub-data part of the second source vector. The data of the second index identification part is 1, indicating that the first sub-operand is the second bit in the first sub-data part, that is, the first sub-operand is the sixth element in the second source vector.

[0121] Next, the micro-architecture in the processor of the electronic device in the embodiment of the present application is introduced.

[0122] For example, Figure 4A According to some embodiments of the present application, a schematic diagram of a micro-architecture is shown.

[0123] like Figure 4A As shown, the micro-architecture includes components such as an instruction queue, a decoder, a register file, and an operation unit, as well as the connection between them.

[0124] The decoder is used to decode the instructions read from the instruction queue and convert them into control signals that the processor can understand and execute. These control signals are then used to instruct other components in the processor how to operate. The decoding process involves parsing out the operation code (opcode) and possible address code (address) in the instruction, and generating corresponding control signals based on this information. In an embodiment of the present application, the decoder can also parse out the index identifier in the vector instruction of the index mode, and generally, the index identifier consists of a first index identifier part and a second index identifier part.

[0125] For example, the decoder can identify different types of instructions (such as arithmetic operations, logical operations, data transfer, etc.) and generate corresponding control signals based on the type and operand of the instruction. These signals are then sent to the operation unit and other related components to perform the operations specified by the instruction.

[0126] The register file is a place in the processor for storing temporary data. It usually consists of multiple registers. These registers include general registers, special registers (such as status registers, program counters, etc.). The main function of the register file is to provide fast data access speed to support the processor's fast calculation and data transmission requirements.

[0127] In some embodiments of the present application, the operand in the register may be divided into N sub-data parts according to the number of first operation units, so that the register file reads a certain part of the data in the register through the corresponding read port.

[0128] The register file also includes a data port. For example, the register file is usually designed with multiple read ports to read operands from multiple registers at the same time.

[0129] Illustratively, in some embodiments of the present application, each read port in the register file may be configured into N sub-ports, and each sub-port may read corresponding data from a corresponding register.

[0130] In some embodiments of the present application, N subports of a read port may correspond to N operation units. For example, a subport may be connected to an operation unit through a line, so that the data read from the register by the subport may be directly transmitted to the corresponding operation unit.

[0131] In some embodiments of the present application, the N subports of a read port can correspond to the N sub-data parts of the operand in the register. For example, when each subport does not receive the first index identification part, the first subport corresponds to the first sub-data part of the operand in the corresponding register, that is, the first subport can read the first sub-data part in the corresponding register and send the sub-data part to the corresponding first operation unit. Similarly, the second subport can read the second sub-data part in the corresponding register and send the second sub-data part to the second operation unit. In addition, each subport can read each sub-data part in the register in the same clock cycle. When each subport receives the first index identification part, the first sub-data part indicated by the first index identification can be read from the register.

[0132] For example, when the register file reads data in the register through the read port, the sub-port can read the corresponding sub-data portion in the register file according to the first index identification portion, and multiple sub-ports can also read a sub-data portion in the register at the same time.

[0133] The arithmetic unit is the part of the processor's microarchitecture that is responsible for executing instructions. It receives control signals from the decoder and performs corresponding operations or operations based on these signals. The arithmetic unit usually includes multiple functional units, such as arithmetic logic unit, floating point unit, etc., to support different types of instruction execution requirements.

[0134] For example, in an embodiment of the present application, the operation unit may include two first operation units (i.e., N=2), namely, a first operation unit A and a first operation unit B. In the first operation unit A and the first operation unit B, each of the first operation units can support the operation of two 64-bit data, then the source vector in the register in the register file can be 128 bits, that is, the two source vectors used for calculation can be divided into four 64-bit data, and two 64-bit data are allocated to each first operation unit for operation. It can be understood that if the number of corresponding first operation units is 2, then the corresponding read port in the register file can be divided into two sub-ports, each sub-port can read the high 64-bit data or the low 64-bit data of a source vector from the corresponding register, and send the read 64-bit data to the corresponding first operation unit. It can be understood that if a source vector includes 32 bits of elements, it means that a source vector has 4 elements, and the 64-bit data read by a sub-port includes 2 elements.

[0135] It can be understood that in other embodiments, the micro-architecture of the processor may also include more or fewer modules, and more or fewer first pipeline execution units, and the embodiments of the present application do not limit the specific structure of the micro-architecture.

[0136] Next, we will introduce the process of executing pipeline based on the processor microarchitecture.

[0137] In the instruction fetching stage, some modules (such as the front-end module) in the micro-architecture of the processor can obtain the address of the next instruction from the program counter, and then obtain the instruction from the memory or cache through the address of the instruction, and store the instruction in the instruction queue. For example, in some embodiments of the present application, the front-end module can obtain the first instruction, that is, the vector instruction in the index mode, from the memory or cache, and store the instruction in the instruction queue.

[0138] In the decoding stage, the decoder can obtain the first instruction from the instruction queue and decode the first instruction, thereby obtaining the address of the first register corresponding to the first operand, the address of the second register corresponding to the second operand, the first index identification part, the second index identification part and the operation code in the first instruction. Then the decoder sends the address of the first register, the address of the second register and the first index identification part to the register stack, associates the second index identification part with the operation code, and sends the operation code and the second index identification part to the corresponding first operation unit.

[0139] For example, in some embodiments of the present application, the data path in the micro-architecture includes a transmission queue and a transmission module. The transmission queue is used to temporarily store instructions, and the decoder can send the operation code and the second index identification part of the first instruction to the transmission queue. After the operand of the first instruction is prepared, the transmission module can send the first instruction in the transmission queue to the corresponding operation unit for execution.

[0140] In some embodiments, the decoder may also directly send the operation code and the second index identification part to the corresponding operation unit. The register file reads the operand from the corresponding register through the first register address and the second register address. For example, Figure 4B A schematic diagram of a register file is shown according to some embodiments of the present application.

[0141] For example, Figure 4B As shown, the register file includes a first read port, a second read port, a first register and a second register.

[0142] In some embodiments of the present application, the first read port is divided into two sub-ports, and the two sub-ports in the first read port correspond to the operation unit A and the operation unit B respectively. The second read port is also divided into two sub-ports, and the two sub-ports in the second read port also correspond to the operation unit A and the operation unit B respectively. The first operand in the first register is divided into two sub-data parts, and the first operand can be a source vector Zn, and the corresponding first sub-data part is n0, and the second sub-data part is n1. The second operand in the second register is also divided into two sub-data parts, and the second operand can be a source vector Zm, and the first sub-data part is m0, and the second sub-data part is m1.

[0143] In some embodiments of the present application, each subport corresponding to the first read port and the second read port can be connected to a multiplexer (or other selection circuit). The multiplexer is connected to each register in the register file, and the subport can select the corresponding register to read data based on the multiplexer through the address of the register.

[0144] In some embodiments, the register file also includes an address bus, which is used to transmit the address information of the register. When the processor or other processing unit needs to read a register in the register file, the address of the register can be sent to the read port through the address bus. After the read port receives the address, it will use this address to locate the correct register. In the register file, each register has a unique address, which determines the position of the register in the register file.

[0145] For example, in some embodiments of the present application, after the decoder decodes the first instruction, it can send the first register address of the first operand to the first read port through the address bus, and then the first read port sends the first register address to each sub-port, and send the second register address and the first index identification part of the second operand to the second read port through the address bus, and then each second read port sends it to each sub-port.

[0146] After receiving the address of the first register, each sub-interface of the first read port can determine the first register to read data according to the address of the first register and the multiplexer. Then each sub-port reads the corresponding sub-data portion in the first register. It can be understood that the corresponding data portion in the register read by a read port can be pre-set. For example, in the absence of the first index identification portion, the first sub-port of the read port reads the first sub-data portion in the corresponding register, and the second sub-port of the read port reads the second sub-data portion in the corresponding register.

[0147] After receiving the address of the second register and the first index identification part, each sub-port of the second read port can select the second register according to the address of the second register through the multiplexer, and then read the first sub-data part in the second register according to the first index identification part. For example, the first operand can be a source vector Zn, and the source vector Zn includes 4 elements, namely: Zn_elmt[0], Zn_elmt[1], Zn_elmt[2] and Zn_elmt[3]. The second operand can be a source vector Zm, and the source vector Zm includes 4 elements, namely: Zm_elmt[0], Zm_elmt[1], Zm_elmt[2] and Zm_elmt[3]. The source vector Zn is divided into two sub-data parts, the first sub-data part n0: Zm_elmt[0], Zm_elmt[1], and the second sub-data part n1: Zn_elmt[2], Zn_elmt[3]. Similarly, the source vector Zm is also divided into two sub-data parts, the first sub-data part is m0: Zm_elmt[0], Zm_elmt[1]. The second sub-data part is m1: Zm_elmt[2], Zm_elmt[3]. The index identifier is 01, where the first index identifier part is the first bit data 0 of the index identifier, and the second index identifier part is 1. That is, the first sub-data part m0 of the source vector Zm is the first sub-data part, and the element Zm_elmt[1] in the source vector Zm is the first sub-operand.

[0148] The register file can read the first sub-data part n0 of the source vector Zn from the first register according to the address of the first register through the two sub-ports of the first read port: Zn_elmt[0], Zn_elmt[1], and the second sub-data part n1: Zn_elmt[2], Zn_elmt[3]. And the first sub-data part m0 of the source vector Zm can be read from the second register according to the address of the second register and the first index identification part through the two sub-ports of the second read port: Zm_elmt[0], Zm_elmt[1]. That is, the two sub-ports read the two sub-data parts m0.

[0149] In some embodiments, after the register file obtains the corresponding operand, the N sub-data parts in the first operand and the first sub-data part corresponding to the second operand can be sent to the emission queue. At this time, the data of the first instruction in the emission queue has been prepared, and the emission module can send the operation code, operand and second index identification part of the first instruction in the emission queue to the corresponding operation unit.

[0150] Exemplarily, the transmitting module may send N sub-data portions of the first operand to the N first operating units respectively, and send first sub-data portions corresponding to the N second operands to the N first operating units respectively.

[0151] For example, the transmitting module allocates the first sub-data part n0 of the source vector Zn: Zn_elmt[0], Zn_elmt[1] to the first operation unit A, and allocates the second sub-data part n1 of the source vector Zn: Zn_elmt[2] and Zn_elmt[3] to the first operation unit B. And, the first sub-data parts m0 of the two source vectors Zm: Zm_elmt[0], Zm_elmt[1] are allocated to the first operation unit A and the first operation unit B respectively. Exemplarily, in other embodiments, the N sub-ports of the read port in the register file may also be directly connected to each register file, that is, there is no need to set a multiplexer between the N sub-ports of the read port and the register, and the sub-port may determine the corresponding register according to the address of the register, and then read data from the register.

[0152] In some embodiments, after each sub-port on the read port in the register file reads the sub-data portion, the sub-data portion may be directly sent to the corresponding operation unit.

[0153] For example, the first subport of the first read port is connected to the operation unit A through a line. After the subport reads the first sub-data portion n0 of the source vector Zn: Zn_elmt[0], Zn_elmt[1], the sub-data portion can be sent to the first operation unit A. The second subport of the first read port is connected to the first operation unit B through a line. After the subport reads the second sub-data portion n1 of the source vector Zn: Zn_elmt[2], Zn_elmt[3], the sub-data portion can be sent to the first operation unit B. Similarly, the first subport of the second read port of the register file is connected to the first operation unit A. After the subport reads the first sub-data portion m0 of the source vector Zm: Zm_elmt[0], Zm_elmt[1], the sub-data portion can be sent to the first operation unit A. The second sub-port of the second read port is connected to the first operation unit B. After the sub-port reads the first sub-data part m0 of the source vector Zm: Zm_elmt[0], Zm_elmt[1], the sub-data part can be sent to the first operation unit B.

[0154] In the execution segment, after each first operation unit obtains the first sub-data part of the second operand, it can determine the position of the first sub-operand in the first sub-data part according to the second index identification part, and then perform a first operation on each sub-operand in the first operand and the first sub-operand, so as to obtain the first operation result of the first instruction.

[0155] For example, each first operation unit can be configured with a multiplexer, and the first operation unit can determine the first sub-operand from the first sub-data part through the multiplexer according to the second index identification part. When the first operation unit performs the operation, each sub-operand in the first operand can be operated with the first sub-operand, thereby completing the execution process of the first instruction. After that, the micro-architecture of the processor of the electronic device can proceed to subsequent stages, such as memory access, write-back, etc., until the first instruction is completed.

[0156] For example, the first operation unit A and the first operation unit B can perform corresponding operations on the obtained operands, and the corresponding operands include the source vector Zn and the source vector Zm. For example, the first operation unit A can select the second element Zm_elmt[1] in the first sub-data part m0: Zm_elmt[0], Zm_elmt[1] as the first sub-operand according to the multiplexer based on the second index identification part 1, and then operate the first element Zn_elmt[0] in the first sub-data part of the source vector Zn with the first sub-operand Zm_elmt[1], so as to obtain the first element Zf_elmt[0] in the result vector Zf. Similarly, the second element Zn_elmt[1] in the first sub-data part of the source vector Zn is operated with the first sub-operand Zm_elmt[1], so as to obtain the second element Zf_elmt[1] in the vector Zf.

[0157] The first operation unit B can also select the second element Zm_elmt[1] in the first sub-data part m0: Zm_elmt[0], Zm_elmt[1] as the first sub-operand according to the multiplexer based on the second index identification part 1. Then the first element Zn_elmt[2] in the second sub-data part of the source vector Zn is operated with the first sub-operand Zm_elmt[1] to obtain the third element Zf_elmt[2] in the result vector Zf. Similarly, the second element Zn_elmt[3] in the second sub-data part of the source vector Zn is operated with the first sub-operand Zm_elmt[1] to obtain the fourth element Zf_elmt[3] in the vector Zf. Then, part of the elements f0 of the result vector Zf: Zf_elmt[0], Zf_elmt[1] are output by the first operation unit A, and the other part of the elements f1: Zf_elmt[2], Zf_elmt[3] are output by the operation unit B.

[0158] It can be understood that in the microarchitecture of the above-mentioned processor, no additional multiplexer is added between the register file and each first operation unit, thereby reducing the delay in data transmission between the register file and each first operation unit and improving the performance of the processor.

[0159] It can be understood that the structure and connection method in the register stack in the above embodiment are only an example. In other embodiments, the register stack may also include more or fewer structures. The embodiments of the present application do not limit the structure of the register stack and the connection method between the structures.

[0160] Next, the above-mentioned data processing method is introduced.

[0161] For example, Figure 5According to an embodiment of the present application, a flow chart of an implementation of a data processing method is shown.

[0162] It should be noted that the electronic device in the embodiment of the present application may be called a terminal (termina1), a user terminal, a mobile terminal, a user equipment (UE), a terminal device, a mobile station, a mobile terminal (mobile terminal, MT), etc. The terminal device may be a mobile phone, a wearable device, a tablet computer (Pad), a computer with a wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control (industrial control), a wireless terminal in self-driving (self-driving), a wireless terminal in a smart grid (smart grid), a wireless terminal in transportation safety (transportation safety), a wireless terminal in a smart city (smart city), a wireless terminal in a smart home (smart home), etc., which has a processor that can perform vector instruction operations in an index mode.

[0163] like Figure 5 As shown, the process includes:

[0164] S501, the register stack obtains the first instruction to be operated in N first operation units, the first instruction includes an index identifier, and the first instruction indicates to execute a first operation in the first operation unit, the first operation includes each sub-operand in the first operand of the first register, and the operation between the first sub-operand indicated by the index identifier in the second operand of the second register.

[0165] Exemplarily, in some embodiments of the present application, the first instruction is a vector instruction in index mode, and the first instruction includes an index identifier. After detecting the first instruction, the electronic device can decode the first instruction through a decoder to obtain an operation code of the first instruction, a register address of an operand, and an index identifier. It can be understood that the index identifier can be divided into a first index identifier part and a second index identifier part. The operation code is used to indicate that the operand corresponding to the register address of the operand is subjected to a first operation in the first operation unit.

[0166] For example, the operands of the first instruction include source vector Zn and source vector Zm, and the index identifier indicates the xth element in source vector Zm, then the xth element in source vector Zm can be used as the first sub-operand. The first operation is to operate each element in source vector Zn with the first sub-operand in source vector Zm. The operation process can be, for example, an addition operation, a multiplication operation, or a logical operation.

[0167] It can be understood that in some embodiments of the present application, the operand corresponding to the first instruction may be a vector, or a part of a vector, etc.

[0168] After obtaining the address, operation code, first index identification part and second index identification part of the operand, the decoder of the electronic device can send the register address and first index identification part of the operand to the register stack, and the register stack can further obtain the corresponding operand after obtaining the register address and first index identification part of the operand. The decoder can also send the operation code and the second index identification part to the corresponding operation unit through the corresponding data path, for example, the data path includes a transmission queue and a transmission module. The decoder can send the operation code and the second index identification part to the transmission queue to wait for the register stack to prepare the operand of the first instruction. Or the decoder can directly send the operation code and the second index identification part to the corresponding operation unit.

[0169] S502, the register stack obtains N sub-data parts of the first operation data from the first register through the N sub-ports in the first read port, and obtains the first sub-data part where the first sub-operand is located from the second register through the N sub-ports in the second read port.

[0170] Illustratively, in some embodiments of the present application, the register file may obtain the operand from the corresponding register according to the register address and index identifier of the operand.

[0171] For example, in some embodiments of the present application, the operands stored in the registers in the register file may be divided into N parts. The register file may send the address of the register corresponding to the operand of the first instruction and the first index identification part to the corresponding read port through the address bus, and the corresponding read port may determine the corresponding register through the address of the operand, and determine the first sub-data part corresponding to the first sub-operand according to the first index identification part.

[0172] For example, refer to Figure 4BIn the corresponding register stack, in some embodiments of the present application, the register stack can send the address of the first register corresponding to the first operand to the first read port through the address bus, and the N subports in the first read port respectively determine the first register according to the address of the first register through the multiplexer, and then the N subports of the first read port respectively read the corresponding sub-data part of the first operand from the first register. In addition, the register stack can send the address of the second register corresponding to the second operand and the first index identification part to the second read port through the address bus, and the N subports of the second read port determine the second register based on the multiplexer and the address of the second register, and then read the first sub-data part indicated by the first index identification part from the second operand in the second register. In other words, each subport of the second read port reads a first sub-data part. It can be understood that the first sub-operand is located in the first sub-data part.

[0173] For example, refer to Figure 4B , the first operand may be, for example, a source vector Zn, and the second operand may be, for example, a source vector Zm. The register stack may read the first sub-data portion n0 of the source vector Zn through the two sub-ports of the first read port: Zn_elmt[0], Zn_elmt[1]. And the second sub-data portion n1: Zn_elmt[2], Zn_elmt[3]. And the first sub-data portion m0 of the source vector Zm is read simultaneously through the two sub-ports of the second read port: Zm_elmt[0], Zm_elmt[1]. That is, the two sub-ports read the first sub-data portions m0 of the two source vectors Zm.

[0174] S403: The register file distributes the N sub-data parts of the first operand and the first sub-data part to the N first pipeline computing units through the data path.

[0175] It can be understood that in some embodiments of the present application, the electronic device includes N first operating units running in parallel. After the register stack of the electronic device obtains the operand corresponding to the first instruction, the operand corresponding to the first instruction can be distributed to the N first operating units running in parallel through the corresponding data path for calculation.

[0176] For example, corresponding to Figure 4AIn an embodiment, the data path may include, for example, a transmission queue and a transmission module. The register stack may send two sub-data parts n0 and n1 corresponding to the source vector Zn and the first sub-data parts m0 corresponding to the two source vectors Zm to the transmission queue. After the data of the first instruction in the transmission queue is ready, the transmission module may send the operation code corresponding to the first instruction in the transmission queue and the second index identification part 1 to the first operation unit A and the first operation unit B respectively. In addition, the transmission module may also send the sub-data part n0 corresponding to the source vector Zn to the first operation unit A, send the sub-data part n1 corresponding to the source vector Zn to the first operation unit B, and send the first sub-data parts m0 corresponding to the two source vectors Zm to the first operation unit A and the first operation unit B respectively.

[0177] S504, the first operation unit performs a first operation on each sub-operand in the sub-data part of the received first operation data and the first sub-operand to obtain a result of the first operation of the first instruction.

[0178] Exemplarily, in some embodiments of the present application, after each first operation unit obtains the first sub-data part of the second operand, it can determine the position of the first sub-operand in the first sub-data part according to the second index identification part, and then perform a first operation on each sub-operand in the first operand and the first sub-operand, thereby obtaining the first operation result of the first instruction.

[0179] For example, corresponding to Figure 4A In an embodiment of the present invention, the micro-architecture includes a first operation unit A and a first operation unit B. Furthermore, the first operation unit A and the first operation unit B both include a multiplexer.

[0180] The first operation unit A can select the second element Zm_elmt[1] in the first sub-data part m0: Zm_elmt[0], Zm_elmt[1] as the first sub-operand according to the multiplexer based on the second index identification part 1. Then the first operation unit A operates the first element Zn_elmt[0] in the first sub-data part of the source vector Zn with the first sub-operand Zm_elmt[1] based on the operation code, thereby obtaining the first element Zf_elmt[0] in the result vector Zf. Similarly, the second element Zn_elmt[1] in the first sub-data part of the source vector Zn is operated with the first sub-operand Zm_elmt[1] to obtain the second element Zf_elmt[1] in the vector Zf.

[0181] The first operation unit B can also select the second element Zm_elmt[1] in the first sub-data part m0: Zm_elmt[0], Zm_elmt[1] as the first sub-operand according to the multiplexer based on the second index identification part 1. Then, based on the operation code, the first element Zn_elmt[2] in the second sub-data part of the source vector Zn is operated with the first sub-operand Zm_elmt[1] to obtain the third element Zf_elmt[2] in the result vector Zf. Similarly, the second element Zn_elmt[3] in the second sub-data part of the source vector Zn is operated with the first sub-operand Zm_elmt[1] to obtain the fourth element Zf_elmt[3] in the vector Zf. Then, a part of the elements f0 of the result vector Zf: Zf_elmt[0], Zf_elmt[1] is output by the first operation unit A, and another part of the elements f1: Zf_elmt[2], Zf_elmt[3] is output by the operation unit B.

[0182] Exemplarily, during the operation of the vector instruction in the above index mode, the various first operation units do not need to be coupled to each other, and do not need to transmit data to each other, thereby reducing the delay of the pipeline and the complexity of control, and there is no need to add additional circuits (such as multiplexers, etc.) between the first operation unit and the register file, thereby reducing the delay of the data transmission process between the register file and the first operation unit, so as to improve the performance of the processor of the electronic device. It can be understood that the above scheme can meet the normal vector instruction operation process and the index mode vector instruction operation process, and has good applicability.

[0183] The electronic devices involved in the above embodiments are introduced below.

[0184] For example, Figure 6 According to some embodiments of the present application, a schematic structural diagram of an electronic device 100 is shown.

[0185] The electronic device 100 can be used to implement the data processing methods provided in the aforementioned embodiments.

[0186] like Figure 6 As shown, the electronic device 100 includes one or more processors 101, a system memory 102, a non-volatile memory (NVM) 103, a communication interface 104, an input / output device 105, and a system control logic unit 106 for coupling the processor 101, the system memory 102, the non-volatile memory 103, the communication interface 104 and the input / output (I / O) device 105. Among them:

[0187] The processor 101 may include one or more processing units, for example, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a microprocessor (MCU), an artificial intelligence (AI) processor or a programmable logic device (field programmable gate array, FPGA), a neural network processor (neural-network processing unit, NPU), etc. The processing module or processing circuit may include one or more single-core or multi-core processors. In some embodiments, a micro-architecture may be configured in the CPU to perform operations on vector instructions in index mode.

[0188] The system memory 102 is a volatile memory, such as a random-access memory (RAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc. The system memory is used to temporarily store data and / or instructions. For example, in some embodiments, the system memory 102 can be used to store operands corresponding to instructions, and can also be used to store instructions of the data processing methods provided in the aforementioned embodiments.

[0189] The non-volatile memory 103 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, the non-volatile memory 103 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as a hard disk drive (HDD), a compact disc (CD), a digital versatile disc (DVD), a solid-state drive (SSD), etc. In some embodiments, the non-volatile memory 103 may also be a removable storage medium, such as a secure digital (SD) memory card, etc. In other embodiments, the non-volatile memory 103 may be used to store instructions of the data processing methods provided in the aforementioned embodiments, etc.

[0190] In particular, the system memory 102 and the non-volatile memory 103 may respectively include: a temporary copy and a permanent copy of the instruction 107. The instruction 107 may include: when executed by at least one of the processors 101, the electronic device 100 implements the data processing method provided by each embodiment of the present application.

[0191] The communication interface 104 may include a transceiver for providing a wired or wireless communication interface for the electronic device 100, thereby communicating with any other suitable device through one or more networks. In some embodiments, the communication interface 104 may be integrated into other components of the electronic device 100, for example, the communication interface 104 may be integrated into the processor 101. In some embodiments, the electronic device 100 may communicate with other devices through the communication interface 104.

[0192] The input / output (I / O) device 105 may include input devices such as a keyboard, a mouse, etc., and output devices such as a display, etc. A user may interact with the electronic device 100 through the input / output (I / O) device 105 .

[0193] The system control logic unit 106 may include any suitable interface controller to provide any suitable interface with other modules of the electronic device 100. For example, in some embodiments, the system control logic unit 106 may include one or more memory controllers to provide interfaces to the system memory 102 and the non-volatile memory 103.

[0194] In some embodiments, at least one of the processors 101 may be packaged together with the logic of one or more controllers for the system control logic unit 106 to form a system in package (SiP). In other embodiments, at least one of the processors 101 may also be integrated with the logic of one or more controllers for the system control logic unit 106 on the same chip to form a system-on-chip (SoC).

[0195] Understandably, Figure 6 The structure of the electronic device 100 shown is only an example. In other embodiments, the electronic device 100 may include more or fewer components than shown, or combine some components, or separate some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0196] It is understandable that the electronic device 100 can be any electronic device, including but not limited to a mobile phone, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, etc., and the embodiments of the present application are not limited thereto.

[0197] The embodiments of the present application also provide a program product, which, when executed on an electronic device, can enable the electronic device to implement the methods provided in the aforementioned embodiments.

[0198] An embodiment of the present application further provides a readable storage medium, in which one or more programs are stored. When the one or more programs are executed by an electronic device, the electronic device implements the methods provided in the aforementioned embodiments.

[0199] The various embodiments of the mechanism disclosed in the present application can be implemented in hardware, software, firmware or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device and at least one output device.

[0200] Program code can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor, a microcontroller, an application specific integrated circuit, or a microprocessor.

[0201] Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

[0202] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed over a network or through other computer-readable media. Therefore, the machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to floppy disks, optical disks, optical discs, compact disc-read only memory (CD-ROMs), magneto-optical disks, read-only memory (ROM), random-access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or tangible machine-readable storage for transmitting information using the Internet in electrical, optical, acoustic or other forms of propagation signals (e.g., carrier waves, infrared signals, digital signals, etc.). Therefore, the machine-readable medium includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0203] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0204] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0205] It should be noted that, in the examples and description of the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprise one" do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0206] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present application.

Claims

1. A data processing method, applied to an electronic device, characterized in that: The processor of the electronic device includes a register file and N first operation units; wherein the register file includes a plurality of registers and a plurality of read ports, each of the read ports includes N sub-ports, and one of the sub-ports is used to read one sub-data portion of the N sub-data portions of the operand stored in the register, where N is an integer greater than 1; the method includes: The processor detects a first instruction for performing a first operation in the N first operation units, where the first instruction includes an index identifier; The first operation includes operations between each sub-operand in the first operand and the first sub-operand indicated by the index identifier in the second operand, the first operand is an operand in a first register of the multiple registers, and the second operand is an operand in a second register of the multiple registers; The processor obtains N sub-data parts of the first operand from the first register through N sub-ports of the first read port among the multiple read ports, and sends the N sub-data parts to the N first operation units respectively. and, obtaining a first sub-data portion of the second operand from the second register through N sub-ports of a second read port among the plurality of read ports, and sending the first sub-data portion to the N first operation units, wherein the first sub-data portion is a sub-data portion where the first sub-operand is located among the N sub-data portions of the second operand; The processor obtains the operation result between the sub-data part of the first operand allocated to each first operation unit and the first sub-operand through each first operation unit.

2. The method according to claim 1, characterized in that The first instruction includes a first register address of the first register; The acquiring, according to the N sub-ports of the first read port among the multiple read ports, the N sub-data parts of the first operation data from the first register respectively, comprises: Based on the first register address, determine from the plurality of registers that the first operand is located in the first register, and based on N subports of the first read port, obtain the N sub-data portions from the first register; The N sub-ports of the first read port respectively correspond to the N sub-data parts in the first register.

3. The method according to claim 1, characterized in that The first instruction further includes a second register address of the second register, and the index identifier includes a first index identifier portion; The acquiring, according to the N sub-ports of the second read port among the multiple read ports, the first sub-data parts where the N first sub-operands are located from the second register respectively, comprises: determining, based on the second register address, from the plurality of registers that the second operand is located in the second register; determining, based on the first index identification portion, that the first sub-operand is located in the first sub-data portion; According to the N sub-ports of the second read port, the first sub-data parts where the N first sub-operands are located are respectively obtained from the second register.

4. The method according to claim 3, characterized in that The index identifier includes a second index identifier part in addition to the first index identifier part, and the method further includes: According to the second index identification part, the first sub-data is determined from the first sub-data part, and according to each of the first operation units, each sub-operand of the sub-data part of the first operand received by each of the first operation units is subjected to the first operation with the first sub-operand.

5. The method according to claim 1, characterized in that The N sub-ports of the second read port include a first sub-port, and the N first operation units include a first sub-operation unit associated with the first sub-port, and the first sub-port is used to distribute the acquired first sub-data portion to the first sub-operation unit.

6. The method according to claim 3, characterized in that The number of bits of the index identifier is determined according to the number of sub-operands in the second operand; The first index identification part is the first m bits of the index identification, m=log2(N), and N is an exponent of 2.

7. The method according to claim 1, characterized in that One of the sub-data parts includes at least one sub-operand.

8. The method according to claim 1, characterized in that: The first instruction is a vector instruction in index mode.

9. An electronic device, characterized in that: The invention comprises: a memory for storing instructions; At least one processor is used to execute the instructions so that the electronic device implements the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The readable storage medium stores instructions, and when the instructions are executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 8.

11. A computer program product, characterized in that When the computer program product is executed on a device, the device is caused to perform the method according to any one of claims 1 to 8.

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