Byte code generation method, machine code generation method and equipment

Abstract

The embodiment of the invention provides a byte code generation method and device and a machine code generation method and device, and the byte code generation method comprises the steps that a target source code is obtained, first processing is applied to the target source code, and the first processing comprises the steps that a target statement used for integer operation in the target source code is replaced with a preset target function; according to the first processed target source code, a target byte code is generated, the target byte code comprises a byte code instruction generated according to a preset function, and the byte code instruction indicates that integer operation corresponding to the target statement is executed through a preset machine instruction sequence and overflow check for the integer operation is executed.

Description

Technical Field

[0001] The embodiments of this specification belong to the field of blockchain and virtual machine technology, and in particular, to a bytecode generation method, a machine code generation method and a device. Background Art

[0002] In scenarios where applications or programs are run based on virtual machines, such as in scenarios where smart contracts are run, integer calculations with overflow checks are often used extensively to ensure the security of integer calculations. The existing method for performing overflow checks on integer operations can perform overflow checks by forming a check logic using multiple bytecode instructions, or by calling the API (Application Programming Interface) of the host runtime environment of the virtual machine to perform overflow checks. However, in the scheme of checking overflows through multiple bytecode instructions, multiple bytecode instructions are often compiled into excessive machine instructions during actual execution, thereby generating and executing a large number of machine instructions during the actual operation of the application, and the computing performance is poor. The scheme of performing overflow checks through the host API will result in frequent switching between the virtual machine and the host runtime environment, which can bring additional overhead for function calls and memory operations, with a large computing cost and poor computing performance. Summary of the invention

[0003] The purpose of the present invention is to provide a bytecode generation method and a machine code generation method, which can perform overflow checks on integer operations with lower computational cost and higher efficiency in a running scenario of an application or program based on a virtual machine.

[0004] To achieve the above-mentioned purpose, the first aspect of the present specification provides a bytecode generation method, comprising: obtaining a target source code, applying a first processing to the target source code, the first processing comprising: replacing a target statement for integer operation in the target source code with a preset target function; generating a target bytecode according to the target source code after the first processing, the target bytecode comprising bytecode instructions generated according to the preset function, the bytecode instructions instructing to execute the integer operation corresponding to the target statement through a preset machine instruction sequence, and to perform an overflow check on the integer operation.

[0005] The second aspect of this specification provides a method for generating a machine code, comprising: obtaining a target bytecode obtained by the above method; generating a target machine code according to the target bytecode and the target processor type, wherein the target machine code includes a machine instruction sequence determined according to the above bytecode instructions.

[0006] A third aspect of the present specification provides a computing device, comprising: a processor; and a memory, wherein a program is stored, wherein when the processor executes the program, the following operations are performed: obtaining a target source code, applying a first processing to the target source code, the first processing comprising: replacing a target statement for integer operations in the target source code with a preset target function; generating a target bytecode based on the target source code after the first processing, the target bytecode comprising bytecode instructions generated according to the preset function, the bytecode instructions indicating the execution of integer operations corresponding to the target statements through a preset machine instruction sequence, and an overflow check for the integer operations.

[0007] In the bytecode generation scheme and machine code generation scheme provided in the embodiments of this specification, a target source code can be obtained, and a first process is applied to the target source code, including replacing the target statement for integer operations in the target source code with a preset target function. Furthermore, a target bytecode can be generated based on the target source code after the first process, and the target bytecode includes a bytecode instruction generated according to a preset function, and the bytecode instruction indicates that the integer operation corresponding to the target statement is executed through a preset machine instruction sequence, and an overflow check for the integer operation is performed. After obtaining the target bytecode, a target machine code can be generated based on the target bytecode and the target processor type, and the target machine code includes a machine instruction sequence determined according to the above-mentioned bytecode instruction. Through this method, in the running scenario of an application or program based on a virtual machine, an overflow check can be performed on integer operations with a lower computational cost and more efficiently. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0009] Figure 1 It is a schematic diagram of a scheme for integer operation overflow checking in a virtual machine environment;

[0010] Figure 2 It is a schematic diagram of another solution for integer operation overflow checking in a virtual machine environment;

[0011] Figure 3 is a schematic diagram of a bytecode generation method in an embodiment of this specification;

[0012] Figure 4 is a flow chart of a bytecode generation method in an embodiment of this specification;

[0013] Figure 5 is a flow chart of a method for generating a machine code in an embodiment of this specification;

[0014] Figure 6 It is an architectural diagram of a bytecode generation device in an embodiment of this specification;

[0015] Figure 7 It is an architectural diagram of a machine code generation device in one embodiment of this specification. DETAILED DESCRIPTION

[0016] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this specification.

[0017] As mentioned above, in scenarios where applications or programs are run based on virtual machines, such as in scenarios where smart contracts are run, integer calculations with overflow checks are often used extensively to ensure the security of integer calculations. Overflow checks (OverflowCheck) are used to detect and process overflow errors that may occur during operations. Overflow errors occur when the calculation result exceeds the range that can be represented by the data type. When the result of an integer operation exceeds the maximum value of a specific integer type or is less than its minimum value, an integer overflow error occurs. There are existing solutions for overflow checking of integer operations. One is to check whether there is an overflow by forming a check logic through bytecode instructions. This solution can be called a solution for checking overflow through bytecode instructions. The other is to perform overflow checks by calling the host API (Application Programming Interface) of the virtual machine running environment. This solution can be called a solution for checking overflow by calling the host environment API. However, in actual production scenarios, the solution for checking overflow through bytecode instructions often requires a large number of bytecode instructions to check whether there is an overflow. Moreover, due to the differences in data processing architecture between the virtual machine on which bytecode depends and the processor on which machine code depends, these bytecode instructions are often compiled into excessive machine instructions and then executed when the application is actually running, resulting in poor computing performance, especially in smart contract running scenarios that make extensive use of integer calculations.

[0018] Figure 1 This is a schematic diagram of a solution for integer operation overflow checking in a virtual machine environment. Figure 1As shown, the overflow logic logic composed of bytecode instructions may include multiple bytecode instructions, such as bytecode instruction 1, bytecode instruction 2, bytecode instruction 3... These bytecode instructions usually perform overflow checks on integer operations based on the data processing mode of the virtual machine. When the application is actually running, these bytecode instructions are often compiled into machine instructions and then run. However, since bytecode instructions usually do not have a one-to-one correspondence with machine code instructions on a specific processor (Processor), there is often a difference in the data processing architecture between the virtual machine on which the bytecode depends and the processor on which the machine code depends. For example, the WebAssembly (Wasm) virtual machine is a virtual machine for running WebAssembly bytecodes, which has a stack-based data processing architecture, while the processor usually has a register-based data processing architecture. As a result, the compilation of bytecode instructions into machine code instructions is usually not one-to-one, and each bytecode instruction in multiple bytecode instructions can be actually compiled into one or more machine code instructions, thereby generating and executing a large number of machine instructions when the application is actually running, resulting in poor computing performance.

[0019] Figure 2 is a schematic diagram of another solution for integer operation overflow checking in a virtual machine environment. Figure 2 As shown in the figure, if the host operating environment of the virtual machine pre-sets an API for overflow checking of integer operations, the API of the host operating environment can be called to perform overflow checking on integer operations when integer operations are performed inside the virtual machine. However, the problem with this solution is that it will lead to frequent switching between the bytecode operating environment and the host operating environment, thereby bringing additional overhead of function calls and memory operations, high computational cost, and poor computational performance.

[0020] In order to solve the above technical problems, the embodiments of this specification propose a bytecode generation method and a corresponding machine code generation method. Figure 3 FIG. 1 is a schematic diagram of a method for generating bytecodes in an embodiment of the present specification. Figure 3 As shown, for example, the application source code containing integer operations written in a high-level programming language can be compiled into bytecodes, and the overflow check for integer operations is indicated by a specific bytecode instruction in the bytecode. The bytecode instruction itself does not execute the overflow check logic based on the virtual machine, but instructs to perform overflow check on integer operations through a preset machine instruction sequence. Thereafter, when the application is actually running, a machine code can be generated and run according to the bytecode, and the machine code includes the machine instruction sequence executed by the bytecode instruction, and the overflow check for integer operations is performed through the machine instruction sequence.

[0021] The advantages of this method are: first, the generated bytecode does not include a large number of bytecode instructions that actually execute the overflow check logic, but only represents the overflow check for integer operations through, for example, a specific placeholder instruction. While ensuring the integer overflow check when the program is actually running, especially in the scenario of high-frequency integer operations, the number of instructions used for integer overflow checks in the bytecode is greatly reduced. Second, the overflow check of integer operations can be performed directly through a machine instruction sequence. Compared with the solution of calling the host environment API to check the overflow, additional function calls and memory accesses are avoided, and the computing performance is better. Third, compared with the solution of checking overflow through bytecode instructions, the overflow check of integer operations is performed directly through a machine instruction sequence, and the characteristics of different processors can be fully utilized. For example, in some embodiments, the overflow check instruction of a specific processor can be used to perform overflow checks, further improving computing performance.

[0022] A bytecode generation method provided by an embodiment of this specification is further described below. Figure 4 FIG. 1 is a flow chart of a method for generating bytecode in an embodiment of this specification. Figure 4 As shown, the method at least comprises the following steps:

[0023] Step S401: obtaining a target source code, and applying a first process to the target source code, wherein the first process includes: replacing a target statement for integer operation in the target source code with a preset target function;

[0024] Step S403: Generate a target bytecode based on the target source code after the first processing, wherein the target bytecode includes bytecode instructions generated according to the preset function, and the bytecode instructions indicate executing integer operations corresponding to the target statements through a preset machine instruction sequence, and performing overflow checks on the integer operations.

[0025] First, in step S401, a target source code is obtained and a first process is applied to the target source code. The first process may be: a target statement for integer operation in the target source code is replaced with a preset target function. The target function indicates to execute integer operation of the target statement and to perform overflow check on the integer operation.

[0026] In different embodiments, the target source code may be a source code (Source Code) written in different specific high-level programming (High Level Programming Language) languages. In one embodiment, for example, it may be one of C++, C# (C Sharp), Python, Java, etc. The target statement is a statement used for integer operations in the target source code. In different embodiments, the target statement used for integer operations may not be used, and the target function used to replace the target statement may also be different. In different embodiments, the type of integer operations in the target statement (for example, multiplication or addition, and the integer operations of division and addition are essentially multiplication and addition) may be different. Therefore, in different embodiments, the target statement may be replaced according to the target function corresponding to the type of integer operations in the target statement. In one embodiment, the function may also include parameters used for integer operations in the target statement.

[0027] In one example, the target statement may be, for example, a C++ statement: "int result = a + b;". The target function used to replace the target statement may be, for example, "checked_add (a, b, &result)", where the function indicates to execute the integer addition operation of the target statement and perform overflow check on it.

[0028] Then, in step S403, a target bytecode may be generated according to the target source code after the first processing. The target bytecode may include bytecode instructions generated according to a preset function, and the bytecode instructions may instruct to execute integer operations corresponding to the target statement through a preset machine instruction sequence, and to perform overflow checks on integer operations.

[0029] Bytecode is a low-level code representation generated by a compiler that is independent of specific hardware and operating system. It consists of a series of bytecode instructions, which are not directly executed on the hardware of the target machine, but need to be interpreted or further compiled in a specific virtual machine (VM) environment before they can run. In different embodiments, the target bytecode can be different specific types of bytecodes, which is not limited in this specification. In one embodiment, for example, it can be Wasm (WebAssembly) bytecode.

[0030] In different embodiments, the representation form of the bytecode instruction generated according to the preset function may be different. In one embodiment, the bytecode instruction may point to an external call instruction (call) of a preset machine instruction sequence. In different embodiments, the type of integer operation in the target statement may be different, and the type of parameters participating in the integer operation (e.g., signed or unsigned 32-bit integers, signed or unsigned 64-bit integers, etc.) may also be different. Therefore, in different embodiments, a machine instruction sequence corresponding to the type of integer operation and the type of parameters participating in the integer operation may be indicated to execute the integer operation corresponding to the target statement and to perform an overflow check for the integer operation. In one embodiment, the bytecode instruction may be specifically expressed as: "(call$checked_i32_add(local.get 0)(local.get1))", wherein call represents an external call instruction, and $checked_i32_add represents a machine instruction sequence pointing to a preset execution of signed 32-bit integer addition and overflow check.

[0031] Machine code is a binary code that can be directly executed by a computer, and is the underlying interactive language between computer hardware and software. Generally, different processor architectures (such as x86, ARM, etc.) have different machine instruction sets, so the corresponding machine codes are also different. The machine instruction sets of different generations of processors with the same processor architecture are often different, and the corresponding machine codes may also be different. In different embodiments, the preset processor type may be different. In one embodiment, for example, it may be one or more of x86, x64, ARM32, and ARM64. In addition, integers generally have multiple subtypes, such as signed 8-bit integers (i8), signed 16-bit integers (i16), signed 32-bit integers (i32), signed 64-bit integers (i64), signed 128-bit integers (i128), unsigned 8-bit (u8), unsigned 16-bit (u16), unsigned 32-bit (u32), unsigned 64-bit (u64), unsigned 128-bit (u128), etc. Among them, a signed number refers to a number that can represent a positive number, a negative number, and zero, and a signed number refers to a number that can represent a positive number and zero. In order to facilitate overflow checks on integer operations of different integer operation types and operation parameter types on different processor types. Different corresponding machine instruction sequences can be set in advance for different processor types, integer operation types, and operation parameter types. Therefore, in one embodiment, the preset machine instruction sequence may include a machine instruction sequence for performing integer operations on a preset processor type for the integer operation type and operation parameter type corresponding to the target statement, and performing overflow checks on the integer operations.

[0032] In some scenarios, the machine instruction set of the processor type (e.g., X64) on which the machine code is based includes specific machine instructions for performing addition operations of various parameter types and performing overflow checks on them. In order to perform overflow checks on integer operations more efficiently, when the machine code is used to run a specific type of integer addition operation on the processor type, integer operations and overflow checks can be performed by specific machine instructions. Therefore, in one embodiment, the target statement may be a statement for integer addition. The processor type may include a first processor type (e.g., an X64 processor), the machine instruction set corresponding to the first processor type includes a first instruction for performing integer addition and applying overflow checks to integer addition, the machine instruction sequence includes a first machine instruction sequence for execution on the first processor type, and the first machine instruction sequence includes the first instruction. In different specific embodiments, the specific machine instructions included in the first machine instruction sequence may be different. In a specific example, the first machine instruction sequence may, for example, be:

[0033] "addl%edi,%esi / / Addition instruction with overflow check

[0034] jo$overflowLabel"

[0035] Among them, addl represents a machine instruction for adding %edi and %esi and performing overflow check on the addition operation, and "jo$overflowLabel" means that if the addition operation causes overflow, it jumps to the position of $overflowLabel for processing.

[0036] In some scenarios, the machine instruction set of the processor type (e.g., ARM64) on which the machine code is based does not include specific machine instructions that can perform integer addition operations of specific parameter types (e.g., signed or unsigned 8-bit or 16-bit integers (i8 / i16 / u8 / u16)) and perform overflow checks on the operations. In this scenario, corresponding machine instruction sequences can be set for integer addition operations of these parameter types, respectively. Specifically, in one embodiment, the target statement can be a statement for integer addition of a predetermined first digit, where the first digit is 8 bits or 16 bits. The processor type may include a second processor type, and the machine instruction sequence includes a second machine instruction sequence for execution on the second processor type. The second machine instruction sequence can be used to perform the following process: expand the first parameter of the first digit to 32 bits, expand the second parameter of the first digit to 32 bits, apply a summation operation to the expanded first parameter and the expanded second parameter to obtain a 32-bit summation result; apply an expansion operation to the first low-order digit in the summation result to obtain a 32-bit expansion result, and determine whether the sum between the first parameter and the second parameter overflows based on whether the summation result and the expansion result are the same. In different specific embodiments, the specific machine instructions included in the first machine instruction sequence may be different. In a specific example, the parameter type of integer addition is a signed 8-bit integer or a signed 16-bit integer (i8 / i16), and the first machine instruction sequence can be, for example:

[0037] "sxtb w8,w0

[0038] add w8,w8,w1,sxtb

[0039] sxtb w9,w8

[0040] cmp w9,w8

[0041] b.ne$overflowLabel"

[0042] Among them, "sxtb w8,w0" is used to expand the signed 8-bit / 16-bit w0 to 32 bits, "add w8,w8,w1,sxtb" expands the signed 8-bit / 16-bit w1 to 32 bits, applies the sum operation to the expanded w0 and w1, obtains the 32-bit sum result and saves it in w8. "sxtb w9,w8" expands the lower 8 bits / lower 16 bits of w8 to 32 bits and saves it in w9 (except the lower 8 bits / lower 16 bits, the values ​​of the remaining bits are all 0). "cmp w9,w8 b.ne$overflowLabel" means to determine whether the sum of w0 and w1 overflows according to whether w8 and w9 are the same.

[0043] In another specific example, the parameter type of integer addition is a signed 8-bit integer or a signed 16-bit integer (u8 / u16), and the first machine instruction sequence may be, for example:

[0044] “and w8,w0,#0xffff

[0045] Add w8,w8,w1,uxth

[0046] and w9,w8,#0xffff

[0047] cmp w9,w8

[0048] b.ne$overflowLabel"

[0049] Among them, "and w8,w0,#0xffff" is used to expand the unsigned 8-bit / 16-bit w0 to 32 bits, "Add w8,w8,w1,uxth" expands the signed 8-bit / 16-bit w1 to 32 bits, applies the sum operation to the expanded w0 and w1, obtains the 32-bit sum result and saves it in w8. "sxtb w9,w8" expands the lower 8-bit / lower 16-bit of w8 to 32 bits and saves it in w9 (except the lower 8-bit / lower 16-bit, the values ​​of the remaining bits are all 0). "cmp w9,w8 b.ne$overflowLabel" determines whether the sum of w0 and w1 overflows according to whether w8 and w9 are the same.

[0050] In some scenarios, the machine instruction set of the processor type (e.g., ARM64) on which the machine code is based only includes machine instructions for performing integer addition of a specific parameter type (e.g., i32 / i64 / u32 / u64) and performing overflow checks on the operation. When the machine code is used to run integer addition operations of a specific parameter type on the processor type, integer operations and overflow checks can be performed by specific machine instructions. Therefore, in one embodiment, the target statement can be a statement for integer addition of a predetermined second digit, and the second digit is 32 bits or 64 bits. The processor type includes a second processor type, and the machine instruction set corresponding to the second processor type includes a second instruction for performing integer addition of a second digit and applying overflow checks to integer addition of the second digit, and the machine instruction sequence includes a third machine instruction sequence for execution on the second processor type, and the third machine instruction sequence includes the second instruction. In different specific embodiments, the specific machine instructions included in the first machine instruction sequence may be different.

[0051] In a specific example, the third machine instruction sequence may be, for example:

[0052] "adds w8,w0,w1 / / Addition instruction with overflow check

[0053] b.vs$overflowLabel"

[0054] Among them, adds represents a machine instruction for performing a 32 / 64-bit addition operation on w0 and w1 and performing an overflow check on the addition operation, and "b.vs$overflowLabel" means that if the addition operation causes an overflow, it jumps to the location of $overflowLabel for processing.

[0055] In some scenarios, the machine instruction set of the processor type (e.g., ARM64) on which the machine code is based does not include specific machine instructions that can perform integer addition operations of specific parameter types (e.g., signed or unsigned 128-bit integers (i128 / u128)) and perform overflow checks on the operations, but an efficient machine instruction sequence can be obtained by performing integer addition operations of other parameter types (e.g., signed or unsigned 64-bit integers (i64 / u64)) and performing overflow checks on the operations. Therefore, in one embodiment, the target statement can be a statement for integer addition of 128-bit numbers. The processor type can include a second processor type, and the machine instruction sequence includes a fourth machine instruction sequence for execution on the second processor type. The fourth machine instruction sequence can be used to perform the following process: determine the carry flag by summing the first part of the low 64 bits of the 128-bit first parameter and the second part of the low 64 bits of the 128-bit second parameter, determine the overflow flag according to the summing of the third part of the high 64 bits of the first parameter, the fourth part of the high 64 bits of the second parameter, and the carry flag; determine whether the sum between the first parameter and the second parameter overflows according to the overflow flag. In different specific embodiments, the specific machine instructions included in the fourth machine instruction sequence may be different.

[0056] In a specific example, the fourth machine instruction sequence may be, for example:

[0057] "adds x8,x0,x2

[0058] adcs x9,x1,x3

[0059] b.vs$overflowLabel"

[0060] Among them, adds x8,x0,x2 represents the sum operation of the lower 64 bits of the first parameter and the lower 64 bits of the second parameter, and the operation also determines the carry flag, adcs x9,x1,x3 represents the sum operation of the upper 64 bits of the first parameter, the upper 64 bits of the second parameter, and the carry flag, and the operation also determines the overflow flag. b.vs$overflowLabel means that if the overflow flag indicates overflow, it is determined that the sum between the first parameter and the second parameter overflows.

[0061] In addition to integer addition, integer operations also include integer multiplication. In different embodiments, for integer multiplication of processor types and different parameter types, corresponding different machine instruction sequences can be preset. In one embodiment, the target statement can be a statement for integer multiplication. The processor type may include a first processor type (e.g., X64), the machine instruction set corresponding to the first processor type includes a third instruction for performing integer multiplication and applying overflow check to integer multiplication, and the machine instruction sequence includes a fifth machine instruction sequence for execution on the first processor type, and the fifth machine instruction sequence includes the third instruction. In different specific embodiments, the specific machine instructions included in the fifth machine instruction sequence may be different.

[0062] In a specific example, the fifth machine instruction sequence may be, for example:

[0063] "imul%edi,%esi;

[0064] jo$overflowLabel"

[0065] Among them, imul represents a machine instruction for multiplying the signed %edi and %esi and performing overflow check on the multiplication operation, and "jo$overflowLabel" means that if the multiplication operation causes overflow, it jumps to the location of $overflowLabel for processing.

[0066] In another embodiment, the target statement may be a statement for integer multiplication of a predetermined signed first digit, the first digit being 8 bits or 16 bits. The processor type may include a second processor type (e.g., ARM64), and the machine instruction sequence includes a sixth machine instruction sequence for execution on the second processor type. The sixth machine instruction sequence may be used to perform the following process: extending the first parameter of the signed first digit to 32 bits, extending the second parameter of the signed first digit to 32 bits, applying a product operation to the extended first parameter and the extended second parameter to obtain a 32-bit product result; performing an extension operation on the first digit of the low bit of the product result to obtain a 32-bit extended result, and determining whether the product between the first parameter and the second parameter overflows according to whether the product result and the extended result are the same. In different specific embodiments, the specific machine instructions included in the sixth machine instruction sequence may be different.

[0067] In a specific example, the sixth machine instruction sequence may be, for example:

[0068] "sxth w8,w1

[0069] sxth w9,w0

[0070] mul w8,w9,w8

[0071] sxth w9,w8

[0072] cmp w9,w8

[0073] b.ne$overflowLabel"

[0074] Among them, "sxth w8,w1" means to extend the signed w1 to 32 bits and save it in w8. "sxth w9,w0" means to extend the signed w0 to 32 bits and save the result in w9. "mul w8,w9,w8" means to apply the product operation to w9 and w8 and save the result in w8. "sxth w9,w8 cmp w9,w8" means to perform the extension operation on the lower 8 bits / 16 bits of w8 (determined by the number of bits of w0 and w1), obtain the 32-bit extension result and save it in w9, and determine whether w9 and w8 are the same. "b.ne$overflowLabel" means if w9 and w8 are not the same, jump to the location of $overflowLabel for overflow processing.

[0075] In another embodiment, the target statement may be a statement for integer multiplication of a predetermined unsigned first digit, the first digit being 8 bits or 16 bits. The processor type may include a second processor type (e.g., ARM64), and the machine instruction sequence includes a seventh machine instruction sequence for execution on the second processor type. The seventh machine instruction sequence is used to perform the following process: extending the first parameter of the unsigned first digit to 32 bits, extending the second parameter of the unsigned first digit to 32 bits, applying a product operation to the extended first parameter and the extended second parameter to obtain a 32-bit product result; determining whether the product between the first parameter and the second parameter overflows according to whether the upper 16 bits of the product result are all 0. In different specific embodiments, the specific machine instructions included in the seventh machine instruction sequence may be different.

[0076] In a specific example, the seventh machine instruction sequence may be, for example:

[0077] “and w8,w1,#0xffff

[0078] and w9,w0,#0xffff

[0079] mul w8,w9,w8

[0080] tst w8,#0xffff0000

[0081] b.ne$overflowLabel"

[0082] Among them, "and w8,w1,#0xffff" is used to expand the unsigned w1 to 32 bits, "and w9,w0,#0xffff" expands the unsigned w0 to 32 bits, and "mul w8,w9,w8" means to apply the product operation to the expanded w1 and the expanded w0, obtain the 32-bit product result and save it in w8. "tst w8,#0xffff0000" is used to determine whether the upper 16 bits of w8 are all 0, and "b.ne$overflowLabel" jumps to the position of $overflowLabel for overflow processing if the upper 16 bits of w8 are not all 0.

[0083] In another embodiment, the target statement may be a statement for signed 32-bit integer multiplication. The processor type may include a second processor type (e.g., ARM64), and the machine instruction sequence includes an eighth machine instruction sequence for execution on the second processor type. The eighth machine instruction sequence is used to perform the following process: determine a signed 64-bit first value based on the product result of the signed 32-bit first parameter and the signed 32-bit second parameter, and logically shift the first value right by 32 bits to obtain a second value; determine whether the product between the first parameter and the second parameter overflows based on whether the value obtained by arithmetic right shifting the first value by 31 bits is equal to the second value. In different specific embodiments, the specific machine instructions included in the eighth machine instruction sequence may be different.

[0084] In a specific example, the eighth machine instruction sequence may be, for example:

[0085] "smull x8,w0,w1

[0086] lsr x9,x8,#32

[0087] cmp w9,w8,asr#31

[0088] b.ne$overflowLabel"

[0089] Among them, "smull x8,w0,w1" is used to determine the product of the signed 32-bit w0 and the signed 32-bit w1 and save it to the 64-bit x8. "lsr x9,x8,#32cmp w9,w8,asr#31" means to logically shift x8 by 32 bits to get x9, and then determine whether the value obtained by arithmetic right shift of w8 by 31 bits is equal to w9. "b.ne$overflowLabel" means that if w8 is not equal to w9 after arithmetic right shift of 31 bits, jump to the position of $overflowLabel for overflow processing.

[0090] In one embodiment, the target statement may be a statement for signed 64-bit integer multiplication. The processor type may include a second processor type (e.g., ARM64), and the machine instruction sequence may include a ninth machine instruction sequence for execution on the second processor type. The ninth machine instruction sequence is used to perform the following process: determine a signed 64-bit first value according to the product result of the signed 64-bit first parameter and the signed 64-bit second parameter, determine a signed 64-bit third value according to the high 64 bits of the 128-bit product result between the signed 64-bit first parameter and the signed 64-bit second parameter; determine whether the product between the first parameter and the second parameter overflows according to whether the value obtained by arithmetic right shifting the first value by 63 bits is equal to the third value. In different specific embodiments, the specific machine instructions included in the ninth machine instruction sequence may be different.

[0091] In a specific example, the ninth machine instruction sequence may be, for example:

[0092] "mul x8,x0,x1

[0093] smulh x9,x0,x1

[0094] cmp x9,x8,asr#63

[0095] b.ne$overflowLabel"

[0096] Among them, "mul x8,x0,x1" obtains the 64-bit product of the signed 64-bit x0 and the signed 64-bit w1, and saves the result in the 64-bit x8. "smulh x9,x0,x1 cmp x9,x8,asr#63" means to obtain the high 64 bits of the 128-bit product of the signed 64-bit x0 and the signed 64-bit w1, and save it in x9. Then compare whether the value obtained by arithmetic right shift of x8 by 63 bits is equal to x9. "b.ne$overflowLabel" means that if x8 is not equal to x9 after arithmetic right shift of 63 bits, jump to the position of $overflowLabel for overflow processing.

[0097] In another embodiment, the target statement may be a statement for unsigned 32-bit integer multiplication. The processor type includes a second processor type (e.g., ARM64), and the machine instruction sequence includes a tenth machine instruction sequence for execution on the second processor type. The tenth machine instruction sequence is used to perform the following process: determine an unsigned 64-bit first value based on the product result of an unsigned 32-bit first parameter and an unsigned 32-bit second parameter; determine whether the product between the first parameter and the second parameter overflows based on whether all bits after the first value is logically shifted right by 32 bits are 0. In different specific embodiments, the specific machine instructions included in the tenth machine instruction sequence may be different.

[0098] In a specific example, the tenth machine instruction sequence may be, for example:

[0099] "umull x8,w0,w1

[0100] cmp xzr,x8,lsr#32

[0101] b.ne$overflowLabel"

[0102] Among them, "umull x8,w0,w1" means to calculate the product of unsigned 32-bit integers w0+w1 within the 64-bit range and save the result in 64-bit x8, "cmp xzr,x8,lsr#32" means to determine whether all bits of x8 are 0 after logical right shift of 32 bits. "b.ne$overflowLabel" means if all bits of x8 are not 0 after logical right shift of 32 bits, jump to the position of $overflowLabel for overflow processing.

[0103] In one embodiment, the target statement may be a statement for unsigned 64-bit integer multiplication. The processor type includes a second processor type (e.g., ARM64), and the machine instruction sequence includes an eleventh machine instruction sequence for execution on the second processor type. The eleventh machine instruction sequence is used to perform the following process: determine a first value based on the upper 64 bits of the 128-bit product result of the unsigned 64-bit first parameter and the unsigned 64-bit second parameter; determine whether the product between the first parameter and the second parameter overflows based on whether all bits of the first value are 0. In different specific embodiments, the specific machine instructions included in the eleventh machine instruction sequence may be different.

[0104] In a specific example, the eleventh machine instruction sequence may be, for example:

[0105] "umulh x8,x0,x1

[0106] cmp xzr,x8

[0107] b.ne$overflowLabel"

[0108] Among them, "umulh x8,x0,x1 cmp xzr,x8" means to calculate the product of unsigned 64-bit integers x0 and x1 in the 128-bit range, and put the high 64 bits of the result into the 64-bit x8. Then, compare whether all bits of x8 are 0. "b.ne$overflowLabel" means that if all bits of x8 are not 0, jump to the position of $overflowLabel for overflow processing.

[0109] According to another embodiment of the present specification, a corresponding machine code generation method is also provided. Figure 5 is a flow chart of a method for generating a machine code in an embodiment of this specification, such as Figure 5 As shown, the method comprises at least the following steps:

[0110] S501: Get Pass Figure 1 The method shown obtains the target bytecode;

[0111] S503: Generate a target machine code according to the target bytecode and the target processor type, wherein the target machine code includes Figure 1 The bytecode instructions described in the method shown determine a sequence of machine instructions.

[0112] According to another embodiment, a bytecode generation device is also provided. Figure 6 is an architectural diagram of a bytecode generation device in an embodiment of this specification, such as Figure 6 As shown, the device 600 includes:

[0113] The first acquisition unit 61 is configured to acquire a target source code and apply a first process to the target source code, wherein the first process includes: replacing a target statement for integer operation in the target source code with a preset target function;

[0114] The first generation unit 62 is configured to generate a target bytecode based on the target source code after the first processing, wherein the target bytecode includes bytecode instructions generated according to the preset function, and the bytecode instructions indicate the execution of integer operations corresponding to the target statement through a preset machine instruction sequence, as well as overflow checks for the integer operations.

[0115] According to another embodiment, a device for generating a machine code is also provided. Figure 7 is an architecture diagram of a machine code generation device in an embodiment of this specification, such as Figure 7 As shown, the device 700 includes:

[0116] The second acquisition unit 71 is configured to acquire Figure 1 The method shown obtains the target bytecode;

[0117] The second generating unit 72 is configured to generate a target machine code according to the target bytecode and the target processor type, wherein the target machine code includes Figure 1 The bytecode described in the illustrated method refers to a certain sequence of machine instructions.

[0118] On the other hand, the present specification provides a computing device, including: a processor; and a memory, in which a program is stored, wherein when the processor executes the program, the following operations are performed: obtaining a target source code, applying a first processing to the target source code, the first processing including: replacing a target statement for integer operation in the target source code with a preset target function; generating a target bytecode based on the target source code after the first processing, the target bytecode including bytecode instructions generated according to the preset function, the bytecode instructions instructing to execute the integer operation corresponding to the target statement through a preset machine instruction sequence, and an overflow check for the integer operation.

[0119] On another aspect, the present specification provides a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute any one of the above methods.

[0120] On the other hand, the present specification provides a computer program product, including a computer program / instruction, which implements any of the above methods when executed by a processor.

[0121] In the 1990s, improvements to a technology could be clearly distinguished as hardware improvements (for example, improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the method flow). However, with the development of technology, many improvements to the method flow today can be regarded as direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement in a method flow cannot be implemented using a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask a chip manufacturer to design and produce a dedicated integrated circuit chip. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0122] The controller can be implemented in any appropriate manner, for example, the controller can take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code manner, the controller can be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, this controller can be considered as a hardware component, and the devices included therein for implementing various functions can also be regarded as structures within the hardware component. Or even, the devices for implementing various functions can be regarded as both software modules for implementing the method and structures within the hardware component.

[0123] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a server system. Of course, the present application does not exclude that with the development of computer technology in the future, the computer that implements the functions of the above embodiments may be, for example, a personal computer, a laptop computer, a vehicle-mounted human-computer interaction device, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0124] Although one or more embodiments of the present specification provide method operation steps as described in the embodiments or flow charts, more or less operation steps may be included based on conventional or non-creative means. The order of steps listed in the embodiments is only one way of executing the order of many steps, and does not represent the only execution order. When the device or terminal product in practice is executed, it can be executed in sequence or in parallel according to the method shown in the embodiments or the drawings (for example, a parallel processor or a multi-threaded processing environment, or even a distributed data processing environment). The term "include", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, product or equipment including a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such a process, method, product or equipment. In the absence of more restrictions, it is not excluded that there are other identical or equivalent elements in the process, method, product or equipment including the elements. For example, if the words first, second, etc. are used to represent the name, they do not represent any specific order.

[0125] For the convenience of description, the above devices are described in various modules according to their functions. Of course, when implementing one or more of the present specification, the functions of each module can be implemented in the same or more software and / or hardware, or the module implementing the same function can be implemented by a combination of multiple sub-modules or sub-units, etc. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0126] The present invention is described with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0127] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0129] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0130] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0131] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage, graphene storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0132] It should be understood by those skilled in the art that one or more embodiments of the present specification may be provided as a method, system or computer program product. Therefore, one or more embodiments of the present specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, one or more embodiments of the present specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0133] One or more embodiments of the present specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. One or more embodiments of the present specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0134] Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. In the description of this specification, the description of the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic representation of the above terms does not necessarily target the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0135] The above description is only an example of one or more embodiments of the present specification and is not intended to limit one or more embodiments of the present specification. For those skilled in the art, one or more embodiments of the present specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification shall be included in the scope of the claims.

Claims

1. A method for generating bytecode, comprising: Obtaining a target source code, and applying a first process to the target source code, wherein the first process comprises: replacing a target statement for integer operation in the target source code with a preset target function; According to the target source code after the first processing, a target bytecode is generated, wherein the target bytecode includes bytecode instructions generated according to the preset function, and the bytecode instructions indicate the execution of integer operations corresponding to the target statements through a preset machine instruction sequence, as well as overflow checks for the integer operations.

2. The method according to claim 1, wherein: The preset machine instruction sequence includes: a machine instruction sequence for performing integer operations on a preset processor type for an integer operation type and an operation parameter type corresponding to a target statement, and performing overflow checks on the integer operations.

3. The method according to claim 1, wherein: The target statement is a statement for integer addition; The processor type includes a first processor type, a machine instruction set corresponding to the first processor type includes a first instruction for performing integer addition and applying overflow check to the integer addition, and the machine instruction sequence includes a first machine instruction sequence for execution on the first processor type, wherein the first machine instruction sequence includes the first instruction.

4. The method according to claim 2, wherein: The target statement is a statement for integer addition of a predetermined first digit, the first digit being 8 digits or 16 digits; The processor type comprises a second processor type, the sequence of machine instructions comprises a second sequence of machine instructions for execution on the second processor type; The second machine instruction sequence is used to execute the following process: extending the first parameter of the first digit to 32 bits, extending the second parameter of the first digit to 32 bits, applying a summation operation to the extended first parameter and the extended second parameter to obtain a 32-bit summation result; applying an extension operation to the first digit of the low order in the summation result to obtain a 32-bit extension result, and determining whether the sum between the first parameter and the second parameter overflows based on whether the summation result and the extension result are the same.

5. The method according to claim 2, wherein: The target statement is a statement for integer addition of a predetermined second digit, and the second digit is 32 bits or 64 bits; The processor type includes a second processor type, the machine instruction set corresponding to the second processor type includes a second instruction for performing integer addition of a second-digit number and applying an overflow check to the integer addition of the second-digit number, and the machine instruction sequence includes a third machine instruction sequence for execution on the second processor type, and the third machine instruction sequence includes the second instruction.

6. The method according to claim 2, wherein: The target statement is a statement for integer addition of 128-bit numbers; The processor type comprises a second processor type, the sequence of machine instructions comprises a fourth sequence of machine instructions for execution on the second processor type; The fourth machine instruction sequence is used to execute the following process: determine the carry flag by summing the first part of the low 64 bits of the 128-bit first parameter and the second part of the low 64 bits of the 128-bit second parameter, and determine the overflow flag according to the summing operation of the third part of the high 64 bits of the first parameter, the fourth part of the high 64 bits of the second parameter, and the carry flag; determine whether the sum between the first parameter and the second parameter overflows according to the overflow flag.

7. The method according to claim 2, wherein: The target statement is a statement for integer multiplication; The processor type includes a first processor type, the machine instruction set corresponding to the first processor type includes a third instruction for performing integer multiplication and applying overflow check to the integer multiplication, and the machine instruction sequence includes a fifth machine instruction sequence for execution on the first processor type, and the fifth machine instruction sequence includes the third instruction.

8. The method according to claim 2, wherein: The target statement is a statement for integer multiplication of a predetermined signed first digit, the first digit being 8 bits or 16 bits; the processor type comprises a second processor type, the sequence of machine instructions comprises a sixth sequence of machine instructions for execution on the second processor type; The sixth machine instruction sequence is used to perform the following process: extending a first parameter having a signed first digit to 32 bits, extending a second parameter having a signed first digit to 32 bits, applying a product operation to the extended first parameter and the extended second parameter to obtain a 32-bit product result; An expansion operation is performed on the first low-order digit of the product result to obtain a 32-bit expansion result, and whether the product between the first parameter and the second parameter overflows is determined according to whether the product result and the expansion result are the same.

9. A method for generating a machine code, comprising: Obtain the target bytecode obtained by the method according to claim 1; A target machine code is generated according to the target bytecode and the target processor type, wherein the target machine code includes a machine instruction sequence determined according to the bytecode instruction according to claim 1.

10. A computer device comprising: processor; and a memory, wherein a program is stored, wherein when the processor executes the program, the following operations are performed: Obtaining a target source code, and applying a first process to the target source code, wherein the first process comprises: replacing a target statement for integer operation in the target source code with a preset target function; According to the target source code after the first processing, a target bytecode is generated, wherein the target bytecode includes bytecode instructions generated according to the preset function, and the bytecode instructions indicate the execution of integer operations corresponding to the target statements through a preset machine instruction sequence, as well as overflow checks for the integer operations.

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