Fault processing method of server, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a server fault processing method, a storage medium and electronic equipment, and the method comprises the steps: obtaining first time information, the first time information comprises at least one of a first moment and a second moment, the first moment is a moment when a first fault occurs, and the second moment is a moment when a second fault occurs; acquiring second time information, wherein the second time information is a third moment when the voltage regulator of the power management integrated chip is powered on; and generating a target control instruction set based on the first time information and the second time information, wherein the target control instruction set is used for controlling the server to execute a preset fault processing operation. According to the method and the device, the problems of temporary fault-free detection of the memory of the integrated PMIC chip and corresponding fault processing measures and methods in the prior art are solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of servers, and in particular, to a server fault handling method, a storage medium, and an electronic device. Background Art

[0002] In the related art, the power supply module (PMIC chip) is integrated into the memory. The PMIC chip on the memory refers to a power management integrated circuit used to manage and control the power supply of the memory. Specifically, the PMIC chip of the memory is mainly responsible for providing a stable power supply, managing and monitoring the power supply of the memory, and protecting the memory from power fluctuations and overloads. Regarding how the above-mentioned PMIC chip can perform real-time fault reporting and fault handling, no effective solution has been proposed in the prior art. Summary of the invention

[0003] The embodiments of the present application provide a server fault handling method, a storage medium, and an electronic device to at least solve the problem of temporary failure detection and corresponding fault handling measures for the memory of an integrated PMIC chip in the related art.

[0004] According to an embodiment of the present application, a server fault handling method is provided, including: obtaining first time information, the first time information including at least one of a first moment and a second moment, the first moment being the moment when a first fault occurs, and the second moment being the moment when a second fault occurs, the first fault being a fault detected by a processor on a register of a power management integrated chip, the processor being used to execute BIOS firmware, and the second fault being a fault obtained by a baseboard controller on a register of the power management integrated chip; obtaining second time information, the second time information being a third moment when a voltage regulator of the power management integrated chip is powered on; generating a target control instruction set based on the first time information and the second time information, the target control instruction set being used to control the server to perform preset fault handling operations.

[0005] In an exemplary embodiment, a target control instruction set is generated based on first time information and second time information, including: in response to a first moment being earlier than a third moment, a first control instruction in the target control instruction set is generated, the first control instruction is used to determine fault information, generate a fault log, and shield a communication channel where a faulty memory is located, the fault information includes at least an address where the fault occurs, and the fault log is generated by a baseboard controller based on the fault information.

[0006] In an exemplary embodiment, generating a target control instruction set based on first time information and second time information includes: in response to the first moment being later than the third moment, generating a second control instruction in the target control instruction set, the second control instruction being used to re-power on the server.

[0007] In an exemplary embodiment, a target control instruction set is generated based on first time information and second time information, including: in response to the second moment being later than the third moment, a third control instruction in the target control instruction set is generated, the third control instruction is used to shut down the server, repower on the server, and detect whether a first fault occurs during the server power-on process and locate the slot where the first fault occurs, and the third control instruction is also used to shield the communication channel where the faulty memory is located when the first fault occurs.

[0008] In an exemplary embodiment, determining fault information includes: using a processor to poll a register of a power management integrated chip on a memory module to obtain a query result; in response to the query result including a register fault, locating an address where the fault occurred based on the query result to obtain fault information.

[0009] In an exemplary embodiment, a method for detecting a second fault includes: obtaining memory information, the memory information including a voltage signal and a temperature signal, the voltage signal being generated by a voltage regulator when a register fails, the voltage signal being acquired by a complex programmable logic device inside a server, the temperature signal being acquired by a temperature sensor on a memory module, and the temperature signal being used to determine the temperature of the memory; determining whether the voltage signal is the same as a set voltage signal, wherein the set voltage signal is a level signal generated by a voltage regulator corresponding to the memory when the memory is normal; if the voltage signal is different from the set voltage signal, determining that a second fault has occurred in the memory corresponding to the voltage signal; determining whether the temperature of the memory is greater than a set temperature value, wherein the set temperature value is the maximum temperature allowed for normal operation of the memory; if the temperature of the memory is greater than the set temperature value, determining that a second fault has occurred in the memory corresponding to the temperature signal.

[0010] In an exemplary embodiment, re-powering on the server includes: controlling a baseboard controller to restart, and sending a power-on instruction to other target components in the server through the restarted baseboard controller.

[0011] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0012] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0013] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0014] Through the present application, by obtaining the first time information and the second time information, and controlling the server to execute the preset fault handling operation (such as alarm) based on the first time information and the second time information, the technical effect of performing fault handling according to the different types of faults and the different times of occurrence is achieved, making the fault handling more timely and intelligent, and minimizing the impact on the server. The related technology currently has no fault detection and corresponding fault handling measures for the memory of the integrated PMIC chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a hardware structure block diagram of a server device according to a server fault handling method of an embodiment of the present application;

[0016] Figure 2 is a flow chart of a method for handling a server failure according to an embodiment of the present application;

[0017] Figure 3 is a PMIC fault reporting system architecture diagram according to an embodiment of the present application;

[0018] Figure 4 This is a hardware diagram of a BMC detecting a memory power signal according to an embodiment of the present application;

[0019] Figure 5 is a flow chart of a method for handling a server failure according to an embodiment of the present application;

[0020] Figure 6 It is a flowchart of a method for handling server failures according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0023] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 1 FIG. 1 is a hardware structure block diagram of a server device of a server fault handling method according to an embodiment of the present application. Figure 1 As shown, the server device may include one or more ( Figure 1Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the server device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0024] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the fault handling method of the server in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0025] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0026] Specifically, the existing terms appearing in this application are explained as follows: NGN: Next Generation Network. DDR5: Double Data Rate 5, the fifth generation of double data rate random access memory (SDRAM) technology. PMIC: Power Management Integrated Circuit. CPLD: Complex Programmable Logic Device. TSOD: Temperature sensor on DIMM. RCD: Registering Clock Drive. BMC: Baseboard Management Controller. VR: Voltage Regulator. BIOS: Basic Input and Output System. PSU: Power Supply Unit. MUX: multiplexer. POST: Power On Self-Test. PECI: Platform Environment Control Interface.

[0027] A PMIC chip (Power Management Integrated Circuit) is an integrated circuit that integrates multiple power management functions. It is commonly used in electronic devices to manage and control power supply to provide stable power to various components and subsystems. PMIC chips can implement functions such as power switching, voltage regulation, current control, battery charge and discharge management, and temperature monitoring to ensure the normal operation and safety of the equipment. The design and selection of PMIC chips have an important impact on the power consumption, efficiency, and performance of electronic equipment.

[0028] Before DDR5 (Double Data Rate 5 fifth-generation double data rate random access memory (SDRAM) technology), the power of the memory was provided by a separate memory power supply circuit on the motherboard. Starting from DDR5, the memory has integrated the power supply module (PMIC chip) into the memory. The PMIC chip on the DDR5 memory refers to the power management integrated circuit used to manage and control the power supply of the DDR5 memory. Specifically, the PMIC chip of the DDR5 memory is mainly responsible for providing a stable power supply, power management and monitoring of the DDR5 memory, and protecting the DDR5 memory from power fluctuations and overload problems. Different DDR5 memory products may use different PMIC chips. Common PMIC chip manufacturers include Infineon, Texas Instruments, ADI, etc.

[0029] I3C is a new type of serial bus interface, the full name is Improved Inter-Integrated Circuit (Enhanced Inter-IC Communication Protocol). It was developed by the MIPI Alliance (Mobile Industry Processor Interface) to replace the I2C (Inter-Integrated Circuit) and SMBus (System Management Bus) interfaces. While maintaining backward compatibility with I2C devices, the I3C interface provides higher data transfer rates, lower power consumption, and more functions. It can be used to connect various sensors, memories, and other peripherals, and is widely used in mobile devices, the Internet of Things, automotive electronics, and other fields. The rate of the I3C interface can vary depending on the specific implementation and device support. In general, the maximum rate of the I3C interface can reach 12.5Mbps, which is several times faster than the traditional I2C interface. In addition, I3C also supports multi-host parallel transmission and high-speed data mode, which can further increase the data transfer rate.

[0030] In this embodiment, a method for handling server failure is provided. Figure 2 is a flow chart of a method for handling a server failure according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:

[0031] Step S102, obtaining first time information, the first time information includes at least one of a first moment and a second moment, the first moment is the moment when the first fault occurs, and the second moment is the moment when the second fault occurs, the first fault is a fault detected by the processor on the register of the power management integrated chip, the processor is used to execute the BIOS firmware, and the second fault is a fault detected by the baseboard controller on the register of the power management integrated chip; fault detection includes various types of detection, such as monitoring the voltage, current, temperature values ​​of each module of the PMIC, etc. When at least one of the above parameters exceeds the set threshold, an alarm is issued and the fault is detected.

[0032] Step S104, obtaining second time information, where the second time information is a third moment of powering on the voltage regulator of the power management integrated chip;

[0033] Step S106: Generate a target control instruction set based on the first time information and the second time information, where the target control instruction set is used to control the server to perform a preset fault handling operation.

[0034] Through the present application, by obtaining the first time information and the second time information, and controlling the server to execute the preset fault handling operation based on the first time information and the second time information, the technical effect of handling faults according to different types of faults and different times of occurrence is achieved, making fault handling more timely and intelligent, and minimizing the impact on the server. The related technology currently has no fault detection and corresponding fault handling measures for the memory of the integrated PMIC chip.

[0035] The execution subject of the above steps may be a server, a terminal, etc., but is not limited thereto.

[0036] In the related art, when a PMIC fails, the server will shut down directly. Since DDR5 integrates the PMIC chip into the memory for the first time, there is currently no very intuitive fault alarm and fault handling method. Based on this, the present application proposes an error reporting method and a fault handling method when a PMIC fails, which allows users to easily locate the specific memory and perform fault handling.

[0037] The execution order of step S102 and step S104 is interchangeable, that is, step S104 may be executed first, and then step S102.

[0038] like Figure 3The PMIC fault reporting system architecture diagram is shown. All devices on the DDR5 DIMM (power management integrated circuit [PMIC], thermal sensor [TS] / temperature sensor [TSOD], register clock driver [RCD]) are connected to the SPD HUB via local I3C*. The SPD HUB is connected to the CPU via the I3C* bus. All local DIMM devices (including the SPD HUB) are visible as terminal devices on the SPD I3C* bus. The SPD controller in the CPU is the I3C* master device, so that the CPU can access the PMIC on each DIMM through I3C.

[0039] like Figure 4 The figure shows the hardware diagram of BMC detecting memory power signal. The current hardware design of Intel platform is that the POWER GOOD signals of every four DIMMs are connected together to form a POWER GOOD signal connected to CPLD, and CPLD is connected to BMC, so that BMC can detect the POWER GOOD signal of memory. When the memory is normal, the POWER GOOD signal of memory is high. When PMIC fails, POWER GOOD will be pulled low. BMC can detect that the POWER GOOD signal of memory is pulled low, but BMC has no way to detect which memory the POWER GOOD signal belongs to.

[0040] The PMIC specification stipulates that 11 events will trigger internal VR disable, which means that PMIC failure will trigger VR disable of memory. When VR disable is triggered, the POWER GOOD signal of the memory will be pulled low, and the CPLD will detect the abnormal voltage of the memory. At this time, the CPLD will shut down the server. When the server is running normally, if the PMIC of a certain memory fails, the server will shut down immediately. If you send a command or manually press the power button to start the server at this time, the server cannot start normally because the POWER GOOD fail state of the memory has not been released and does not conform to the normal power-on logic. Therefore, the server will still shut down at a certain stage of startup. In the current system design, since the power good signals of the four memory DIMMs are connected together, the BMC has no way to detect and locate which DIMM has a PMIC failure. By detecting the first fault, the CPU can accurately detect the fault address of the PMIC.

[0041] In the specific embodiment of the present application, there are two situations when PMIC fails. The first situation is at the beginning of the boot process, before the BIOS enables the memory VR (BIOS firmware enables the voltage regulator of the memory), the BIOS will isolate and report the faulty memory information; the second situation is after the BIOS enables the memory VR, that is, in the later stage of the boot process and when running under the OS, in this case the system is shut down first, and then AC reboot, and the faulty memory information is isolated and reported during the boot process. Memory VR enable means that the memory is powered on normally.

[0042] In an exemplary embodiment, a target control instruction set is generated based on first time information and second time information, including: in response to a first moment being earlier than a third moment, a first control instruction in the target control instruction set is generated, the first control instruction is used to determine fault information, generate a fault log, and shield a communication channel where a faulty memory is located, the fault information includes at least an address where the fault occurs, and the fault log is generated by a baseboard controller based on the fault information.

[0043] In an exemplary embodiment, generating a target control instruction set based on first time information and second time information includes: in response to the first moment being later than the third moment, generating a second control instruction in the target control instruction set, the second control instruction being used to re-power on the server.

[0044] like Figure 6 The flowchart of the embodiment of the case where a fault occurs before the memory VR is enabled during the boot process is shown. Step 1: The AC is powered on, the server is powered on, and the PMIC enters the configuration mode, which is not the write protection mode.

[0045] Step 2: BIOS polls the PMIC registers of all DIMMs through I3C to locate the DIMM with the faulty PMIC. Because after a PMIC fails, the error information will be recorded in non-volatile registers, so these registers can be checked to determine whether there is a PMIC failure.

[0046] Step 3: BIOS sends the specific information of the memory with PMIC failure and PMIC register information to BMC, and BMC generates logs and alarms after receiving them. In this way, users can locate the specific slot and replace the memory.

[0047] Step 4: BIOS sets the faulty PMIC register to release the power good abnormal state, and disables the channel where the faulty memory is located to isolate the faulty memory.

[0048] Step 5: Enable the VR of all normal memories to power on the memories normally.

[0049] Step 6: Initialize all normal memories. After initialization is complete, set the PMIC of all memories to write protection mode.

[0050] Step 7: BIOS polls the PMIC registers of all memories again to check if there is any fault in the memory PMIC. If there is a fault, the information of the faulty memory is sent to the BMC, and the BMC performs an AC reboot and starts again from step 1. If there is no fault, continue to boot up.

[0051] In an exemplary embodiment, a target control instruction set is generated based on first time information and second time information, including: in response to the second moment being later than the third moment, a third control instruction in the target control instruction set is generated, the third control instruction is used to shut down the server, repower on the server, and detect whether a first fault occurs during the server power-on process and locate the slot where the first fault occurs, and the third control instruction is also used to shield the communication channel where the faulty memory is located when the first fault occurs.

[0052] In DDR5 memory, multiple memory sticks (DIMMs) usually share one or more data channels. If the PMIC of a DIMM fails, for the sake of system stability and performance, it is necessary to disable (i.e. stop using) the channel (communication channel) where the faulty DIMM is located, rather than the entire memory system. This is because: the unstable power supply of the faulty memory may cause data read and write errors. By disabling the channel, data corruption or system instability can be prevented. Although disabling a channel will reduce the available memory bandwidth, compared to a complete shutdown or restart, this method can keep the system running to a certain extent and avoid greater performance loss. Disabling the faulty memory channel can reduce unnecessary power loads and help with the system's thermal management and energy efficiency. Through this series of operations, the system can safely isolate and handle power supply failures in DDR5 memory while minimizing the impact on system performance and ensuring that the server or computer can continue to operate stably.

[0053] DIMM is the abbreviation of "Dual In-line Memory Module", which is a memory module standard used in computers and servers. In DDR5 technology, DIMM refers to a memory module that complies with the DDR5 specification, which not only contains DRAM chips (dynamic random access memory) for storing data, but also integrates other important components and circuits to achieve higher performance, lower power consumption and better signal integrity.

[0054] like Figure 5The flowchart of the PMIC failure after the memory VR is enabled is shown. Step 1: After the PMIC fails, the PMIC triggers the internal VR disable and the POWER GOOD signal is pulled low.

[0055] Step 2: CPLD detects that the memory POWER GOOD signal is abnormal, the server shuts down, and the BMC reports the log of memory POWER GOOD fail. Under normal circumstances, the POWER GOOD signal is high, and when the POWER GOOD signal is low, it indicates an electrical abnormality.

[0056] Step 3: After the BMC detects that a memory stick is POWER GOOD abnormal, it proactively sends a command to the power supply to execute ACreboot, that is, power off the entire server and then power it on again.

[0057] Reason for AC reboot: During normal operation, the BIOS sends a VR Enable command to the DIMM during the boot process, the memory is powered on, and then some initialization work is performed on the PMIC. After the initialization work is completed, the BIOS will set all DIMM PMICs to the "write protection" state. When a PMIC fails, after the system is shut down, if the power is not turned off and the system is turned on, the POWER GOOD signal of the memory will be pulled low. To release this state, you need to disconnect the AC and restart to release the PMIC from the "write protection" state. Only then can the BIOS set the PMIC register to isolate the faulty memory.

[0058] Step 4: After the BMC restarts, issue the power on command to start the server.

[0059] Execute AC reboot, all power on the server mainboard will be restored, and the BMC will also restart. After the BMC restarts, if there is a log indicating that the server was shut down due to abnormal memory voltage before the restart, a startup command will be sent to the server.

[0060] Step 5: During the boot process, after the BIOS detects a PMIC fault, it isolates the corresponding memory and reports specific memory and PMIC register information to the BMC, which records it in the log and issues an alarm. The user can get specific error information from the BMC and perform other actions such as replacing the memory.

[0061] In an exemplary embodiment, determining fault information includes: using a processor to poll a register of a power management integrated chip on a memory module to obtain a query result; in response to the query result including a register fault, locating an address where the fault occurred based on the query result to obtain fault information.

[0062] Specifically, polling is a method of computer communication and data acquisition in which the central processing unit (CPU) or other master device periodically or continuously checks the status or data of slave devices (such as sensors, memory, peripherals, etc.) to determine whether there is new information or events that need to be processed. In polling mode, the master device actively initiates queries instead of waiting for the slave device to send an interrupt signal to notify the status change.

[0063] During operation, the CPU will periodically access the temperature sensor (TSOD) on the memory to read the current temperature information. TSOD is a temperature sensor embedded in the DDR memory module, which is used to monitor the temperature of the memory to prevent performance degradation or hardware damage caused by overheating.

[0064] In order to optimize resource utilization and avoid bus conflicts between the CPU and BMC, a MUX (multiplexer) is used to switch control of the I3C bus at different stages, allowing the CPU to poll during the POST stage, while the BMC performs real-time monitoring and polling during the OS running stage.

[0065] In this way, both the CPU and BMC can effectively monitor memory temperature, but the BMC's monitoring is more real-time and detailed, and can respond to temperature anomalies in a timely manner without interrupting the normal operation of the system, thereby improving the stability and security of the system.

[0066] In an exemplary embodiment, a method for detecting a second fault includes: obtaining memory information, the memory information including a voltage signal and a temperature signal, the voltage signal being generated by a voltage regulator when a register fails, the voltage signal being acquired by a complex programmable logic device inside a server, the temperature signal being acquired by a temperature sensor on a memory module, and the temperature signal being used to determine the temperature of the memory; determining whether the voltage signal is the same as a set voltage signal, wherein the set voltage signal is a level signal generated by a voltage regulator corresponding to the memory when the memory is normal; if the voltage signal is different from the set voltage signal, determining that a second fault has occurred in the memory corresponding to the voltage signal; determining whether the temperature of the memory is greater than a set temperature value, wherein the set temperature value is the maximum temperature allowed for normal operation of the memory; if the temperature of the memory is greater than the set temperature value, determining that a second fault has occurred in the memory corresponding to the temperature signal.

[0067] In an exemplary embodiment, the server is powered on again, including: controlling the baseboard controller to restart, and sending power-on instructions to other target components in the server through the restarted baseboard controller. In the related art, the server can only print the information of PMIC failure in the BIOS serial port, without alarming in the BMC, and is limited by the hardware design limitations, and cannot accurately locate which memory voltage is abnormal. The present application can accurately report the information of PMIC failure through the cooperation of BIOSBMC without changing the existing hardware design. When the PMIC fails, it will automatically shut down. If you send a command or manually press the power button to turn on the server at this time, the server cannot start normally. If you need to restore to normal, you need to manually disconnect the AC. After the present application detects that the memory POWER GOOD signal is abnormal, it will automatically perform an AC reboot. If you are in the computer room, you don’t need to manually unplug the power cord to perform an AC reboot, which is easy to maintain.

[0068] With the technical solution of the present application, after the BMC detects that the memory POWER GOOD abnormality causes shutdown, it sends a command to the PSU to reboot the AC. After the AC is powered on, the BIOS locates the PMIC fault memory information and sends the fault memory detailed information to the BMC. After the BMC receives the PMIC fault memory information sent by the BIOS, it records the log and issues an alarm to notify the user to replace the memory.

[0069] The detection methods of the first fault and the second fault are different. The first fault is detected by the processor, and the second fault is detected by the BMC. In an optional embodiment, BIOS (Basic Input Output System): During the boot phase, BIOS is mainly responsible for hardware initialization and basic function detection. It reads the register of PMIC through the I3C bus to check whether there is a fault record. Once a fault is found, BIOS will take action, such as isolating the faulty memory channel to avoid instability when the system is powered on. BIOS will also set the register of PMIC to write protection mode to prevent unauthorized access. POST (Power-On Self-Test) is a series of hardware check programs executed by BIOS (Basic Input Output System) after the boot phase to verify whether the basic functions of the server hardware are normal, such as CPU, memory, hard disk, etc. During the POST phase, the BIOS firmware is executed by the processor to access the PMIC register through the I3C bus, check the PMIC status, identify and handle potential hardware faults, such as PMIC failure or memory overheating. BIOS, the full name of Basic Input / Output System, is a program stored in a ROM (Read Only Memory) chip on the server motherboard. It contains a series of basic hardware initialization codes and self-test programs, and is the first software that runs when the PC system starts. The main responsibilities of BIOS include: BIOS is responsible for identifying and initializing the hardware resources in the system, including CPU, memory, disk, display adapter, etc. BIOS performs the POST process to check the system hardware and verify whether it is in normal working condition. If a hardware failure is found, BIOS will notify the user through a specific error code or sound signal. If the POST process passes, BIOS will read the boot program (usually the boot loader of the operating system) from the preset boot device (such as a hard disk) and hand over control to the boot program to start the operating system.

[0070] The CPU is the "brain" of the computer, responsible for executing instructions and performing calculations. During the POST phase, the CPU's role is mainly reflected in: the CPU reads the BIOS program from the motherboard ROM and executes the initialization and self-test code therein. The CPU will access and test hardware resources according to the BIOS instructions, such as reading the PMIC register through the I3C bus to check the power management status of the memory. If the BIOS detects a hardware failure during the POST process, the CPU will follow the instructions of the BIOS and may stop the boot process or skip the initialization of the faulty hardware so that the system can continue to boot to a usable state.

[0071] BMC (Baseboard Management Controller): After POST is completed and the OS phase is entered, BMC takes over the hardware monitoring responsibilities of the server, including real-time monitoring of the PMIC status register through the I3C bus, and monitoring the temperature information of the TSOD (temperature sensor). BMC monitoring focuses more on the real-time and continuity during operation. It can continuously check the voltage, current, temperature and other indicators of the PMIC. Once an over-threshold situation is found, it will immediately record and alarm. If necessary, it can also notify the CPU through the PECI interface to take temperature-related protection measures.

[0072] Optionally, the BMC can switch control of the PMIC on the DIMM through a multiplexer and the CPU.

[0073] The MUX (multiplexer) acts as a switch for the communication channel, allowing the CPU or BMC to control the I3C bus at different points in time to access the devices on the DIMM. Specifically:

[0074] A port of the MUX that is connected to the CPU on the motherboard. During the POST (Power On Self-Test) phase, the CPU accesses devices such as the PMIC and TSOD on the DIMM through this port for initialization, configuration, and fault detection.

[0075] Another port of the MUX is connected to the BMC (Baseboard Management Controller). During the OS (Operating System) operation phase, the control is switched from the CPU to the BMC, which monitors the PMIC status on the DIMM in real time through this port, including parameters such as voltage, current, and temperature, to ensure the stability and security of the server hardware during operation.

[0076] This design allows the CPU and BMC to use the I3C bus at different time points, avoiding possible communication conflicts when they access the devices on the DIMM at the same time, while also ensuring that the devices on the DIMM can be monitored and managed efficiently and in real time. The switching of the MUX is controlled by the CPLD (complex programmable logic device), further improving the flexibility and reliability of the system's management of DIMM devices.

[0077] Among them, the CPU detects PMIC failures through the I3C component, and the BMC can choose to obtain the power good signal of the PMIC VR through the CPLD, or communicate with the SPD HUB through the I3C component. SPD HUB can be understood as SerialPresence Detect Hub, which is a key component on the DDR5 DIMM and is used to manage the communication between various devices connected to the memory module through the I3C bus. The role of SPD HUB is somewhat similar to a small communication management center. It receives data from various devices on the DIMM (such as PMIC, TSOD, RCD, etc.), and integrates this data and sends it to the CPU or BMC on the motherboard through the I3C bus for processing.

[0078] On DDR5 DIMM, SPD HUB connects to these devices through the local I3C bus. The "local" here means that these connections and communications are limited to the inside of the DIMM module. The I3C bus is an improved I2C bus that can provide higher data transfer rates and richer functions, making it very suitable for high-speed communication between devices inside the module.

[0079] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0080] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0081] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0082] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0083] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0084] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0085] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0086] The embodiments of the present application also provide a computer program, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in any one of the above method embodiments.

[0087] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0088] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0089] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for handling server failures, characterized in that: include: Acquire first time information, the first time information includes at least one of a first moment and a second moment, the first moment is the moment when the first fault occurs, the second moment is the moment when the second fault occurs, the first fault includes a fault detected by a processor on a register of a power management integrated chip, the processor is used to execute BIOS firmware, and the second fault includes a fault detected by a baseboard controller on a register of the power management integrated chip; acquire second time information, the second time information is a third moment when a voltage regulator of the power management integrated chip is powered on; A target control instruction set is generated based on the first time information and the second time information, and the target control instruction set is used to control the server to perform a preset fault handling operation.

2. The method according to claim 1, characterized in that: Generating a target control instruction set based on the first time information and the second time information includes: In response to the first moment being earlier than the third moment, a first control instruction in the target control instruction set is generated, the first control instruction being used to determine fault information, generate a fault log, and shield a communication channel where a faulty memory is located, the fault information at least including an address where the fault occurred, and the fault log is generated by the baseboard controller based on the fault information.

3. The method according to claim 1, characterized in that Generating a target control instruction set based on the first time information and the second time information includes: In response to the first moment being later than the third moment, a second control instruction in the target control instruction set is generated, wherein the second control instruction is used to re-power on the server.

4. The method according to claim 1, characterized in that: Generating a target control instruction set based on the first time information and the second time information includes: In response to the second moment being later than the third moment, a third control instruction in the target control instruction set is generated, the third control instruction being used to shut down the server, power on the server again, and detect whether the first fault occurs during the power-on process of the server and locate the slot where the first fault occurs. The third control instruction is also used to shield the communication channel where the faulty memory is located when the first fault occurs during the power-on process.

5. The method according to claim 2, characterized in that: Determine the fault information, including: Using the processor to poll the register of the power management integrated chip on the memory module to obtain the query result; In response to the query result including a register fault, the fault occurrence address is located based on the query result to obtain the fault information.

6. The method according to claim 1, characterized in that The second fault detection method includes: Acquire memory information, the memory information including a voltage signal and a temperature signal, the voltage signal being generated by a voltage regulator when a register fails, the voltage signal being acquired by a complex programmable logic device inside the server, and the temperature signal being acquired by a temperature sensor on a memory module, and the temperature signal being used to determine the temperature of the memory; Determine whether the voltage signal is the same as a set voltage signal, wherein the set voltage signal is a level signal generated by a voltage regulator corresponding to the memory when the memory is normal; When the voltage signal is different from the set voltage signal, determining that a second fault occurs in the memory corresponding to the voltage signal; Determine whether the temperature of the memory is greater than a set temperature value, wherein the set temperature value is the maximum temperature allowed for normal operation of the memory; When the temperature of the memory is greater than the set temperature value, it is determined that a second fault occurs in the memory corresponding to the temperature signal.

7. The method according to claim 3 or 4, characterized in that: Re-powering on the server includes: controlling the baseboard controller to restart, and sending a power-on instruction to other target components in the server through the restarted baseboard controller.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 7 when executed by a processor.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 7 are implemented.

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