Full-duplex UART data self-checking device and method

Abstract

The invention belongs to the technical field of electronic communication, and discloses a full-duplex UART data self-checking device and method.When a configuration module receives a self-checking instruction, the whole device enters a self-checking mode, a selection module sends output data output by an output processing module to an input processing module, and the input processing module sends the output data to the full-duplex UART data self-checking device; the input processing module processes output data in the same way as input data and sends processed target length data to the data bit comparison module, the data bit comparison module compares preset output data with the target length data passing through the output processing module and the input processing module, and if the two pieces of data are consistent, the data bit comparison module sends the target length data to the output processing module. If yes, the two processing modules work normally, otherwise, problems occur in the circuit, and reminding is carried out by outputting a data bit detection signal. According to the application, the correctness of the data can be automatically detected in the front and back end verification links, the circuit modules with errors are eliminated, and the transmission accuracy of the UART data is ensured.

Description

Technical Field

[0001] The present application relates to the field of electronic communication technology, and in particular to a full-duplex UART data self-test device and method. Background Art

[0002] UART is a universal serial, asynchronous communication bus. The bus has two data lines, TXD is used to send data, and RXD is used to receive data. It can realize full-duplex sending and receiving. It is often used for communication between host and auxiliary devices in embedded systems. UART has a fixed frame format for sending and receiving data. TXD / RXD defaults to high level. After the baud rate of the data is configured, a frame of low-level start bit will appear when the data starts to be sent or received, followed by the data bit, followed by a check bit, followed by a frame of high-level stop bit, and the data level remains high when idle.

[0003] Most of the existing UART circuits will directly output and receive data, and only receive data and compare check bits internally. If a design error occurs under special circumstances in the circuit, or a circuit error occurs during process manufacturing, for example, the user end transmits data A, and the data becomes B under the wrong circuit, in this case, even if a check code is used, the check code is the correct check code for data B, and the data error caused by this situation cannot be perceived at the receiving end. Summary of the invention

[0004] The present application provides a full-duplex UART data self-checking device and method, which can automatically detect the correctness of data within the front-end and back-end verification links, eliminate erroneous circuit modules, and ensure the transmission accuracy of UART data.

[0005] In a first aspect, an embodiment of the present application provides a full-duplex UART data self-test device, including a selection module, a configuration module, an input processing module, an output processing module, and a data bit comparison module;

[0006] The configuration module is used to receive the self-test instruction and send the self-test instruction to the selection module and the input processing module respectively; receive the data length configuration instruction and send it to the input processing module;

[0007] and, receiving preset output data, sending the preset output data to the output processing module, and when receiving the self-check instruction, sending the preset output data to the data bit comparison module and the output processing module respectively;

[0008] The selection module is used to receive input data and output data, and send the output data to the input processing module when receiving the self-check instruction; and send the input data to the input processing module when not receiving the self-check instruction;

[0009] The input processing module is used to convert the input data or output data into target length data according to the data length configuration instruction, and send the target length data to the data bit comparison module when receiving the self-check instruction;

[0010] The data bit comparison module is used to compare whether the target length data and the preset output data are consistent, and output a data bit detection signal when at least one bit of data is inconsistent;

[0011] The output processing module is used to receive preset output data, process the preset output data into output data in a UART frame format, and send the output data to the selection module.

[0012] Furthermore, the device also includes a check bit comparison module and a logic module;

[0013] The configuration module is also used to receive the verification configuration instruction and send it to the input processing module;

[0014] The selection module is also used to send the input data or output data to the check bit comparison module;

[0015] The input processing module is also used to send the check configuration instruction and the target length data to the check bit comparison module when receiving the check configuration instruction;

[0016] The check bit comparison module is used to check the target length data and the output data according to the check configuration instruction, and when the check result is incorrect, send a check bit detection signal to the logic module;

[0017] The data bit comparison module is also used to send a data bit detection signal to the logic module;

[0018] The logic module is used for outputting a self-check error signal according to the check bit detection signal and the data bit detection signal.

[0019] Furthermore, the data transmission baud rate of the configuration module, the input processing module, the output processing module and the data bit comparison module is a preset baud rate.

[0020] Furthermore, the data length in the data length configuration instruction is greater than or equal to 5 bits and less than or equal to 8 bits.

[0021] Furthermore, the check mode in the check configuration instruction includes odd check and even check.

[0022] Furthermore, the check bit comparison module is specifically used to output a check bit detection signal when the check bit of the target length data is inconsistent with the check bit of the output data.

[0023] Furthermore, both the input data and the output data are serial data streams conforming to the UART frame format.

[0024] Further, the logic module is an OR gate;

[0025] The parity bit detection signal, data bit detection signal and self-test error signal are all valid at high level.

[0026] Further, the selection module is a two-way selector;

[0027] The first input terminal is used to receive input data, and the second input terminal is used to receive output data.

[0028] In a second aspect, an embodiment of the present application provides a full-duplex UART data self-test method, comprising:

[0029] The configuration module receives the self-check instruction and sends it to the selection module and the input processing module respectively;

[0030] The selection module receives input data and output data, and sends the output data to the input processing module when receiving the self-check instruction; and sends the input data to the input processing module when not receiving the self-check instruction;

[0031] The configuration module receives the data length configuration instruction and sends it to the input processing module;

[0032] The input processing module converts the input data or output data into target length data according to the data length configuration instruction, and sends the target length data to the data bit comparison module when receiving the self-check instruction;

[0033] The configuration module receives the preset output data, sends the preset output data to the output processing module, and when receiving the self-test instruction, sends the preset output data to the data bit comparison module and the output processing module respectively;

[0034] The output processing module receives the preset output data, processes the preset output data into output data in a UART frame format, and sends the output data to the selection module;

[0035] The data bit comparison module compares whether the target length data and the preset output data are consistent, and outputs a data bit detection signal when at least one bit of data is inconsistent.

[0036] In summary, compared with the prior art, the technical solution provided in the embodiment of the present application has at least the following beneficial effects:

[0037] A full-duplex UART data self-test device provided by an embodiment of the present application, when the configuration module receives a self-test instruction, the entire device enters a self-test mode, the selection module sends the output data output by the output processing module to the input processing module, the input processing module processes the output data in the same way as the input data, and sends the processed target length data to the data bit comparison module, the data bit comparison module compares the preset output data with the target length data after the output processing module and the input processing module, if the two data are consistent, it means that the two processing modules are working normally, otherwise it means that there is a problem inside the circuit, resulting in a change in the data after the processing module, at this time, a reminder is given by outputting a data bit detection signal. The above device can automatically detect the correctness of the data in the front-end and back-end verification links, and can perform early internal data self-test in actual use to exclude circuit modules with errors, thereby ensuring the transmission accuracy of UART data. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A structural diagram of a full-duplex UART data self-test device provided by an exemplary embodiment of the present application.

[0039] Figure 2 A structural diagram of a full-duplex UART data self-test device provided as yet another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0041] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0042] See also Figure 1 The embodiment of the present application provides a full-duplex UART data self-test device, including a selection module, a configuration module, an input processing module, an output processing module and a data bit comparison module; the configuration module is used to receive a self-test instruction, and send the self-test instruction to the selection module and the input processing module respectively; receive a data length configuration instruction, and send it to the input processing module; and receive preset output data, send the preset output data to the output processing module, and when receiving the self-test instruction, send the preset output data to the data bit comparison module and the output processing module respectively.

[0043] The selection module is used to receive input data and output data, and sends the output data to the input processing module when receiving the self-test instruction; and sends the input data to the input processing module when not receiving the self-test instruction. Specifically, the selection module can be a two-way selector; the first input end is used to receive input data, and the second input end is used to receive output data.

[0044] The input processing module is used to convert input data or output data into target length data according to the data length configuration instruction, and send the target length data to the data bit comparison module when receiving the self-check instruction.

[0045] The data bit comparison module is used to compare whether the target length data and the preset output data are consistent, and output a data bit detection signal when at least one bit of data is inconsistent. The output processing module is used to receive the preset output data, process the preset output data into output data in UART frame format, and send it to the selection module.

[0046] The input data RXD and the output data TXD are both serial data streams that conform to the UART frame format, that is, 1 bit of corresponding data is transmitted every other frame.

[0047] When using the applied UART data self-test function, the user can select the configuration to use the self-test function in the configuration register of the configuration module, that is, input the self-test instruction, and at the same time send the preset output data to the configuration module through the external bus. The data length in the data length configuration instruction is greater than or equal to 5 bits and less than or equal to 8 bits. The configuration of this data length is also selected in the configuration register of the configuration module. At the same time, the transmission rate register ( Figure 1 The preset baud rate corresponding to the data transmission of each module is configured (not shown yet), and the data transmission baud rate of the configuration module, input processing module, output processing module and data bit comparison module are all the preset baud rate. When performing self-test, different preset baud rates can be configured multiple times to realize the detection of data transmission of the circuit at different baud rates.

[0048] Specifically, in the non-self-test mode, that is, when the configuration module does not receive the self-test instruction, the selection module sends the input data to the input processing module, and the input processing module converts the input data into the target length data of the data length specified in the data length configuration instruction, and stores it in the register waiting to be read. After entering the self-test mode, the configuration module will receive the preset output data and send it to the selection module and the output processing module respectively; the output processing module converts it into a serial data stream (output data) that conforms to the UART frame format and sends it. When the selection module receives the self-test instruction as a high level, it will replace the original input data RXD with the output data TXD of the output processing module and send it to the input processing module for processing. After the input processing module converts the output data into the target length data of the data length specified in the data length configuration instruction, it sends it to the data bit comparison module.

[0049] The target length data is compared with the preset output data in the data bit comparison module. If one or more bits of data are different, a high-level valid data bit detection signal will be generated.

[0050] The above embodiment provides a full-duplex UART data self-test device. When the configuration module receives the self-test instruction, the entire device enters the self-test mode. The selection module sends the output data output by the output processing module to the input processing module. The input processing module processes the output data in the same way as the input data, and sends the processed target length data to the data bit comparison module. The data bit comparison module compares the preset output data with the target length data after the output processing module and the input processing module. If the two data are consistent, it means that the two processing modules are working normally. Otherwise, it means that there is a problem inside the circuit, resulting in changes in the data after the processing module. At this time, a reminder is given by outputting a data bit detection signal. The above device can automatically detect the correctness of the data in the front-end and back-end verification links. In actual use, it can perform early internal data self-test to exclude circuit modules with errors and ensure the transmission accuracy of UART data.

[0051] In some embodiments, see Figure 2 , the device also includes a check bit comparison module and a logic module.

[0052] The logic module may be an OR gate.

[0053] The configuration module is also used to receive the verification configuration instruction and send it to the input processing module.

[0054] The check mode in the check configuration instruction includes odd check and even check.

[0055] The selection module is further used to send the input data or the output data to the check bit comparison module.

[0056] The input processing module is also used to send the verification configuration instruction and the target length data to the check bit comparison module when receiving the verification configuration instruction; the check bit comparison module is used to verify the target length data and the output data according to the verification configuration instruction, and when the verification result is incorrect, send a check bit detection signal to the logic module.

[0057] The data bit comparison module is also used to send a data bit detection signal to the logic module.

[0058] The logic module is used for outputting a self-check error signal according to the check bit detection signal and the data bit detection signal.

[0059] Specifically, the user may also input a check configuration instruction in a configuration register of the configuration module, wherein the check configuration instruction is used to instruct the determination and check method of the check bit of the data.

[0060] After receiving the check configuration instruction, the check bit comparison module compares the check bit in the target length data and the check bit of the input data / output data according to the specified check mode (such as odd check or even check). When the check bit of the target length data and the check bit of the input data / output data are inconsistent, a high-level valid check bit detection signal is output.

[0061] Since the logic module is an OR gate, as long as any one of the check bit detection signal and the data bit detection signal is at a high level, the logic module will output a high level self-check error signal.

[0062] For example, during a UART self-test, the preset baud rate is configured to be 115200, the data length is 8 bits, the check function is enabled and the check mode is odd check. The user inputs the preset output data 8'h76 to the UART through the bus. If an internal circuit error occurs due to process or other reasons, the bit [2] of the preset output data is flipped and tampered with after generating the corresponding target length data 8'h72, and after the output processing module processes the preset output data, the check bit of the transmitted output data TXD becomes 1. At this time, if the register of the input processing module is directly connected to the UART at the receiving end, the external UART will receive the wrong data 8'h72 and think it is correct data, but in fact it has deviated from the real data. At this time, when the self-test device of the present application is used before transmission, it will be found that the two sets of data are different when comparing the data bits, and the data bit detection signal is set to 1. After the user finds that the data bit detection signal is at a high level, he will find that the circuit is defective.

[0063] It is worth noting that the check function can also be executed in non-self-check mode, that is, the check bit is judged on the input data and the corresponding converted target length data. Therefore, the selection module and the input processing module do not necessarily send the corresponding data and instructions to the check bit comparison module in the self-check mode (when receiving the self-check instruction).

[0064] The above embodiment adds the check bit detection on the basis of the data bit self-check, and the output of the final self-check error signal is a combination of the data bit detection result and the check bit detection result, which further improves the accuracy of the UART self-check.

[0065] Another embodiment of the present application provides a full-duplex UART data self-test method, including:

[0066] Step S1, the configuration module receives the self-check instruction and sends it to the selection module and the input processing module respectively.

[0067] Step S2, the selection module receives input data and output data, and sends the output data to the input processing module when receiving a self-check instruction; and sends the input data to the input processing module when not receiving a self-check instruction.

[0068] Step S3: the configuration module receives the data length configuration instruction and sends it to the input processing module.

[0069] Step S4, the input processing module converts the input data or output data into target length data according to the data length configuration instruction, and sends the target length data to the data bit comparison module when receiving the self-check instruction.

[0070] Step S5, the configuration module receives the preset output data, sends the preset output data to the output processing module, and when receiving the self-check instruction, sends the preset output data to the data bit comparison module and the output processing module respectively.

[0071] Step S6, the output processing module receives the preset output data, processes the preset output data into output data in a UART frame format, and sends the output data to the selection module.

[0072] Step S7, the data bit comparison module compares the target length data with the preset output data to see if they are consistent, and outputs a data bit detection signal when at least one bit of the data is inconsistent.

[0073] For the specific limitations of a full-duplex UART data self-test method provided in this embodiment, reference may be made to the above embodiment of a full-duplex UART data self-test device, which will not be described in detail here.

[0074] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A full-duplex UART data self-test device, characterized in that: It includes a selection module, a configuration module, an input processing module, an output processing module and a data bit comparison module; The configuration module is used to receive a self-check instruction and send the self-check instruction to the selection module and the input processing module respectively; receive a data length configuration instruction and send it to the input processing module; and receiving preset output data, sending the preset output data to the output processing module, and sending the preset output data to the data bit comparison module and the output processing module respectively when receiving a self-check instruction; The selection module is used to receive input data and output data, and send the output data to the input processing module when receiving the self-check instruction; sending input data to the input processing module when no self-check instruction is received; The input processing module is used to convert input data or output data into target length data according to the data length configuration instruction, and send the target length data to the data bit comparison module when receiving the self-check instruction; The data bit comparison module is used to compare whether the target length data and the preset output data are consistent, and output a data bit detection signal when at least one bit of data is inconsistent; The output processing module is used to receive the preset output data, process the preset output data into the output data in the UART frame format, and send the output data to the selection module.

2. The full-duplex UART data self-test device according to claim 1, characterized in that: It also includes a check bit comparison module and a logic module; the configuration module is also used to receive the check configuration instruction and send it to the input processing module; The selection module is also used to send the input data or the output data to the check bit comparison module; The input processing module is also used to send the check configuration instruction and the target length data to the check bit comparison module when receiving the check configuration instruction; The check bit comparison module is used to check the target length data and the output data according to the check configuration instruction, and when the check result is incorrect, send a check bit detection signal to the logic module; The data bit comparison module is also used to send the data bit detection signal to the logic module; The logic module is used for outputting a self-check error signal according to the check bit detection signal and the data bit detection signal.

3. The full-duplex UART data self-test device according to claim 1, characterized in that: The data transmission baud rate of the configuration module, the input processing module, the output processing module and the data bit comparison module is a preset baud rate.

4. The full-duplex UART data self-test device according to claim 1, characterized in that: The data length in the data length configuration instruction is greater than or equal to 5 bits and less than or equal to 8 bits.

5. The full-duplex UART data self-test device according to claim 2, characterized in that: The check mode in the check configuration instruction includes odd check and even check.

6. The full-duplex UART data self-test device according to claim 5, characterized in that: The check bit comparison module is specifically used to output a check bit detection signal when the check bit of the target length data is inconsistent with the check bit of the output data.

7. The full-duplex UART data self-test device according to claim 1, characterized in that: The input data and the output data are both serial data streams conforming to the UART frame format.

8. The full-duplex UART data self-test device according to claim 2, characterized in that: The logic module is an OR gate; the check bit detection signal, the data bit detection signal and the self-check error signal are all valid at a high level.

9. The full-duplex UART data self-test device according to claim 1, characterized in that: The selection module is a dual-way selector; the first input end is used to receive input data, and the second input end is used to receive output data.

10. A full-duplex UART data self-test method, characterized in that: include: The configuration module receives the self-check instruction and sends it to the selection module and the input processing module respectively; The selection module receives input data and output data, and sends the output data to the input processing module upon receiving a self-check instruction; sending input data to the input processing module when no self-check instruction is received; The configuration module receives the data length configuration instruction and sends it to the input processing module; The input processing module converts the input data or the output data into target length data according to the data length configuration instruction, and sends the target length data to the data bit comparison module when receiving the self-check instruction; The configuration module receives preset output data, sends the preset output data to the output processing module, and upon receiving a self-check instruction, sends the preset output data to the data bit comparison module and the output processing module respectively; The output processing module receives the preset output data, processes the preset output data into the output data in the UART frame format, and sends the output data to the selection module; The data bit comparison module compares whether the target length data and the preset output data are consistent, and outputs a data bit detection signal when at least one bit of data is inconsistent.

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