Method and system for monitoring FPGA state in CT equipment, medium and equipment

Abstract

The invention provides an FPGA state monitoring method and system in CT equipment, a medium and equipment, and the method comprises the steps: sending a state reading command with target board card information to each board card in the CT equipment through a man-machine interaction module, feeding back the FPGA state information in the board card to the man-machine interaction module after the target board card receives the state reading command, and sending the FPGA state information to the computer through the man-machine interaction module; and the human interaction module displays the read state information of the FPGA. According to the method, on the premise that the hardware cost is not increased, the states of all the FPGAs in the CT equipment can be accurately and rapidly displayed through the DMS software, and rapid fault positioning and troubleshooting of the CT equipment are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA status monitoring, and in particular to a method, system, medium and device for monitoring the status of an FPGA in a CT device. Background Art

[0002] In order to achieve rapid and accurate data transmission in CT equipment, most CT equipment on the market now uses FPGA chips to complete data transmission. At the same time, in order to reduce costs, the FPGA chip only contains the PL end, which results in the FPGA operating status cannot be viewed when the CT equipment is running.

[0003] In order to ensure the normal operation and troubleshooting of the equipment, it is particularly important to accurately and quickly obtain the operating status information of the FPGA without increasing the hardware cost.

[0004] Patent document CN106951356A discloses a method for monitoring the status information of a signal interface processing board, including: power-on information monitoring, a one-time monitoring is performed after power-on, and power-on monitoring information is output to provide a reference when the signal interface processing board is in an abnormal state after power-on; frame information monitoring, monitoring various types of information contained in each frame of data distributed and output at this moment, and outputting frame monitoring information, so as to provide data frame conditions when data is stuck; real-time information monitoring, the real-time information includes detailed information showing the transmission data rate and the details contained in each module, outputting real-time refresh monitoring information, and showing the real-time information when locating the problem; top-level monitoring, receiving all the above monitoring information, and outputting the monitoring information. However, this patent cannot completely solve the existing technical problems, nor can it meet the needs of the present invention. Summary of the invention

[0005] In view of the defects in the prior art, the object of the present invention is to provide a method, system, medium and device for monitoring the state of FPGA in CT equipment.

[0006] The method for monitoring the FPGA status in the CT device provided by the present invention comprises: sending a status reading command with target board information to each board in the CT device through a human-computer interaction module, and after receiving the status reading command, the target board feeds back the FPGA status information in the board to the human-computer interaction module, and the human interaction module displays the read FPGA status information;

[0007] The CT device includes a DCB board with a DCB_FPGA chip, a DIF board with a DIF_FPGA chip, and a DBB board with a DBB_FPGA chip;

[0008] The human-computer interaction module is connected to the DCB board, the other end of the DCB board is connected to the DIF board, and the other end of the DIF board is connected to the DBB board.

[0009] Preferably, when the target board is a DIF board or a DBB board, the status reading command further includes a communication address of the target board.

[0010] Preferably, the human-computer interaction module is specifically DMS software, and the DMS software includes a drop-down box for board selection, including DCB, DIF, DBB, ADL and ADR;

[0011] The DMS interface displays the status information of each board;

[0012] The DMS software includes a drop-down box for DIF board and DBB board communication address selection;

[0013] ADL and ADR are temporarily reserved interfaces for reading detector parameters;

[0014] The DMS software selects the board status to be read, clicks OK, and sends the information to the GCC board through the network port. The GCC board is located in the stator part of the equipment, and communicates with the host computer through the network cable for parameters, and communicates with the DCB embedded in the rotor part through the CAN bus through the slip ring. The GCC board sends the scanning information sent by the host computer to each corresponding component, and transmits the feedback information of each component to the host computer.

[0015] Preferably, the DCB embedded chip sends information to the FPGA chip of the DCB through EIM communication.

[0016] Preferably, if the DMS software user selects a DCB board, the DCB board sends all address information to the DCB embedded through EIM, the DCB embedded sends it to the GCC through the CAN bus, the GCC sends it to the DMS software through the network port, and the information is displayed by the DMS software.

[0017] Preferably, if the DMS software user selects a DIF board, the DCB board sends the address information to the FPGA chip of the DIF board via the differential signal line, and the DIF feeds the address information back to the DCB via the differential signal line, and finally the information is displayed by the DMS software.

[0018] Preferably, if the DMS software user selects a DBB board, the DCB board sends the address information to the DIF board via a differential signal line, and the DIF board sends the address information to the FPGA chip of the DBB board via a differential signal line, and then passes it to the DCB, and finally the information is displayed through the DMS software.

[0019] The monitoring system of the FPGA status in the CT device provided by the present invention comprises: sending a status reading command with target board information to each board in the CT device through a human-computer interaction module, after receiving the status reading command, the target board feeds back the FPGA status information in the board to the human-computer interaction module, and the human interaction module displays the read FPGA status information.

[0020] According to the computer-readable storage medium storing a computer program provided by the present invention, when the computer program is executed by a processor, the steps of the method for monitoring the state of FPGA in a CT device are implemented.

[0021] The electronic device provided according to the present invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the steps of the method for monitoring the state of FPGA in the CT device are implemented.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The method for monitoring the FPGA status in the CT device provided by the present invention can accurately and quickly display the status of each FPGA in the CT device through the DMS software without increasing the hardware cost, thereby realizing rapid fault location and troubleshooting of the CT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0025] Figure 1 The DMS software interface of the present invention;

[0026] Figure 2 This is a schematic diagram of the connection relationship between the boards in the CT device of the present invention;

[0027] Figure 3 DMS software interface for DCB to read parameter results;

[0028] Figure 4 DMS software interface for reading parameter results for DIF;

[0029] Figure 5a to Figure 5c All are DMS software interfaces of DBB reading parameter results. DETAILED DESCRIPTION

[0030] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0031] Example

[0032] The present invention relates to a state monitoring method of FPGA in a CT device, wherein the CT device includes a DCB board with a DCB_FPGA chip, a DIF board with a DIF_FPGA chip, and a DBB board with a DBB_FPGA chip. DMS software is used as a human-computer interaction module, and a drop-down box in the upper left corner of the DMS software is for board selection, including DCB, DIF, DBB, ADL and ADR. The DMS interface displays the state information of each board. The middle drop-down box of the DMS software is for selecting the communication address of the DIF board and the DBB board.

[0033] The human-computer interaction module exchanges data with GCC through the network port. GCC is located in the stator part of the CT equipment and is used to process information interaction between the upper computer and the lower computer. GCC exchanges data with DCB embedded through the CAN bus.

[0034] The method specifically includes: sending a status read command with target board information to each board in the CT device through the human-computer interaction module. After receiving the status read command, the target board feeds back the FPGA status information in the board to the human-computer interaction module, and the human-computer interaction module displays the read FPGA status information. When the target board is a DIF board and a DBB board, the status read command also includes the communication address of the target board. The DMS software selects the board status to be read, clicks OK, and sends the information to the GCC board through the network port. The GCC board sends the information to the DCB embedded chip through the CAN bus. The DCB embedded chip sends the information to the DCB FPGA chip through EIM communication. If the DMS software user selects a DCB board, the DCB board will send all address information to the DCB embedded through EIM, the DCB embedded will send it to the GCC through the CAN bus, and the GCC will send it to the DMS software through the network port. The information is sent to the DMS software through the network port. It is displayed through the DMS software. If the DMS software user selects the DIF board, the DCB board will send the address information to the FPGA chip of the DIF board through the differential signal line (LVDS), and the DIF will feed back the address information to the DCB through the differential signal line. Finally, the information is displayed through the DMS software. If the DMS software user selects the DBB board, the DCB board will send the address information to the DIF board through the differential signal line, and the DIF board will send the address information to the FPGA chip of the DBB board through the differential signal line. The address information will be transmitted to the DCB in the same way, and finally the information is displayed through the DMS software.

[0035] Below, combined with the attached Figure 1 - Figure 5 further describes the present invention in detail: Figure 1 As shown in the figure, the Module in the upper left corner of the DMS software interface is used to select different boards including ADL, ADR, DIF, DBB, and DCB, among which ADL and ADR are used to read the detector status information; the DBB board is located at the front end of the acquisition link, used to control the working status of the detector, and unpack and verify the data transmitted by the detector; the DIF board is located in the middle of the acquisition link, used to unpack and verify the data transmitted by 52 DBBs, and send the re-packaged data to the DCB; the DCB board is located at the back end of the acquisition link, mainly to unpack and verify the data transmitted by the two DIFs, and re-sort the data and send it to the host computer through optical fiber; the middle Address can select different addresses to display different information of the DIF board when selecting the DIF board; the OK button in the upper right corner, after selecting the board and the middle address, click the OK button to read the FPGA status feedback information of the selected board in the information box below.

[0036] Figure 2It is a system block diagram of the present invention, wherein the DMS software is located in the PC, and exchanges data with the GCC through the network port. The GCC is located in the stator part of the CT device and is used to process the information exchange between the upper computer and the lower computer. The GCC exchanges data with the DCB embedded system through the CAN bus, and the DCB embedded system exchanges data with the DCB_FPGA through the EIM bus. The DCB_FPGA exchanges data with the DIF_FPGA through the differential signal line (LVDS), and the DIF_FPGA exchanges data with the DBB_FPGA through the LVDS. The data type is distinguished at the bus address 14. If the data sent is 16'haaaa, the status information to be read this time is the status information of the DCB_FPGA; if the data sent is 16'hbbbb, then this The status information that needs to be read this time is the status information of DIF_FPGA; if it is sent as 16'hcccc, the status information that needs to be read this time is the status information of DBB_FPGA; if the data received by DCB_FPGA at EIM address 14 is not 16'haaaa, the data will be sent to the DIF board via LVDS. The DIF board will judge the data. If it is 16'hbbbb, it will read the following DMS address information, and then send the data of the address information back via LVDS and finally display it on the DMS software. If it is 16'hcccc, the data will be sent to the DBB board via LVDS. The DBB board will read the DMS address information, send the data of the address information back via LVDS and finally display it on the DMS software.

[0037] Figure 3 Read parameter results for DCB. Because FPGA has the advantage of parallel processing of information, the key information of the data can be recorded and stored in the register during the data acquisition process. For example, during the data acquisition process, DCB will receive the data transmitted by DIF through LVDS, and after serial-to-parallel processing in DCB, it will form a data frame with 3C3C as the packet header, FCFC as the packet tail, and CRC check. When DCB unpacks the data frame to obtain valid data, it will count the header and tail of each received data packet, and compare the local CRC check result with the CRC check result in the data frame. If they are different, the different results will be recorded. After the data acquisition is completed, the recorded information can be read through the DMS software, such as Figure 3As shown, DCB_VER_ADDR is the decimal display of the hexadecimal program version, 16'd1 is 16'h1, so the program version is 001 version; similarly, DCB_VER_DATE_ADDR is the date, 16'd1287 is 16'h507, which is the date of May 7; STA0_ADDR is the low 16 bits for counting the header of the data frame transmitted from DIF, STA1_ADDR is the high 16 bits for counting the header of the data frame transmitted from DIF; STA2_ADDR is the low 16 bits for counting the tail of the data frame transmitted from DIF, STA3_ADDR is the high 16 bits for counting the tail of the data frame transmitted from DIF; STA13_ADDR is the count of CRC check errors. The remaining addresses are not explained in the content of the present invention.

[0038] Figure 4 The result of reading the version date of DIF is 16'd1287 is 16'h507, so the program date is May 7. Because the data transmission between DCB and DIF is transmitted via LVDS, the address of one DIF is read each time. There are two DIF boards in the system, so the interface is displayed as DIFL and DIFR. During the data acquisition process, key information will also be recorded. For example, for the data frame transmitted by the DBB board, the DIF board will also count the header, tail and CRC check errors while unpacking, and will also count the header and tail of the data packet sent. In this way, when a fault occurs, it can be determined whether a packet loss has occurred between DIF and DCB by reading the number of headers and tails received by DCB and the number of headers and tails sent by DIF. The remaining addresses are not explained in the content of the present invention.

[0039] like Figure 5a to Figure 5c , is the result of DBB reading the version date, 16'd1287 is 16'h507, so the program date is May 7. Because the data transmission between DIF and DBB is transmitted via LVDS, only one DBB address can be read each time. There are 52 DBB boards in the system, so the interface displays dbb0-dbb51. During the data acquisition process, DBB will also record key information, such as recording the temperature value in the detector data packet and counting the header and tail of the data packet sent. When a fault occurs, the header and tail of the packet sent by DBB and the header and tail of the packet received by DIF can be compared to determine whether data loss has occurred in this link. The remaining addresses are not explained in the content of the present invention.

[0040] Those skilled in the art know that, in addition to implementing the system, device and its various modules provided by the present invention in a purely computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, the system, device and its various modules provided by the present invention can be considered as a hardware component, and the modules included therein for implementing various programs can also be considered as structures within the hardware component; the modules for implementing various functions can also be considered as both software programs for implementing the method and structures within the hardware component.

[0041] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A method for monitoring the FPGA status in a CT device, characterized in that: include: A status reading command with target board information is sent to each board in the CT device through the human-computer interaction module. After receiving the status reading command, the target board feeds back the FPGA status information in the board to the human-computer interaction module, and the human interaction module displays the read FPGA status information. The CT device includes a DCB board with a DCB_FPGA chip, a DIF board with a DIF_FPGA chip, and a DBB board with a DBB_FPGA chip; The human-computer interaction module is connected to the DCB board, the other end of the DCB board is connected to the DIF board, and the other end of the DIF board is connected to the DBB board.

2. The method for monitoring the FPGA status in a CT device according to claim 1, characterized in that: When the target board is a DIF board or a DBB board, the status reading command further includes the communication address of the target board.

3. The method for monitoring the FPGA status in a CT device according to claim 1, characterized in that: The human-computer interaction module is specifically the DMS software, which includes a drop-down box for board selection, including DCB, DIF, DBB, ADL and ADR; The DMS interface displays the status information of each board; The DMS software includes a drop-down box for DIF board and DBB board communication address selection; ADL and ADR are temporarily reserved interfaces for reading detector parameters; The DMS software selects the board status to be read, clicks OK, and sends the information to the GCC board through the network port. The GCC board is located in the stator part of the equipment, and communicates with the host computer through the network cable for parameters, and communicates with the DCB embedded in the rotor part through the CAN bus through the slip ring. The GCC board sends the scanning information sent by the host computer to each corresponding component, and transmits the feedback information of each component to the host computer.

4. The method for monitoring the FPGA status in a CT device according to claim 1, characterized in that: The DCB embedded chip sends information to the DCB FPGA chip through EIM communication.

5. The method for monitoring the FPGA status in a CT device according to claim 1, characterized in that: If the DMS software user selects a DCB board, the DCB board sends all address information to the DCB embedded through the EIM, the DCB embedded sends it to the GCC through the CAN bus, the GCC sends it to the DMS software through the network port, and the information is displayed by the DMS software.

6. The method for monitoring the FPGA status in a CT device according to claim 1, characterized in that: If the DMS software user selects a DIF board, the DCB board sends the address information to the FPGA chip of the DIF board through the differential signal line, and the DIF feeds the address information back to the DCB through the differential signal line, and finally the information is displayed through the DMS software.

7. The method for monitoring the FPGA status in a CT device according to claim 1, characterized in that: If the DMS software user selects a DBB board, the DCB board sends the address information to the DIF board via the differential signal line, and the DIF board sends the address information to the FPGA chip of the DBB board via the differential signal line, and then passes it to the DCB, and finally the information is displayed through the DMS software.

8. A monitoring system for FPGA status in a CT device, characterized in that: A method for monitoring the FPGA status in a CT device according to any one of claims 1 to 7, comprising: sending a status reading command with target board information to each board in the CT device through a human-computer interaction module, and after receiving the status reading command, the target board feeds back the FPGA status information in the board to the human-computer interaction module, and the human interaction module displays the read FPGA status information.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method for monitoring the state of an FPGA in a CT device according to any one of claims 1 to 7 are implemented.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the computer program is executed by a processor, the steps of the method for monitoring the state of an FPGA in a CT device according to any one of claims 1 to 7 are implemented.

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