Multi-thread beam debugging method and device and artificial intelligence chip

Abstract

The invention provides a multi-thread beam debugging method and device and an artificial intelligence chip, and relates to the technical field of artificial intelligence, and the method comprises the steps: determining an expected thread beam to trigger debugging based on a comparison result of instruction information of executing an original program by each thread beam and instruction information stored in a target register group, and a thread beam identifier of each thread beam; sending debugging trigger information to a processor to enable the processor to send debugging enabling information to each thread bundle, and controlling the unexpected thread bundle to wait for the expected thread bundle to be debugged; based on the debugging enabling information, controlling the expected thread bundle to execute the debugging program based on an instruction address of the debugging program stored in the target register group; and sending debugging ending information to the processor to enable the processor to send debugging stopping information to each thread bundle, and controlling each thread bundle to continue to execute the original program. According to the method and the device provided by the invention, the debugging aiming at the specific thread beam can be realized in the multi-thread beam parallel computing process.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to a multi-threaded bundle debugging method, device and artificial intelligence chip. Background Art

[0002] As the size of programs continues to grow, software developers have an increasingly urgent need for program functionality. They expect hardware to provide precise debugging support, allowing developers to check the execution of instructions line by line or section by section, and then deeply analyze the execution characteristics of the program. In this way, developers can more efficiently optimize program performance and ensure efficient operation of the software.

[0003] However, in parallel computing, multiple warps participate in scheduling and arbitration at the same time, and the execution content of each warp is both independent and different from each other. Most existing program debugging methods are only applicable to single-threaded programs and cannot meet the debugging needs of multi-warp parallel computing.

[0004] Therefore, how to implement multi-threaded bundle debugging in parallel computing has become a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0005] The present invention provides a multi-threaded bundle debugging method, device and artificial intelligence chip, which are used to solve the technical problem of how to implement multi-threaded bundle debugging in parallel computing.

[0006] The present invention provides a multi-thread warp debugging method, comprising: Determine the expected warp to trigger debugging based on the comparison result of the instruction information of the original program executed by each warp and the instruction information stored in the target register group, and the warp identifier of each warp; Sending debug trigger information to a processor so that the processor sends debug enable information to each thread warp, and controls an unexpected thread warp to wait for the expected thread warp to be debugged; Based on the debugging enable information, controlling the expected thread warp to execute the debugging program based on the instruction address of the debugging program stored in the target register group; Debug end information is sent to the processor, so that the processor sends debug stop information to each thread warp, and controls each thread warp to continue to execute the original program.

[0007] In some embodiments, the target register set is a memory-mapped input / output register; the target register set includes a mode enable register, a trigger information register, and a debugger instruction address register; The mode enable register is used to define the debugging trigger mode and the number of the trigger information registers; the trigger mode includes an instruction address trigger mode or an instruction type trigger mode; The trigger information register is used to store instruction information for triggering debugging; the instruction information includes an instruction address or an instruction type; The debugger instruction address register is used to store the instruction address of the debugger.

[0008] In some embodiments, the step of determining the expected warp to trigger debugging based on the comparison result of the instruction information of the original program executed by each warp with the instruction information stored in the target register group, and the warp identifier of each warp, includes: Determine that each thread warp triggers debugging based on a comparison result between instruction information of the original program executed by each thread warp and instruction information stored in the target register group; Based on the comparison result between the warp identifiers of each warp and the warp identifier of the expected warp, it is determined that the expected warp triggers debugging.

[0009] In some embodiments, the debug trigger information includes a warp identifier of a warp that triggers debug; and the processor is configured to determine that the warp is the expected warp based on the warp identifier of the warp.

[0010] In some embodiments, after controlling the expected thread warp to execute the debug program based on the instruction address of the debug program stored in the target register group based on the debug enable information, the method further includes: The executed instruction addresses of the original program are recorded; and the processor is configured to control each thread warp to continue to execute the original program based on the executed instruction addresses after debugging is completed.

[0011] In some embodiments, the processor is configured to configure the target register set based on a trigger mode, an instruction address, an instruction type of the original program and an instruction address of the debugger.

[0012] The present invention provides a multi-thread bundle debugging device, comprising: A comparison module, configured to determine an expected warp to trigger debugging based on a comparison result between instruction information of each warp executing the original program and instruction information stored in the target register group, and warp identifiers of each warp; A first sending module, configured to send debugging trigger information to a processor, so that the processor sends debugging enable information to each thread warp, and controls an unexpected thread warp to wait for the expected thread warp to be debugged; an execution module, configured to control the expected thread warp to execute the debug program based on an instruction address of the debug program stored in the target register group based on the debug enable information; The second sending module is used to send debugging end information to the processor, so that the processor sends debugging stop information to each thread warp to control each thread warp to continue executing the original program.

[0013] The present invention provides an artificial intelligence chip, comprising: The target register group is used to define the debugging trigger mode and store the instruction information for triggering debugging and the instruction address of the debugger; A scheduling control unit is connected to the target register group and is used to execute the multi-thread warp debugging method and control the expected warp to be debugged among the multiple warps.

[0014] The present invention provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the multi-threaded warp debugging method is implemented when the processor executes the computer program.

[0015] The present invention provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the multi-thread warp debugging method is implemented.

[0016] The multi-thread bundle debugging method, device and artificial intelligence chip provided by the present invention store instruction information for triggering debugging and instruction address of the debugging program in advance in the target register group. During the process of each thread bundle executing the instruction information of the original program, it is determined whether the thread bundle triggers debugging by comparing the instruction information, and whether it is the expected thread bundle by the thread bundle identifier. Therefore, debugging can be performed for a specific thread bundle during the multi-thread bundle parallel computing process. The processor is used to enable and stop debugging, and the unexpected thread bundle is controlled to wait for the expected thread bundle for debugging, thereby avoiding data pollution and achieving accurate debugging for the specific thread bundle. In addition, only the target register group needs to be configured, and the original program does not need to be modified, thereby avoiding the change of instruction address caused by replacing the original program instructions or inserting debugging instructions, thereby improving the accuracy of multi-thread bundle debugging in parallel computing and improving the efficiency of multi-thread bundle debugging. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a flowchart diagram of the multi-threaded warp debugging method provided by the present invention.

[0020] Figure 2 It is a schematic diagram of the software program provided by the present invention.

[0021] Figure 3 Schematic diagram of the target register group provided by the present invention.

[0022] Figure 4 It is a structural schematic diagram of the multi-thread bundle debugging device provided by the present invention.

[0023] Figure 5 This is one of the structural schematic diagrams of the artificial intelligence chip provided by the present invention.

[0024] Figure 6 This is the second structural schematic diagram of the artificial intelligence chip provided by the present invention.

[0025] Figure 7 It is a working schematic diagram of the scheduling control unit provided by the present invention.

[0026] Figure 8 It is a schematic diagram of the execution flow of the debugging program provided by the present invention.

[0027] Fig. 9 It is a schematic diagram of the jump of the thread warp state provided by the present invention.

[0028] Fig.10 It is a schematic diagram of multi-thread bundle debugging provided by the present invention.

[0029] Fig.11 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units or modules is not necessarily limited to those steps or units or modules that are clearly listed, but may include other steps or units or modules that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] Setting breakpoints and single-step execution are the basis for accurate debugging. The following methods are used in related technologies for program debugging: (1) Set breakpoints in the software program. When debugging a program, insert a breakpoint instruction where a problem may occur. When the program is executed on the hardware, when it reaches a breakpoint, it enters debug mode and executes the debug program. This method requires modifying the content of the original program. The modification method includes replacing a certain instruction of the original program with a breakpoint instruction or inserting a breakpoint instruction at a certain position. There is generally data dependency between the previous and next instructions in the program. Replacing instructions requires careful consideration of the program content and then replacing them at a location that does not affect the program function. The usage requirements and restrictions are high. Inserting a breakpoint instruction will change the program sequence after the breakpoint, resulting in inaccurate debugging.

[0033] (2) Setting hardware breakpoints. That is, using the debug address register defined by the hardware to implement breakpoints. After the program executes to the defined debug address, it enters the debug mode and executes the debug program. This method relies on the number of debug address registers reserved in the hardware, which is easily limited in number and can only debug instruction addresses, lacking flexibility.

[0034] (3) Set the single-step execution register. After configuring this register, the program will jump to the debugger every time it executes an instruction, and then perform exception handling and execution. After using this method, the original program will enter the debug mode every time it executes an instruction, and then execute the debugger. This method may introduce redundant debugging and trigger at locations that do not need debugging.

[0035] The above methods can only be applied to single-thread execution debugging and cannot meet the debugging requirements of multi-threaded parallel computing.

[0036] In order to solve the shortcomings of related technologies, Figure 1 FIG. 1 is a flow chart of the multi-thread bundle debugging method provided by the present invention. Figure 1 As shown, the method includes step 110 , step 120 , step 130 and step 140 .

[0037] Step 110 : Determine the expected warp triggering debugging based on the comparison result between the instruction information of the original program executed by each warp and the instruction information stored in the target register group, and the warp identifier of each warp.

[0038] Specifically, the execution subject of the multi-thread warp debugging method provided in the embodiment of the present invention is a multi-thread warp debugging device. The device can be implemented by software, such as a multi-thread warp debugging program running in an artificial intelligence chip, etc.; it can also be implemented by hardware, such as a warp scheduler (WarpScheduler) that executes the multi-thread warp debugging method in an artificial intelligence chip, etc.

[0039] A warp is a collection of threads that share the same instruction stream during execution. These threads run the same instructions simultaneously in a single instruction multiple data (SIMD) manner, but process different data. For example, in some artificial intelligence chips, a warp usually contains 32 threads.

[0040] The warp ID is the unique number of the warp. The warp ID can be calculated from the thread index and is used to distinguish different warps. The expected warp is a specific warp that is expected to be debugged. The number of expected warps can be one or more. Accordingly, the remaining warps except the expected warp can be considered as unexpected warps. The number of unexpected warps can be zero or more.

[0041] The original program refers to the initial version of the program, that is, the program code that has not been modified, optimized or debugged. The debugger refers to the program code used to detect, locate and repair errors (bugs) in the original program.

[0042] Figure 2 is a schematic diagram of the software program provided by the present invention, such as Figure 2 As shown in the figure, PC stands for Program Counter, PC0~PCN stands for instruction addresses 0 to N. Inst stands for Instruction, Inst0~InstN stands for instruction addresses 0 to N. Each instruction has a unique corresponding instruction address.

[0043] Instruction information refers to information related to instruction execution, usually including instruction address and instruction type. The instruction address is the value of the program counter, which is used to identify the location of the currently executed instruction in the memory. It determines the execution order of the program and supports operations such as branching, jumping, and function calling. Instruction type refers to the functional classification of instructions, such as arithmetic instructions, logical instructions, memory access instructions, control flow instructions, and special instructions.

[0044] The target register group refers to a storage unit in the artificial intelligence chip for temporarily storing information such as data, instructions or addresses. Instruction information for triggering debugging can be stored in the target register group. These instruction information can be set in advance according to debugging requirements. In an embodiment of the present invention, debugging specifically refers to breakpoint debugging, which pauses the execution of the program by setting a breakpoint in the code. A breakpoint is a mark that instructs the debugger to pause when the program executes to that location, allowing the developer to check the status of the program.

[0045] During the process of executing the original program by each thread warp, the instruction information executed by each thread warp can be compared with the instruction information stored in the target register group, for example, the instruction address or instruction type can be compared. If the comparison result is consistent, it can be determined that each thread warp is triggered for debugging. Then, the thread warp identifier of each thread warp that triggers debugging is compared with the thread warp identifier of the expected thread warp. If the comparison result is consistent, it can be determined that the expected thread warp triggers debugging.

[0046] Step 120: Send debugging trigger information to the processor, so that the processor sends debugging enable information to each thread warp, and controls the unexpected thread warp to wait for the expected thread warp to be debugged.

[0047] Specifically, the processor is used to manage each thread bundle. In an embodiment of the present invention, the processor can be a central processing unit (CPU) for managing thread bundles independent of the artificial intelligence chip, or a processor for managing thread bundles set inside the artificial intelligence chip, such as a streaming multiprocessor (SM) set in some graphics processing units (GPUs). The streaming multiprocessor and the thread bundle scheduler jointly implement the management of thread bundles.

[0048] Debug trigger information may be sent to the processor, where the information is used to prompt the processor that the expected thread warp has run to an instruction address that may trigger debugging or that the instruction type processed may trigger debugging.

[0049] After receiving the debug trigger information, the processor can send debug enable information (debugmode on) to each thread bundle. For the expected thread bundle, the expected thread bundle can be controlled to execute the debug program; for the unexpected thread bundle, it is necessary to wait for the expected thread bundle to be debugged. This is to prevent the unexpected thread bundle from continuing to execute the original program in debug mode and updating the data, causing data pollution.

[0050] Step 130 : Based on the debugging enable information, control the intended thread warp to execute the debugging program based on the instruction address of the debugging program stored in the target register group.

[0051] Specifically, after receiving the debug enable information sent by the processor, the intended thread warp may be controlled to obtain the debug program code according to the instruction address of the debug program stored in the target register group, thereby executing the debug program.

[0052] Step 140: Send debugging end information to the processor, so that the processor sends debugging stop information to each thread warp, and controls each thread warp to continue executing the original program.

[0053] Specifically, after the expected warp finishes executing the debug program, debugging end information may be sent to the processor.

[0054] After receiving the debugging end information, the processor may send debugging stop information (debugmode off) to each thread warp. Each thread warp may continue to obtain instruction information of the original program and execute the original program.

[0055] The multi-thread bundle debugging method provided by the embodiment of the present invention determines the expected thread bundle to trigger debugging based on the comparison result of the instruction information of each thread bundle executing the original program and the instruction information stored in the target register group, as well as the thread bundle identifier of each thread bundle; sends debugging trigger information to the processor so that the processor sends debugging enable information to each thread bundle, and controls the unexpected thread bundle to wait for the expected thread bundle to be debugged; based on the debugging enable information, controls the expected thread bundle to execute the debugging program based on the instruction address of the debugging program stored in the target register group; sends debugging end information to the processor so that the processor sends debugging stop information to each thread bundle, and controls each thread bundle to continue to execute the original program; because the instruction information for triggering debugging is pre-stored in the target register group and the instruction address of the debugging program. In the process of each thread bundle executing the instruction information of the original program, whether the thread bundle triggers debugging is determined by comparing the instruction information, and whether it is the expected thread bundle is determined by the thread bundle identifier. Debugging can be implemented for a specific thread bundle during multi-thread bundle parallel computing. Debugging is enabled and debugged by the processor, and unexpected thread bundles are controlled to wait for the expected thread bundle for debugging, thereby avoiding data pollution and realizing accurate debugging for a specific thread bundle. In addition, only the target register group needs to be configured, and the original program does not need to be modified, thereby avoiding the change of instruction addresses caused by replacing the original program instructions or inserting debugging instructions, thereby improving the accuracy of multi-thread bundle debugging in parallel computing and improving the efficiency of multi-thread bundle debugging.

[0056] It should be noted that each implementation of the present invention can be freely combined, the order can be changed, or it can be executed separately, and does not need to rely on or depend on a fixed execution order.

[0057] In some embodiments, the target register set is a memory-mapped input-output register; the target register set includes a mode enable register, a trigger information register, and a debugger instruction address register; The mode enable register is used to define the debugging trigger mode and the number of trigger information registers; the trigger mode includes the instruction address trigger mode or the instruction type trigger mode; The trigger information register is used to store the instruction information for triggering debugging; the instruction information includes the instruction address or the instruction type; The debugger instruction address register is used to store the debugger instruction address.

[0058] Specifically, the target register group can be implemented using memory-mapped input and output registers (MMIO registers). Memory-mapped input and output registers refer to mapping the control registers and data registers of hardware devices to registers in the address space of the processor through memory-mapped I / O (MMIO) technology. In this way, the operating system and programs can access the hardware devices through conventional memory access instructions (such as read and write operations) without using special input / output instructions.

[0059] Figure 3 is a schematic diagram of the target register group provided by the present invention, such as Figure 3 As shown, the target register group includes a mode enable register, a trigger information register, and a debugger instruction address register. Each register may include 32 bits.

[0060] The mode enable register may be numbered R0, which is used to define the debug trigger mode and the number of trigger information registers; the trigger mode includes the instruction address trigger mode or the instruction type trigger mode. For example, the first and second bits in the register may represent bit[1:0], and when these two bits are 00, it indicates the instruction address trigger mode; when these two bits are 01, it indicates the instruction type trigger mode; other values ​​are temporarily reserved. The third to 32nd bits in the register may represent bit[31:2], which may be used to define the number of trigger information registers.

[0061] The number of trigger information registers can be set according to actual needs. There can be multiple trigger information registers (the number is N), and the number can be expressed as R1~RN. Generally, N is 8 or 16.

[0062] In the instruction address trigger mode, the trigger information register is used to store the instruction address that triggers debugging. When the original program executes to the instruction address, an interrupt is triggered and debugging is started.

[0063] In the instruction type trigger mode, the trigger information register is used to store the instruction type that triggers debugging. For example, bits 32 to 17 in the register can represent bit[31:16], which is used to store the instruction type; bits 16 to 1 in the register can represent bit[15:0], which is used to store the trigger count M corresponding to the instruction type. When the original program executes this instruction type, an interrupt is triggered and debugging is entered. After the debugging is completed, the trigger count M is updated to M-1. When the instruction type is executed next time, the interrupt continues to be triggered, debugging is entered, and the trigger count is updated again. Multiple instruction types can be configured, and the trigger counts for each instruction type can be customized.

[0064] The debugger instruction address register may be numbered RN+1, and is used to store the debugger instruction address, and specifically may be the initial instruction address of the debugger.

[0065] The multi-thread warp debugging method provided by the embodiment of the present invention configures the target register group, pre-sets the trigger mode, the instruction information for triggering debugging and the instruction address of the debugging program, and can debug a specific thread warp during the multi-thread warp parallel computing process by comparing the instruction information.

[0066] In some embodiments, based on the comparison result of the instruction information of the original program executed by each thread warp and the instruction information stored in the target register group, and the thread warp identifier of each thread warp, determining the expected thread warp to trigger debugging includes: Determine that each thread warp triggers debugging based on a comparison result between instruction information of the original program executed by each thread warp and instruction information stored in the target register group; Based on the comparison result between the warp identifiers of each warp and the warp identifier of the expected warp, it is determined that the expected warp triggers debugging.

[0067] Specifically, the multi-threaded bundle debugging device can specifically perform a comparison function of instruction information, including comparison of instruction addresses and instruction types. When performing the comparison of instruction addresses, the multi-threaded bundle debugging device determines whether to jump according to the comparison result of the instruction addresses, and then executes the jump program. When performing the comparison of instruction types, the multi-threaded bundle debugging device can also record the number of times the instruction type has been triggered, and determine whether to jump according to the comparison result of the instruction type and the number of times it has been triggered, and then execute the jump program.

[0068] First, the instruction information of the original program executed by each thread warp is compared with the instruction information stored in the target register group. If the comparison result of the instruction information is consistent, it can be determined that each thread warp triggers debugging. Considering that the execution speed of each thread warp is different, the above comparison is also performed in sequence, but each thread warp will be compared.

[0069] Furthermore, the warp identifiers of the warps that trigger debugging are compared with the warp identifiers of the expected warps. If the comparison result of the warp identifiers is consistent, it can be determined that the expected warp triggers debugging.

[0070] The multi-thread warp debugging method provided by the embodiment of the present invention can debug a specific warp during the multi-thread warp parallel computing process by comparing instruction information with warp identifiers.

[0071] In some embodiments, the debug triggering information includes a warp identifier of a warp that triggers debug; and the processor is configured to determine that the warp is an expected warp based on the warp identifier of the warp.

[0072] Specifically, the debugging trigger information sent by the multi-thread warp debugging apparatus to the processor should at least include the warp identifier of the warp that triggers debugging.

[0073] After receiving the debug trigger information, the processor may also compare the warp identifier of the warp with the warp identifier of the expected warp. If the comparison result of the warp identifiers is consistent, it may be determined that the expected warp triggers debugging, thereby sending debug enable information to each warp.

[0074] The multi-thread warp debugging method provided by the embodiment of the present invention determines the expected warp to trigger debugging through a processor, thereby improving the accuracy of implementing multi-thread warp debugging in parallel computing.

[0075] In some embodiments, after controlling the expected warp to execute the debug program based on the instruction address of the debug program stored in the target register group based on the debug enable information, the method further includes: The executed instruction addresses of the original program are recorded; the processor is configured to control each thread warp to continue to execute the original program based on the executed instruction addresses after debugging is completed.

[0076] Specifically, the multi-thread warp debugging device also records the executed instruction addresses of the original program when entering debugging. After debugging is completed, each thread warp can be controlled to continue to execute the instructions in the original program according to the executed instruction addresses.

[0077] The multi-thread warp debugging method provided by the embodiment of the present invention records the executed instruction addresses of the original program and controls each thread warp to continue executing the original program after debugging is completed, which can ensure that the execution logic and state of the original program are not disturbed by the debugging process, improve the reliability of debugging, support complex debugging operations, and reduce the impact of debugging on program performance.

[0078] In some embodiments, the processor is configured to configure the target register set based on a trigger mode, an instruction address, an instruction type of the original program, and an instruction address of the debugger.

[0079] Specifically, before executing the original program through the multi-threaded warp, the trigger mode, instruction address, instruction type of the original program and the instruction address of the debugger may be determined in advance.

[0080] The mode enable register in the target register group is configured according to the trigger mode; the trigger information register in the target register group is configured according to the instruction address or instruction type; and the debugger instruction address register in the target register group is configured according to the debugger instruction address.

[0081] The multi-thread warp debugging method provided by the embodiment of the present invention configures the target register group in advance, avoids setting breakpoints in the original program, and does not need to set breakpoints through hardware. It can debug specific thread warps during multi-thread warp parallel computing, improves debugging reliability, supports complex debugging operations, and reduces the impact of debugging on program performance.

[0082] The following describes an apparatus provided by an embodiment of the present invention. The apparatus described below and the method described above can refer to each other.

[0083] Figure 4 Schematic diagram of the structure of the multi-thread bundle debugging device provided by the present invention. Figure 4 As shown, the device comprises: A comparison module 410 is used to determine the expected warp triggering debugging based on the comparison result between the instruction information of the original program executed by each warp and the instruction information stored in the target register group, and the warp identifier of each warp; A first sending module 420 is used to send debugging trigger information to the processor, so that the processor sends debugging enable information to each thread warp, and controls the unexpected thread warp to wait for the expected thread warp to be debugged; An execution module 430 is used to control the expected thread warp to execute the debug program based on the instruction address of the debug program stored in the target register group based on the debug enable information; The second sending module 440 is used to send debugging end information to the processor, so that the processor sends debugging stop information to each thread warp to control each thread warp to continue executing the original program.

[0084] The multi-thread bundle debugging device provided by the embodiment of the present invention determines that the expected thread bundle triggers debugging based on the comparison result of the instruction information of each thread bundle executing the original program and the instruction information stored in the target register group, as well as the thread bundle identifier of each thread bundle; sends debugging trigger information to the processor so that the processor sends debugging enable information to each thread bundle, and controls the unexpected thread bundle to wait for the expected thread bundle to be debugged; based on the debugging enable information, controls the expected thread bundle to execute the debugging program based on the instruction address of the debugging program stored in the target register group; sends debugging end information to the processor so that the processor sends debugging stop information to each thread bundle, and controls each thread bundle to continue to execute the original program; Since the instruction information for triggering debugging and the instruction address of the debugger are pre-stored in the target register group, in the process of each thread bundle executing the instruction information of the original program, whether the thread bundle triggers debugging is determined by comparing the instruction information, and whether it is an expected thread bundle is determined by the thread bundle identifier, so that debugging can be performed on a specific thread bundle during multi-thread bundle parallel computing; debugging is enabled and debugged by the processor, and unexpected thread bundles are controlled to wait for expected thread bundles for debugging, thereby avoiding data pollution and achieving precise debugging on specific thread bundles; the accuracy of multi-thread bundle debugging in parallel computing is improved, and the efficiency of multi-thread bundle debugging is improved.

[0085] Figure 5 This is one of the structural schematic diagrams of the artificial intelligence chip provided by the present invention, such as Figure 5 As shown, the artificial intelligence chip 500 includes: The target register group 510 is used to store instruction information for triggering debugging.

[0086] The scheduling control unit 520 is connected to the target register group 510 and is used to execute the multi-thread warp debugging method in the above embodiment and control the expected warp to be debugged among the multiple warps.

[0087] Specifically, artificial intelligence chips can be graphics processing units (GPUs), general-purpose graphics processing units (GPGPUs), domain-specific architectures (DSAs), etc.

[0088] The artificial intelligence chip provided by the embodiment of the present invention, in a parallel computing scenario, can pre-store instruction information for triggering debugging and the instruction address of the debugging program in the target register group because a target register group and a scheduling control unit are set. In the process of each thread bundle executing the instruction information of the original program, the scheduling control unit determines whether the thread bundle triggers debugging by comparing the instruction information, and determines whether it is an expected thread bundle by the thread bundle identifier, so that debugging can be implemented for a specific thread bundle during multi-thread bundle parallel computing; thereby improving the accuracy of multi-thread bundle debugging in parallel computing and improving the efficiency of multi-thread bundle debugging.

[0089] Figure 6 This is the second structural diagram of the artificial intelligence chip provided by the present invention, such as Figure 6 As shown, the artificial intelligence chip 500 includes not only a target register group 510 and a scheduling control unit 520, but also an instruction cache unit 530, an instruction fetch unit 540, a decoding unit 550 and an execution unit 560. The processor 600 can be a processor set inside the artificial intelligence chip, or a processor independent of the artificial intelligence chip. The external storage 610 is a storage device connected to the artificial intelligence chip. The target register group can specifically be an MMIO register group.

[0090] The AI ​​chip introduces the MMIO register group, configures the MMIO registers and debugger through the processor (Host side), and realizes the synchronization and debugging of multiple thread warps. Among them, the MMIO register group defines the setting and triggering mode of breakpoints, and supports triggering based on instruction addresses and instruction types. The debugger and Host implement targeted debugging of specific thread warps (Expect Warp), and support debugging one or more thread warps at the same time. The scheduling control unit obtains the information in the MMIO register group and the program instruction information, triggers interrupts and retains the execution status of the original program.

[0091] Figure 7 is a schematic diagram of the operation of the scheduling control unit provided by the present invention, such as Figure 7 As shown, the scheduling control unit can perform a comparison function of instruction information, including comparison of instruction addresses and instruction types.

[0092] The scheduling control unit obtains the instruction information executed by the thread warp through the decoding unit, and records the number of times the instruction type has been triggered through the state machine when the interrupt triggers the comparator to compare the execution instruction type. According to the comparison result, it determines whether to jump, performs resource check, and then executes the jump program.

[0093] In the above embodiment, the processor (Host end) can configure the MMIO register group; receive the debugging request of each thread warp, determine whether it is an expected thread warp (Expect Warp), if it is, turn on the debugging mode, if not, ignore it. When the expected thread warp completes the current breakpoint debugging, turn off the debugging mode. When the processor detects that the expected thread warp has completed all breakpoint debugging, and then receives a debugging request from an unexpected thread warp (non-Expect Warp), it directly notifies it to exit.

[0094] In the above embodiment, the functional pseudo code of the debugging program is as follows: send signal->host loop: if(warp_id==expect id) wait debug mode on save temp reg dump reg / mem … send signal->host wait exit break else(warp_id!=expect id) wait exit break step return Figure 8 It is a schematic diagram of the execution flow of the debugging program provided by the present invention, such as Figure 8 As shown in the figure, the debugger is used to define the execution behavior of the hardware after entering the debug mode. The debugger and the host end jointly realize the execution synchronization and execution behavior definition of multiple thread bundles. The debugger has the following functions: sending requests to the host end; comparing the thread bundle identifiers of each thread bundle with the thread bundle identifiers of the expected thread bundle; exporting (Dump) registers and storage data; breakpoint recovery.

[0095] Based on the above embodiments, the overall process of the multi-thread warp debugging method provided by the present invention is described: 1. The host (processor) performs initialization configuration of the MMIO registers, sets the interrupt trigger mode and trigger enable, and configures the trigger information, such as configuring the trigger point such as the instruction address or the trigger count corresponding to the instruction type.

[0096] 2. The host loads the original program into the instruction cache unit.

[0097] 3. Each thread warp starts running, the instruction fetch unit initiates an instruction fetch request to the instruction cache unit, and the instruction cache unit returns the instruction.

[0098] 4. The decoding unit parses the instruction content and transmits it to the scheduling control unit.

[0099] 5. The scheduling control unit manages the allocation according to the instruction information and sends it to the execution unit for processing. Since the execution of each warp is independent and different, when the first or several warps execute to the debugging breakpoint, the scheduling control unit saves the original program execution instruction address, then jumps into the debugging program and sends a signal to the host. The host and the scheduling control unit each determine whether it is an expected warp.

[0100] (1) Host side: If yes, send debug mode on signal to all thread warps; if not, ignore it.

[0101] (2) Scheduling control unit: The scheduling control unit also compares the thread number identifier of the thread bundle with the thread bundle identifier of the expected thread bundle. If so, it waits for the host to enable and then executes the user-defined debugging program. After the execution is completed, it waits for the host to notify it to exit the debugging mode. If not, it directly waits for the host to notify it to exit the debugging mode.

[0102] (3) When the host receives a signal that the expected thread bundle has executed to the breakpoint, it turns on the debug mode; when it receives a signal that the expected thread bundle has completed executing the debug program, it turns off the debug mode.

[0103] 6. The expected thread bundle execution speed is uncertain. If the thread bundle that executes to the breakpoint first is not the expected thread bundle, it stops at the else branch of the debugger and waits to exit. Other thread bundles continue to execute. When the expected thread bundle executes to the breakpoint, the host turns on the debug mode. When the debug mode is turned on, some thread bundles may not reach the breakpoint yet. At this time, they jump directly to the debugger and stop at the else branch.

[0104] In debug mode, other thread warps are stopped and only the expected thread warp is working to prevent data pollution caused by the execution of unexpected thread warps.

[0105] 7. The debug trigger mode is divided into instruction address-based and instruction type-based. When triggered based on instruction address, when the thread bundle executes the original program to the corresponding instruction address, it is triggered and jumps to the debugger. When triggered based on instruction type, the scheduling control unit obtains the triggered instruction type and trigger number, combines the current instruction information of the decoding unit, determines whether to trigger, and then jumps to the debugger. After the expected thread bundle executes the debugger once, all thread bundles resume the original program execution state and continue execution.

[0106] 8. When the expected thread bundle executes all debugging breakpoints, if the host receives an unexpected thread bundle that executes to a breakpoint, an exit signal is directly generated.

[0107] 9. All thread warps continue to execute the original program until it ends.

[0108] Fig. 9 Schematic diagram of the jump of the thread warp state provided by the present invention, such as Fig. 9 As shown in the figure, the states of a warp are IDLE, RUN, and DEBUG. In the RUN state, the warp starts and executes the original program; in the DEBUG state, the debugger is executed. These three states can jump to each other.

[0109] Fig.10 Schematic diagram of multi-thread bundle debugging provided by the present invention, such as Fig.10 As shown, the original program has 2 breakpoints and 3 types of warps, namely Warp K, Warp M and Warp N. Warp M is the expected warp, and the number can be one or more. Warp K is an unexpected warp that executes faster than the expected warp, and the number can be zero or more. Warp N is an unexpected warp that executes slower than the expected warp, and the number can be zero or more.

[0110] When entering debug mode for the first time, Warp K first executes to the first breakpoint and enters the else branch of the debugger to wait. After Warp M executes to the first breakpoint, the host turns on debug mode, and then Warp M executes the debugger, forcing Warp N to enter debug mode and wait. Note that Warp N has not executed to the first breakpoint at this time.

[0111] When entering debug mode for the second time, Warp N executes to the first breakpoint and enters the else branch of the debugger to wait. After Warp M executes to the second breakpoint, the host turns on debug mode, and then Warp M executes the debugger, forcing Warp K to enter debug mode and wait. Note that Warp K has not executed to the second breakpoint at this time.

[0112] After Warp M completes all breakpoint debugging. After that, when Warp K executes to the second breakpoint, the host directly notifies to exit because it is an unexpected thread bundle. When Warp N executes to the second breakpoint, the host directly notifies to exit because it is an unexpected thread bundle.

[0113] Fig.11is a schematic diagram of the structure of the electronic device provided by the present invention, such as Fig.11 As shown, the electronic device may include: a processor (Processor) 1110, a communication interface (Communications Interface) 1120, a memory (Memory) 1130 and a communication bus (Communications Bus) 1140, wherein the processor 1110, the communication interface 1120, and the memory 1130 communicate with each other through the communication bus 1140. The processor 1110 may call the logic command in the memory 1130 to execute the method described in the above embodiment, for example: Based on the comparison results of the instruction information of the original program executed by each thread bundle and the instruction information stored in the target register group, as well as the thread bundle identifier of each thread bundle, determine the expected thread bundle to trigger debugging; send debug trigger information to the processor, so that the processor sends debug enable information to each thread bundle, and controls the unexpected thread bundle to wait for the expected thread bundle for debugging; based on the debug enable information, control the expected thread bundle to execute the debug program based on the instruction address of the debug program stored in the target register group; send debug end information to the processor, so that the processor sends debug stop information to each thread bundle, and controls each thread bundle to continue executing the original program.

[0114] In addition, the logic commands in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several commands to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program code.

[0115] The processor in the electronic device provided in the embodiment of the present invention can call the logic instructions in the memory to implement the above method. Its specific implementation method is consistent with the implementation method of the aforementioned method and can achieve the same beneficial effects, which will not be repeated here.

[0116] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method provided in the above embodiments is implemented.

[0117] Its specific implementation is consistent with the aforementioned method implementation and can achieve the same beneficial effects, so it will not be repeated here.

[0118] An embodiment of the present invention provides a computer program product, including a computer program. When the computer program is executed by a processor, the method described above is implemented.

[0119] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative work.

[0120] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-threaded bundle debugging method, characterized in that: include: Determine the expected warp to trigger debugging based on the comparison result of the instruction information of the original program executed by each warp and the instruction information stored in the target register group, and the warp identifier of each warp; Sending debug trigger information to a processor so that the processor sends debug enable information to each thread warp, and controls an unexpected thread warp to wait for the expected thread warp to be debugged; Based on the debugging enable information, controlling the expected thread warp to execute the debugging program based on the instruction address of the debugging program stored in the target register group; Debug end information is sent to the processor, so that the processor sends debug stop information to each thread warp, and controls each thread warp to continue to execute the original program.

2. The multi-thread warp debugging method according to claim 1, characterized in that: The target register group is a memory-mapped input and output register; the target register group includes a mode enable register, a trigger information register and a debugger instruction address register; The mode enable register is used to define the debugging trigger mode and the number of the trigger information registers; the trigger mode includes an instruction address trigger mode or an instruction type trigger mode; The trigger information register is used to store instruction information for triggering debugging; the instruction information includes an instruction address or an instruction type; The debugger instruction address register is used to store the instruction address of the debugger.

3. The multi-thread warp debugging method according to claim 1, characterized in that: The step of determining the expected warp to trigger debugging based on the comparison result between the instruction information of the original program executed by each warp and the instruction information stored in the target register group, and the warp identifier of each warp, includes: Determine that each thread warp triggers debugging based on a comparison result between instruction information of the original program executed by each thread warp and instruction information stored in the target register group; Based on the comparison result between the warp identifiers of each warp and the warp identifier of the expected warp, it is determined that the expected warp triggers debugging.

4. The multi-thread warp debugging method according to claim 1, characterized in that: The debugging triggering information includes a warp identifier of a warp that triggers debugging; and the processor is configured to determine that the warp is the expected warp based on the warp identifier of the warp.

5. The multi-thread warp debugging method according to claim 1, characterized in that: After controlling the expected thread warp to execute the debug program based on the instruction address of the debug program stored in the target register group based on the debug enable information, the method further includes: Recording the executed instruction addresses of the original program; The processor is configured to control each thread warp to continue executing the original program based on the executed instruction address after debugging ends.

6. The multi-thread warp debugging method according to claim 1, characterized in that: The processor is configured to configure the target register group based on a trigger mode, an instruction address, an instruction type of the original program and an instruction address of the debugger.

7. A multi-threaded bundle debugging device, characterized in that: include: A comparison module, configured to determine an expected warp to trigger debugging based on a comparison result between instruction information of each warp executing the original program and instruction information stored in the target register group, and warp identifiers of each warp; A first sending module, configured to send debugging trigger information to a processor, so that the processor sends debugging enable information to each thread warp, and controls an unexpected thread warp to wait for the expected thread warp to be debugged; an execution module, configured to control the expected thread warp to execute the debug program based on an instruction address of the debug program stored in the target register group based on the debug enable information; The second sending module is used to send debugging end information to the processor, so that the processor sends debugging stop information to each thread warp to control each thread warp to continue executing the original program.

8. An artificial intelligence chip, characterized in that: include: The target register group is used to define the debugging trigger mode and store the instruction information for triggering debugging and the instruction address of the debugger; A scheduling control unit is connected to the target register group and is used to execute the multi-thread warp debugging method according to any one of claims 1 to 6, and control the expected warp in multiple warps for debugging.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the multi-thread warp debugging method according to any one of claims 1 to 6 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the multi-thread warp debugging method according to any one of claims 1 to 6 is implemented.

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