EFUSE control device, method and system

Abstract

The invention provides an EFUSE control device, method and system, and the control device comprises a register configuration module, an input processing module, a read-write control module, a comparison module and a time sequence output module. The register configuration module is used for receiving a CPU bus signal, generating a parallel instruction according to the bus signal and outputting the parallel instruction to the input processing module; the input processing module is used for selecting a parallel instruction sent by a CPU (Central Processing Unit) or a serial instruction generated by the outside to be output to the read-write control module according to the high-low state of the signal level of the mode selection port; the read-write control module is used for generating a corresponding read operation enable signal or a write operation enable signal according to the instruction output by the input processing module; the time sequence output module is used for outputting a corresponding EFUSE programming time sequence signal according to the read or write operation enable signal to execute read operation or write operation on the EFUSE; the comparison module is used for comparing the value written into the current EFUSE bit and judging whether the current EFUSE bit is written successfully or not. The control device is wide in application range.

Description

Technical Field

[0001] The invention belongs to the field of EFUSE control, and in particular relates to an EFUSE control device, method and system. Background Art

[0002] EFUSE is a one-time programmable memory. Each bit in its storage space can only be programmed once, and the value of the bit cannot be modified after programming. It is usually used to store chip information, such as version number, production date and key. In the existing EFUSE controller solution, most EFUSE controller modules use serial data input to ensure reliable data storage. Chips with EFUSE modules often have different application requirements. For example, during the test process, a test machine is required to perform read and write programming tests on the EFUSE module. The programming instructions output by the test machine are a series of serial pulse signals. During the operation of the chip, the CPU module may access the EFUSE module multiple times, and the CPU module accesses the EFUSE module through a set of parallel buses.

[0003] How to design an EFUSE controller with wide application requirements and high data storage reliability is a problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, the present invention provides an EFUSE control device, method and system for solving the deficiencies of the prior art.

[0005] In order to achieve the above object, the present invention adopts the following technical scheme:

[0006] The embodiment of the present invention provides an EFUSE control device, comprising: a register configuration module, an input processing module, a read-write control module, a comparison module and a timing output module;

[0007] The register configuration module is electrically connected to the input processing module; the timing output module is electrically connected to the input processing module through the read-write control module; the timing output module is electrically connected to the EFUSE memory; the input end of the register configuration module is electrically connected to the CPU bus, and the comparison module is electrically connected to the read-write control module;

[0008] The register configuration module is used to receive CPU bus signals, and generate parallel instructions according to the bus signals and output them to the input processing module; the input processing module is used to select the parallel instructions sent by the CPU or the serial instructions generated by the outside according to the high and low states of the mode selection port signal level and output them to the read-write control module; the read-write control module is used to generate the corresponding read operation enable signal or write operation enable signal according to the instructions output by the input processing module; the timing output module is used to output the corresponding EFUSE programming timing signal according to the read or write operation enable signal to perform a read operation or a write operation on the EFUSE; the comparison module is used to compare the value written to the current EFUSE bit. If the comparison result is wrong, a comparison error interrupt signal is generated and returned to the CPU and the position of the bit with the error in the EFUSE memory module is output. If the comparison result is correct, it means that the current EFUSE bit is written successfully. The comparison of the value written to the current EFUSE bit is to compare the value to be written with the value read after writing the efuse.

[0009] Furthermore, the input processing module includes: an instruction cache unit, a parallel-to-serial unit and a data selection unit; the instruction cache unit is used to cache parallel programming instructions sent by the CPU; the parallel-to-serial unit receives parallel instructions output by the configuration register and converts the parallel instructions into serial instructions; the data selection unit decides whether to output instructions input by the serial input port or instructions input by the parallel output port and processed by the parallel-to-serial unit according to a mode selection signal.

[0010] Furthermore, the instruction cache unit converts a set of parallel programming instructions sent by the CPU and writes them into the instruction buffer as instruction data, wherein the instruction data is a 39-bit data obtained by splicing the write enable signal wren, the valid data signal vdata[31:0] and the write address signal waddr[5:0]. Among them, the valid data signal vdata[31:0] is the result of the AND of the write data signal wdata[31:0] and the write mask word signal wdmask[31:0].

[0011] Further, the read-write control module includes an instruction parsing unit and a control unit;

[0012] The instruction parsing unit uses a shift register to receive the instruction output by the input processing module, and parses the received programming instruction to generate a read-write enable signal and input it into the control unit. The read-write enable signal includes a read enable signal and a write enable signal.

[0013] The control unit generates a corresponding read control signal or a write control signal according to the enable signal output by the instruction parsing unit and outputs it to the timing output module.

[0014] Furthermore, the state machine of the control unit in the read-write control module includes five states: waiting state, write operation state, write-complete read state, read operation state and completion state;

[0015] When the control unit receives a read enable signal, the control module state machine jumps from the waiting state to the read operation state. When the timing output module outputs the read operation timing completion, the control module state machine jumps from the read operation state to the completion state, and outputs the EFUSE read operation completion signal before jumping back to the waiting state from the completion state. When the control unit receives a write enable signal, the control module state machine jumps from the waiting state to the write operation state. When the timing output module outputs the write operation timing completion, the control module state machine jumps from the write operation state to the write-completed read state. When the read EFUSE data is judged to be written successfully by the comparison module, the state machine jumps to the completion state, and outputs the EFUSE write operation completion signal before jumping back to the waiting state from the completion state.

[0016] Furthermore, the parallel programming instruction output by the register configuration module includes a write mask word signal; the write operation is performed only on the valid bits of the write mask word and the bits whose corresponding write data bits are 1, and the remaining bits are not written.

[0017] Furthermore, after receiving the parallel instructions output by the register configuration module, the output processing module serializes the parallel instructions by means of a parallel-to-serial unit; the parallel-to-serial unit uses a register to record the positions of valid bits in the data to be written, and generates corresponding serial programming instructions according to the recorded bit positions and the write address signal; and generates an equal number of serial instructions according to the number of valid bits in the write data to perform read and write operations on the corresponding bits in the EFUSE.

[0018] Further, the timing output module includes: a timing adjustment register input port, a control input port, an EFUSE timing output port and a status output port; the timing adjustment register input port receives the timing adjustment counter CNT_NUM parameter output by the register configuration module, the control input port receives the read control signal or the write control signal output by the read-write control module, the timing output port outputs the corresponding EFUSE read-write operation timing signal pair according to the read-write type of the control signal to perform a read operation or a write operation on the EFUSE, and the status output port outputs the EFUSE read or write operation completion flag signal; the timing adjustment register CNT_NUM is a multi-bit wide register, which is divided into multiple intervals according to the delay requirements, and each interval can be used to configure counters with different delays.

[0019] Furthermore, the EFUSE control device further comprises: an error correction module; the error correction module is used to mark an error correction if writing fails; the EFUSE storage space is divided into multiple storage spaces of the same length, and the length of each storage space is 1+M+N bits; each storage space has 1 bit for marking the error type of the stored data, M bits for marking the location information of the error data, and N bits for storing data; 2 M ≥N; the error types are unsuccessful writing of 0 into 1 and data 0 being mistakenly written into 1; the error correction module performs error correction processing on the stored data according to the stored data, the error type and the location information.

[0020] The embodiment of the present invention provides an EFUSE control method, comprising the following steps:

[0021] S1: Calculate the count value of each partition of the timing adjustment register CNT_NUM according to the clock frequency;

[0022] S2: receiving serial or parallel programming instructions according to the mode selection signal, performing serial processing and generating a read / write operation enable signal;

[0023] S3: Generate corresponding read / write control signals according to the read / write operation enable signal;

[0024] S4: Output EFUSE read / write operation timing signal according to the read / write control signal and the value of the timing adjustment register CNT_NUM, and perform corresponding read / write operations on EFUS;

[0025] S5: After the write operation is completed, determine whether the current bit of EFUSE is written successfully. If not, output a write error status flag signal and perform the write operation again.

[0026] An embodiment of the present invention provides an EFUSE control system, comprising: an EFUSE and any one of the above EFUSE control devices.

[0027] An EFUSE control device proposed in the present invention adopts an input parsing module to receive programming instructions sent by an external device. The programming instructions can be a series of serial pulse signals or parallel instruction data. The input parsing module includes two groups of programming instruction input ports, one is a serial programming instruction input port, and the other is a parallel programming instruction input port; a mode selection signal line is used to indicate whether the currently input programming instruction is a serial programming instruction or a parallel programming instruction; so that the application range of the EFUSE controller is more extensive.

[0028] The EFUSE control device uses a multi-bit wide timing adjustment register CNT_NUM to store the count value of the delay counter. The value in the CNT_NUM register can be configured according to the working clock frequency, thereby automatically adjusting the count value of the EFUSE read / write control signal delay counter, thereby ensuring that the EFUSE control device outputs the correct EFUSE module read / write control timing signal within a wide frequency working clock range.

[0029] A comparison module is used in the EFUSE control device. Since EFUSE can only write one bit at a time, the comparison module is used to read and compare the data of the currently written bit after each single-bit write operation is completed to determine whether the value of the bit is written successfully, so as to avoid the accuracy of the data in the EFUSE memory affected by programming errors, resulting in chip operation errors. Data writing is safe and reliable, and it is not easy to make mistakes. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 A schematic diagram of the module structure of an EFUSE control device provided by the present invention;

[0032] Figure 2 A schematic diagram of the unit structure of an EFUSE control device provided by the present invention;

[0033] Figure 3 It is the state transition diagram of the internal state machine of the control unit in the read-write control module;

[0034] Figure 4 This is a schematic diagram of the interval division of the timing adjustment register CNT_NUM;

[0035] Figure 5 A waveform diagram showing that the EFUSE control device receives a parallel instruction to perform a write operation on the EFUSE;

[0036] Figure 6 A waveform diagram showing that the EFUSE control device receives a parallel instruction to perform a read operation on the EFUSE;

[0037] Figure 7 A timing diagram of the EFUSE control device receiving a serial instruction to perform a write operation on the EFUSE;

[0038] Figure 8A timing diagram of the EFUSE control device receiving a serial instruction to perform a read operation on the EFUSE;

[0039] Fig. 9 The present invention provides a flow chart of an EFUSE control method. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] In order to make the technical solution and advantages of the present invention clearer, the technical solution of the present invention is described clearly and completely in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] like Figure 1 As shown, the present invention provides an EFUSE control device, including: a register configuration module, an input processing module, a read-write control module, a timing output module and a comparison module.

[0043] The register configuration module is electrically connected to the input processing module; the timing output module is electrically connected to the input processing module through the read-write control module; the timing output module is electrically connected to the EFUSE memory; the input end of the register configuration module is electrically connected to the CPU bus, and the comparison module is electrically connected to the read-write control module.

[0044] The register configuration module is used to receive CPU bus signals, and generate parallel instructions according to the bus signals and output them to the input processing module; the input processing module is used to select the parallel instructions sent by the CPU or the serial instructions generated by the outside according to the high and low states of the signal levels of the mode selection port to output to the read-write control module; the read-write control module is used to generate the corresponding read operation enable signal or write operation enable signal according to the instructions output by the input processing module; the timing output module is used to output the corresponding EFUSE programming timing signal according to the read or write operation enable signal to perform a read operation or a write operation on the EFUSE; the comparison module is used to compare the value written to the current EFUSE bit. If the comparison result is incorrect, a comparison error interrupt signal is generated and returned to the CPU and the position of the bit with the programming error in the EFUSE memory module is output. If the comparison result is correct, it indicates that the current EFUSE bit is written successfully. When the EFUSE bit is written successfully, the next write operation is executed. When the EFUSE bit fails to be written, the write operation can be re-executed. After the EFUSE completes the write operation, the read-write control module outputs a write operation completion flag signal to trigger the comparison module to compare. The comparison of the value written to the current EFUSE bit is to compare the value to be written with the value read after writing EFUSE. The EFUSE control device uses an interrupt method to return the error status information and the position of the corresponding error bit, which can effectively reduce the time occupied by the EFUSE control device on the CPU processor and improve the execution efficiency of the CPU processor.

[0045] In another embodiment, the EFUSE control device may further include: an error correction module; the error correction module is used to mark an error correction if writing fails; the EFUSE storage space is divided into multiple storage spaces of the same length, and the length of each storage space is 1+M+N bits; each storage space has 1 bit for marking the error type of the stored data, M bits for marking the location information of the error data, and N bits for storing data; M ≥N; the error types are unsuccessful writing of 0 into 1 and data 0 being mistakenly written into 1; the error correction module performs error correction processing on the stored data according to the stored data, the error type and the location information.

[0046] In the efuse write operation, the probability of a piece of data being wrong is limited, and the number of bits of data errors in a certain length can be set to only 1. Since the parallel programming instructions output by the register configuration module contain write mask word signals; the write operation only performs write operations on the bits where the write mask word is valid and the bits whose corresponding write data bits are 1, and the remaining bits are not written. In the error probability, the error probability of a bit being written from 0 to 1 unsuccessfully is much greater than the error probability of a bit being written from 0 to 1 by mistake. We can use one bit to indicate the type of error in a piece of data. The default value 0 indicates that a bit is not successfully written from 0 to 1, and the data bit is still 0; 1 indicates that a bit should be data 0, but is mistakenly written to 1. How many bits are used to indicate the position number of the data error. The rest is used to store data.

[0047] When the data writing is still unsuccessful after the preset number of re-write operations, the error correction module records and saves the position of the bit, so that when reading the data, the information recorded by the error correction module is used to perform error correction processing on each bit of the read data, and the bit that should be written as 1 but cannot be written as 1 is found, and the corresponding bit data in the read data is replaced with 1 according to this information, and output to the reading call module for use. Writing in this application refers to setting each bit from the default value 0 to 1, and the comparison module mainly compares whether the bit that needs to be set to 0 as 1 has successfully performed the corresponding write operation. When some bits are physically damaged, even if they are re-written many times, they still cannot be written successfully, and a certain storage space needs to be opened to store which specific bit data cannot be successfully written from 0 to 1. Through this mark, when reading the corresponding data, the corresponding data is corrected to ensure the accuracy of the read data. The storage space of efuse can be divided into multiple small storage units of the same length, each small storage unit has a part to store data, and the other part cannot perform a write operation from 0 to 1 because of the storage mark. For example, the efuse storage space can be divided into multiple small storage units with a length of 32 bits. Each small storage unit uses 26 bits to store data, and 1 bit of the other 6 bits is used to mark the situation where 0 is mistakenly written to 1 or 0 is written to 1 unsuccessfully; which bit of the 26-bit data cannot perform the write operation from 0 to 1. The other 5 bits are used to mark which bit of the 26-bit data cannot perform the write operation from 0 to 1. If the 24th bit of data fails to be written from 0 to 1 multiple times, the 5-bit bit position used for marking is set to 11000 to indicate that the 24th bit of data is written abnormally. When reading data, the 24th bit of data is 0, and combined with the 5-bit bit of 11000, it can be seen that the 24th bit of data is written abnormally, and the 24th bit of data needs to be corrected to 1 and output to the data reading unit. If it is divided into multiple small storage units with a length of 64 bits, 57 bits are used to store data, 1 bit is used to mark the error type; 6 bits are used to mark which bit of the 57-bit data is wrong and needs to be corrected.

[0048] See also Figure 1 and Figure 2 As shown, the EFUSE control device is described in detail below.

[0049] First, the main input and output ports of each module are described in detail.

[0050] The register configuration module includes: a data bus input port and a parallel instruction output port. The data bus input port receives the register configuration data sent by the CPU; the register configuration module parses the configuration data according to the bus clock signal and outputs the parallel instruction from the parallel instruction output port.

[0051] The input processing module includes: an instruction cache unit, a serial input port, a parallel input port, a mode selection port and an instruction output port. The instruction cache unit is used to cache the parallel programming instructions sent by the CPU. The serial input port receives serial instructions sent by an external device or apparatus; the parallel input port receives parallel instructions output from the register configuration module; the high and low level signal states of the mode selection port determine whether the instruction output port outputs the EFUSE programming instructions input by the serial input port or the EFUSE programming instructions input by the parallel input port after being processed by the parallel-to-serial unit.

[0052] The read-write control module includes: an instruction input port, a status input port, a control output port and a status output port. The instruction input port receives the serial EFUSE programming instruction output by the input processing module, the status input port receives the status flag signal output by the timing output module, and the control output port outputs the EFUSE read-write control signal to the timing output module. The status output port outputs the operation completion flag signal to the comparison module according to the input status signal of the status input port.

[0053] The comparison module includes: a status input port and a status output port. The status input port receives the EFUSE module operation completion flag signal, and the comparison module performs a comparison operation on the bit value in the current EFUSE module according to the write operation completion flag signal, and outputs the comparison result status flag signal to the read-write control module through the status output port.

[0054] The timing output module includes: a timing adjustment register input port, a control input port, an EFUSE timing output port and a status output port. The timing adjustment register input port receives the timing adjustment counter CNT_NUM parameter output by the register configuration module, the control input port receives the read control signal or write control signal output by the read-write control module, the timing output port outputs the corresponding EFUSE read-write operation timing signal pair according to the read-write type of the control signal to perform a read operation or a write operation on the EFUSE, and the status output port outputs the EFUSE read or write operation completion flag signal.

[0055] See also Figure 2 , the sub-unit structure of each module is described in detail below.

[0056] The input processing module includes: an instruction cache unit, a parallel-to-serial unit and a data selection unit, wherein the instruction cache unit is used to cache the parallel programming instructions sent by the CPU; the parallel-to-serial unit receives the parallel instructions output by the configuration register and converts the parallel instructions into serial instructions; the data selection unit determines whether to output the instructions input by the serial input port or the instructions input by the parallel output port after being processed by the parallel-to-serial unit according to the mode selection signal. The source of the instructions can be a serial instruction issued by an external device or apparatus, or a parallel instruction generated by a CPU processor; in this way, the application requirements of the EFUSE controller are more extensive.

[0057] The instruction cache unit converts a set of parallel programming instructions sent by the CPU and writes them into the instruction buffer as instruction data. The instruction data is a data with a bit width of 39 bits obtained by splicing the write enable signal wren, the valid data signal vdata[31:0] and the write address signal waddr[5:0]. Among them, the valid data signal vdata[31:0] is the result of the write data signal wdata[31:0] and the write mask word signal wdmask[31:0]. In one embodiment, the capacity of the EFUSE memory is 64x32bit, and the size of the instruction cache area is set to 64. It is worth noting that the size of the instruction cache area needs to be set according to the size of the EFUSE memory and the actual usage. The beneficial effect of this method is that by adding an instruction cache unit, the programming instructions sent by the CPU processor are pre-processed and cached before being executed in sequence, and the error status information and the corresponding error bit position information are returned in an interrupt mode, which can effectively reduce the EFUSE control device The time occupied by the CPU processor and improve the execution efficiency of the CPU processor.

[0058] The existing EFUSE programming and burning time is relatively long and can only be burned bit by bit. The CPU processor can only send the next programming instruction to program the next address of the EFUSE module after judging the burning completion status signal. This method makes the EFUSE control device occupy too much time of the CPU processor and reduce the execution efficiency of the CPU processor. The present application adds an instruction cache unit to pre-process and cache the programming instructions sent by the CPU processor before executing them in sequence. The execution efficiency of the CPU processor is greatly improved.

[0059] In a specific embodiment, the default value of the mode selection signal is 0, indicating that the programming instruction generated by the CPU processor is selected as the read and write operation instruction of the EFUSE module. When the mode selection signal value is 1, it indicates that the programming instruction issued by the external device or apparatus is selected as the read and write operation instruction of the EFUSE module. The input processing module can only output one instruction at the same time, which includes the EFUSE read operation instruction and the EFUSE write operation instruction, and the next instruction can be output only when the current instruction is executed.

[0060] The read-write control module includes: an instruction parsing unit and a control unit, wherein the instruction parsing unit can use a shift register to receive the instruction output by the input processing module, and parse the received programming instruction to generate a read enable signal or a write enable signal; the control unit generates a corresponding read control signal or a write control signal according to the enable signal output by the instruction parsing unit, so as to control the timing output module to output an EFUSE read operation timing signal or an EFUSE write operation timing signal.

[0061] If the read / write control module outputs a read control signal, the timing output module outputs a read operation timing signal according to the EFUSE module read timing protocol; if the read / write control module outputs a write control signal, the timing output module outputs a write operation timing signal according to the EFUSE module write programming timing protocol.

[0062] In one exemplary embodiment, see Figure 3 As shown, the control unit state machine in the read-write control module includes a waiting state, a write operation state, a read-after-write state, a read operation state and a completion state. The control unit state machine jumps to the corresponding branch execution according to the control signal output by the instruction parsing unit. When the control unit receives a read enable signal, the control module state machine jumps from the waiting state to the read operation state. When the timing output module outputs the read operation timing and completes, the control module state machine jumps from the read operation state to the completion state, and jumps back to the waiting state from the completion state after outputting the EFUSE read operation completion signal; when the control unit receives a write enable signal, the control module state machine jumps from the waiting state to the write operation state. When the timing output module outputs the write operation timing and completes, the control module state machine jumps from the write operation state to the read-after-write state. When the read EFUSE data is judged to be written successfully by the comparison module, the state machine jumps to the completion state, and jumps back to the waiting state from the completion state after outputting the EFUSE write operation completion signal.

[0063] The parallel programming instructions output by the register configuration module include the read-write start signal cpu_op_start, the write enable signal cpu_wr_en, the write address signal cpu_waddr, the write data signal cpu_wdata and the write mask signal cpu_wdmask. The write address, write data and write mask bit width can all be set to 32 bits. The write mask bit is 1 and the bit corresponding to the write data is the valid write bit, that is, only the valid bit of the write mask and the bit corresponding to the write data bit is 1 are written, and the remaining bits are not written. That is, if the lower eight bits of the write mask are 0, the lower eight bits of the write data are ignored by default, and the lower eight bits are treated as 0 in the actual writing process. Setting the mask signal makes the write data setting more flexible and changeable.

[0064] Since EFUSE can only write one bit at a time, after receiving the parallel programming instruction output by the register configuration module, the parallel-to-serial unit serializes the parallel programming instruction. Specifically, the parallel-to-serial unit uses a register to record the location of the valid bit in the data to be written, and generates a corresponding serial instruction according to the recorded bit location and the write address signal; according to the number of valid bits in the write data, it generates the same number of serial instructions to read and write the corresponding bits in the EFUSE module, so as to realize the sequential reading and writing operations of multiple bits of EFUSE through one parallel instruction, which greatly facilitates the reading and writing operations of EFUSE.

[0065] Preferably, in one embodiment, the timing adjustment register CNT_NUM is divided into five intervals, each interval is used to store the count value of delay of different time lengths according to the current working clock frequency, and the maximum working clock frequency range that the EFUSE module can reach depends on the bit width allocated for storing the delay count value. Specifically, the division method in this example is as follows: Figure 4 As shown, CNT_NUM[31:21] is used to store the count value of delay one, CNT_NUM[20:13] is used to store the count value of delay two, CNT_NUM[12:7] is used to store the count value of delay three, CNT_NUM[6:3] is used to store the count value of delay four, and CNT_NUM[2:0] is used to store the count value of delay five. The count value calculation formula is: count value = [(Td*fhclk) / 2]*10 -3 , the result is rounded up; Td is the delay time, in ns; fhclk is the clock frequency, in MHz.

[0066] The beneficial effect of dividing the timing control register CNT_NUM is that by dividing a 32-bit wide register and storing the count values ​​required for different delays, the number of configuration registers is saved and the port signal is simplified while meeting the requirements of the wide frequency range of the EFUSE module. It should be noted that the delay time length of each interval is set according to the timing of the read and write operation signal of the EFUSE module. In practical applications, the bit width of the register can be 8 / 16 / 32 / 64 bits. Those skilled in the art should divide the timing adjustment register CNT_NUM into intervals and set the count value according to actual needs.

[0067] like Figure 5 As shown, when writing data to the EFUSE memory module through the CPU processor bus, first, the EFUSE write operation instruction configuration data is sent to the register configuration module to generate parallel EFUSE programming instructions. In one embodiment, the EFUSE memory capacity is 64x32bit, and the valid write bits in the write data in the parallel EFUSE programming instructions are the bits that need to write data to the corresponding positions of the EFUSE module in sequence. After being processed by the input processing module, the parallel EFUSE programming instructions output serial programming instructions with the same number of valid write bits, and the read-write control module generates a read-write enable signal to trigger the timing output module to output the corresponding EFUSE module timing signal. In one embodiment, the EFUSE module timing signal includes addr[10:0], pd, ps, csb, pgenb, strobe, load and mr, wherein addr[10:0] is the data written into the EFUSE module, which is the serial write instruction data sequentially outputted after the parallel EFUSE programming instruction is processed by the parallel-to-serial unit in the input processing module. The read-write control module controls the timing output module to output the EFUSE write timing signal to write to the EFUSE module according to the serial write instruction data. A serial programming instruction can only write to one bit in the EFUSE module and cannot be changed after the write operation is completed.

[0068] like Figure 6 As shown, when reading data from the EFUSE memory module through the CPU processor bus, the parallel-to-serial unit in the input processing module converts the parallel EFUSE read operation instruction into serial read instruction data, and the read-write control module controls the timing output module to output the EFUSE read timing signal according to the serial read instruction data to perform a read operation on the EFUSE module. The read-write control module reads 32-bit wide data at one time through the q[31:0] port and stores it in the register, and returns the acquired data to the CPU processor bus.

[0069] like Figure 7 and 8As shown, when the EFUSE memory module is read and written by serial programming instructions, the read-write control module controls the timing output module based on the serial programming instructions to output the EFUSE read timing signal or the write timing signal to perform read and write operations on the EFUSE module. During a write operation, a serial programming instruction can only perform a write operation on one bit in the EFUSE memory. During a read operation, the read-write control module will read 32-bit wide data at a time through the q[31:0] port.

[0070] An EFUSE control method, such as Fig. 9 As shown, the method comprises the following steps:

[0071] S1: Calculate the count value of each partition of the timing adjustment register CNT_NUM according to the clock frequency.

[0072] S2: Receive serial or parallel programming instructions according to the mode selection signal, and perform serial processing to generate a read / write operation enable signal.

[0073] S3: The read / write control module generates corresponding read / write control signals according to the read / write operation enable signal.

[0074] S4: Output the EFUSE read / write operation timing signal according to the read / write control signal and the value of the timing adjustment register CNT_NUM, and perform corresponding read / write operations on the EFUS module.

[0075] S5: After the write operation is completed, it is determined whether the current EFUSE bit is written successfully according to the comparison result status flag signal output by the comparison module.

[0076] If unsuccessful, a write error status flag signal is output and the process returns to step S2 to perform the write operation again.

[0077] Based on the same inventive concept, another embodiment of the present invention further provides an EFUSE control system, the system comprising the EFUSE control device and EFUSE described in any of the above embodiments, the EFUSE control device is connected to the CPU processor bus and other external devices or apparatuses, and performs read and write operations on the EFUSE by receiving serial or parallel programming instructions.

[0078] In the several embodiments provided by the present invention, it should be understood that the disclosed methods and devices can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0079] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An EFUSE control device, characterized in that: include: Register configuration module, input processing module, read / write control module, comparison module and timing output module; The register configuration module is electrically connected to the input processing module; the timing output module is electrically connected to the input processing module through the read-write control module; the timing output module is electrically connected to the EFUSE memory; the input end of the register configuration module is electrically connected to the CPU bus, and the comparison module is electrically connected to the read-write control module; The register configuration module is used to receive CPU bus signals and generate parallel instructions according to the bus signals and output them to the input processing module; The input processing module is used to select the parallel instruction sent by the CPU or the serial instruction generated by the outside to be output to the read-write control module according to the high and low states of the signal level of the mode selection port; the read-write control module is used to generate the corresponding read operation enable signal or write operation enable signal according to the instruction output by the input processing module; the timing output module is used to output the corresponding EFUSE programming timing signal according to the read or write operation enable signal to perform a read operation or a write operation on the EFUSE; the comparison module is used to compare the value written to the current EFUSE bit. If the comparison result is incorrect, a comparison error interrupt signal is generated and returned to the CPU and the position of the bit with the programming error in the EFUSE memory module is output. If the comparison result is correct, it indicates that the current EFUSE bit is written successfully.

2. The device according to claim 1, characterized in that The input processing module includes: an instruction cache unit, a parallel-to-serial unit and a data selection unit; the instruction cache unit is used to cache parallel programming instructions sent by the CPU; the parallel-to-serial unit receives parallel instructions output by the configuration register and converts the parallel instructions into serial instructions; the data selection unit determines whether to output instructions input by the serial input port or instructions input by the parallel output port and processed by the parallel-to-serial unit according to a mode selection signal.

3. The device according to claim 1, characterized in that The read-write control module includes an instruction parsing unit and a control unit; The instruction parsing unit uses a shift register to receive the instruction output by the input processing module, and parses the received programming instruction to generate a read-write enable signal and input it into the control unit. The read-write enable signal includes a read enable signal and a write enable signal. The control unit generates a corresponding read control signal or a write control signal according to the enable signal output by the instruction parsing unit and outputs it to the timing output module.

4. The device according to claim 3, characterized in that The state machine of the control unit in the read-write control module includes five states: waiting state, write operation state, write-complete read state, read operation state and completion state; When the control unit receives a read enable signal, the control module state machine jumps from the waiting state to the read operation state. When the timing output module outputs the read operation timing completion, the control module state machine jumps from the read operation state to the completion state, and outputs the EFUSE read operation completion signal before jumping back to the waiting state from the completion state. When the control unit receives a write enable signal, the control module state machine jumps from the waiting state to the write operation state. When the timing output module outputs the write operation timing completion, the control module state machine jumps from the write operation state to the write-completed read state. When the read EFUSE data is judged to be written successfully by the comparison module, the state machine jumps to the completion state, and outputs the EFUSE write operation completion signal before jumping back to the waiting state from the completion state.

5. The device according to claim 1, characterized in that The parallel programming instruction output by the register configuration module includes a write mask word signal; the write operation is performed only on the valid bits of the write mask word and the bits whose corresponding write data bits are 1, and the remaining bits are not written.

6. The device according to claim 5, characterized in that After receiving the parallel instructions output by the register configuration module, the output processing module serializes the parallel instructions by the parallel-to-serial unit; the parallel-to-serial unit uses a register to record the position of the valid bits in the data to be written, and generates corresponding serial programming instructions according to the recorded bit positions and write address signals; and generates the same number of serial instructions according to the number of valid bits in the write data to perform read and write operations on the corresponding bits in EFUSE.

7. The device according to claim 5, characterized in that The timing output module includes: a timing adjustment register input port, a control input port, an EFUSE timing output port and a status output port; the timing adjustment register input port receives the timing adjustment counter CNT_NUM parameter output by the register configuration module, the control input port receives the read control signal or the write control signal output by the read-write control module, the timing output port outputs the corresponding EFUSE read-write operation timing signal pair according to the read-write type of the control signal to perform a read operation or a write operation on the EFUSE, and the status output port outputs the EFUSE read or write operation completion flag signal; the timing adjustment register CNT_NUM is a multi-bit wide register, which is divided into multiple intervals according to the delay requirement, and each interval can be used to configure counters with different delays.

8. The device according to claim 1, characterized in that Also includes: Error correction module; The error correction module is used to write an error correction mark if it fails; the EFUSE storage space is divided into multiple storage spaces of the same length, and the length of each storage space is 1+M+N bits; Each storage space has 1 bit for marking the error type of the stored data, M bits for marking the location information of the error data, and N bits for storing data; M ≥N; the error types are unsuccessful writing of 0 into 1 and data 0 being mistakenly written into 1; the error correction module performs error correction processing on the stored data according to the stored data, the error type and the location information.

9. An EFUSE control method, characterized in that: The steps include: S1: Calculate the count value of each partition of the timing adjustment register CNT_NUM according to the clock frequency; S2: receiving serial or parallel programming instructions according to the mode selection signal, performing serial processing and generating a read / write operation enable signal; S3: Generate corresponding read / write control signals according to the read / write operation enable signal; S4: Output EFUSE read / write operation timing signal according to the read / write control signal and the value of the timing adjustment register CNT_NUM, and perform corresponding read / write operations on EFUS; S5: After the write operation is completed, determine whether the current bit of EFUSE is written successfully. If not, output a write error status flag signal and perform the write operation again.

10. An EFUSE control system, characterized in that: include: EFUSE and the EFUSE control device according to any one of claims 1 to 8.

Images