Signal analysis method and device, electronic equipment and storage medium
By constructing the interconnected signal timing chart of multi-FPGA systems and performing static timing analysis, the criticality coefficient of interconnected signals is calculated, and the problem of poor distinction between interconnected signals in multi-FPGA systems is solved, and system timing optimization and performance improvement are achieved.
Patent Information
- Application Number
- CN202411981213.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-04-29
AI Technical Summary
In the compilation process of multi-FPGA systems, the interconnected signal is not distinctive, resulting in the increase in the delays of key signals and non-critical signals year-on-year, thereby losing system performance.
By determining the interconnected signal timing chart of the prototype verification system, a static timing analysis algorithm is used to determine the target timing margin of each interconnected signal, and the target timing margin is processed based on the clock correlation coefficient, and the criticality coefficient of the interconnected signal is calculated.
The timing criticality analysis and extraction of interconnected signals between FPGAs in multiple FPGA systems is realized, and the timing-driven design division of the system, system routing and time-division multiplexing ratio allocation is carried out based on the extracted key, effectively optimizing the system timing and improving system performance.
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Figure CN119903795A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer application technology, and in particular to a signal analysis method, device, electronic equipment and storage medium. Background Art
[0002] In the front-end design of digital chips, field-programmable gate arrays (FPGAs) are often used for design verification, namely FPGA prototyping technology. For the current design projects of very large-scale integrated circuits that often contain hundreds of millions of gates, the resources of a single FPGA are limited, and multiple FPGAs are often required to work together to verify the entire design logic.
[0003] The multi-FPGA system prototype verification compilation process is divided into important links such as circuit design, logic synthesis, circuit partitioning, system wiring, time division multiplexing ratio allocation, pin allocation, internal layout and wiring, and configuration file generation. In the prior art, when compiling the above links, interconnection signals are usually treated equally, and the interconnection signal distinction is not strong. When performing corresponding processing, it usually produces results such as the delay of key signals and non-key signals increases year-on-year, which leads to system performance loss. Summary of the invention
[0004] The present invention provides a signal analysis method, device, electronic device and storage medium to solve the technical problem that the interconnected signal distinction is not strong during the compilation stage, and when performing corresponding processing, the delay between key signals and non-key signals increases year-on-year, thereby causing system performance loss.
[0005] According to one aspect of the present invention, there is provided a signal analysis method, the method comprising:
[0006] Determine a prototype verification system, and construct an interconnection signal timing diagram corresponding to the prototype verification system, wherein the interconnection signal timing diagram includes chip models of multiple field programmable gate arrays, interconnection signals across the chip models, timing paths corresponding to the interconnection signals, and path delay values corresponding to the timing paths;
[0007] Performing timing analysis on the interconnect signal timing diagram by a static timing analysis algorithm to determine a target timing margin corresponding to each of the interconnect signals, wherein the target timing margin is determined based on the path delay value corresponding to the timing path of the interconnect signal;
[0008] For each of the interconnected signals, determine the clock domain in which the timing path corresponding to the interconnected signal is located, determine the clock correlation coefficient corresponding to the clock domain, and process the input target timing margin and clock correlation coefficient through a preset signal analysis algorithm to obtain the criticality coefficient corresponding to the interconnected signal.
[0009] According to another aspect of the present invention, there is provided a signal analysis device, the device comprising:
[0010] A timing diagram construction module is used to determine a prototype verification system and construct an interconnection signal timing diagram corresponding to the prototype verification system, wherein the interconnection signal timing diagram includes chip models of multiple field programmable gate arrays, interconnection signals across the chip models, timing paths corresponding to the interconnection signals, and path delay values corresponding to the timing paths;
[0011] A static timing analysis module, configured to perform timing analysis on the interconnect signal timing diagram by using a static timing analysis algorithm to determine a target timing margin corresponding to each of the interconnect signals, wherein the target timing margin is determined based on the path delay value corresponding to the timing path of the interconnect signal;
[0012] The criticality extraction module is used to determine, for each of the interconnected signals, the clock domain in which the timing path corresponding to the interconnected signal is located, determine the clock correlation coefficient corresponding to the clock domain, and process the input target timing margin and clock correlation coefficient through a preset signal analysis algorithm to obtain the criticality coefficient corresponding to the interconnected signal.
[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:
[0014] at least one processor; and
[0015] a memory communicatively connected to the at least one processor; wherein,
[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the signal analysis method described in any embodiment of the present invention.
[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the signal analysis method described in any embodiment of the present invention when executed.
[0018] The technical solution of the embodiment of the present invention is to determine a prototype verification system, construct an interconnection signal timing diagram corresponding to the prototype verification system, wherein the interconnection signal timing diagram includes chip models of multiple field programmable gate arrays, interconnection signals across the chip models, timing paths corresponding to the interconnection signals, and path delay values corresponding to the timing paths; perform timing analysis on the interconnection signal timing diagram through a static timing analysis algorithm, and determine the target timing margin corresponding to each interconnection signal, wherein the target timing margin is determined based on the path delay value corresponding to the timing path of the interconnection signal; for each interconnection signal, determine the clock domain where the timing path corresponding to the interconnection signal is located, determine the clock correlation coefficient corresponding to the clock domain, and process the input target timing margin and clock correlation coefficient through a pre-set signal analysis algorithm to obtain the criticality coefficient corresponding to the interconnection signal. The present invention realizes the analysis and extraction of the timing criticality of interconnection signals between FPGAs in a multi-FPGA system, and performs timing-driven design partitioning, system routing, and time division multiplexing ratio allocation in the compilation process of the prototype verification system based on the extracted criticality, which can effectively optimize the system timing and improve system performance.
[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0021] Figure 1 is a flow chart of a signal analysis method provided according to Embodiment 1 of the present invention;
[0022] Figure 2 is an example diagram of an interconnect signal timing diagram provided according to an embodiment of the present invention;
[0023] Figure 3 is a flow chart of a signal analysis method provided according to Embodiment 2 of the present invention;
[0024] Figure 4 is an overall flow chart of a signal analysis method provided according to an embodiment of the present invention;
[0025] Figure 5is a structural schematic diagram of a signal analysis device provided according to Embodiment 3 of the present invention;
[0026] Figure 6 It is a schematic diagram of the structure of an electronic device for implementing the signal analysis method according to an embodiment of the present invention. DETAILED DESCRIPTION
[0027] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0029] Embodiment 1
[0030] Figure 1 A flow chart of a signal analysis method is provided for the first embodiment of the present invention. This embodiment is applicable to the case where a driver is compiled based on a signal timing diagram. The method can be executed by a signal analysis device, which can be implemented in the form of hardware and / or software, and can be configured in a computer. Figure 1 As shown, the method includes:
[0031] S110, determining a prototype verification system, and constructing an interconnection signal timing diagram corresponding to the prototype verification system.
[0032] The prototype verification system can be understood as a chip verification platform based on FPGA. The prototype verification system can include multiple FPGAs.
[0033] The interconnect signal timing diagram can be understood as the timing diagram corresponding to the prototype verification system. Figure 2 As shown, Figure 2The present invention provides an example diagram of an interconnection signal timing diagram according to an embodiment of the present invention. The interconnection signal timing diagram includes chip models of multiple field programmable gate arrays, interconnection signals across the chip models, timing paths corresponding to the interconnection signals, and path delay values corresponding to the timing paths.
[0034] The field programmable gate array can be understood as a chip whose internal structure can be changed by programming.
[0035] The chip model can be understood as a construction model corresponding to the FPGA.
[0036] The interconnection signal can be understood as a cross-FPGA signal. The interconnection signal timing diagram constructed in the present invention only includes cross-FPGA interconnection signals, and does not include signals within a single FPGA.
[0037] The timing path may be understood as a logical path of the interconnection signal during transmission.
[0038] The path delay value can be understood as the logical delay value of the interconnect signal transmitted on the timing path. Optionally, the timing path may include multiple nodes, and the path delay value is related to the number of nodes in the timing path. Exemplarily, the path delay value may be 0.1 seconds, 0.2 seconds, or 0.5 seconds, etc.
[0039] S120, performing timing analysis on the interconnect signal timing diagram using a static timing analysis algorithm to determine a target timing margin corresponding to each of the interconnect signals.
[0040] The static timing analysis algorithm (STA) can be understood as a timing verification algorithm in integrated circuit design. Specifically, by inputting the interconnect signal timing diagram into STA, the target timing margin corresponding to each interconnect signal can be directly obtained.
[0041] The target timing margin is determined based on the path delay value corresponding to the timing path of the interconnected signal. The target timing margin is the difference between the actual arrival time and the required arrival time of the interconnected signal. The actual arrival time and the required arrival time are directly obtained by analyzing the nodes in the timing path through STA.
[0042] Optionally, performing timing analysis on the interconnect signal timing diagram by using a static timing analysis algorithm to determine a target timing margin corresponding to each interconnect signal includes:
[0043] Determine the signal arrival time corresponding to each interconnect signal in the interconnect signal timing diagram by a static timing analysis algorithm, wherein the signal arrival time is determined based on the path delay value, and the signal arrival time includes an actual arrival time and a required arrival time;
[0044] For the interconnect signal, the target timing margin is determined according to the actual arrival time and the required arrival time.
[0045] The signal arrival time may represent the absolute time when the signal actually calculates that it arrives at the end of a timing path in the logic circuit, that is, it is equal to the time when the signal arrives at the start of a path plus the sum of the time when the signal is transmitted between logic units on the path.
[0046] The required arrival time may represent the absolute time when a timing constraint for normal operation of a circuit requires a signal to arrive at an end point of a path in a logic circuit.
[0047] Specifically, based on STA, the slack value (i.e., the target timing margin) corresponding to each interconnected signal can be obtained, and the calculation formula is: slack = require-arrival, wherein slack represents the target timing margin, require represents the required arrival time, and arrival represents the actual arrival time; determine the clock domain in which the timing path corresponding to the slack value is located.
[0048] It should be noted that the target timing margin is inversely proportional to the timing risk of the interconnect signal, that is, the smaller the target timing margin, the greater the timing risk of the interconnect signal.
[0049] S130. For each interconnected signal, determine the clock domain in which the timing path corresponding to the interconnected signal is located, determine the clock correlation coefficient corresponding to the clock domain, and process the input target timing margin and clock correlation coefficient through a preset signal analysis algorithm to obtain a criticality coefficient corresponding to the interconnected signal.
[0050] Among them, in the embodiment of the present invention, the clock domain in which the timing path corresponding to each of the interconnection signals is located is related to the specifications of the FPGA corresponding to the interconnection signal, and is not specifically limited here.
[0051] The clock correlation coefficient can be understood as a coefficient related to the clock domain. Optionally, the clock correlation coefficient can be a clock cycle corresponding to the clock domain. Exemplarily, the clock cycle can be 5MHZ, 10MHZ or 20MHZ, etc.
[0052] The signal analysis algorithm can be understood as a custom algorithm. The signal analysis algorithm can calculate the criticality coefficient according to the input target timing margin and the clock correlation coefficient. The criticality coefficient represents the criticality of the interconnect signal.
[0053] Optionally, the clock correlation coefficient includes a clock period corresponding to the clock domain;
[0054] The step of processing the input target timing margin and clock correlation coefficient by a preset signal analysis algorithm to obtain a criticality coefficient corresponding to the interconnection signal includes:
[0055] Determine the inverse of the clock cycle to obtain a first cycle inverse;
[0056] The product of the first cycle inverse and the target timing margin is used as the criticality coefficient of the interconnect signal.
[0057] The inverse of the first cycle can be understood as the inverse of the clock cycle. Specifically, the signal analysis algorithm can be implemented based on the following formula:
[0058] Slack Ratio = Slack*f(clk);
[0059] f(clk)=1 / Tcycle;
[0060] Among them, Slack Ratio represents the criticality coefficient, Slack represents the target timing margin, f(clk) represents the inverse of the first cycle, and Tcycle represents the clock cycle.
[0061] Optionally, before the input target timing margin and clock correlation coefficient are processed by a preset signal analysis algorithm, the method further includes:
[0062] Determine a clock critical coefficient corresponding to the clock domain;
[0063] The step of processing the input target timing margin and clock correlation coefficient by a preset signal analysis algorithm to obtain a criticality coefficient corresponding to the interconnection signal includes:
[0064] Determine the product of the clock period and the clock critical coefficient to obtain a critical period;
[0065] Determine the inverse of the key period to obtain the inverse of the second period;
[0066] The product of the second cycle inverse and the target timing margin is used as a criticality coefficient corresponding to the interconnection signal.
[0067] Among them, the clock critical coefficient characterizes the criticality of the clock domain. In an embodiment of the present invention, the clock domains in which the timing paths corresponding to different interconnected signals are located may be different. The clock critical coefficients corresponding to different clock domains may be different or the same. Optionally, the clock critical coefficient corresponding to the clock domain may be determined based on a pre-set clock domain critical coefficient mapping library, and the clock domain critical coefficient mapping library may include multiple clock domains, multiple clock critical coefficients, and a mapping relationship between clock domains and clock critical coefficients. The clock critical coefficient may be an integer greater than 1. Exemplarily, the clock critical coefficient may be 2, 3, or 5, etc. Specifically, the signal analysis algorithm may also be implemented based on the following formula:
[0068] Slack Ratio = Slack*f(clk);
[0069] f(clk)=1 / Tcycle*a;
[0070] Among them, Slack Ratio represents the criticality coefficient, Slack represents the target timing margin, f(clk) represents the inverse of the first cycle, Tcycle represents the clock cycle, and a represents the clock criticality coefficient.
[0071] Based on the above implementation scheme, the clock critical coefficient of the timing path of different clock domains is introduced, and the effect of more accurately calculating the timing criticality of the interconnected signal is achieved, which is more instructive for the compilation of the driver. The criticality coefficient of the interconnected signal of the present invention refers to the degree of influence of the signal on the maximum operating frequency of the system. The higher the criticality, the easier it is to become the bottleneck point of the system operating frequency. If there are two interconnected signals and their timing paths belonging to different clock domains, if they have the same size path delay, the timing paths under two different clock domains, usually the interconnected signal under the high-frequency fast clock domain is more critical, because the clock cycle is small, it is easier to cause timing violations. If the two interconnected signals are treated equally, there is a problem that the difference of the original clock criticality is lost, and the timing optimization is difficult to achieve the preset effect. Therefore, by introducing the criticality of the timing path of different clock domains (i.e., the clock criticality coefficient), a more accurate criticality coefficient of the interconnected signal can be obtained.
[0072] The technical solution of the embodiment of the present invention is to determine a prototype verification system, construct an interconnection signal timing diagram corresponding to the prototype verification system, wherein the interconnection signal timing diagram includes chip models of multiple field programmable gate arrays, interconnection signals across the chip models, timing paths corresponding to the interconnection signals, and path delay values corresponding to the timing paths; perform timing analysis on the interconnection signal timing diagram through a static timing analysis algorithm, and determine the target timing margin corresponding to each interconnection signal, wherein the target timing margin is determined based on the path delay value corresponding to the timing path of the interconnection signal; for each interconnection signal, determine the clock domain where the timing path corresponding to the interconnection signal is located, determine the clock correlation coefficient corresponding to the clock domain, and process the input target timing margin and clock correlation coefficient through a pre-set signal analysis algorithm to obtain the criticality coefficient corresponding to the interconnection signal. The present invention realizes the analysis and extraction of the timing criticality of interconnection signals between FPGAs in a multi-FPGA system, and performs timing-driven design partitioning, system routing, and time division multiplexing ratio allocation in the compilation process of the prototype verification system based on the extracted criticality, which can effectively optimize the system timing and improve system performance.
[0073] Embodiment 2
[0074] Figure 3 This is a flow chart of a signal analysis method provided in the second embodiment of the present invention. This embodiment refines the interconnect signal timing diagram corresponding to the prototype verification system constructed in the above embodiment. Figure 3 As shown, the method includes:
[0075] S210: Determine a timing modeling file set corresponding to the prototype verification system.
[0076] The timing modeling file set can be understood as a file set for constructing an interconnect signal timing diagram. Optionally, the timing modeling file set includes multiple netlist files and at least one interconnection file. The netlist file may include text data describing the circuit connection status of a single field programmable gate array in the prototype verification system. The interconnection file may include text data describing the connection relationship of the top-level interface in each of the netlist files.
[0077] S220 , constructing an interconnect signal timing diagram of the prototype verification system based on the timing modeling file set and the timing diagram construction conditions.
[0078] The timing diagram construction condition is related to the traversal result of the timing device in the field programmable gate array.
[0079] Optionally, constructing the interconnect signal timing diagram of the prototype verification system based on the timing modeling file set and the timing diagram construction condition includes:
[0080] Traversing the target port of the field programmable gate array recorded in the timing modeling file, and stopping the traversal and obtaining the target traversal result when the timing diagram construction condition is met, wherein the timing diagram construction condition includes traversing to the first-level timing device, and the target port includes an input port and / or an output port;
[0081] A preliminary timing diagram is obtained based on the target traversal result, and the preliminary timing diagram is simplified based on a path simplification criterion to obtain an interconnection signal timing diagram, wherein the path simplification criterion includes retaining one timing path for each of the clock domains corresponding to each of the target ports.
[0082] The sequential device may be understood as a sequential logic element. Optionally, the sequential device may include a trigger, a counter, a register, etc. The traversing to the sequential device at the first level may refer to traversing to a port of the sequential device at the first level.
[0083] The target traversal result includes a depth traversal result or a breadth traversal result. The preliminary timing diagram can be understood as a timing diagram constructed based on the target traversal result. The path simplification criterion is a criterion for simplifying the timing paths in the preliminary timing diagram.
[0084] Optionally, the simplifying the preliminary timing diagram based on a path simplification criterion to obtain an interconnection signal timing diagram includes:
[0085] Simplifying the preliminary timing diagram based on a path simplification criterion to obtain a simplified timing diagram;
[0086] For each retained timing path in the simplified timing diagram, non-critical path nodes in the timing path are determined and deleted to obtain an interconnected signal timing diagram, wherein the non-critical path nodes are intermediate nodes of the timing path.
[0087] There is one timing path in each of the clock domains in the simplified timing diagram.
[0088] Exemplarily, the retained timing path is A->B->C, and the path nodes include A, B, and C. If the non-critical path node in the timing path is B, then node B is deleted to obtain the target timing path A->C.
[0089] Optionally, traversing the target ports of the field programmable gate array recorded in the timing modeling file includes:
[0090] Performing a deep traversal on the input port and the output port of the field programmable gate array recorded in the timing modeling file respectively by using a deep traversal algorithm;
[0091] Alternatively, the input port and the output end of the field programmable gate array recorded in the timing modeling file are respectively traversed by a breadth-traversal algorithm.
[0092] The depth traversal algorithm and the breadth traversal algorithm can be understood as two basic graph traversal algorithms.
[0093] Based on the above embodiment scheme, the constructed interconnect signal timing diagram only includes interconnect signals across FPGAs, and the timing path is simplified to a great extent, which reduces the scale of the timing diagram and further improves the efficiency of signal analysis.
[0094] The overall process of constructing the interconnect signal timing diagram of the prototype verification system based on the timing modeling file set and the timing diagram construction conditions is specifically described as follows:
[0095] It should be understood that the interconnected signal timing diagram may include all the information recorded in the circuit netlist file of the entire multi-FPGA system. The interconnected signal timing diagram may be a directed graph. The nodes of the timing path in the timing diagram may be top-level ports or pins of timing devices inside the FPGA. The edges of the timing diagram are directed edges between nodes, and the direction is consistent with the direction of the signal flow in the circuit netlist file. In the present invention, the timing diagram only models cross-FPGA signals, which can reduce the scale of the timing diagram and thus improve the efficiency of signal analysis. Specifically, a depth-first traversal or a breadth-first traversal is performed from the input port and output port of each FPGA, respectively. The condition for stopping the traversal is to traverse to the first-level timing device, and the constructed timing diagram is a timing diagram only related to cross-FPGA signals.
[0096] Furthermore, the timing diagram obtained above can be trimmed and optimized to reduce the size of the timing diagram. The specific trimming criterion is to retain only one timing path in each clock domain within each port, and other nodes and edges can be deleted.
[0097] Furthermore, the retained timing path is further compressed, for example, A->B->C can be compressed to A->C, wherein the edges belonging to the cross-FPGA signals during the compression process cannot be compressed and need to be retained.
[0098] Combination Figure 2 The overall process of constructing the interconnect signal timing diagram of the prototype verification system based on the timing modeling file set and the timing diagram construction conditions is further specifically described as follows:
[0099] Figure 2 The example diagram shown is a prototype verification system with three FPGAs. Four sequential logic modules are implemented, namely registers R1, R2, R3 and R4 in the diagram; three combinatorial logic modules are implemented, namely C1, C2 and C3 in the diagram. There are two interconnection signals Signal1 and Signal2 between the FPGAs.
[0100] The starting point and the end point of the timing path are both timing devices (or equivalent timing devices). In static timing analysis, the signal path from the starting timing device to the end timing device is a timing path (TimingPath) of the signal. Figure 2 The interconnection signal Signal2 shown, R3 in FPGA2 is the starting point of the timing path where the signal is located, R4 in FPGA3 is the end point of the timing path where the signal is located, the path from point F to point M is the timing path where the interconnection signal is located, and the logic delay (path delay value) of the interconnection signal is the path delay from point F to point M.
[0101] If an interconnect signal has multiple timing start points or multiple timing end points, the signal is said to have multiple timing paths. In this case, the logic delay of the signal is defined as the maximum path delay among the multiple timing paths. Figure 2 The interconnection signal Signal1 shown has two timing path starting points (ie, R1 and R2) and two timing paths from point A to point E and from point B to point E. The logic delay of the signal is the maximum of the two timing paths.
[0102] S230: Perform timing analysis on the interconnect signal timing diagram using a static timing analysis algorithm to determine a target timing margin corresponding to each of the interconnect signals.
[0103] S240. For each of the interconnected signals, determine the clock domain in which the timing path corresponding to the interconnected signal is located, determine the clock correlation coefficient corresponding to the clock domain, and process the input target timing margin and clock correlation coefficient through a preset signal analysis algorithm to obtain a criticality coefficient corresponding to the interconnected signal.
[0104] The technical solution of the embodiment of the present invention is to determine the timing modeling file set corresponding to the prototype verification system, wherein the timing modeling file set includes multiple netlist files and at least one interconnection file; and to construct the interconnection signal timing diagram of the prototype verification system based on the timing modeling file set and the timing diagram construction condition, wherein the timing diagram construction condition is related to the traversal result of the timing device in the field programmable gate array. The effect of only including the interconnection signals across FPGAs in the constructed interconnection signal timing diagram is achieved.
[0105] Figure 4 FIG. 1 is an overall flow chart of a signal analysis method provided according to an embodiment of the present invention. Figure 4 As shown, the present invention proposes a timing modeling scheme for interconnection signals of a multi-FPGA system, and a timing criticality analysis and extraction scheme for interconnection signals provided by a timing diagram constructed based on the above modeling method, which increases more accurate differentiation for interconnection signals, has guiding significance for the compilation process of a timing-driven prototype verification system, and can optimize system timing during compilation processing based on this, thereby improving the bottleneck of system performance.
[0106] The timing criticality extraction scheme of interconnected signals of the present invention can be used to guide the compilation of multiple FPGA prototypes, and generate compilation results driven by accurate signal timing criticality, which is convenient for optimizing system timing during compilation processing, reducing system performance loss, and improving the maximum operable frequency of the system.
[0107] Embodiment 3
[0108] Figure 5 FIG. 1 is a schematic diagram of the structure of a signal analysis device provided in Embodiment 3 of the present invention. Figure 5 As shown, the device includes: a timing diagram construction module 310, a static timing analysis module 320 and a criticality extraction module 330.
[0109] Among them, the timing diagram construction module 310 is used to determine the prototype verification system and construct the interconnection signal timing diagram corresponding to the prototype verification system, wherein the interconnection signal timing diagram includes chip models of multiple field programmable gate arrays, interconnection signals across the chip models, timing paths corresponding to the interconnection signals, and path delay values corresponding to the timing paths; the static timing analysis module 320 is used to perform timing analysis on the interconnection signal timing diagram through a static timing analysis algorithm to determine the target timing margin corresponding to each of the interconnection signals, wherein the target timing margin is determined based on the path delay value corresponding to the timing path of the interconnection signal; the criticality extraction module 330 is used to determine the clock domain in which the timing path corresponding to the interconnection signal is located for each of the interconnection signals, determine the clock correlation coefficient based on the clock domain, and process the input target timing margin and clock correlation coefficient through a preset signal analysis algorithm to obtain the criticality coefficient corresponding to the interconnection signal.
[0110] The technical solution of the embodiment of the present invention is to determine a prototype verification system, construct an interconnection signal timing diagram corresponding to the prototype verification system, wherein the interconnection signal timing diagram includes chip models of multiple field programmable gate arrays, interconnection signals across the chip models, timing paths corresponding to the interconnection signals, and path delay values corresponding to the timing paths; perform timing analysis on the interconnection signal timing diagram through a static timing analysis algorithm, and determine the target timing margin corresponding to each interconnection signal, wherein the target timing margin is determined based on the path delay value corresponding to the timing path of the interconnection signal; for each interconnection signal, determine the clock domain where the timing path corresponding to the interconnection signal is located, determine the clock correlation coefficient corresponding to the clock domain, and process the input target timing margin and clock correlation coefficient through a pre-set signal analysis algorithm to obtain the criticality coefficient corresponding to the interconnection signal. The present invention realizes the analysis and extraction of the timing criticality of interconnection signals between FPGAs in a multi-FPGA system, and performs timing-driven design partitioning, system routing, and time division multiplexing ratio allocation in the compilation process of the prototype verification system based on the extracted criticality, which can effectively optimize the system timing and improve system performance.
[0111] Optionally, the clock correlation coefficient includes a clock period corresponding to the clock domain; the criticality extraction module 330 is specifically used to:
[0112] Determine the inverse of the clock cycle to obtain a first cycle inverse;
[0113] The product of the first cycle inverse and the target timing margin is used as the criticality coefficient of the interconnect signal.
[0114] Optionally, the criticality extraction module 330 further includes:
[0115] A key coefficient determination unit, used for determining the clock key coefficient corresponding to the clock domain before processing the input target timing margin and clock correlation coefficient by a preset signal analysis algorithm;
[0116] The key extraction module 330 is specifically used for:
[0117] Determine the product of the clock period and the clock critical coefficient to obtain a critical period;
[0118] Determine the inverse of the key period to obtain the inverse of the second period;
[0119] The product of the second cycle inverse and the target timing margin is used as a criticality coefficient corresponding to the interconnection signal.
[0120] Optionally, the criticality extraction module 330 is specifically configured to:
[0121] Determine the product of the clock period and the period correction coefficient to obtain the corrected clock period;
[0122] Determine the corrected inverse of the clock cycle to obtain a second cycle inverse;
[0123] The product of the second cycle inverse and the target timing margin is used as a criticality coefficient corresponding to the interconnection signal.
[0124] Optionally, the timing diagram construction module 310 includes: a file determination unit and a timing diagram construction unit;
[0125] The file determination unit is used to determine a timing modeling file set corresponding to the prototype verification system, wherein the timing modeling file set includes a plurality of netlist files and at least one interconnection file;
[0126] The timing diagram construction unit is used to construct the interconnect signal timing diagram of the prototype verification system based on the timing modeling file set and the timing diagram construction conditions, wherein the timing diagram construction conditions are related to the traversal results of the timing devices in the field programmable gate array.
[0127] Optionally, the timing diagram construction unit includes: an interface traversal subunit and a path simplification subunit;
[0128] The interface traversal subunit is used to traverse the target port of the field programmable gate array recorded in the timing modeling file, and stop the traversal and obtain the target traversal result when the timing diagram construction condition is met, wherein the timing diagram construction condition includes traversing to the timing device of the first level, and the target port includes an input port and / or an output port;
[0129] The path simplification subunit is used to obtain a preliminary timing diagram based on the target traversal result, and simplify the preliminary timing diagram based on a path simplification criterion to obtain an interconnection signal timing diagram, wherein the path simplification criterion includes retaining one timing path for each of the clock domains corresponding to each of the target ports.
[0130] Optionally, the path simplification subunit is specifically used to:
[0131] Simplifying the preliminary timing diagram based on a path simplification criterion to obtain a simplified timing diagram;
[0132] For each retained timing path in the simplified timing diagram, non-critical path nodes in the timing path are determined and deleted to obtain an interconnected signal timing diagram, wherein the non-critical path nodes are intermediate nodes of the timing path.
[0133] Optionally, the interface traversal subunit is specifically used for:
[0134] Performing a deep traversal on the input port and the output port of the field programmable gate array recorded in the timing modeling file respectively by using a deep traversal algorithm;
[0135] Alternatively, the input port and the output end of the field programmable gate array recorded in the timing modeling file are respectively traversed by a breadth-traversal algorithm.
[0136] Optionally, the static timing analysis module 320 is specifically used for:
[0137] Determine the signal arrival time corresponding to each interconnect signal in the interconnect signal timing diagram by a static timing analysis algorithm, wherein the signal arrival time is determined based on the path delay value, and the signal arrival time includes an actual arrival time and a required arrival time;
[0138] For the interconnect signal, the target timing margin is determined according to the actual arrival time and the required arrival time.
[0139] The signal analysis device provided in the embodiment of the present invention can execute the signal analysis method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.
[0140] Embodiment 4
[0141] Figure 6 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.
[0142] like Figure 6As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.
[0143] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.
[0144] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as a signal analysis method.
[0145] In some embodiments, the signal analysis method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the signal analysis method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the signal analysis method in any other appropriate manner (e.g., by means of firmware).
[0146] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.
[0147] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.
[0148] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0149] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).
[0150] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.
[0151] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.
[0152] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.
[0153] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A signal analysis method, characterized in that: include: Determine a prototype verification system, and construct an interconnection signal timing diagram corresponding to the prototype verification system, wherein the interconnection signal timing diagram includes chip models of multiple field programmable gate arrays, interconnection signals across the chip models, timing paths corresponding to the interconnection signals, and path delay values corresponding to the timing paths; Performing timing analysis on the interconnect signal timing diagram by a static timing analysis algorithm to determine a target timing margin corresponding to each of the interconnect signals, wherein the target timing margin is determined based on the path delay value corresponding to the timing path of the interconnect signal; For each of the interconnected signals, determine the clock domain in which the timing path corresponding to the interconnected signal is located, determine the clock correlation coefficient corresponding to the clock domain, and process the input target timing margin and clock correlation coefficient through a preset signal analysis algorithm to obtain the criticality coefficient corresponding to the interconnected signal.
2. The method according to claim 1, characterized in that The clock correlation coefficient includes a clock period corresponding to the clock domain; The step of processing the input target timing margin and clock correlation coefficient by a preset signal analysis algorithm to obtain a criticality coefficient corresponding to the interconnection signal includes: Determine the inverse of the clock cycle to obtain a first cycle inverse; The product of the first cycle inverse and the target timing margin is used as the criticality coefficient of the interconnect signal.
3. The method according to claim 2, characterized in that Before the input target timing margin and clock correlation coefficient are processed by a preset signal analysis algorithm, the method further includes: Determine a clock critical coefficient corresponding to the clock domain; The step of processing the input target timing margin and clock correlation coefficient by a preset signal analysis algorithm to obtain a criticality coefficient corresponding to the interconnection signal includes: Determine the product of the clock period and the clock critical coefficient to obtain a critical period; Determine the inverse of the key period to obtain the inverse of the second period; The product of the second cycle inverse and the target timing margin is used as a criticality coefficient corresponding to the interconnection signal.
4. The method according to claim 1, characterized in that: The interconnect signal timing diagram corresponding to the prototype verification system is constructed, including: Determine a timing modeling file set corresponding to the prototype verification system, wherein the timing modeling file set includes a plurality of netlist files and at least one interconnection file; The interconnect signal timing diagram of the prototype verification system is constructed based on the timing modeling file set and the timing diagram construction condition, wherein the timing diagram construction condition is related to the traversal result of the timing device in the field programmable gate array.
5. The method according to claim 4, characterized in that The method of constructing the interconnect signal timing diagram of the prototype verification system based on the timing modeling file set and the timing diagram construction condition includes: Traversing the target port of the field programmable gate array recorded in the timing modeling file, and stopping the traversal and obtaining the target traversal result when the timing diagram construction condition is met, wherein the timing diagram construction condition includes traversing to the timing device of the first level, and the target port includes an input port and / or an output port; A preliminary timing diagram is obtained based on the target traversal result, and the preliminary timing diagram is simplified based on a path simplification criterion to obtain an interconnection signal timing diagram, wherein the path simplification criterion includes retaining one timing path for each of the clock domains corresponding to each of the target ports.
6. The method according to claim 5, characterized in that The step of simplifying the preliminary timing diagram based on a path simplification criterion to obtain an interconnection signal timing diagram includes: Simplifying the preliminary timing diagram based on a path simplification criterion to obtain a simplified timing diagram; For each retained timing path in the simplified timing diagram, non-critical path nodes in the timing path are determined and deleted to obtain an interconnected signal timing diagram, wherein the non-critical path nodes are intermediate nodes of the timing path.
7. The method according to claim 5, characterized in that The traversing the target ports of the field programmable gate array recorded in the timing modeling file includes: Performing a deep traversal on the input port and the output port of the field programmable gate array recorded in the timing modeling file respectively by using a deep traversal algorithm; Alternatively, the input port and the output end of the field programmable gate array recorded in the timing modeling file are respectively traversed by a breadth-traversal algorithm.
8. The method according to claim 1, characterized in that The performing timing analysis on the interconnect signal timing diagram by using a static timing analysis algorithm to determine a target timing margin corresponding to each interconnect signal includes: Determine the signal arrival time corresponding to each interconnect signal in the interconnect signal timing diagram by a static timing analysis algorithm, wherein the signal arrival time is determined based on the path delay value, and the signal arrival time includes an actual arrival time and a required arrival time; For the interconnect signal, the target timing margin is determined according to the actual arrival time and the required arrival time.
9. A signal analysis device, characterized in that: include: A timing diagram construction module is used to determine a prototype verification system and construct an interconnection signal timing diagram corresponding to the prototype verification system, wherein the interconnection signal timing diagram includes chip models of multiple field programmable gate arrays, interconnection signals across the chip models, timing paths corresponding to the interconnection signals, and path delay values corresponding to the timing paths; A static timing analysis module, configured to perform timing analysis on the interconnect signal timing diagram by using a static timing analysis algorithm to determine a target timing margin corresponding to each of the interconnect signals, wherein the target timing margin is determined based on the path delay value corresponding to the timing path of the interconnect signal; The criticality extraction module is used to determine, for each of the interconnected signals, the clock domain in which the timing path corresponding to the interconnected signal is located, determine the clock correlation coefficient corresponding to the clock domain, and process the input target timing margin and clock correlation coefficient through a preset signal analysis algorithm to obtain the criticality coefficient corresponding to the interconnected signal.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the signal analysis method according to any one of claims 1 to 8 when executed.