Incremental satisfiability problem solution search method and system and computer equipment

Abstract

The invention provides a solution search method and system for an incremental satisfiability problem and computer equipment, and the method comprises the steps: respectively mapping Miter circuits formed by two sequential logic circuits in each clock period into a conjunctive normal form, and selecting a conjunctive normal form corresponding to a specified clock period as a basic conjunctive normal form, a conjunctive normal form corresponding to a subsequent clock period is an increment conjunctive normal form, and increment clauses of the increment conjunctive normal form relative to the basic conjunctive normal form are calculated; taking a satisfaction solution of the basic conjunctive normal form as a basic solution, and when solution search is performed on the incremental conjunctive normal form, setting other solution variables except solution variables related to incremental clauses in the basic solution to be in a fixed and non-turnover state according to the incremental clauses of the to-be-solved incremental conjunctive normal form relative to the basic conjunctive normal form; variable overturning is carried out on the overturning solution variable to construct the initial solution of the SLS algorithm, so that when the SLS is applied to solve the incremental satisfiability problem, the problem does not need to be completely constructed again, and the solving time and cost are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of computer software verification, and in particular to a method, system and computer device for searching a solution to an incremental satisfiability problem. Background Art

[0002] Circuit equivalence checking (EC) is a key technology to verify whether two circuit designs are functionally equivalent. In integrated circuit design, as the complexity of the design continues to increase, designs at different stages may have multiple expressions, including RTL-level descriptions, netlists after logic synthesis, and netlists in the subsequent physical design stage. Ensuring that the circuit function does not change between these stages is one of the important tasks of design verification. If two circuits are functionally equivalent, they will produce the same output under the same input conditions. Equivalence verification can ensure the correctness of the design from high-level description to the final implementation, reduce errors in the design, and improve the reliability and security of the circuit. It is widely used in design processes such as logic synthesis, low-power conversion, and timing optimization to help verify the functional consistency of different optimized circuits with the original design, thereby avoiding functional failures caused by design errors.

[0003] In order to verify whether two circuits are equivalent, a miter circuit (comparison circuit) is usually used. The miter circuit is composed of two circuits to be verified through a special structure, and its output is used to determine whether the two circuits are equivalent. The specific construction process is as follows: keep the inputs of the two circuits A and B to be verified consistent, that is, they accept the same input signal. Perform an XOR operation on the outputs of circuit A and circuit B to generate a comparison signal. If the outputs of the two circuits are consistent under all input conditions, the XOR result is zero. If the XOR result is not zero under certain input conditions, it means that the functions of the two circuits are not equivalent. For stateless combinational logic, the miter circuit can be directly mapped to a conjunctive normal form (CNF), while for stateful and time-varying sequential logic, it is necessary to generate multiple combinational logics representing the current clock cycle by exhausting the internal state of the circuit in different clock cycles, and map them to multiple conjunctive normal forms for solution. By detecting whether the output of the miter circuit is non-zero, it can be concluded whether the two circuits are equivalent. This structured comparison method provides a basis for circuit equivalence verification. The use of SAT solvers in equivalence verification systems is currently the mainstream approach.

[0004] The Boolean satisfiability problem (SAT problem) is a problem of determining whether a given propositional logic formula is satisfiable. A SAT problem is usually expressed in the form of conjunctive normal form (CNF), which consists of the conjunction of several clauses. Among the scenarios corresponding to the satisfiability problem (SAT problem), there is a type of scenario that requires solving a set of approximate SAT problems, or continuously solving a SAT problem that changes over time. The software that solves the SAT problem is called a SAT solver. The SAT solver can be called as a whole executable program for solving, or as a software library, and the calling program calls its interface for more detailed solving. At present, the mainstream SAT solving algorithms are divided into two types: CDCL (conflict driven clause learning) and SLS (stochastic local search). The mainstream solvers usually use CDCL as the main framework and combine SLS for optimization.

[0005] The existing CDCL / SLS hybrid solution algorithm for SAT problems in incremental scenarios has the following shortcomings:

[0006] 1. Among the known algorithms and implementations, only the CDCL algorithm supports incremental solving and provides an interface for incremental solving in its implementation. The known SLS algorithm does not support incremental solving and does not provide an interface for incremental solving. Therefore, in the scenario of incremental SAT problems, the CDCL / SLS hybrid algorithm cannot improve performance by introducing SLS.

[0007] 2. The mainstream CDCL / SLS hybrid algorithm needs to reconstruct the SLS solver every time it calls SLS, and release the corresponding space after use, and cannot retain the previous calculation information. At the same time, it takes a lot of time to exchange complete SAT problem information and initialize the construction between solvers. Therefore, in the scenario of incremental solution, the hybrid solution algorithm introduces a lot of additional time and storage space overhead. Summary of the invention

[0008] In view of the above problems, the present invention is proposed to provide a solution search method, system and computer device for an incremental satisfiability problem that overcomes the above problems or at least partially solves the above problems.

[0009] One aspect of the present invention provides a method for searching for a solution to an incremental satisfiability problem, the method being used to implement equivalence verification of sequential logic circuits, comprising:

[0010] The Miter circuits formed by the two sequential logic circuits to be verified in each clock cycle are respectively mapped into a conjunction normal form, the conjunction normal form corresponding to the Miter circuit formed in the specified clock cycle is selected as the basic conjunction normal form, and the conjunction normal forms corresponding to the Miter circuits formed in each clock cycle after the current specified clock cycle are all used as incremental conjunction normal forms, and the incremental clauses of each incremental conjunction normal form relative to the basic conjunction normal form are respectively calculated, and the basic conjunction normal form and the incremental conjunction normal form constitute a conjunction normal form set; each incremental conjunction normal form in the conjunction normal form set has some identical clauses with the basic conjunction normal form;

[0011] Taking the satisfied solution of the basic conjunctive normal form as the basic solution, when searching for the solution of the incremental conjunctive normal form in the conjunctive normal form set, according to the incremental clause of the target conjunctive normal form to be solved in the conjunctive normal form set relative to the basic conjunctive normal form, setting the other solution variables in the basic solution except the solution variables related to the incremental clause to a fixed and non-reversible state;

[0012] The initial solution of the SLS algorithm is constructed by flipping the flippable solution variables in the basic solution, and the target conjunction normal form is searched for a solution based on the initial solution, so as to realize the equivalence verification of the logic circuit according to the solution result.

[0013] Optionally, the method further comprises:

[0014] In the process of searching for a satisfactory solution of the target conjunction normal form according to the initial solution, when a preset first restart condition is met, a first initial solution after restart is constructed according to a preset initial solution reconstruction strategy, and a second initial solution after restart is constructed by continuously performing variable flipping on flippable solution variables in the basic solution;

[0015] Estimate the computational cost of searching for a solution to the target conjunction normal form using the first initial solution and the second initial solution, select the initial solution with lower computational cost as the initial solution after restart, and use it to search for a solution to the target conjunction normal form.

[0016] Optionally, the estimating the computational effort of searching for a solution to the target conjunction normal form using the first initial solution and the second initial solution includes:

[0017] The computational complexity of the two solution methods is estimated based on the corresponding clause length, number of variables and / or ratio of variable values ​​when the first initial solution or the second initial solution is used to search for a solution of the target conjunction normal form.

[0018] Optionally, the method further comprises:

[0019] Monitor the iterative exit conditions of the current solution search process;

[0020] When the current solution search process does not meet the iteration exit condition, if the score value of the solution variable assignment found during the solution search for the target conjunctive normal form is higher than the score value of the historical best assignment, the current solution variable assignment is taken as the best assignment and the solution is continued; if a satisfying solution is found during the solution search for the target conjunctive normal form, the next target conjunctive normal form to be solved in the conjunctive normal form set is solved; otherwise, continue to select flippable solution variables to perform variable flipping to search for the target conjunctive normal form.

[0021] Optionally, the iteration exit condition includes that the search time is greater than a preset time threshold and / or the memory space usage is greater than a preset memory space threshold.

[0022] Optionally, before selecting the conjunction normal form corresponding to the Miter circuit formed by the specified clock cycle as the basic conjunction normal form, the method further includes:

[0023] Get all clauses included in the target conjunction normal form to be solved in the conjunction normal form set;

[0024] Perform clause propagation and search for conflicting clauses. If no conflicting clauses are found during clause propagation, then whenever a preset second restart condition is met, determine whether a preset switching solver condition is met, wherein the switching solver condition is periodic switching.

[0025] If the preset conditions for switching solvers are met, the incremental SLS solver is switched to solve the problem;

[0026] If the preset conditions for switching solvers are not met, the scores of variable assignments are updated and the variable phases are reset.

[0027] Optionally, the method further comprises:

[0028] If conflicting clauses are found during clause propagation, conflict analysis is performed to obtain learned clauses and backtracking positions;

[0029] Append the learned clause to the clause list and backtrack;

[0030] If high-quality branches are obtained during the search process, the SLS algorithm is used to reconstruct the initial solution of the SLS algorithm based on the high-quality branches, and search sampling is performed in the corresponding search space based on the obtained initial solution. The search results are returned as heuristic information to continue clause propagation and find conflicting clauses.

[0031] In a second aspect, the present invention further provides a solution search system for an incremental satisfiability problem, the system being used to implement equivalence verification of sequential logic circuits, comprising:

[0032] An incremental SLS solver, wherein the incremental SLS solver is configured to: map the Miter circuits formed by the two sequential logic circuits to be verified in each clock cycle into a conjunction normal form respectively, select the conjunction normal form corresponding to the Miter circuit formed in the specified clock cycle as the basic conjunction normal form, and use the conjunction normal forms corresponding to the Miter circuits formed in each clock cycle after the current specified clock cycle as incremental conjunction normal forms, and respectively calculate the incremental clauses of each incremental conjunction normal form relative to the basic conjunction normal form, wherein the basic conjunction normal form and the incremental conjunction normal form constitute a conjunction normal form set; each in the conjunction normal form set An incremental conjunctive normal form has some identical clauses with a basic conjunctive normal form; a satisfied solution of the basic conjunctive normal form is taken as a basic solution, and when searching for solutions of the incremental conjunctive normal form in the conjunctive normal form set, according to the incremental clauses of the target conjunctive normal form to be solved in the conjunctive normal form set relative to the basic conjunctive normal form, the other solution variables in the basic solution except the solution variables related to the incremental clauses are set to a fixed and non-flippable state; the initial solution of the SLS algorithm is constructed by flipping the flippable solution variables in the basic solution, and the target conjunctive normal form is searched for solutions based on the initial solution, so as to realize the equivalence verification of the logic circuit according to the solution result.

[0033] Optionally, the system further comprises an incremental hybrid solver, which switches periodically with the incremental SLS solver and records search information before switching, so as to continue to perform solution search according to the recorded search information after entering the next switching cycle;

[0034] The incremental hybrid solver includes a CDCL solver body and an auxiliary SLS solver, and the two maintain the same clause set. The CDCL solver body is configured to: obtain all clauses included in the target conjunctive normal form to be solved in the conjunctive normal form set; perform clause propagation and find conflicting clauses. If no conflicting clauses are found during the clause propagation process, then whenever a preset second restart condition is met, determine whether the preset switching solver condition is met, and the switching solver condition is periodic switching; if the preset switching solver condition is met, switch to the incremental SLS solver, if the preset switching solver condition is not met, update the variable assignment score and reset the variable phase.

[0035] Optionally, the CDCL solver body is also configured as follows: if conflicting clauses are found during clause propagation, a conflict analysis is performed to obtain learned clauses and backtracking positions, the learned clauses are appended to the clause list, and backtracking is performed; if high-quality branches are obtained during the search process, the auxiliary SLS solver reconstructs the initial solution of the SLS algorithm based on the high-quality branches, performs search sampling in the corresponding search space based on the obtained initial solution, and returns the search results as heuristic information to the CDCL solver body.

[0036] In a third aspect, the present invention further provides a computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned method for searching a solution to the incremental satisfiability problem when executing the computer program.

[0037] The solution search method, system and computer device of the incremental satisfiability problem provided by the embodiment of the present invention propose an incremental SLS solution method for the incremental satisfiability problem in the process of integrated circuit equivalence verification, construct a set of conjunctive normal forms according to the Miter circuits formed by two sequential logic circuits to be verified in each clock cycle, and each conjunctive normal form in the set of conjunctive normal forms is similar. An incremental SLS solution method is proposed for the incremental satisfiability problem. When solving similar conjunctive normal forms, a basic conjunctive normal form is selected and the satisfying solution of the basic conjunctive normal form is used as the basic solution. By calculating the compatibility of other conjunctive normal forms with respect to the basic conjunctive normal form, the basic satisfiability normal form is solved. The incremental clause is used to fix the solution variables in the basic solution except the solution variables related to the incremental clause according to the incremental clause of the target conjunctive normal form to be solved relative to the basic conjunctive normal form when searching for solutions to other conjunctive normal forms, that is, to set them to a fixed and non-flippable state, and construct the initial solution of the SLS algorithm by flipping the variables of other flippable solution variables in the basic solution for solution search. When SLS is applied to solve the incremental satisfiability problem, it is not necessary to completely reconstruct the problem, which reduces the time and storage space overhead of the solution, and quickly and efficiently verifies the equivalence of two sequential logic circuits, which has significant advantages in the verification problem of integrated circuits.

[0038] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0040] Figure 1 A flow chart of a method for searching for a solution to an incremental satisfiability problem provided by an embodiment of the present invention;

[0041] Figure 2 A schematic diagram of a similar conjunction normal form formula proposed in an embodiment of the present invention;

[0042] Figure 3 An SSD system architecture diagram applicable to a solution search method for an incremental satisfiability problem is provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0044] Those skilled in the art will appreciate that, unless otherwise stated, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0045] Those skilled in the art will appreciate that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined.

[0046] The Boolean satisfiability problem (SAT problem) is a problem of determining whether a given propositional logic formula is satisfiable. It has extremely important application value in computer science, artificial intelligence, theorem proving, and especially in the field of EDA (electronic design automation). The input of the SAT solver is usually in the form of conjunctive normal form (CNF), which consists of the conjunction of several clauses. A clause is a disjunction of literals, and a literal is a Boolean variable itself or its negation.

[0047] The existing CDCL algorithm is a tree search algorithm that learns new clauses and performs non-sequential backtracking around reasoning conflicts encountered during the search. It is a complete algorithm. CDCL is a SAT solving algorithm based on backtracking. CDCL will continuously try a certain variable assignment (decision), verify satisfiability and backtrack. CDCL accelerates the finding of conflicting clauses through unit clause propagation. If a conflict is encountered, a conflict analysis is performed, and a new clause is formed as the result of the analysis and added to the original formula. The new clause records the cause of the conflict, so the next backtracking can jump back to a non-adjacent decision, thereby avoiding all assignments that may fall into the same conflict. The CDCL solver also uses heuristic methods, such as recording the activity of active variables / clauses, so as to prioritize those variables that are most likely to cause conflicts.

[0048] SLS is an algorithm that searches for solutions by walking in the solution space based on heuristic information. SAT usually starts with a randomly selected solution and searches the neighboring solution space through heuristic methods to try to find a better solution. A simple SLS algorithm framework is shown below (GSAT):

[0049] 1. Input: CNF formula F of the problem, maximum number of flips MaxFlip, maximum number of attempts MaxTries;

[0050] 2. Within the maximum number of attempts:

[0051] 3. Generate a new assignment σ for F;

[0052] a. Within the maximum number of flips;

[0053] b. If σ satisfies F, return σ (success);

[0054] 4. Choose a variable V to flip. The basis for selection is that flipping this variable V can minimize the number of unsatisfied clauses;

[0055] 5. Flip the V in σ;

[0056] 6. Return failure;

[0057] The SLS algorithm is relatively simple in structure, and does not perform operations such as adding clauses or backtracking. At the same time, SLS is not a complete algorithm. SLS hopes to find a satisfactory solution faster, but it will not perform pruning. If the maximum number of attempts or other constraints are not set, the algorithm will not terminate before a satisfactory solution is found.

[0058] In practical applications, when solving practical application problems, especially in theorem proofs and formal verification of hardware and software systems, SAT solvers are often called frequently to solve a group of similar CNF formulas. Most of the clauses in this group of CNF formulas are the same. When solving this group of CNF formulas one by one, the different parts will be regarded as added or deleted clauses, that is, increments. Incremental solving is a solution technology designed for this type of problem. It maintains a SAT solver and historical solution information, and supports dynamic addition and deletion of clauses. Mainstream incremental solution technologies are mostly based on hypothetical text methods. The idea is that if a clause C may be deleted later, add text I as an activation text to make I satisfy C. ′ =C∨I. When this clause is used, the value of I is assumed to be false, otherwise no assumption is made.

[0059] The existing known and widely used incremental SAT solvers are implemented within the CDCL framework, but do not perform mixed CDCL and SLS solutions. The most critical performance bottleneck of CDCL lies in the process of unit clause propagation and conflict learning. However, clause propagation and conflict learning still need to combine all the clauses in the solved problem. Therefore, incremental learning based entirely on CDCL cannot achieve ideal performance improvement in its corresponding scenarios. Existing methods have the following limitations:

[0060] 1. Among the current mainstream SAT solving algorithms, only CDCL supports incremental technology and provides a series of incremental interfaces, while SLS does not support incremental solving technology and interfaces;

[0061] 2. The mainstream SAT hybrid algorithm needs to reconstruct the SLS solver every time it calls SLS, and release the corresponding space after use. It cannot retain the previous calculation information, and it takes a lot of time to fully transfer CNF and initialize the construction.

[0062] In view of the shortcomings of the existing hybrid incremental solver in the scenario of incrementally solving the SAT problem, such as the SLS part of the existing hybrid incremental solver cannot perform incremental solution, the SLS solver must be completely reconstructed during the solution, resulting in additional time and storage space overhead, and the inability to dynamically switch between incremental solution and complete reconstruction solution, the present invention proposes a solution search method and system for incremental satisfiability problems.

[0063] Figure 1 The flowchart of the incremental satisfiability problem solution search method according to one embodiment of the present invention is schematically shown. The incremental satisfiability problem solution search method proposed in the embodiment of the present invention implements an incremental SLS solver. Figure 1 The solution search method for the incremental satisfiability problem of the embodiment of the present invention specifically includes the following steps:

[0064] S11, map the Miter circuits formed by the two sequential logic circuits to be verified in each clock cycle to a conjunctive normal form respectively, select the conjunctive normal form corresponding to the Miter circuit formed in the specified clock cycle as the basic conjunctive normal form, and use the conjunctive normal forms corresponding to the Miter circuits formed in each clock cycle after the current specified clock cycle as incremental conjunctive normal forms, and calculate the incremental clauses of each incremental conjunctive normal form relative to the basic conjunctive normal form respectively. The basic conjunctive normal form and the incremental conjunctive normal form constitute a conjunctive normal form set. Each incremental conjunctive normal form in the conjunctive normal form set has some of the same clauses as the basic conjunctive normal form. Among them, the specified clock cycle can be the initial clock cycle or any clock cycle other than the initial clock cycle. That is, it is allowed to select the basic conjunctive normal form multiple times during the solution process, and it is allowed to select the conjunctive normal form corresponding to the clock cycle other than the initial clock cycle as the basic conjunctive normal form.

[0065] In the actual solution process, a conjunction normal form for a certain periodic circuit may appear. The performance and effect of solving it according to its corresponding basic conjunction normal form + incremental part are not as good as solving it as a new basic conjunction normal form. Therefore, in the solution process, it is possible to select the conjunction normal form of a certain clock cycle as the new basic conjunction normal form for solution, and perform subsequent solutions based on it to improve the solution efficiency.

[0066] Specifically, the Miter circuits formed by the two sequential logic circuits to be verified in each clock cycle are respectively mapped into a conjunctive normal form, which specifically includes: by reading the hardware description language files of the two sequential logic circuits to be verified, the two sequential logic circuits to be verified have the same number of circuit input terminals and the same number of circuit output terminals, and according to the hardware description language files of the two sequential logic circuits to be verified, the two sequential logic circuits in each clock cycle are respectively represented as combinational circuits composed of logic gates, and a Miter circuit is constructed according to the combinational circuits corresponding to the two sequential logic circuits, and the Miter circuits formed in each clock cycle are respectively mapped into a conjunctive normal form in turn.

[0067] The SLS solver architecture corresponding to the embodiment of the present invention includes an incremental SLS solver.

[0068] In this embodiment, each conjunction normal form in the conjunction normal form set is a group of similar conjunction normal form formulas, and most of the clauses of the formulas of this group of conjunction normal forms are the same, such as Figure 2As shown. A conjunctive normal form is selected from the set of conjunctive normal forms as the basic conjunctive normal form, and the incremental clauses of other conjunctive normal forms formed after the basic conjunctive normal form in the set of conjunctive normal forms relative to the basic conjunctive normal form are calculated to achieve incremental SLS solution. It can be understood that different conjunctive normal forms are essentially different satisfiability problems. The way to select the basic conjunctive normal form is to use the conjunctive normal form corresponding to the satisfiability problem encountered first in the solution process as the basic conjunctive normal form, and the satisfying solution of the problem encountered first becomes the basic solution of the problem encountered later.

[0069] S12. Take the satisfied solution of the basic conjunctive normal form as the basic solution. When searching for solutions of the incremental conjunctive normal form in the conjunctive normal form set, set the solution variables in the basic solution except the solution variables related to the incremental clause to a fixed and irreversible state according to the incremental clause of the target conjunctive normal form to be solved in the conjunctive normal form set relative to the basic conjunctive normal form.

[0070] In this embodiment, flipping means that the Boolean variable X in the basic solution is reassigned to the opposite value, such as reassigning the original value of 1 to 0, and vice versa. In this embodiment, the solution variables other than the solution variables related to the increment clause in the basic solution are fixed and made to be in an irreversible state. The fixed assumption means that some variables in the basic solution are set to be fixed, and the fixed variables cannot be flipped in the subsequent solution process.

[0071] In this embodiment, the method of obtaining the initial solution is not limited to the CDCL algorithm / SLS algorithm or the hybrid solution algorithm.

[0072] S13, constructing an initial solution of the SLS algorithm by performing a variable flipping method on the flippable solution variables in the basic solution, and searching for a solution of the target conjunctive normal form according to the initial solution, so as to implement logic circuit equivalence verification according to the solution result. In this embodiment, each conjunctive normal form is solved in turn, and logic circuit equivalence verification is implemented according to the solution result of each conjunctive normal form.

[0073] The initial solution refers to a set of random assignments to variables, and the generation of the initial solution in the prior art does not rely on any input or prior knowledge. In this embodiment, the initial solution is obtained by randomly flipping the flippable solution variables in the basic solution.

[0074] In the scenario of circuit equivalence verification, what is formed is a CNF problem that is generated in the order of clock cycles and shares some of the same clauses, and the later generated CNF problem is increased or decreased based on the first generated CNF problem. Therefore, such a problem is called an "incremental SAT problem". The ordinary SAT solver regards each CNF problem as an independent problem for solution. The present invention proposes an incremental SAT solver that can use the clause information shared between CNF problems to achieve solution. In a specific embodiment, by reading the RTL-level hardware description language (HDL) code of two sequential logic circuits A and B with the same input and output, starting from the 0th clock cycle, the two circuits in each clock cycle c are respectively represented as combinational circuits composed of logic gates, and then combined into a miter circuit, that is, the inputs of the two circuits are connected to the same excitation signal source, and the outputs of the two circuits are connected to the same output terminal through XOR. The combinational circuit formed at clock cycle c is mapped to a CNF expression and sent to the SAT solver for solution, and the solver returns the result of whether it is satisfied. If the result is satisfied, it means that the two circuits are not equivalent in the c cycle, and vice versa. By summarizing the satisfaction results of each cycle, the equivalence of the two circuits within a certain cycle is determined. If there is a cycle within N cycles in which the two circuits are not equivalent, it means that the two circuits are not equivalent. Otherwise, it means that the two circuits are equivalent. By adopting the technical solution of the present invention, the conjunctive normal form formed by the miter combinational circuit formed by the two sequential logic circuits to be verified in a certain clock cycle, such as the initial clock cycle or the c clock cycle, can be used as the basic conjunctive normal form, and the incremental conjunctive normal form formed by the combinational circuit formed after the current clock cycle is calculated, and each incremental conjunctive normal form and the basic conjunctive normal form have partially identical clauses.

[0075] Specifically, the inputs of the two sequential circuits A and B to be verified must be synchronized in each clock cycle. Assume that there is a clock signal drive to ensure that the two circuits run on the same clock and accept the same input signal. Sequential circuits usually have registers or flip-flops to store internal states. When building the Miter circuit, it is assumed that the initial states of the two circuits A and B are the same. This means that at clock cycle 0, the values ​​of all registers or flip-flops of circuits A and B should be the same. At the end of each clock cycle, the outputs of circuits A and B are obtained respectively. An exclusive OR (XOR) operation is performed on these two outputs to generate a difference signal. If this signal is 0, it means that the outputs of circuits A and B are the same during this cycle; if it is 1, it means that they are not equivalent. With the given initial input and initial state, the internal register / flip-flop states of the two circuits A and B to be compared in a certain clock cycle c are also determined. By making the registers / flip-flops equivalent to new external inputs, the circuits A and B of the c cycle can be converted into combinational circuits represented purely by logic gates (AND, OR, NOT, XOR). Through Tseitin transformation, the combinational circuit represented by logic gates can be expressed as a CNF formula, which can be solved by the SAT solver. The CNF formulas converted by A and B in different clock cycles constitute a set of ordered CNF formulas. Usually, these formulas share the same parts, and the CNF formulas in the later clock cycles will increase or decrease based on the CNF formulas in the earlier clock cycles.

[0076] The solution search method for the incremental satisfiability problem provided by the embodiment of the present invention proposes an incremental SLS solution method for the incremental satisfiability problem in the process of integrated circuit equivalence verification, and constructs a set of conjunction normal forms according to the Miter circuits formed by two sequential logic circuits to be verified in each clock cycle. The conjunction normal forms in the conjunction normal form set are similar. When solving similar conjunction normal forms, a basic conjunction normal form is selected from them and the satisfying solution of the basic conjunction normal form is used as the basic solution. By calculating the incremental clauses of other conjunction normal forms relative to the basic conjunction normal form, when searching for solutions to other conjunction normal forms, the basic solution is removed according to the incremental clauses of the target conjunction normal form to be solved relative to the basic conjunction normal form. A fixed assumption is made on solution variables other than solution variables related to the incremental clause, that is, they are set to a fixed and non-flippable state, and the initial solution of the SLS algorithm is constructed by flipping other flippable solution variables in the basic solution to perform solution search. The present invention can effectively solve the shortcomings of the traditional CDCL algorithm and the SLS algorithm in the incremental solution scenario, so that when SLS is applied to solve the incremental satisfiability problem, the initial solution can be incrementally constructed according to the characteristics of the incremental problem itself for solution search, without having to completely reconstruct the problem, thereby reducing the solution time and storage space overhead, and quickly and efficiently verifying the equivalence of two sequential logic circuits, which has significant advantages in the verification problem of integrated circuits.

[0077] In an embodiment of the present invention, in the process of searching for a satisfactory solution of the target conjunction normal form according to the initial solution, when the preset first restart condition is met, the first initial solution after restart is constructed according to the preset initial solution reconstruction strategy, and the second initial solution after restart is constructed by continuously performing variable flipping on the flippable solution variables in the basic solution. The computational amount, i.e., the computational complexity, of searching for a solution of the target conjunction normal form using the first initial solution and the second initial solution is estimated, and the initial solution with low computational amount is selected as the initial solution after restart, and the target conjunction normal form is searched for a solution. Optionally, the preset first restart condition may be a Luby restart condition. Specifically, if the Luby restart condition is met, a new initial solution is reconstructed and the values ​​of all solution-related data structures are reset. Otherwise, an incremental solution method is adopted, i.e., the initial solution is constructed by performing variable flipping on the flippable solution variables in the basic solution, and the number of variables that need to be flipped is counted, and the complexity of searching for a solution by flipping the initial solution and reconstructing the initial solution is estimated. If the complexity of flipping is higher than that of reconstructing, the initial solution is reconstructed, otherwise it is constructed by flipping.

[0078] In an optional embodiment, the computational amount of searching for a solution to the target conjunctive normal form using the first initial solution and the second initial solution can be estimated in the following manner: the computational amount of the two solution methods is estimated based on the corresponding clause length, number of variables and / or ratio of variable values ​​when searching for a solution to the target conjunctive normal form using the first initial solution or the second initial solution.

[0079] Among them, Luby restart: is a restart strategy. In SLS, the Luby restart strategy is used to periodically reconstruct the initial solution, which can increase the probability of finding a satisfactory solution. The Luby restart strategy is a sequence, and the numbers in this sequence represent the interval between two restarts. The Luby sequence is given as:

[0080] S univer =(1,1,2,1,1,2,4,1,1,2,1,1,2,4,8,...);

[0081] Or in more formal form:

[0082] In this embodiment, the number of variables that need to be flipped refers to the calculation based on the initial solution, the text of the fixed assumption and the introduced random disturbance, which is a heuristic method;

[0083] Reconstruction and flip construction: If Reconstruction is selected, the construction is based on the initial solution. If Flip Construction is selected, the flip construction is performed with the variables in the initial solution that are not fixed as hypotheses.

[0084] The present invention can effectively solve the shortcomings of the traditional CDCL algorithm and the SLS algorithm in the incremental solution scenario, and can dynamically choose whether to construct and solve the problem in an incremental manner or to construct and solve it as a complete new problem according to the characteristics of the incremental problem itself, so as to speed up the implementation of the equivalence verification of sequential logic circuits.

[0085] Furthermore, the present invention can also monitor the iterative exit condition of the current solution search process; when the current solution search process does not reach the iterative exit condition, if the score value of the solution variable assignment found during the solution search process for the target conjunction normal form is higher than the score value of the historical best assignment, the current solution variable assignment is used as the best assignment, and the solution is continued; if a satisfying solution is found during the solution search process for the target conjunction normal form, the next target conjunction normal form to be solved in the conjunction normal form set is solved; otherwise, the flippable solution variable is continued to be selected to perform variable flipping to perform solution search for the target conjunction normal form, and the search result is returned as heuristic information to continue clause propagation and find conflicting clauses. In an optional embodiment, the iterative exit condition includes that the search time is greater than a preset time threshold and / or the memory space usage is greater than a preset memory space threshold.

[0086] In this embodiment, the iteration exit condition is used as the time and space range of the solution. When the time and space range of the solution is not exceeded, if the score of the current solution variable assignment is higher than the score of the current best assignment, then the current assignment is used as the best assignment; if a set of satisfactory solutions is found, it is returned, otherwise the variables that have not been fixed are selected for flipping, and information is collected for subsequent interaction. Specifically, according to a certain heuristic algorithm, one variable is selected from the unfixed variables for flipping. Such a heuristic algorithm will vary with the specific SLS algorithm. For example, in GSAT, the variable score will be used to decide which variable to flip, and the variable score is determined by the difference in the number of conflicting clauses generated after flipping the variable compared to before flipping.

[0087] The score of the solution can be obtained through a preset heuristic algorithm to determine whether the current solution is the current best solution. Collecting information refers to collecting the current solution status, including the selected variables, the current variable assignments, and the scores of each heuristic function.

[0088] The embodiment of the present invention also provides another method for searching for a solution to an incremental satisfiability problem. The method for searching for a solution to an incremental satisfiability problem proposed in the embodiment of the present invention implements a hybrid incremental solver, wherein the hybrid incremental solver includes an incremental SLS solver and an incremental hybrid solver, and the incremental hybrid solver includes a CDCL solver body and an auxiliary SLS solver. The method for searching for a solution to an incremental satisfiability problem in the embodiment of the present invention specifically includes the following steps not shown in the accompanying drawings:

[0089] S21. Obtain all clauses included in the target conjunction normal form to be solved in the conjunction normal form set.

[0090] S22. Perform clause propagation and find conflicting clauses.

[0091] S23. If no conflicting clauses are found during clause propagation, monitor whether the preset second restart condition is met. Among them, the second restart condition depends on the internal implementation of CDCL, and the selectable restart conditions include Luby, inner-outer, glucose style, etc. Among them, inner-outer restart: is a local-global restart strategy, that is, when performing a search task, the problem can be divided into local search and global search. According to this division, the search process can be restarted alternately in local search and global search, so as to find a satisfying solution faster and avoid consuming too much search time in a space without a solution. Glucose style: is an adaptive restart strategy based on machine learning (first appeared in the glucose solver).

[0092] S24. If the preset second restart condition is not met, a variable is selected and assigned a value to continue clause propagation and find conflicting clauses.

[0093] S25. Otherwise, whenever the preset second restart condition is met, determine whether a preset condition of the switching solver is met, where the condition of the switching solver is periodic switching.

[0094] S26. If the preset switching solver conditions are not met, the variable score is updated and the variable phase is reset. Among them, variable score: obtained by heuristic method, the variable score affects which variable is selected as the decision variable for search next time. The variable scoring methods that can be selected include VSIDS and LRB. Among them, VSIDS represents the variable state independent decay score. Each variable has a score. Whenever it is used as a branch variable or as a unit propagation variable, a fixed value is added and decayed at a fixed ratio in each round of search, so as to outline whether a variable has been frequently selected as a branch variable in the past. LRB represents the learning rate. The probability that a variable will lead to a learning clause is inferred through the variables appearing in the conflict clause, so that conflicts can be discovered earlier or it can be proved that the problem has no satisfactory solution. Phase reset: phase refers to whether a Boolean variable should be set to true or false. The phase has an important reference significance for the selection of variables to flip in SLS. Resetting the phase means clearing the value of a variable or setting the variable to its initial value.

[0095] S27, if the preset conditions for switching solvers are met, switch to the incremental SLS solver to execute the following steps: Figure 1 Steps S11 to S13 in the illustrated embodiment are performed until the incremental SLS solver finds a set of satisfiable solutions, returns the results, and exits the loop, or the incremental SLS solver fails to find a satisfactory solution, then after switching the solver, the incremental SLS solver search results are returned to the CDCL solver as heuristic information to continue clause propagation and search for conflicting clauses.

[0096] Furthermore, the method further comprises the following steps:

[0097] S28. If conflicting clauses are found during clause propagation, conflict analysis is performed to obtain the learned clauses and backtracking positions.

[0098] S29, adding the learned clause to the clause list and backtracking. The conflict analysis and backtracking after the conflicting clause is found are consistent with the classic CDCL algorithm, and will not be described in detail in the embodiment of the present invention.

[0099] S30. If a high-quality branch is obtained during the search process, the auxiliary SLS solver is called, and the SLS algorithm is used to reconstruct the initial solution of the SLS algorithm according to the high-quality branch, and the search sampling is performed in the corresponding search space according to the obtained initial solution, and the search results are returned as heuristic information to continue clause propagation and find conflicting clauses. High-quality branches (promising branches): When some assignments to variables are closer to satisfying the solution, they are called high-quality branches. The quality of branches can be scored by different heuristic functions. For example, for a variable set V and an assignment α based on it, If α is greater than a certain constant, we can judge that the assignment α is closer to a satisfying solution.

[0100] S31. If the learned clause obtained during the search process is a high-quality clause, the learned clause is added to the auxiliary SLS solver to help the auxiliary SLS solver find useful heuristic information faster. Among them, high-quality clause: a clause is a high-quality clause, which means that it is a tighter constraint. Prioritizing high-quality clauses can judge satisfiability and unsatisfiability faster than judging other clauses. The quality of a clause is generally measured by literal block distance (LBD). According to its definition, the literal block distance refers to the number of groupings of words based on the decision level of the variables corresponding to each word in the clause.

[0101] The solution search method for the incremental satisfiability problem provided by the embodiment of the present invention has the following advantages compared with the prior art:

[0102] 1. An incremental SLS solution method is proposed, so that when SLS is used to solve incremental problems, there is no need to completely reconstruct the problem, which reduces the time and storage space overhead of the solution, and quickly and efficiently verifies the equivalence of two sequential logic circuits, which has significant advantages in the verification of integrated circuits.

[0103] 2. In the process of incremental SLS solution, we can dynamically switch between partial construction and complete reconstruction of the initial solution, and dynamically choose the difference between the two according to their different solution costs.

[0104] 3. A hybrid solution method for incremental problems is proposed, which makes it possible to use the completeness of the CDCL algorithm to prove non-satisfaction, and to use the heuristic characteristics of SLS to find a satisfying solution more quickly, thereby quickly and efficiently verifying the equivalence of two sequential logic circuits.

[0105] 4. When solving incremental problems based on CDCL, an auxiliary SLS solver is introduced, which makes it possible to screen high-quality clauses for solving, thereby improving the speed of finding satisfying solutions and proving satisfiability, and then quickly and efficiently verifying the equivalence of two sequential logic circuits.

[0106] For the method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0107] In addition, an embodiment of the present invention also provides a solution search system for an incremental satisfiability problem. Figure 3 The following schematically shows the architecture of a system for searching for a solution to an incremental satisfiability problem according to an embodiment of the present invention. Figure 3 The incremental satisfiability problem solution search system of the embodiment of the present invention is used to implement the equivalence verification of sequential logic circuits, including:

[0108] An incremental SLS solver 30, wherein the incremental SLS solver 30 is configured to: map the Miter circuits formed by the two sequential logic circuits to be verified in each clock cycle into a conjunctive normal form respectively, select the conjunctive normal form corresponding to the Miter circuit formed in the specified clock cycle as the basic conjunctive normal form, and use the conjunctive normal forms corresponding to the Miter circuits formed in each clock cycle after the current specified clock cycle as incremental conjunctive normal forms, and calculate the incremental clauses of each incremental conjunctive normal form relative to the basic conjunctive normal form respectively, and the basic conjunctive normal form and the incremental conjunctive normal form constitute a conjunctive normal form set. Each incremental conjunctive normal form in the conjunctive normal form set has some identical clauses with the basic conjunctive normal form; a satisfied solution of the basic conjunctive normal form is taken as a basic solution, and when searching for solutions of the incremental conjunctive normal form in the conjunctive normal form set, according to the incremental clauses of the target conjunctive normal form to be solved in the conjunctive normal form set relative to the basic conjunctive normal form, the other solution variables in the basic solution except the solution variables related to the incremental clauses are set to a fixed and non-flippable state; the initial solution of the SLS algorithm is constructed by flipping the flippable solution variables in the basic solution, and the target conjunctive normal form is searched for solutions based on the initial solution, so as to realize the equivalence verification of the logic circuit according to the solution result.

[0109] In this embodiment, the Miter circuits formed by the two sequential logic circuits to be verified in each clock cycle are respectively mapped into a conjunctive normal form, specifically including: by reading the hardware description language files of the two sequential logic circuits to be verified, the two sequential logic circuits to be verified have the same number of circuit input terminals and the same number of circuit output terminals, according to the hardware description language files of the two sequential logic circuits to be verified, the two sequential logic circuits in each clock cycle are respectively represented as combinational circuits composed of logic gates, and a Miter circuit is constructed according to the combinational circuits corresponding to the two sequential logic circuits, and the Miter circuits formed in each clock cycle are respectively mapped into a conjunctive normal form in turn.

[0110] In this embodiment, the incremental SLS solver 30 is further configured to: in the process of searching for a satisfactory solution to the target conjunction normal form according to the initial solution, when the preset first restart condition is met, construct the first initial solution after restart according to the preset initial solution reconstruction strategy, and continue to construct the second initial solution after restart by flipping the flippable solution variables in the basic solution; estimate the computational amount of searching the target conjunction normal form using the first initial solution and the second initial solution, select the initial solution with low computational amount as the initial solution after restart, and use it to search the target conjunction normal form. Among them, estimating the computational amount of searching the target conjunction normal form using the first initial solution and the second initial solution includes: estimating the computational amount of the two solution methods according to the corresponding clause length, number of variables and / or variable value ratio when searching the target conjunction normal form using the first initial solution or the second initial solution.

[0111] In this embodiment, the incremental SLS solver 30 is also configured to: monitor the iterative exit condition of the current solution search process; when the current solution search process does not reach the iterative exit condition, if the score value of the solution variable assignment found in the solution search process for the target conjunction normal form is higher than the score value of the historical best assignment, the current solution variable assignment is used as the best assignment, and the solution is continued; if a satisfactory solution is found in the solution search process for the target conjunction normal form, the next target conjunction normal form to be solved in the conjunction normal form set is solved; otherwise, the flippable solution variable is continued to be selected to flip the variable to search for the solution of the target conjunction normal form. Among them, the iterative exit condition includes that the search time is greater than a preset time threshold and / or the memory space usage is greater than a preset memory space threshold.

[0112] Reference Figure 3The solution search system for the incremental satisfiability problem of the embodiment of the present invention also includes an incremental hybrid solver 40, which switches with the incremental SLS solver 30 periodically and records search information before switching, so as to continue to perform solution search according to the recorded search information after entering the next switching cycle; wherein the search information includes the scores of variables obtained by the CDCL solver, the phases of variables, and the search results returned by the incremental SLS solver as heuristic information of the CDCL solver.

[0113] The incremental hybrid solver 40 includes a CDCL solver body 401 and an auxiliary SLS solver 402, both of which maintain the same clause set. The CDCL solver body 401 is configured to: obtain all clauses included in the target conjunctive normal form to be solved in the conjunctive normal form set; perform clause propagation and find conflicting clauses. If no conflicting clauses are found during the clause propagation process, then whenever a preset second restart condition is met, determine whether the preset switching solver condition is met, and the switching solver condition is periodic switching; if the preset switching solver condition is met, switch to the incremental SLS solver 30; if the preset switching solver condition is not met, update the variable assignment score and reset the variable phase.

[0114] Optionally, the CDCL solver body 401 is further configured to: if conflicting clauses are found during clause propagation, conflict analysis is performed, learned clauses and backtracking positions are obtained, learned clauses are appended to the clause list, and backtracking is performed; if high-quality branches are obtained during the search process, the auxiliary SLS solver 402 reconstructs the initial solution of the SLS algorithm according to the high-quality branches, performs search sampling in the corresponding search space according to the obtained initial solution, and returns the search results as heuristic information to the CDCL solver body 401. Further, high-quality clauses are used to find solutions faster. If the learned clauses obtained by the CDCL solver body 401 during the search process are high-quality clauses, the learned clauses are added to the auxiliary SLS solver to help the auxiliary SLS solver find useful heuristic information faster. In this embodiment, the auxiliary SLS solver maintains the part of the high-quality clauses in the problem (sentence list / conjunctive normal form). The present invention helps to find a satisfying solution faster by sending high-quality clauses to the auxiliary SLS solver.

[0115] As for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment, and it has corresponding technical effects.

[0116] The solution search system for the incremental satisfiability problem proposed in the present invention includes two main modules, one is an incremental hybrid solver, and the other is an incremental SLS solver. The two solvers are switched regularly, so that the incremental SLS solver can be used to find a satisfying solution faster. In the incremental hybrid solver module, a CDCL solver body and an auxiliary SLS solver are included, and the two maintain the same set of clauses. During the solution process, the CDCL solver passes the clauses and initial solution information to the auxiliary SLS solver, and the auxiliary SLS solver returns the heuristic information to the CDCL solver, thereby helping the CDCL solver to find a satisfying solution faster, and then quickly and efficiently verify the equivalence of two sequential logic circuits.

[0117] In addition, an embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the solution search method for the incremental satisfiability problem are implemented as described above.

[0118] In this embodiment, if the solution search method for the incremental satisfiability problem is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction.

[0119] In addition, an embodiment of the present invention further provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned method for searching for a solution to the incremental satisfiability problem when executing the computer program. Figure 1 Alternatively, when the processor executes the computer program, the functions of each module / unit in the above-mentioned incremental satisfiability problem solution search system embodiment are realized, for example Figure 3 An incremental SLS solver 30 and an incremental hybrid solver 40 are shown.

[0120] The solution search method, system and computer device for the incremental satisfiability problem provided by the embodiment of the present invention realize the incremental solution algorithm based on SLS, and propose the incremental solution interface in the corresponding software implementation, so that when the hybrid algorithm is used for solution, it is not necessary to reconstruct the SLS solver for the complete problem, thereby greatly reducing the time and storage space overhead, and quickly and efficiently verifying the equivalence of two sequential logic circuits, which has significant advantages in the verification problem of integrated circuits. In addition, the present invention can also identify the computational overhead of reconstructing the problem and the incremental solution problem, so that the appropriate solution method can be dynamically selected, and finally the overall performance of the hybrid solution algorithm based on the incremental solution background is improved. The solution search method for the incremental satisfiability problem proposed in this application has a specific technical relationship with the internal structure of the computer system, improves the execution efficiency of the hardware in the solution search process, reduces the storage space overhead, and improves the internal performance of the computer system in the solution search process of the incremental satisfiability problem.

[0121] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, any one of the claimed embodiments may be used in any combination.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for searching for a solution to an incremental satisfiability problem, characterized in that: The method is used to implement equivalence verification of sequential logic circuits, and includes: The Miter circuits formed by the two sequential logic circuits to be verified in each clock cycle are respectively mapped into a conjunction normal form, the conjunction normal form corresponding to the Miter circuit formed in the specified clock cycle is selected as the basic conjunction normal form, and the conjunction normal forms corresponding to the Miter circuits formed in each clock cycle after the current specified clock cycle are all used as incremental conjunction normal forms, and the incremental clauses of each incremental conjunction normal form relative to the basic conjunction normal form are respectively calculated, and the basic conjunction normal form and the incremental conjunction normal form constitute a conjunction normal form set; each incremental conjunction normal form in the conjunction normal form set has some identical clauses with the basic conjunction normal form; Taking the satisfied solution of the basic conjunctive normal form as the basic solution, when searching for the solution of the incremental conjunctive normal form in the conjunctive normal form set, according to the incremental clause of the target conjunctive normal form to be solved in the conjunctive normal form set relative to the basic conjunctive normal form, setting the other solution variables in the basic solution except the solution variables related to the incremental clause to a fixed and non-reversible state; The initial solution of the SLS algorithm is constructed by flipping the flippable solution variables in the basic solution, and the target conjunction normal form is searched for a solution based on the initial solution, so as to realize the equivalence verification of the logic circuit according to the solution result.

2. The method according to claim 1, characterized in that The method further comprises: In the process of searching for a satisfactory solution of the target conjunction normal form according to the initial solution, when a preset first restart condition is met, a first initial solution after restart is constructed according to a preset initial solution reconstruction strategy, and a second initial solution after restart is constructed by continuously performing variable flipping on flippable solution variables in the basic solution; Estimate the computational cost of searching for a solution to the target conjunction normal form using the first initial solution and the second initial solution, select the initial solution with lower computational cost as the initial solution after restart, and use it to search for a solution to the target conjunction normal form.

3. The method according to claim 2, characterized in that The estimated computational amount of searching for a solution of the target conjunction normal form using the first initial solution and the second initial solution includes: The computational complexity of the two solution methods is estimated based on the corresponding clause length, number of variables and / or ratio of variable values ​​when the first initial solution or the second initial solution is used to search for a solution of the target conjunction normal form.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: Monitor the iterative exit conditions of the current solution search process; When the current solution search process does not meet the iteration exit condition, if the score value of the solution variable assignment found during the solution search for the target conjunctive normal form is higher than the score value of the historical best assignment, the current solution variable assignment is taken as the best assignment and the solution is continued; if a satisfying solution is found during the solution search for the target conjunctive normal form, the next target conjunctive normal form to be solved in the conjunctive normal form set is solved; otherwise, continue to select flippable solution variables to perform variable flipping to search for the target conjunctive normal form.

5. The method according to claim 4, characterized in that The iteration exit condition includes that the search time is greater than a preset time threshold and / or the memory space usage is greater than a preset memory space threshold.

6. The method according to claim 1, characterized in that Before selecting the conjunction normal form corresponding to the Miter circuit formed by the specified clock cycle as the basic conjunction normal form, the method further includes: Get all clauses included in the target conjunction normal form to be solved in the conjunction normal form set; Perform clause propagation and search for conflicting clauses. If no conflicting clauses are found during clause propagation, then whenever a preset second restart condition is met, determine whether a preset switching solver condition is met, wherein the switching solver condition is periodic switching. If the preset conditions for switching solvers are met, the incremental SLS solver is switched to solve the problem; If the preset conditions for switching solvers are not met, the scores of variable assignments are updated and the variable phases are reset.

7. The method according to claim 6, characterized in that The method further comprises: If conflicting clauses are found during clause propagation, conflict analysis is performed to obtain learned clauses and backtracking positions; Append the learned clause to the clause list and backtrack; If high-quality branches are obtained during the search process, the SLS algorithm is used to reconstruct the initial solution of the SLS algorithm based on the high-quality branches, and search sampling is performed in the corresponding search space based on the obtained initial solution. The search results are returned as heuristic information to continue clause propagation and find conflicting clauses.

8. A solution search system for an incremental satisfiability problem, characterized in that: The system is used to implement equivalence verification of sequential logic circuits, and includes: An incremental SLS solver, wherein the incremental SLS solver is configured to: map the Miter circuits formed by the two sequential logic circuits to be verified in each clock cycle into a conjunction normal form respectively, select the conjunction normal form corresponding to the Miter circuit formed in the specified clock cycle as the basic conjunction normal form, and use the conjunction normal forms corresponding to the Miter circuits formed in each clock cycle after the current specified clock cycle as incremental conjunction normal forms, and respectively calculate the incremental clauses of each incremental conjunction normal form relative to the basic conjunction normal form, wherein the basic conjunction normal form and the incremental conjunction normal form constitute a conjunction normal form set; each in the conjunction normal form set An incremental conjunctive normal form has some identical clauses with a basic conjunctive normal form; a satisfied solution of the basic conjunctive normal form is taken as a basic solution, and when searching for solutions of the incremental conjunctive normal form in the conjunctive normal form set, according to the incremental clauses of the target conjunctive normal form to be solved in the conjunctive normal form set relative to the basic conjunctive normal form, the other solution variables in the basic solution except the solution variables related to the incremental clauses are set to a fixed and non-flippable state; the initial solution of the SLS algorithm is constructed by flipping the flippable solution variables in the basic solution, and the target conjunctive normal form is searched for solutions based on the initial solution, so as to realize the equivalence verification of the logic circuit according to the solution result.

9. The system according to claim 8, characterized in that The system also includes an incremental hybrid solver, which periodically switches with the incremental SLS solver and records search information before switching, so as to continue to perform solution search according to the recorded search information after entering the next switching cycle; The incremental hybrid solver includes a CDCL solver body and an auxiliary SLS solver, both of which maintain the same clause set. The CDCL solver body is configured to: obtain all clauses included in the target conjunction normal form to be solved in the conjunction normal form set; perform clause propagation and find conflicting clauses. If no conflicting clauses are found during the clause propagation process, then whenever a preset second restart condition is met, determine whether a preset switching solver condition is met, and the switching solver condition is periodic switching; if the preset switching solver condition is met, switch to the incremental SLS solver. If the preset conditions for switching solvers are not met, the variable assignment scores are updated and the variable phases are reset; if conflicting clauses are found during clause propagation, conflict analysis is performed to obtain learned clauses and backtracking positions, the learned clauses are appended to the clause list, and backtracking is performed. If high-quality branches are obtained during the search process, the auxiliary SLS solver reconstructs the initial solution of the SLS algorithm based on the high-quality branches, searches and samples in the corresponding search space based on the obtained initial solution, and returns the search results as heuristic information to the CDCL solver body.

10. A computer device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to any one of claims 1 to 7 when executing the computer program.

Images