Layout generation method and device, nonvolatile storage medium and electronic equipment

Abstract

The invention discloses a layout generation method and device, a nonvolatile storage medium and electronic equipment. The method comprises the steps that an initial layout is acquired, and the initial layout comprises a plurality of first circles corresponding to through silicon vias; a preset silicon column diameter is determined, the first circles are grouped according to the preset silicon column diameter and the distance between each first circle and the adjacent first circle, a plurality of silicon through hole groups are obtained, and each silicon through hole group comprises one first circle or a plurality of first circles with the interval not larger than the preset silicon column diameter; for each silicon through hole group, the silicon column outer contour of the silicon column corresponding to the silicon through hole group is determined according to each first circle corresponding to the silicon through hole group, and each silicon through hole group corresponds to one silicon column; and generating an embedded cavity layout corresponding to the initial layout according to the initial layout and the outer contour of the silicon column. The technical problems of low adjustment efficiency and low accuracy caused by manual adjustment of the outer contour of the silicon column corresponding to the overlapping area in the related technology are solved.

Description

Technical Field

[0001] The present application relates to the field of chip design, and more specifically, to a layout generation method, device, non-volatile storage medium and electronic device. Background Art

[0002] In the current related technology, when generating a layout of an embedded liquid metal silicon substrate, the circle corresponding to the through-silicon via (TSV) in the initial layout is usually directly expanded to a circle with a diameter of the preset silicon column diameter, thereby obtaining the outline of the silicon column. However, the problem with this method is that for TSVs with close spacing, there will be overlapping areas between the expanded circles. At this time, the staff needs to manually adjust the outer contour of the silicon column corresponding to the overlapping area to avoid affecting the heat dissipation efficiency. However, the manual adjustment method has low adjustment efficiency and the accuracy cannot be guaranteed.

[0003] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present application provide a layout generation method, device, non-volatile storage medium and electronic device to at least solve the technical problem of low adjustment efficiency and low accuracy caused by manually adjusting the outer contour of the silicon pillar corresponding to the overlapping area in the related art.

[0005] According to one aspect of an embodiment of the present application, a layout generation method is provided, comprising: obtaining an initial layout, wherein the initial layout includes a plurality of first circles corresponding to through silicon vias; determining a preset silicon column diameter, and grouping the first circles according to the preset silicon column diameter and the distance between each first circle and an adjacent first circle to obtain a plurality of through silicon via groups, wherein each through silicon via group includes a first circle, or a plurality of first circles with a spacing not greater than the preset silicon column diameter; for each through silicon via group, determining the silicon column outer contour of the silicon column corresponding to the through silicon via group according to each first circle corresponding to the through silicon via group, wherein each through silicon via group corresponds to a silicon column; and generating an embedded cavity layout corresponding to the initial layout according to the initial layout and the silicon column outer contour.

[0006] Optionally, determining the outer contour of the silicon column of the silicon column corresponding to the silicon via group based on each first circle corresponding to the silicon via group includes: when the silicon via group contains a first circle, expanding the first circle into a second circle, wherein the second circle and the first circle have the same center and the diameter of the second circle is a preset silicon column diameter; and determining the second circle as the outer contour of the silicon column.

[0007] Optionally, determining the outer contour of the silicon column of the silicon column corresponding to the silicon via group based on each first circle corresponding to the silicon via group includes: when the silicon via group contains two first circles, expanding the two first circles into second circles respectively, wherein the second circle and the first circle have the same center, and the diameter of the second circle is a preset silicon column diameter; determining two common tangents between the two second circles; and determining the outer contour of the silicon column based on the two second circles and the two common tangents, wherein the coverage range of the outer contour of the silicon column includes the two second circles.

[0008] Optionally, the outer contour of the silicon column is composed of two common tangent lines and target arcs respectively extracted from the second circle, wherein two end points of the target arcs are respectively connected to the common tangent lines.

[0009] Optionally, determining the outer contour of the silicon column of the silicon column corresponding to the silicon via group based on each first circle corresponding to the silicon via group includes: when the silicon via group contains three or more first circles, constructing a convex hull based on the center of each first circle, wherein the center of each first circle is located inside the convex hull or in the edge of the convex hull; and determining the outer contour of the silicon column based on the target center located in the edge of the convex hull.

[0010] Optionally, determining the outer contour of the silicon pillar based on the target circle center located in the edge of the convex hull includes: determining a second circle corresponding to each target circle center, wherein the center of the second circle is the target circle center, and the diameter of the second circle is a preset silicon pillar diameter; determining a common tangent line between each adjacent second circle; determining the outer contour of the silicon pillar based on the common tangent line and the second circle, wherein the coverage range of the outer contour of the silicon pillar includes each second circle.

[0011] Optionally, generating an embedded cavity layout corresponding to the initial layout based on the initial layout and the silicon pillar outer contour includes: replacing a first circle in the initial layout with a silicon pillar outer contour corresponding to a silicon through via group where the first circle is located, to obtain the embedded cavity layout.

[0012] According to another aspect of an embodiment of the present application, a layout generation device is also provided, including: a first processing module, used to obtain an initial layout, wherein the initial layout includes multiple first circles corresponding to silicon vias; a second processing module, used to determine a preset silicon column diameter, and group the first circles according to the preset silicon column diameter and the distance between each first circle and an adjacent first circle to obtain multiple silicon via groups, wherein each silicon via group includes one first circle, or multiple first circles with a spacing not greater than the preset silicon column diameter; a third processing module, used to determine, for each silicon via group, the silicon column outer contour of the silicon column corresponding to the silicon via group according to each first circle corresponding to the silicon via group, wherein each silicon via group corresponds to a silicon column; and a fourth processing module, used to generate an embedded cavity layout corresponding to the initial layout according to the initial layout and the silicon column outer contour.

[0013] According to another aspect of an embodiment of the present application, a non-volatile storage medium is provided, in which a program is stored, wherein when the program is running, a device where the non-volatile storage medium is located is controlled to execute a layout generation method.

[0014] According to another aspect of an embodiment of the present application, there is also provided an electronic device, including a memory and a processor, wherein the processor is used to run a program stored in the memory, and the layout generation method is executed when the program is run.

[0015] According to another aspect of an embodiment of the present application, a computer program product is also provided, including a computer program, and the computer program implements the layout generation method when executed by a processor.

[0016] In an embodiment of the present application, an initial layout is obtained, wherein the initial layout includes a plurality of first circles corresponding to through silicon vias; a preset silicon column diameter is determined, and the first circles are grouped according to the preset silicon column diameter and the distance between each first circle and an adjacent first circle to obtain a plurality of through silicon via groups, wherein each through silicon via group includes a first circle, or a plurality of first circles with a spacing not greater than the preset silicon column diameter; for each through silicon via group, a silicon column outer contour of a silicon column corresponding to the through silicon via group is determined according to each first circle corresponding to the through silicon via group, wherein each through silicon via group corresponds to a silicon column ; The embedded cavity layout corresponding to the initial layout is generated based on the initial layout and the outer contour of the silicon pillar. The first circles corresponding to each silicon via are grouped according to the spacing, and the outer contour of the silicon pillar corresponding to each silicon via group is determined according to the corresponding first circles. The purpose of automatically generating the outer contour of the silicon pillar while considering the spacing is achieved, thereby achieving the technical effect of improving the generation efficiency and accuracy of the embedded cavity layout, and further solving the technical problem of low adjustment efficiency and low accuracy caused by manually adjusting the outer contour of the silicon pillar corresponding to the overlapping area in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 It is a structural schematic diagram of a computer terminal (mobile terminal) provided according to an embodiment of the present application;

[0019] Figure 2 It is a flow chart of a layout generation method provided according to an embodiment of the present application;

[0020] Figure 3 It is a flowchart of a grouping process provided according to an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of the outer contour of a silicon column provided according to an embodiment of the present application;

[0022] Figure 5 It is a schematic diagram of a convex hull construction process provided according to an embodiment of the present application;

[0023] Figure 6 is a schematic diagram of another outer profile of a silicon column provided according to an embodiment of the present application;

[0024] Figure 7 It is a schematic diagram of a process for generating a silicon column outer profile according to an embodiment of the present application;

[0025] Figure 8 is a schematic diagram of an initial layout provided according to an embodiment of the present application;

[0026] Fig. 9 is a schematic diagram of an embedded cavity layout provided according to an embodiment of the present application;

[0027] Fig.10 is a schematic diagram of another initial layout provided according to an embodiment of the present application;

[0028] Fig.11 is a schematic diagram of another embedded cavity layout provided according to an embodiment of the present application;

[0029] Fig.12 is a CT image of an embedded cavity provided according to an embodiment of the present application;

[0030] Fig.13 is a CT image of another embedded cavity provided according to an embodiment of the present application;

[0031] Fig.14 It is a structural schematic diagram of a layout generation device provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] At present, the integration density of transistors in chips has increased rapidly, resulting in an increasingly significant heat accumulation effect caused by leakage current in the gate area of ​​transistors in chips, and the working reliability of chips is extremely sensitive to temperature. For every 1°C increase in the safe working temperature, its reliability will decrease by about 5%. The heat dissipation path in the integrated circuit chip packaging structure is mainly to diffuse the local high heat generated in the small area of ​​the chip gate area to the substrate through the thermal interface material, and then to the tube shell, and then dissipate the heat into the atmosphere through thermal management technologies such as air cooling and water cooling outside the tube shell. However, these traditional thermal management technologies are each limited by the shortcomings of low heat dissipation efficiency and difficulty in miniaturization of structures, which are difficult to meet the efficient heat dissipation requirements of the new generation of chips. For this reason, the concept of near-junction heat dissipation is proposed in the relevant technology, and the relevant heat dissipation technology has gradually become the mainstream technical solution to solve the heat dissipation needs. The so-called near-junction heat dissipation is to miniaturize various heat dissipation structures and embed them in the electronic chip packaging structure, and use the embedded heat dissipation structure to bring the liquid cooling medium close to the heating gate area of ​​the electronic chip (with a spacing less than 100μm) to achieve precise control of the junction temperature.

[0035] The embedded liquid metal through-silicon via (TSV) adapter board is a near-junction heat dissipation structure. An embedded cavity is designed in the adapter board layer, and the TSV is wrapped around with silicon pillars to separate the TSV from the liquid metal, so that an embedded cavity filled with liquid metal is formed at the boundary of the silicon pillar and the adapter board to improve the heat transfer efficiency.

[0036] However, the layout automation technology in related technologies mainly uses functions such as automatic component generation and automatic layout and routing, and is suitable for PCB layout drawing, gate-level circuit layout drawing and other fields. For the layout design of embedded liquid metal TSV adapter boards, which requires TSV-based graphical design technology, the existing automation technology is not applicable.

[0037] Therefore, the existing layout design of embedded liquid metal silicon substrates lacks corresponding automation technology. The number of TSVs contained in the silicon substrate is large and densely distributed. Without the use of automation technology, manual layout drawing will lead to defects such as high time cost and high error rate.

[0038] And if the diameter of TSV is directly expanded to the required diameter of silicon column, then the distance between TSV is smaller than the diameter of silicon column, and the silicon column graphics will intersect after expansion, and the intersecting parts need to be manually eliminated to retain the outer contour. In addition, the angle of the intersecting circles is not conducive to the flow of liquid metal, so it will also affect the heat transfer performance of the adapter plate.

[0039] In order to solve the above problems, relevant solutions are provided in the embodiments of the present application, which are described in detail below.

[0040] According to an embodiment of the present application, a method embodiment of a layout generation method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0041] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Figure 1 FIG. 1 shows a hardware structure block diagram of a computer terminal (or mobile device) for implementing a layout generation method. Figure 1 As shown, the computer terminal 10 (or mobile device 10) may include one or more (102a, 102b, ..., 102n are used to illustrate) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 104 for storing data, and a transmission device 106 for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the BUS bus), a network interface, a power supply and / or a camera. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above electronic device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0042] It should be noted that the one or more processors 102 and / or other data processing circuits described above may generally be referred to herein as "data processing circuits". The data processing circuits may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. In addition, the data processing circuit may be a single independent processing module, or may be incorporated in whole or in part into any of the other components in the computer terminal 10 (or mobile device). As described in the embodiments of the present application, the data processing circuit acts as a processor control (e.g., selection of a variable resistor terminal path connected to an interface).

[0043] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the layout generation method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, the above-mentioned layout generation method is realized. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal 10 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0044] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0045] The display may be, for example, a touch screen liquid crystal display (LCD) that enables a user to interact with a user interface of the computer terminal 10 (or mobile device).

[0046] In the above operating environment, the present application embodiment provides a layout generation method, such as Figure 2 As shown, the method comprises the following steps:

[0047] Step S202, obtaining an initial layout, wherein the initial layout includes a plurality of first circles corresponding to through silicon vias;

[0048] In the technical solution provided in step S202, the radii of each first circle are the same.

[0049] Step S204, determining a preset silicon pillar diameter, and grouping the first circles according to the preset silicon pillar diameter and the distance between each first circle and an adjacent first circle to obtain a plurality of through silicon via groups, wherein each through silicon via group includes one first circle, or a plurality of first circles whose spacing is not greater than the preset silicon pillar diameter;

[0050] In the technical solution provided in step S204, the process of grouping each first circle is as follows: Figure 3 As shown, the following steps are included:

[0051] Step S302, collecting circular objects;

[0052] Optionally, in the step of collecting circular objects, the initial layout is traversed to determine all first circles in the initial layout, as well as position information and size information of each first circle, to facilitate subsequent grouping of each first circle.

[0053] Step S304, determining the grouping criteria;

[0054] Optionally, in the step of determining the grouping criteria, it is necessary to determine the preset silicon column diameter input by the user or preset, and determine the grouping criteria based on the preset silicon column diameter. For example, two adjacent first circles whose spacing is not greater than the preset silicon column diameter are determined as a group. And the first circles whose spacings with each adjacent first circle are greater than the preset silicon column diameter are individually grouped.

[0055] Step S306, traversing each first circle and grouping each first circle according to the grouping standard until all the first circles are traversed.

[0056] Optionally, the spacing between each first circle and an adjacent first circle may be determined according to the position information and size information of each first circle, and then the TSV group to which each first circle belongs may be determined according to a grouping standard.

[0057] Step S206, for each TSV group, determining the silicon pillar outer contour of the silicon pillar corresponding to the TSV group according to each first circle corresponding to the TSV group, wherein each TSV group corresponds to one silicon pillar;

[0058] In the technical solution provided in step S206, the step of determining the outer contour of the silicon column of the silicon column corresponding to the silicon via group based on each first circle corresponding to the silicon via group includes: when the silicon via group contains a first circle, expanding the first circle into a second circle, wherein the second circle and the first circle have the same center, and the diameter of the second circle is a preset silicon column diameter; and determining the second circle as the outer contour of the silicon column.

[0059] As an optional embodiment, the step of determining the outer contour of the silicon column of the silicon column corresponding to the silicon via group based on the first circles corresponding to the silicon via group includes: when the silicon via group contains two first circles, expanding the two first circles into second circles respectively, wherein the second circle and the first circle have the same center and the diameter of the second circle is a preset silicon column diameter; determining two common tangents between the two second circles; and determining the outer contour of the silicon column based on the two second circles and the two common tangents, wherein the coverage range of the outer contour of the silicon column includes the two second circles.

[0060] In some embodiments of the present application, the outer contour of the silicon column is composed of two common tangent lines and target arcs respectively extracted from the second circle, wherein two end points of the target arcs are respectively connected to the common tangent lines.

[0061] Optionally, when the through silicon via group corresponds to two first circles, the second circles corresponding to the two first circles are as follows: Figure 4 As shown on the left, the outer contour of the silicon pillar corresponding to the silicon via group is as follows Figure 4 As shown on the right. Figure 4 It can be seen that the target arc is an arc that does not intersect with another second circle. At this time, the outer contour of the silicon column corresponding to the silicon via group is similar to a capsule. In this way, the angle formed by the intersection of the two second circles can be corrected to the common tangent of the two second circles, thereby solving the problem that the heat transfer performance of the adapter plate is affected because the angle is not conducive to the flow of liquid metal.

[0062] As an optional embodiment, the step of determining the outer contour of the silicon column of the silicon column corresponding to the silicon via group based on the first circles corresponding to the silicon via group includes: when the silicon via group contains three or more first circles, constructing a convex hull based on the center of each first circle, wherein the center of each first circle is located inside the convex hull or in the edge of the convex hull; and determining the outer contour of the silicon column based on the target center located in the edge of the convex hull.

[0063] In some embodiments of the present application, the convex hull construction process is as follows: Figure 5 As shown, the following steps are included:

[0064] Step S502, check whether the number of points is ≥ 3;

[0065] The number of points checked in step S502 refers to the number of centers of the first circles in the TSV group.

[0066] Step S504, sorting the centers of circles in the through silicon via group;

[0067] Optionally, a target circle center for constructing the convex hull may be determined during the sorting process, wherein the target circle center is the center of the circle located outside;

[0068] Step S506, constructing an upper convex hull and a lower convex hull respectively according to the center of the target circle;

[0069] Step S508: merge the upper convex hull and the lower convex hull.

[0070] In some embodiments of the present application, the step of determining the outer contour of the silicon pillar based on the target circle center located in the edge of the convex hull includes: determining a second circle corresponding to each target circle center, wherein the center of the second circle is the target circle center, and the diameter of the second circle is a preset silicon pillar diameter; determining a common tangent line between each adjacent second circle; determining the outer contour of the silicon pillar based on the common tangent line and the second circle, wherein the coverage range of the outer contour of the silicon pillar includes each second circle.

[0071] Optionally, when the number of first circles corresponding to the through silicon via group is three, the second circles corresponding to the first circles are as follows: Figure 6 As shown on the left, the outer contour of the silicon pillar corresponding to the silicon via group is as follows Figure 6 Shown on the right.

[0072] Through the above method, it is possible to automatically perform different circle expansion behaviors on silicon via groups with different numbers of TSVs, so as to obtain the outer contour of the silicon column corresponding to each silicon via group. Specifically, if a single TSV is a group, the diameter of the TSV is directly expanded to the input silicon column diameter to generate a second circle, and this second circle is the generated silicon column. If two TSVs are a group, first expand the diameter of the first circle corresponding to the TSV to the input silicon column diameter to generate two new second circles, and then generate the common tangents of the two circles and only retain the outer contour of the figure. This outer contour is the generated silicon column outer contour. After establishing the convex hull, for three or more TSVs, each point constituting the convex hull is used as the center of the circle to generate a second circle with a diameter of the silicon column diameter, and then respectively generate the common tangents between the circles and retain the outer contour of the figure. This outer contour is the generated silicon column outer contour.

[0073] In some embodiments of the present application, there is also provided a Figure 7 The process of generating the outer contour of the silicon pillar shown includes the following steps:

[0074] Step S702, determining the user selection range in the initial layout;

[0075] Step S704, filtering the first circle in the user-selected range;

[0076] Optionally, the screening object is a first circle whose spacing with an adjacent first circle is not greater than a preset silicon column diameter;

[0077] Step S706, grouping the screened first circular shapes to obtain a plurality of through silicon via groups, and determining the outer contours of silicon pillars corresponding to each through silicon via group;

[0078] Step S708, generating a graphic object corresponding to the outer contour of the silicon pillar, and adding the newly generated graphic object to the database.

[0079] Step S208, generating an embedded cavity layout corresponding to the initial layout according to the initial layout and the outer contour of the silicon pillar.

[0080] In the technical solution provided in step S208, generating an embedded cavity layout corresponding to the initial layout based on the initial layout and the outer contour of the silicon pillar includes: replacing the first circle in the initial layout with the outer contour of the silicon pillar corresponding to the silicon through via group where the first circle is located to obtain the embedded cavity layout.

[0081] In some embodiments of the present application, Figure 8 is a schematic diagram of an initial layout of a single CPU computing unit provided according to an embodiment of the present application, Fig. 9 Schematic diagram of the embedded cavity layout corresponding to the initial layout of the single CPU computing unit provided in the embodiment of the present application. Fig. 9 On the left is the 2D embedded cavity layout of the single CPU computing unit TSV adapter board. Fig. 9 The middle is the main view of the 3D embedded cavity layout of the single CPU computing unit TSV adapter board corresponding to the initial layout. Fig. 9 The right side is a side view of the 3D embedded cavity layout of the single CPU computing unit TSV adapter board corresponding to the initial layout. Among them, the single CPU computing unit TSV adapter board is an electronic component mainly used in the fields of high-performance computing and data transmission.

[0082] In some embodiments of the present application, Fig.10 is a schematic diagram of an initial layout of a single-band T / R subarray provided according to an embodiment of the present application, Fig.11 Schematic diagram of the embedded cavity layout corresponding to the initial layout of the single-band T / R subarray provided in the embodiment of the present application. Fig.11 On the left is the 2D embedded cavity layout of the TSV adapter board for the single-band T / R subarray. Fig.11 In the middle is the main view of the 3D embedded cavity layout of the TSV adapter board for the single-band T / R subarray.

[0083] Fig.11On the right is a side view of the 3D embedded cavity layout of the TSV adapter board for the single-band T / R subarray. The T / R subarray is a key component in the phased array radar system, used to transmit and receive signals. The T / R subarray consists of multiple T / R modules, each of which contains a transmitter and a receiver. The TSV adapter board for the single-band T / R subarray is an intermediate layer that connects the single-band T / R subarray with the TSV packaged chip, and realizes vertical and horizontal transmission of signals through TSV technology. This adapter board helps to increase signal transmission speed and reduce power consumption, and is a key component of modern microwave and RF systems.

[0084] After obtaining the embedded cavity layout, etching and bonding can be performed according to the embedded cavity layout to obtain the required TSV adapter board. Then, industrial CT can be used to detect the embedded cavity in the TSV adapter board, and the following can be obtained: Fig.12 and 13 CT image of the embedded cavity shown. Fig.12 This is a CT scan of a single CPU computing unit TSV adapter board. Fig.13 CT scan of the TSV adapter board of a single-band T / R subarray.

[0085] The invention adopts the method of obtaining an initial layout, wherein the initial layout includes a plurality of first circles corresponding to through silicon vias; determining a preset silicon column diameter, and grouping the first circles according to the preset silicon column diameter and the distance between each first circle and an adjacent first circle, to obtain a plurality of through silicon via groups, wherein each through silicon via group includes one first circle, or a plurality of first circles with a spacing not greater than the preset silicon column diameter; for each through silicon via group, determining the silicon column outer contour of the silicon column corresponding to the through silicon via group according to each first circle corresponding to the through silicon via group, wherein each through silicon via group corresponds to one silicon column; generating an embedded cavity layout corresponding to the initial layout according to the initial layout and the silicon column outer contour, by grouping the first circles corresponding to each through silicon via according to the spacing, and determining the silicon column outer contour corresponding to each through silicon via group according to each first circle corresponding to the through silicon via group, the purpose of automatically generating the silicon column outer contour in consideration of the spacing is achieved, thereby realizing the technical effect of improving the generation efficiency and accuracy of the embedded cavity layout, and further solving the technical problem of low adjustment efficiency and low accuracy due to manual adjustment of the silicon column outer contour corresponding to the overlapping area in the related art.

[0086] The embodiment of the present application also provides an automatic design and generation software for an embedded cavity plate. The software can be a .NET software implemented based on the AutoCAD API, and its programming language can be any existing programming language such as C# language, which is not limited by the embodiment of the present application. The software can efficiently process complex embedded cavity silicon column designs, which can significantly shorten the design cycle, reduce the design time and labor costs, reduce the possibility of design errors, and improve the manufacturability and yield rate of the embedded liquid metal TSV adapter plate. And according to different input parameters, multiple design schemes can be quickly generated to quickly adapt to design requirements, further expanding the application scope of the embedded liquid metal TSV adapter plate in various chips.

[0087] The present application embodiment provides a layout generation device, Fig.14 is a schematic diagram of the structure of the device. Fig.14 It can be seen that the device includes: a first processing module 140, used to obtain an initial layout, wherein the initial layout includes a plurality of first circles corresponding to silicon vias; a second processing module 142, used to determine a preset silicon column diameter, and group the first circles according to the preset silicon column diameter and the distance between each first circle and the adjacent first circle to obtain a plurality of silicon via groups, wherein each of the silicon via groups includes one first circle, or a plurality of first circles with a spacing not greater than the preset silicon column diameter; a third processing module 144, used to determine, for each of the silicon via groups, the silicon column outer contour of the silicon column corresponding to the silicon via group according to each of the first circles corresponding to the silicon via group, wherein each of the silicon via groups corresponds to one silicon column; a fourth processing module 146, used to generate an embedded cavity layout corresponding to the initial layout according to the initial layout and the silicon column outer contour.

[0088] In some embodiments of the present application, the step in which the third processing module 144 determines the outer contour of the silicon column of the silicon column corresponding to the silicon via group based on the first circles corresponding to the silicon via group includes: when the silicon via group contains a first circle, expanding the first circle into a second circle, wherein the second circle and the first circle have the same center and the diameter of the second circle is a preset silicon column diameter; and determining the second circle as the outer contour of the silicon column.

[0089] In some embodiments of the present application, the step of the third processing module 144 determining the outer contour of the silicon column of the silicon column corresponding to the silicon via group based on the first circles corresponding to the silicon via group includes: in the case where the silicon via group contains two first circles, respectively expanding the two first circles into second circles, wherein the second circle and the first circle have the same center, and the diameter of the second circle is a preset silicon column diameter; determining two common tangents between the two second circles; determining the outer contour of the silicon column based on the two second circles and the two common tangents, wherein the coverage range of the outer contour of the silicon column includes the two second circles.

[0090] In some embodiments of the present application, the outer contour of the silicon column is composed of two common tangent lines and target arcs respectively extracted from the second circle, wherein two end points of the target arcs are respectively connected to the common tangent lines.

[0091] In some embodiments of the present application, the step of the third processing module 144 determining the outer contour of the silicon column of the silicon column corresponding to the silicon via group based on the first circles corresponding to the silicon via group includes: when the silicon via group contains three or more first circles, constructing a convex hull based on the center of each first circle, wherein the center of each first circle is located inside the convex hull or in the edge of the convex hull; determining the outer contour of the silicon column based on the target center located in the edge of the convex hull.

[0092] In some embodiments of the present application, the step in which the third processing module 144 determines the outer contour of the silicon pillar based on the target circle center located in the edge of the convex hull includes: determining a second circle corresponding to each target circle center, wherein the center of the second circle is the target circle center, and the diameter of the second circle is a preset silicon pillar diameter; determining a common tangent line between each adjacent second circle; determining the outer contour of the silicon pillar based on the common tangent line and the second circle, wherein the coverage range of the outer contour of the silicon pillar includes each second circle.

[0093] In some embodiments of the present application, the step of the fourth processing module 146 generating an embedded cavity layout corresponding to the initial layout based on the initial layout and the outer contour of the silicon pillar includes: replacing the first circle in the initial layout with the outer contour of the silicon pillar corresponding to the silicon through hole group where the first circle is located, to obtain the embedded cavity layout.

[0094] It should be noted that the various modules in the above-mentioned layout generation device can be program modules (for example, a set of program instructions that implement a certain specific function) or hardware modules. For the latter, it can be expressed in the following forms, but is not limited to this: the expression form of each of the above-mentioned modules is a processor, or the functions of each of the above-mentioned modules are implemented by a processor.

[0095] According to an embodiment of the present application, a non-volatile storage medium is also provided, in which a program is stored, wherein when the program is running, the device where the non-volatile storage medium is located is controlled to execute the following layout generation method: obtaining an initial layout, wherein the initial layout includes multiple first circles corresponding to silicon vias; determining a preset silicon column diameter, and grouping the first circles according to the preset silicon column diameter and the distance between each first circle and an adjacent first circle to obtain multiple silicon via groups, wherein each silicon via group includes one first circle, or multiple first circles with a spacing not greater than the preset silicon column diameter; for each silicon via group, determining the silicon column outer contour of the silicon column corresponding to the silicon via group according to each first circle corresponding to the silicon via group, wherein each silicon via group corresponds to one silicon column; generating an embedded cavity layout corresponding to the initial layout according to the initial layout and the silicon column outer contour.

[0096] According to an embodiment of the present application, there is also provided an electronic device, comprising a memory and a processor, the processor being used to run a program stored in the memory, and the following layout generation method being executed when the program is run: obtaining an initial layout, wherein the initial layout includes a plurality of first circles corresponding to through silicon vias; determining a preset silicon column diameter, and grouping the first circles according to the preset silicon column diameter and the distance between each first circle and an adjacent first circle to obtain a plurality of through silicon via groups, wherein each through silicon via group includes a first circle, or a plurality of first circles with a spacing not greater than the preset silicon column diameter; for each through silicon via group, determining the silicon column outer contour of the silicon column corresponding to the through silicon via group according to each first circle corresponding to the through silicon via group, wherein each through silicon via group corresponds to a silicon column; and generating an embedded cavity layout corresponding to the initial layout according to the initial layout and the silicon column outer contour.

[0097] According to an embodiment of the present application, a computer program product is also provided, including a computer program, which implements the following layout generation method when executed by a processor: obtaining an initial layout, wherein the initial layout includes multiple first circles corresponding to silicon vias; determining a preset silicon column diameter, and grouping the first circles according to the preset silicon column diameter and the distance between each first circle and an adjacent first circle to obtain multiple silicon via groups, wherein each silicon via group includes one first circle, or multiple first circles with a spacing not greater than the preset silicon column diameter; for each silicon via group, determining the silicon column outer contour of the silicon column corresponding to the silicon via group according to each first circle corresponding to the silicon via group, wherein each silicon via group corresponds to one silicon column; generating an embedded cavity layout corresponding to the initial layout according to the initial layout and the silicon column outer contour.

[0098] In some embodiments of the present application, the above-mentioned computer program product may be .NET software implemented based on AutoCAD API, and its programming language may be any existing programming language such as C# language, and the embodiments of the present application do not impose any limitation on this.

[0099] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0100] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0101] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0102] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0103] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), mobile hard disk, disk or optical disk, etc. Various media that can store program codes.

[0104] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A layout generation method, characterized in that: include: Acquire an initial layout, wherein the initial layout includes a plurality of first circles corresponding to through silicon vias; Determine a preset silicon column diameter, and group the first circles according to the preset silicon column diameter and the distance between each first circle and an adjacent first circle to obtain a plurality of through silicon via groups, wherein each of the through silicon via groups includes one first circle, or a plurality of first circles whose spacing is not greater than the preset silicon column diameter; For each of the through silicon via groups, determining the outer contour of the silicon column corresponding to the through silicon via group according to each of the first circles corresponding to the through silicon via group, wherein each of the through silicon via groups corresponds to one silicon column; An embedded cavity layout corresponding to the initial layout is generated according to the initial layout and the outer contour of the silicon pillar.

2. The layout generation method according to claim 1, characterized in that: Determining the outer contour of the silicon column corresponding to the through silicon via group according to each of the first circles corresponding to the through silicon via group includes: In the case where the through silicon via group includes one of the first circles, the first circle is expanded into a second circle, wherein the second circle has the same center as the first circle, and the diameter of the second circle is the preset silicon column diameter; The second circle is determined to be the outer contour of the silicon column.

3. The layout generation method according to claim 1, characterized in that: Determining the outer contour of the silicon column corresponding to the through silicon via group according to each of the first circles corresponding to the through silicon via group includes: In the case where the through silicon via group includes two of the first circles, the two first circles are respectively expanded into second circles, wherein the second circle and the first circle have the same center, and the diameter of the second circle is the preset silicon column diameter; determining two common tangent lines between two of said second circles; The outer contour of the silicon column is determined according to the two second circles and the two common tangent lines, wherein the coverage of the outer contour of the silicon column includes the two second circles.

4. The layout generation method according to claim 3, characterized in that: The outer contour of the silicon column is composed of the two common tangent lines and target arcs respectively extracted from the second circle, wherein two end points of the target arcs are respectively connected to the common tangent lines.

5. The layout generation method according to claim 1, characterized in that: Determining the outer contour of the silicon column corresponding to the through silicon via group according to each of the first circles corresponding to the through silicon via group includes: When the through silicon via group includes three or more first circles, a convex hull is constructed according to the center of each of the first circles, wherein the center of each of the first circles is located inside the convex hull or on the edge of the convex hull; The outer contour of the silicon pillar is determined according to a target circle center located in the edge of the convex hull.

6. The layout generation method according to claim 5, characterized in that: Determining the outer contour of the silicon pillar according to the target circle center located in the edge of the convex hull includes: Determine a second circle corresponding to each of the target circle centers, wherein the center of the second circle is the target circle center, and the diameter of the second circle is the preset silicon column diameter; Determining a common tangent line between adjacent second circles; The outer contour of the silicon pillar is determined according to the common tangent line and the second circle, wherein the coverage of the outer contour of the silicon pillar includes each of the second circles.

7. The layout generation method according to claim 1, characterized in that: Generating an embedded cavity layout corresponding to the initial layout according to the initial layout and the outer contour of the silicon pillar includes: The first circle in the initial layout is replaced by the outer contour of the silicon column corresponding to the through silicon via group where the first circle is located, to obtain the embedded cavity layout.

8. A layout generation device, characterized in that: include: A first processing module is used to obtain an initial layout, wherein the initial layout includes a plurality of first circles corresponding to through silicon vias; a second processing module, configured to determine a preset silicon column diameter, and group the first circles according to the preset silicon column diameter and the distance between each first circle and an adjacent first circle, to obtain a plurality of through silicon via groups, wherein each of the through silicon via groups includes one first circle, or a plurality of first circles whose spacing is not greater than the preset silicon column diameter; A third processing module is configured to determine, for each of the through silicon via groups, the outer contour of the silicon pillar corresponding to the through silicon via group according to each of the first circles corresponding to the through silicon via group, wherein each of the through silicon via groups corresponds to one silicon pillar; The fourth processing module is used to generate an embedded cavity layout corresponding to the initial layout according to the initial layout and the outer contour of the silicon pillar.

9. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a program, wherein when the program is executed, the device where the non-volatile storage medium is located is controlled to execute the layout generation method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: A memory and a processor, wherein the processor is used to run a program stored in the memory, wherein the layout generation method described in any one of claims 1 to 7 is executed when the program is run.

11. A computer program product, characterized in that The invention comprises a computer program, which implements the layout generation method according to any one of claims 1 to 7 when being executed by a processor.

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