Layout method and device of input / output module of chip, equipment and medium

Abstract

The embodiment of the invention provides a layout method and device for an input / output module of a chip, equipment and a medium. The method comprises the following steps: acquiring an initial total area and a schematic circuit diagram of the input / output module; dividing the input / output module into a plurality of sub-regions according to the initial total area, and determining an initial sub-area corresponding to each sub-region; performing iterative optimization on the initial sub-area of each sub-area according to the schematic circuit diagram, and determining a target sub-area corresponding to each sub-area; according to the target sub-area corresponding to each sub-area, determining a corresponding sub-area layout; and merging the plurality of optimized sub-regions to obtain a target layout of the input / output module. According to the embodiment of the invention, the input / output module is divided into the plurality of sub-regions, and the layout of the input / output module is optimized by optimizing the areas of the plurality of sub-regions, so that the unnecessary space occupation area is reduced, the manufacturing cost of a chip is reduced, and the market competitiveness is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a layout method for an input / output module of a chip and a layout device for an input / output module of a chip. Background Art

[0002] In chip design and the semiconductor industry, input / output modules are essential components for chips to communicate with the outside world. They are responsible for data transmission, reception, and exchange of control signals, and their performance directly affects the efficiency and reliability of the entire system. The area optimization of input / output modules plays a vital role in reducing manufacturing costs, improving integration, and product competitiveness. However, in the traditional layout design of input / output modules, in order to avoid the latch effect, the distance between the two parts is often pulled far, resulting in low space utilization and unnecessary cost increase. Summary of the invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a layout method, device, apparatus and medium for an input / output module of a chip that overcomes the above problems or at least partially solves the above problems.

[0004] According to a first aspect of an embodiment of the present invention, a method for laying out an input / output module of a chip is provided, the method comprising:

[0005] Get the initial total area and circuit schematics of the input / output module;

[0006] Dividing the input / output module into a plurality of sub-areas according to the initial total area, and determining an initial sub-area corresponding to each sub-area;

[0007] Iteratively optimize the initial sub-area of ​​each sub-area according to the circuit schematic to determine the target sub-area corresponding to each sub-area;

[0008] Determine the corresponding sub-region layout according to the target sub-area corresponding to each sub-region;

[0009] The optimized multiple sub-regions are merged to obtain the target layout of the input / output module.

[0010] Optionally, the iterative optimization of the initial sub-area of ​​each sub-region according to the circuit schematic includes:

[0011] According to the simulated annealing algorithm, determine the current temperature value and the cooling step length;

[0012] Lowering the current temperature value according to the cooling step length;

[0013] After the current temperature value decreases, adjusting the device layout in each sub-area according to the circuit schematic;

[0014] Calculating the device layout area in the sub-region after each adjustment so that the device layout area in the sub-region after each adjustment is smaller than the area of ​​the previous adjustment; the number of times the device layout in the sub-region is adjusted is equal to the number of times the current temperature value is reduced;

[0015] When the preset conditions are met, the iterative optimization stops.

[0016] Optionally, stopping the iterative optimization when a preset condition is met includes:

[0017] According to the simulated annealing algorithm, determine the temperature reduction coefficient and the termination temperature value;

[0018] Determine the area difference between the sub-region area before adjustment and the sub-region area after adjustment;

[0019] When the area difference is less than a preset threshold, the iterative optimization is stopped, or

[0020] When the area difference is greater than or equal to a preset threshold, the product of the current new temperature value and the temperature reduction coefficient is calculated, and the iterative optimization is stopped when the product is less than or equal to the termination temperature value.

[0021] Optionally, adjusting the device layout in each sub-region according to the circuit schematic diagram includes:

[0022] Get design rules;

[0023] The input / output pin layout of the devices in each sub-area is adjusted according to the circuit schematic and the design rule.

[0024] Optionally, the design rule includes: a device distance between two sub-regions is greater than a minimum safety distance for a latch effect to occur.

[0025] Optionally, merging the optimized multiple sub-areas to determine the target layout of the input / output module includes:

[0026] Protective devices are respectively arranged around the optimized multiple sub-areas;

[0027] Isolating each sub-area according to the protection device;

[0028] The sub-regions surrounding the protection device are merged to determine a target layout of the input / output module, and the target layout complies with the design rules.

[0029] Optionally, the plurality of sub-regions include: an N-channel metal oxide semiconductor field effect transistor region, a P-channel metal oxide semiconductor field effect transistor region, a resistor region, a P-type electrostatic discharge protection device region and an N-type electrostatic discharge protection device region.

[0030] According to a second aspect of an embodiment of the present invention, a layout device for an input / output module of a chip is provided, the device comprising:

[0031] A first acquisition module, used to acquire an initial total area and a circuit schematic diagram of an input / output module;

[0032] A first determining module, configured to divide the input / output module into a plurality of sub-areas according to the initial total area, and determine an initial sub-area corresponding to each sub-area;

[0033] A second determination module is used to iteratively optimize the initial sub-area of ​​each sub-area according to the circuit schematic diagram to determine the target sub-area corresponding to each sub-area;

[0034] A third determination module is used to determine the corresponding sub-region layout according to the target sub-area corresponding to each sub-region;

[0035] The first merging module is used to merge the optimized multiple sub-regions to obtain the target layout of the input / output module.

[0036] Optionally, the second determining module includes:

[0037] The first determination submodule is used to determine the current temperature value and the cooling step length according to the simulated annealing algorithm;

[0038] A first temperature reduction submodule, configured to reduce the current temperature value according to the temperature reduction step length;

[0039] A first adjustment submodule, configured to adjust the device layout in each sub-area according to the circuit schematic after the current temperature value decreases;

[0040] A first calculation submodule is used to calculate the device layout area in the sub-region after each adjustment, so that the device layout area in the sub-region after each adjustment is smaller than the previous area; the number of times the device layout in the sub-region is adjusted is equal to the number of times the current temperature value is reduced;

[0041] The first stopping submodule is used to stop the iterative optimization when a preset condition is met.

[0042] Optionally, the first stopping submodule includes:

[0043] A first determining unit, used to determine a temperature reduction coefficient and a termination temperature value according to the simulated annealing algorithm;

[0044] A second determining unit, used to determine an area difference between the area of ​​the sub-region before adjustment and the area of ​​the sub-region after adjustment;

[0045] a first stopping unit, configured to stop the iterative optimization when the area difference is less than a preset threshold, or

[0046] When the area difference is greater than or equal to a preset threshold, the product of the current new temperature value and the temperature reduction coefficient is calculated, and the iterative optimization is stopped when the product is less than or equal to the termination temperature value.

[0047] Optionally, the first adjustment submodule includes:

[0048] A first acquisition unit, used for acquiring design rules;

[0049] The first adjustment unit is used to adjust the input / output pin layout of the devices in each sub-area according to the circuit schematic and the design rule.

[0050] Optionally, the design rule includes: a device distance between two sub-regions is greater than a minimum safety distance for a latch effect to occur.

[0051] Optionally, the first merging module includes:

[0052] A first setting submodule is used to respectively set protection devices around the optimized multiple sub-areas;

[0053] A first isolation submodule, used to isolate each sub-area according to the protection device;

[0054] The first merging submodule is used to merge the sub-regions surrounding the protection device to obtain the target layout of the input / output module, and make the target layout comply with the design rules.

[0055] Optionally, the plurality of sub-regions include: an N-channel metal oxide semiconductor field effect transistor region, a P-channel metal oxide semiconductor field effect transistor region, a resistor region, a P-type electrostatic discharge protection device region and an N-type electrostatic discharge protection device region.

[0056] According to a third aspect of the present invention, there is provided an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the method for laying out the input / output module of the chip as described in any one of the above items are implemented.

[0057] According to a fourth aspect of the present invention, there is provided a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the steps of the method for laying out the input / output module of a chip as described in any one of the above items are implemented.

[0058] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:

[0059] The embodiment of the present invention provides a layout method for the input / output module of a chip, which obtains the initial total area and circuit schematic diagram of the input / output module; divides the input / output module into multiple sub-areas according to the initial total area, and determines the initial sub-area corresponding to each sub-area; iteratively optimizes the initial sub-area of ​​each sub-area according to the circuit schematic diagram, and determines the target sub-area corresponding to each sub-area; determines the corresponding sub-area layout according to the target sub-area corresponding to each sub-area; and merges the optimized multiple sub-areas to obtain the target layout of the input / output module. The embodiment of the present invention divides the input / output module into multiple sub-areas, and optimizes the layout of the input / output module by optimizing the areas of the multiple sub-areas, so as to reduce unnecessary space occupation area, and also reduces the manufacturing cost of the chip and improves market competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 It is a flowchart of the steps of a layout method of an input / output module of a chip provided by an embodiment of the present invention;

[0061] Figure 2 It is a structural block diagram of a layout device for an input / output module of a chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0062] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0063] One of the core concepts of the embodiments of the present invention is to divide the input / output module into multiple sub-areas, and optimize the layout of the input / output module by optimizing the areas of the multiple sub-areas to reduce unnecessary space occupation, thereby reducing the manufacturing cost of the chip and improving market competitiveness.

[0064] Reference Figure 1 , shows a flowchart of a layout method of an input / output module of a chip provided by an embodiment of the present invention, and the method may specifically include the following steps:

[0065] Step 101, obtaining the initial total area and circuit schematic diagram of the input / output module;

[0066] First, determining the initial total area of ​​the input / output module is to evaluate the available space resources. The input / output modules are usually located at the edge of the chip because they need to communicate directly with the outside world. Knowing the specific dimensions of these areas helps plan how to use the limited silicon area most effectively. Reasonable space allocation can avoid unnecessary waste and ensure that all necessary input / output pins can be properly placed. In addition, information on the total area also helps predict manufacturing costs, because the chip area is directly related to production costs, and smaller chips mean lower costs and higher yields. Secondly, obtaining the circuit schematic is the basis for understanding the internal logical structure of the input / output module. The schematic describes in detail how the various subsystems are connected and the signal flow path, which is crucial to achieving efficient physical layout. By analyzing the schematic, designers can identify critical signal paths, power networks, and other factors that have a significant impact on performance. This allows targeted measures to be taken during the layout stage to reduce the impact of delays, noise, and other adverse factors.

[0067] Step 102, dividing the input / output module into a plurality of sub-areas according to the initial total area, and determining an initial sub-area corresponding to each sub-area;

[0068] The plurality of sub-regions include: an N-channel metal oxide semiconductor field effect transistor region, a P-channel metal oxide semiconductor field effect transistor region, a resistor region, a P-type electrostatic discharge protection device region, and an N-type electrostatic discharge protection device region.

[0069] By dividing the input / output module into multiple sub-regions with specific functions, such as the N-channel MOSFET region, the P-channel MOSFET region, the resistor region, the P-type ESD protection device region, and the N-type ESD protection device, more refined design and management can be achieved. This division enables the components in each sub-region to be optimally laid out according to their unique electrical characteristics and physical requirements, avoiding problems that may be caused by mixing different types of components together, such as signal interference or poor heat dissipation. And the determination of the initial sub-area of ​​each sub-region is based on a comprehensive evaluation and planning of the entire input / output module. This step ensures that the proportional relationship between the various sub-regions is reasonable, meeting both functional requirements and taking into account space utilization. For example, the N-channel MOSFET and P-channel MOSFET regions usually require a larger area to support high current handling capabilities, while the resistors, P-type ESD protection devices, and N-type ESD protection devices can be flexibly adjusted in size according to specific application scenarios. In this way, designers can minimize unnecessary space occupation without affecting functionality, thereby reducing the overall size and manufacturing cost of the chip.

[0070] Specifically, the N-type ESD protection device area can be placed at the bottom, because the source end of the N-type ESD protection device needs to be connected to the ground, and the periphery of the chip is the ground. Taking into account the principle of nearby wiring, it can be directly connected to the ground. Above the N-type ESD protection device area is the P-type ESD protection device area. Considering that their drain ends need to be connected together with the drain ends of the N-type ESD protection device, and the ESD protection device needs to be away from the control circuit in the middle, the P-type ESD protection device is placed in this position. Above the P-type ESD protection device area is the resistor area. Since the resistor is a passive device, it will not have a latching effect with the ESD protection device. If the resistor is not placed in this area, the area needs to be enlarged to keep other devices away from the P-type ESD protection device, so the resistor will be placed here. Above the resistor area is the P-channel metal oxide semiconductor field effect transistor area. Since the P-channel metal oxide semiconductor field effect transistor and the P-type ESD protection device are both P-type tubes, the same type will not have a latching effect, so the P-channel metal oxide semiconductor field effect transistor will be placed in this area. The height of the P-channel MOSFET device is effectively utilized to save area. If an N-channel MOSFET is placed, the distance between the N-channel MOSFET and the P-type electrostatic discharge protection device needs to meet the latch effect, which will increase the area. The N-channel MOSFET region is set above the P-channel MOSFET region.

[0071] In addition, it can also include capacitor area, diode array area, analog circuit area, clock buffer and driver area, interface protocol logic area, power management unit area, thermistor or temperature sensor area, etc. The capacitor area is used to stabilize the power supply voltage, reduce noise, and provide transient current; the diode array area is used to implement various protection functions, such as overvoltage protection, reverse bias protection, etc.; the analog circuit area can contain multiple analog circuit elements; the clock buffer and driver area is used to distribute and strengthen the clock signal to ensure accurate synchronization across the chip; the interface protocol logic area is used to implement the control logic and state machine required for a specific communication protocol; the power management unit area is responsible for the distribution and management of power; the thermistor or temperature sensor area is used to monitor the chip temperature to prevent overheating damage.

[0072] Step 103, iteratively optimizing the initial sub-area of ​​each sub-area according to the circuit schematic diagram, and determining the target sub-area corresponding to each sub-area;

[0073] Through iterative optimization, it is possible to ensure that the components in each sub-area are optimally configured according to their unique electrical characteristics and physical requirements, avoiding problems that may be caused by mixing different types of components together, such as signal interference or poor heat dissipation. For critical signal paths, such as high-speed data lines and clock lines, iterative optimization can minimize path length, reduce delays and noise, and improve signal integrity. By making multiple adjustments to the initial sub-areas of each sub-area, it is possible to minimize unnecessary space occupation without affecting functionality, thereby reducing the overall size and manufacturing cost of the chip.

[0074] Step 104, determining the corresponding sub-region layout according to the target sub-area corresponding to each sub-region;

[0075] By determining the target sub-area, the electrical characteristics and physical requirements in each sub-area can be accurately matched. Layout optimization based on the target sub-area can significantly improve space utilization. Through multiple iterative adjustments, unnecessary space occupation can be reduced as much as possible without affecting the function, reducing the overall size and manufacturing cost of the chip. The compact layout not only saves silicon resources, but also simplifies the wiring complexity, making chip design simpler and accelerating product time to market. In addition, the optimized layout helps to improve production yield, reduce the impact of parasitic effects and other adverse factors, thereby reducing manufacturing risks and costs. And a reasonable target sub-area helps improve thermal management and electromagnetic compatibility. Sub-areas with high power consumption should be properly distributed to avoid local overheating and ensure uniform heat distribution. By optimizing the heat dissipation channel, the impact of excessive temperature on device life and reliability can be effectively prevented. At the same time, a reasonable layout also helps to reduce electromagnetic radiation and anti-interference, especially in situations involving high-frequency signals, which can significantly improve the stability and market competitiveness of the product.

[0076] Step 105: merge the optimized multiple sub-regions to obtain the target layout of the input / output module.

[0077] By merging multiple optimized sub-areas, it is possible to ensure that the various functional areas can work together seamlessly to form an efficient overall system. Each sub-area has been individually optimized to maximize its specific functional performance. However, when these sub-areas are considered in isolation, the interactions between them may be overlooked. Therefore, merging the optimized sub-areas can ensure consistency and collaboration between all functional components, avoid potential conflicts or redundancies, and improve the overall performance of the system. In addition, merging the optimized sub-areas helps to achieve a compact and efficient physical layout. Individually optimized sub-areas may have certain limitations in space utilization, but by merging, the relative positions between the sub-areas can be more flexibly adjusted, reducing unnecessary blank space and wiring length. Furthermore, merging the optimized sub-areas provides greater flexibility and adaptability. Different application scenarios and technical specifications may require different configurations, and merging based on optimized sub-areas allows designers to flexibly adjust the design to ensure that the final product can adapt to various market needs. With the advancement of technology and changes in market demand, this method based on merging optimized sub-areas can also provide a solid foundation for future upgrades and improvements.

[0078] In one embodiment, step 103 may include the following sub-steps:

[0079] Sub-step S11, determining the current temperature value and the cooling step length according to the simulated annealing algorithm;

[0080] Sub-step S12, lowering the current temperature value according to the cooling step length;

[0081] Sub-step S13, after the current temperature value decreases, adjusting the device layout in each sub-area according to the circuit schematic;

[0082] The simulated annealing algorithm provides a systematic optimization framework that allows designers to start from an initial configuration and gradually improve the layout solution through a series of iterations. In this process, "temperature" is a key parameter that determines the degree of exploration of the search space. The high temperature stage allows large random changes, allowing the algorithm to explore different possibilities extensively; as the temperature gradually decreases, the amplitude of the changes decreases, and finally converges to a more ideal layout solution. This gradual optimization method helps to avoid premature convergence to a suboptimal solution and find a better overall layout. Determining the current temperature value and the cooling step size is one of the core steps of the simulated annealing algorithm. The initial temperature is usually set high to ensure sufficient exploration; and the cooling step size determines the speed at which the temperature decreases at each iteration. A reasonable cooling strategy is crucial to the success of the algorithm: if the temperature is cooled too quickly, it may cause the algorithm to converge too early and lose the opportunity for further optimization; conversely, cooling too slowly will increase the computing time and reduce efficiency. Therefore, choosing an appropriate cooling step size requires comprehensive consideration of factors such as problem complexity, expected optimization effect, and computing resources.

[0083] Adjusting the device layout in each sub-area according to the circuit schematic after each temperature decrease is a key step in turning theory into practice. This process involves consideration of specific electrical characteristics and physical requirements, such as signal path length, power distribution, thermal management, etc. By continuously adjusting the layout, signal integrity can be gradually optimized, parasitic effects can be reduced, heat dissipation efficiency can be improved, and coordination between functional areas can be ensured. In addition, the effect of the new layout can be evaluated after each adjustment, such as performance indicators, power consumption levels, etc., so as to adjust the optimization direction in a timely manner.

[0084] In one embodiment, the sub-step S13 may include the following sub-steps:

[0085] Sub-step S131, obtaining design rules; the design rules include: the device distance between the two sub-regions is greater than the minimum safety distance for the latch effect to occur.

[0086] Sub-step S132, adjusting the input / output pin layout of the devices in each sub-area according to the circuit schematic and the design rule.

[0087] Design rules provide basic safety and technical guidance for chip layout. In particular, the provisions that the distance between devices in two sub-areas is greater than the minimum safe distance for latch-up effects are intended to prevent catastrophic failures caused by the conduction of parasitic bipolar transistors. Latch-up effects may cause current to flow through the device uncontrollably, thereby permanently damaging the chip. By ensuring sufficient spacing, this risk can be effectively avoided and the long-term stable operation of the chip can be guaranteed. In addition, design rules also cover other requirements such as wiring width, interlayer connections, power and ground networks, etc. to ensure the feasibility and reliability of the manufacturing process. Pin layout adjustments based on circuit schematics are to achieve optimal functional configuration and signal path optimization. The circuit schematic describes in detail the connection methods between various subsystems and the signal flow paths, which is essential for achieving efficient physical layout. By analyzing the schematics, designers can identify critical signal paths, power networks, and other factors that have a significant impact on performance, and take targeted measures to reduce the impact of delays, noise, and other adverse factors. For example, high-speed signal lines should be as short as possible and away from power lines to reduce interference; while power and ground lines need to be carefully arranged to ensure stable power supply and good grounding.

[0088] Reasonable pin layout can improve signal integrity and electromagnetic compatibility, reduce electromagnetic radiation and immunity, especially when high-frequency signals are involved. Sub-areas with high power consumption should be properly distributed to avoid local overheating, ensure uniform heat distribution, and optimize heat dissipation channels. The optimized pin layout can reduce wiring complexity, make chip design simpler, speed up product launch time, improve production yield, and reduce manufacturing costs. In addition to adjusting the input / output pin layout of devices in each sub-area, it is also possible to merge the common ends of the devices, optimize the relative positions between devices, wiring paths, and the distribution of power and ground networks.

[0089] Sub-step S14, calculating the device layout area in the sub-region after each adjustment, so that the device layout area in the sub-region after each adjustment is smaller than the area of ​​the previous adjustment; the number of times the device layout in the sub-region is adjusted is equal to the number of times the current temperature value is reduced;

[0090] Sub-step S15, when the preset conditions are met, stop the iterative optimization.

[0091] Calculating the device layout area in each adjusted sub-region and ensuring that it decreases is a key measure to ensure that the optimization process moves in the right direction. This practice helps avoid capricious or ineffective adjustments during the optimization process and ensures that each iteration can bring substantial improvements. As the temperature value gradually decreases, each adjustment should reduce unnecessary space occupation without sacrificing functionality, thereby achieving a more compact layout. This not only reduces the overall size of the chip, but also simplifies the wiring complexity, reduces the impact of parasitic effects and other unfavorable factors, and ultimately improves production yield and cost-effectiveness. And setting the number of device layout adjustments to equal the number of times the current temperature value is reduced is an important feature of the simulated annealing algorithm. This setting ensures that each temperature stage has enough time for exploration and optimization, but does not excessively extend the calculation time. The initial high temperature stage allows large random changes, allowing the algorithm to explore different possibilities extensively; as the temperature gradually decreases, the amplitude of the changes decreases, and finally converges to a more ideal layout solution. A reasonable cooling strategy is crucial to finding the global optimal solution, and linking the number of adjustments to temperature changes ensures the systematic and effective nature of this process.

[0092] Stopping iterative optimization when preset conditions are met is a guarantee mechanism to ensure that the optimization process is both thorough and efficient. Preset conditions can be based on a variety of factors, such as achieving predetermined performance indicators, area reduction ratios, and the upper limit of the number of iterations. When these conditions are met, it indicates that the optimization has achieved the expected goals, and the marginal benefits of continuing iterations may be limited. Therefore, timely termination of optimization can not only save computing resources, but also speed up the time to market. In addition, clear stopping conditions can also help improve the predictability and controllability of the design process, ensuring that the project proceeds as planned.

[0093] In one embodiment, the sub-step S15 may include the following sub-steps:

[0094] Sub-step S151, determining a temperature reduction coefficient and a termination temperature value according to the simulated annealing algorithm;

[0095] Sub-step S152, determining the area difference between the sub-region area before adjustment and the sub-region area after adjustment;

[0096] Sub-step S153, when the area difference is less than a preset threshold, stop the iterative optimization; or, when the area difference is greater than or equal to the preset threshold, calculate the product of the current new temperature value and the cooling coefficient, and stop the iterative optimization when the product is less than or equal to the termination temperature value.

[0097] The simulated annealing algorithm provides a systematic optimization framework that allows designers to start from an initial configuration and gradually improve the layout solution through a series of iterations. In this process, "temperature" is a key parameter that determines the degree of exploration of the search space. The high temperature stage allows large random changes, allowing the algorithm to explore different possibilities extensively; as the temperature gradually decreases, the amplitude of the change decreases, and finally converges to a more ideal layout solution. Reasonable setting of the cooling coefficient and the termination temperature value can control the speed and accuracy of the optimization process, ensuring that the best solution is found within a limited time.

[0098] Determine the area difference between the sub-region area before adjustment and the sub-region area after adjustment as an important evaluation indicator in the optimization process. After each iteration, calculating the area difference can help determine whether the current adjustment has brought substantial improvements. When the area difference is less than the preset threshold, it means that there is limited room for further optimization. Stopping the iteration at this time can avoid unnecessary waste of calculations. On the contrary, if the area difference is greater than or equal to the preset threshold, it indicates that there is still optimization potential and iterations should continue. When the area difference is greater than or equal to the preset threshold, calculate the product of the current new temperature value and the cooling coefficient, and decide whether to stop the iteration based on whether the product is less than or equal to the termination temperature value. This dynamic adjustment mechanism ensures that the optimization process will neither converge prematurely nor continue indefinitely. In this way, the optimization can be terminated in a timely manner while ensuring sufficient exploration, thereby improving efficiency.

[0099] In one embodiment, step 105 may include the following sub-steps:

[0100] Sub-step S21, respectively setting protection devices around the optimized multiple sub-areas;

[0101] Sub-step S22, isolating each sub-area according to the protection device;

[0102] Sub-step S23, merging the sub-regions surrounding the protection device to determine a target layout of the input / output module, and making the target layout comply with the design rule.

[0103] First, setting up protection devices around each sub-area can effectively prevent external interference and transient voltage from damaging the internal circuit. For example, protection devices can quickly respond to electrostatic discharge events, discharge overvoltage to the ground, and avoid damage to sensitive components. Decoupling capacitors help stabilize the power supply voltage, reduce noise, and improve signal integrity. In this way, protection devices provide an additional safety barrier for each sub-area and enhance the reliability of the system. Secondly, using protection devices to isolate each sub-area can not only avoid mutual interference between different functional areas, but also simplify wiring and thermal management. Different types of sub-areas have different electrical characteristics and working conditions, and there may be parasitic effects or thermal effects on each other. Through isolation, it is possible to ensure that each sub-area operates independently, reduce unnecessary interactions, and improve overall performance. In addition, reasonable isolation also helps to reduce electromagnetic radiation and anti-interference, especially in high-frequency signal processing situations, which is crucial to the stability and market competitiveness of the product.

[0104] For example, the protection device can be a guard ring, which is usually made of highly doped P-type or N-type silicon material, depending on the type of active area to be protected. It prevents parasitic effects, edge effects, and external interference from affecting these areas. By surrounding the guard ring, it can provide an effective shielding mechanism to ensure the stability and reliability of the internal circuit. Latch-up effect refers to the phenomenon of continuous large current flow caused by the accidental turn-on of parasitic bipolar transistors in the circuit, which may cause permanent damage to the chip. The guard ring avoids this catastrophic failure by providing a low impedance path to guide the current that may cause latch-up effect. It effectively confines the high electric field within the guard ring and prevents it from spreading to sensitive active areas. At the edge of the silicon wafer, the electric field strength is high, which can easily cause problems such as increased leakage current or reduced breakdown voltage. The guard ring can effectively shield these edge effects and improve the breakdown voltage and reliability of the device. By surrounding the active area, it makes the electric field distribution more uniform, reduces the electric field concentration at the edge, and thus reduces the risk of local overheating and breakdown.

[0105] Guard rings can also increase the breakdown voltage of the device, especially in high-voltage applications. By adjusting the doping concentration and width of the guard ring, the breakdown voltage can be significantly increased without affecting the performance of the device. This not only enhances the voltage resistance of the device, but also improves the reliability and safety of the overall system. There are often some undesirable parasitic effects in semiconductor devices, such as parasitic bipolar transistors, parasitic capacitance, etc. The guard ring can effectively suppress these parasitic effects through physical isolation, ensuring that the signal transmission in the active area is purer and more stable. This is especially important for high-speed digital circuits and analog circuits because they are very sensitive to noise and interference. The guard ring can also play a certain electromagnetic shielding role, reducing the impact of external electromagnetic interference on the internal circuit. This is especially important for high-frequency circuits and wireless communication equipment because it can improve signal integrity and noise immunity, ensuring that the system works normally in a complex electromagnetic environment.

[0106] Merging sub-regions surrounded by protection devices to determine the target layout is a key step in achieving a compact and efficient design. The optimized sub-regions have taken into account factors such as functional requirements, space utilization, and thermal management, and the presence of protection devices further ensures the safety and independence of each sub-region. During the merging process, designers can adjust the relative positions of each sub-region according to actual needs to ensure the shortest signal path and the simplest wiring while meeting the heat dissipation requirements. This approach not only reduces the overall size and manufacturing cost of the chip, but also improves production yield and reduces the impact of parasitic effects and other adverse factors. Finally, making the target layout strictly comply with the design rules is the basis for ensuring manufacturing feasibility and long-term stable operation. The design rules cover requirements from wiring width, inter-layer connection to minimum safety distance to ensure accuracy and reliability during the manufacturing process. For example, the device distance between two sub-regions must be greater than the minimum safety distance for latch-up effect to prevent current from flowing through the device uncontrollably. By ensuring that the target layout meets all design rules, potential manufacturing problems can be avoided and the quality and performance of the chip can be guaranteed.

[0107] The embodiment of the present invention provides a layout method for the input / output module of a chip, which obtains the initial total area and circuit schematic diagram of the input / output module; divides the input / output module into multiple sub-areas according to the initial total area, and determines the initial sub-area corresponding to each sub-area; iteratively optimizes the initial sub-area of ​​each sub-area according to the circuit schematic diagram, and determines the target sub-area corresponding to each sub-area; determines the corresponding sub-area layout according to the target sub-area corresponding to each sub-area; and merges the optimized multiple sub-areas to obtain the target layout of the input / output module. The embodiment of the present invention divides the input / output module into multiple sub-areas, and optimizes the layout of the input / output module by optimizing the areas of the multiple sub-areas, so as to reduce unnecessary space occupation area, and also reduces the manufacturing cost of the chip and improves market competitiveness.

[0108] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0109] Reference Figure 2 , shows a structural block diagram of a layout device for an input / output module of a chip provided by an embodiment of the present invention, which may specifically include the following modules:

[0110] A first acquisition module 201 is used to acquire an initial total area and a circuit schematic diagram of an input / output module;

[0111] A first determining module 202, configured to divide the input / output module into a plurality of sub-areas according to the initial total area, and determine an initial sub-area corresponding to each sub-area;

[0112] A second determination module 203 is used to iteratively optimize the initial sub-area of ​​each sub-area according to the circuit schematic diagram to determine the target sub-area corresponding to each sub-area;

[0113] The third determination module 204 is used to determine the corresponding sub-region layout according to the target sub-area corresponding to each sub-region;

[0114] The first merging module 205 is used to merge the optimized multiple sub-regions to obtain the target layout of the input / output module.

[0115] In one embodiment, the second determining module includes:

[0116] The first determination submodule is used to determine the current temperature value and the cooling step length according to the simulated annealing algorithm;

[0117] A first temperature reduction submodule, configured to reduce the current temperature value according to the temperature reduction step length;

[0118] A first adjustment submodule, configured to adjust the device layout in each sub-area according to the circuit schematic after the current temperature value decreases;

[0119] A first calculation submodule is used to calculate the device layout area in the sub-region after each adjustment, so that the device layout area in the sub-region after each adjustment is smaller than the previous area; the number of times the device layout in the sub-region is adjusted is equal to the number of times the current temperature value is reduced;

[0120] The first stopping submodule is used to stop the iterative optimization when a preset condition is met.

[0121] In one embodiment, the first stopping submodule includes:

[0122] A first determining unit, used to determine a temperature reduction coefficient and a termination temperature value according to the simulated annealing algorithm;

[0123] A second determining unit, used to determine an area difference between the area of ​​the sub-region before adjustment and the area of ​​the sub-region after adjustment;

[0124] a first stopping unit, configured to stop the iterative optimization when the area difference is less than a preset threshold, or

[0125] When the area difference is greater than or equal to a preset threshold, the product of the current new temperature value and the temperature reduction coefficient is calculated, and the iterative optimization is stopped when the product is less than or equal to the termination temperature value.

[0126] In one embodiment, the first adjustment submodule includes:

[0127] A first acquisition unit, used for acquiring design rules;

[0128] The first adjustment unit is used to adjust the input / output pin layout of the devices in each sub-area according to the circuit schematic and the design rule.

[0129] In one embodiment, the design rule includes: a device distance between two sub-regions is greater than a minimum safety distance for a latch-up effect to occur.

[0130] In one embodiment, the first merging module includes:

[0131] A first setting submodule is used to respectively set protection devices around the optimized multiple sub-areas;

[0132] A first isolation submodule, used to isolate each sub-area according to the protection device;

[0133] The first merging submodule is used to merge the sub-regions surrounding the protection device to obtain the target layout of the input / output module, and make the target layout comply with the design rules.

[0134] In one embodiment, the plurality of sub-regions include: an N-channel metal oxide semiconductor field effect transistor region, a P-channel metal oxide semiconductor field effect transistor region, a resistor region, a P-type electrostatic discharge protection device region, and an N-type electrostatic discharge protection device region.

[0135] The embodiment of the present invention provides a layout method for the input / output module of a chip, which obtains the initial total area and circuit schematic diagram of the input / output module; divides the input / output module into multiple sub-areas according to the initial total area, and determines the initial sub-area corresponding to each sub-area; iteratively optimizes the initial sub-area of ​​each sub-area according to the circuit schematic diagram, and determines the target sub-area corresponding to each sub-area; determines the corresponding sub-area layout according to the target sub-area corresponding to each sub-area; and merges the optimized multiple sub-areas to obtain the target layout of the input / output module. The embodiment of the present invention divides the input / output module into multiple sub-areas, and optimizes the layout of the input / output module by optimizing the areas of the multiple sub-areas, so as to reduce unnecessary space occupation area, and also reduces the manufacturing cost of the chip and improves market competitiveness.

[0136] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0137] An embodiment of the present invention further provides an electronic device, including:

[0138] It includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, each process of the layout method embodiment of the input / output module of the above-mentioned chip is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0139] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the layout method embodiment of the input / output module of the above-mentioned chip are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0140] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0141] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0142] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0143] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0144] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0145] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0146] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0147] The above is a detailed introduction to a layout method of an input / output module of a chip and a layout device of an input / output module of a chip provided by the present invention. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A layout method for an input / output module of a chip, characterized in that: The method comprises: Get the initial total area and circuit schematics of the input / output module; Dividing the input / output module into a plurality of sub-areas according to the initial total area, and determining an initial sub-area corresponding to each sub-area; Iteratively optimize the initial sub-area of ​​each sub-area according to the circuit schematic to determine the target sub-area corresponding to each sub-area; Determine the corresponding sub-region layout according to the target sub-area corresponding to each sub-region; The optimized multiple sub-regions are merged to obtain the target layout of the input / output module.

2. The layout method of the chip input / output module according to claim 1, characterized in that: The iterative optimization of the initial sub-area of ​​each sub-region according to the circuit schematic diagram comprises: According to the simulated annealing algorithm, determine the current temperature value and the cooling step length; Lowering the current temperature value according to the cooling step length; After the current temperature value decreases, adjusting the device layout in each sub-area according to the circuit schematic; Calculating the device layout area in the sub-region after each adjustment so that the device layout area in the sub-region after each adjustment is smaller than the area of ​​the previous adjustment; the number of times the device layout in the sub-region is adjusted is equal to the number of times the current temperature value is reduced; When the preset conditions are met, the iterative optimization stops.

3. The layout method of the chip input / output module according to claim 2, characterized in that: When the preset condition is met, stopping the iterative optimization includes: According to the simulated annealing algorithm, determine the temperature reduction coefficient and the termination temperature value; Determine the area difference between the sub-region area before adjustment and the sub-region area after adjustment; When the area difference is less than a preset threshold, the iterative optimization is stopped, or When the area difference is greater than or equal to a preset threshold, the product of the current new temperature value and the temperature reduction coefficient is calculated, and the iterative optimization is stopped when the product is less than or equal to the termination temperature value.

4. The layout method of the chip input / output module according to claim 2, characterized in that: The adjusting the device layout in each sub-area according to the circuit schematic diagram includes: Get design rules; The input / output pin layout of the devices in each sub-area is adjusted according to the circuit schematic and the design rule.

5. The layout method of the chip input / output module according to claim 4, characterized in that: The design rule includes: the device distance between the two sub-areas is greater than the minimum safety distance for the latch effect to occur.

6. The layout method of the chip input / output module according to claim 5, characterized in that: The step of merging the optimized multiple sub-regions to obtain the target layout of the input / output module includes: Protective devices are respectively arranged around the optimized multiple sub-areas; Isolating each sub-area according to the protection device; The sub-regions surrounding the protection device are merged to obtain a target layout of the input / output module, and the target layout is made to comply with the design rules.

7. The layout method of the chip input / output module according to claim 1, characterized in that: The plurality of sub-regions include: an N-channel metal oxide semiconductor field effect transistor region, a P-channel metal oxide semiconductor field effect transistor region, a resistor region, a P-type electrostatic discharge protection device region, and an N-type electrostatic discharge protection device region.

8. A layout device for an input / output module of a chip, characterized in that: The device comprises: A first acquisition module, used to acquire an initial total area and a circuit schematic diagram of an input / output module; A first determining module, configured to divide the input / output module into a plurality of sub-areas according to the initial total area, and determine an initial sub-area corresponding to each sub-area; A second determination module is used to iteratively optimize the initial sub-area of ​​each sub-area according to the circuit schematic diagram to determine the target sub-area corresponding to each sub-area; A third determination module is used to determine the corresponding sub-region layout according to the target sub-area corresponding to each sub-region; The first merging module is used to merge the optimized multiple sub-regions to obtain the target layout of the input / output module.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of laying out the input / output module of the chip according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the layout method of the input / output module of the chip as described in any one of claims 1 to 7 are implemented.

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