Chip topology network of neuron computer

Abstract

The invention relates to a chip topology network of a neuron computer, which comprises M rows * N columns of modules, each module is composed of nodes, and each node is composed of a chip; each node is provided with a node controller, a data controller, a signal controller, a first data line, a second data line and a signal line, the first data line is arranged in the column direction of the chip and electrically connected with the chip in the column, the second data line is arranged in the row direction of the chip and electrically connected with the chip in the row, and the first data line is connected with the data controller; the second data line and the signal line are connected with the signal controller; the data controller sends the received first pulse data to a corresponding chip to be synchronized; and the signal controller sends the received second pulse data to the corresponding to-be-synchronized chip, and controls the corresponding to-be-synchronized chip to perform time step synchronization calculation in response to the time step synchronization signal sent by the node controller. The chip topology network has high expandability, and meanwhile, the efficient interconnection operation of the multi-module chip array can be realized.

Description

Technical Field

[0001] The present application relates to the technical field of neuron computers, and in particular to a chip topology network of a neuron computer. Background Art

[0002] A neural computer refers to a new type of computer system based on neuromorphic hardware, usually composed of multiple pieces of neuromorphic hardware.

[0003] STDP (Spike Time-Dependent Plasticity) is one of the most widely used learning algorithms in spiking neural networks. The calculations of most neuromorphic chips need to consider the concept of time steps that map real time constraints. Therefore, all neurons involved in neural network applications must complete spike data calculations within a specific time step. In the many-core architecture, all involved neuromorphic cores must complete spike calculations within a specific time step, and the iterative process of the time step is completed under the control of the time step synchronization module.

[0004] The time-step synchronization function of general neuromorphic hardware is integrated into the on-chip network. However, for neuromorphic hardware systems with large-scale chip integration, the time-step synchronization between chips must take into account the data transmission and computing efficiency within and outside the chip. Therefore, how to optimize the design of time-step synchronization has become one of the goals explored by researchers. Summary of the invention

[0005] Based on this, it is necessary to provide a method to address the above technical problems, which can enable time-step synchronization signals to be transmitted and recognized in an orderly manner in a large-scale neuromorphic hardware system, thereby realizing a scalable, highly available neuron chip topology network with large-scale neuromorphic hardware cascade operation.

[0006] In a first aspect, the present application provides a chip topology network of a neuron computer, wherein the neuron chip topology network includes modules of M rows×N columns, adjacent modules are interconnected through a first Ethernet interface, each module is composed of q×k nodes, each node is composed of m×n chips, and adjacent chips are interconnected through a GPIO interface;

[0007] Each node is provided with a node controller, m data controllers and n signal controllers, and the node controller is communicatively connected with each of the data controllers and the signal controllers;

[0008] Each node is also provided with m first data lines arranged along the chip column direction and electrically connected to the chip in the column, n second data lines arranged along the chip row direction and electrically connected to the chip in the row, and n signal lines, wherein the first data lines are connected to a data controller, and the second data lines and the signal lines are connected to a signal controller; the data controller is used to send the first pulse data transmitted by the first opposite end module sent by the first Ethernet to the corresponding chip to be synchronized through the first data lines;

[0009] The signal controller is used to send the second pulse data transmitted by the second opposite end module sent by the first Ethernet to the corresponding chip to be synchronized through the second data line, and in response to the time step synchronization signal sent by the node controller, control the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line.

[0010] In one embodiment, a second Ethernet interface is provided between adjacent modules, and the second Ethernet interface is interconnected with the communication interface of the external software system, and is used to transmit the third pulse data received from the external software system via the second Ethernet to the chip to be synchronized in the module via the first data line or the second data line.

[0011] In one of the embodiments, the signal controller is further used to respond to the first synchronization configuration information transmitted by the first Ethernet or the second Ethernet, monitor the synchronization characteristic signal of the corresponding chip to be synchronized on the second data line, and if the synchronization characteristic signal is monitored, respond to the time step synchronization signal sent by the node controller, and control the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line.

[0012] In one of the embodiments, the first synchronization configuration information includes master channel configuration information and slave channel configuration information;

[0013] The first signal controller is used to respond to the main channel configuration information transmitted by the first Ethernet or the second Ethernet, monitor the first ready signal reported by the second signal controller, and trigger the time step synchronization signal of the second signal controller if the first ready signal is monitored; the second signal controller controls the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line in response to the time step synchronization signal;

[0014] wherein the second signal controller is in the same node as the first signal controller and responds to slave channel configuration information transmitted via the first Ethernet or the second Ethernet;

[0015] The first ready signal is generated after the second signal controller monitors the synchronization characteristic signal of the chip to be synchronized connected to it.

[0016] In one embodiment, the first node controller is used to respond to the master node configuration information transmitted by the first Ethernet or the second Ethernet, monitor the second ready signal reported by the second node controller, and trigger the time step synchronization signal of the second node controller if the second ready signal is monitored; the second node controller responds to the time step synchronization signal and triggers the time step synchronization signal of the third signal controller in communication with it;

[0017] Wherein, the second node controller is in the same module as the first node controller and responds to slave node configuration information transmitted via the first Ethernet or the second Ethernet;

[0018] The third signal controller is communicatively connected with the second node controller and responds to the primary channel configuration information transmitted by the first Ethernet or the second Ethernet;

[0019] The second ready signal is generated after the second node controller monitors the third ready signal reported by the third signal controller; the third ready signal is generated after the third signal controller monitors the synchronization characteristic signal of the chip to be synchronized connected thereto and the fourth ready signal reported by the fourth signal controller;

[0020] The fourth signal controller and the third signal controller are in the same node and respond to the slave channel configuration information transmitted by the first Ethernet or the second Ethernet; the fourth ready signal is generated after the fourth signal controller monitors the synchronization characteristic signal of the chip to be synchronized connected to it.

[0021] In one embodiment, the first node controller is further used to respond to the master node configuration information transmitted by the first Ethernet or the second Ethernet, monitor the fifth ready signal reported by the fifth signal controller in communication with it, and if the fifth ready signal is monitored, trigger the time step synchronization signal of the fifth signal controller; the fifth signal controller responds to the time step synchronization signal, controls the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line, and triggers the time step synchronization signal of the sixth signal controller;

[0022] Wherein, the fifth signal controller is located in the same node as the first node controller and responds to the primary channel configuration information transmitted by the first Ethernet or the second Ethernet;

[0023] The sixth signal controller is located in the same node as the first node controller and responds to the slave channel configuration information transmitted by the first Ethernet or the second Ethernet;

[0024] The fifth ready signal is generated after the fifth signal controller monitors the synchronization characteristic signal reported by the chip to be synchronized connected thereto and the sixth ready signal reported by the sixth signal controller;

[0025] The sixth ready signal is generated after the sixth signal controller monitors the synchronization characteristic signal reported by the chip to be synchronized connected to it.

[0026] In one embodiment, the synchronization characteristic signal includes a time step fixed period signal, a standby signal, a first time step separation signal,

[0027] The time step fixed period signal is a time step period estimation result generated after the chip to be synchronized receives the first pulse data or the second pulse data or the third pulse data transmitted by the first data line or the second data line;

[0028] The standby signal is a standby signal generated after the chip to be synchronized completes the first pulse data, the second pulse data, or the third pulse data of the previous time step;

[0029] The first time step separation signal is used to separate the calculation data of each time step of the third pulse data.

[0030] In one embodiment, the synchronization characteristic signal further includes: a second time step separation signal for separating the calculation data of each time step of the first pulse data or the second pulse data.

[0031] In one embodiment, the synchronization characteristic signal further includes: a timing delay signal,

[0032] The timing delay signal is a signal generated by delaying the first pulse data or the second pulse data received by the chip to be synchronized through the first data line or the second data line.

[0033] In one embodiment, q=k, and m=n.

[0034] In the chip topology network of the above-mentioned neuron computer, a node controller, a data controller and a signal controller are arranged in each module, and the node controller is communicatively connected with each of the data controllers and the signal controllers; each node is also provided with m first data lines arranged along the chip column direction and electrically connected to the chip in the column, n second data lines and n signal lines arranged along the chip row direction and electrically connected to the chip in the row, the first data line is connected to the data controller, and the second data line and the signal line are connected to the signal controller; the data controller is used to send the first pulse data transmitted by the first opposite module sent by the first Ethernet to the corresponding chip to be synchronized through the first data line; the signal controller is used to send the second pulse data transmitted by the second opposite module sent by the first Ethernet to the corresponding chip to be synchronized through the second data line, and in response to the time step synchronization signal sent by the node controller, the corresponding chip to be synchronized is controlled through the signal line to perform time step synchronization calculation, thereby constructing a new chip topology network of neuron computer hardware, which has high scalability and realizes efficient interconnection and operation of multi-module chip arrays. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A structural block diagram of a chip topology network of a neuron computer in one embodiment;

[0037] Figure 2 is a structural block diagram of a module in an embodiment;

[0038] Figure 3 A schematic diagram of a structure of applying A to perform time step synchronization calculation in a chip topology network of a neuron computer in one embodiment;

[0039] Figure 4 A schematic diagram of the timing relationship of simultaneously calculating multiple time steps in a chip topology network of a neuron computer in one embodiment;

[0040] Figure 5 FIG. 4 is a diagram showing the internal structure of a neuron computer device in one embodiment. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0042] Unless otherwise defined, the technical terms or scientific terms involved in this application should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the" and the like involved in this application do not indicate a quantitative limitation, and may represent the singular or plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0043] In one embodiment, a neuron chip topology network is provided, such as Figure 1 As shown, the neuron chip topology network includes M rows×N columns of modules, and adjacent modules are interconnected via a first Ethernet interface. Figure 2 As shown, each module consists of q×k nodes, each node consists of m×n chips, and each adjacent chip is interconnected through a GPIO interface.

[0044] Wherein, q and k are both positive integers, q = k. m and n are both positive integers, m = n.

[0045] Each node is provided with a node controller, m data controllers and n signal controllers, and the node controller is communicatively connected with each of the data controllers and the signal controllers.

[0046] Each node is also provided with m first data lines arranged along the chip column direction and electrically connected to the chips in the column, m second data lines arranged along the chip row direction and electrically connected to the chips in the row, and m signal lines. The first data line is connected to the data controller, and the second data line and the signal line are connected to the signal controller.

[0047] The data controller is used for sending the first pulse data transmitted by the first opposite end module sent by the first Ethernet to the corresponding chip to be synchronized through the first data line.

[0048] The signal controller is used to send the second pulse data transmitted by the second opposite end module sent by the first Ethernet to the corresponding chip to be synchronized through the second data line, and in response to the time step synchronization signal sent by the node controller, control the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line.

[0049] It should be noted that within each module, the chips between nodes only interact with pulse data, and the chip's time step synchronization signal needs to be transmitted by signal lines.

[0050] More specifically, a second Ethernet interface is provided between the adjacent modules, and the second Ethernet interface is interconnected with the communication interface of the external software system. The second Ethernet interface is interconnected with the communication interface of the external software system, and is used to transmit the third pulse data received from the external software system via the second Ethernet to the chip to be synchronized in the module via the first data line or the second data line.

[0051] Preferably, the first Ethernet interface is a 10 Gigabit Ethernet interface, and the second Ethernet interface is a Gigabit Ethernet interface. The node is FPGA hardware.

[0052] In this embodiment, m data controllers and n signal controllers are mounted on a node, wherein the data controller electrically connected to the chip in the column is connected to the entire column of n chips, and the signal controller electrically connected to the chip in the column is connected to the entire row of m chips to achieve time step synchronization control of the m×n chip array, and the chips are interconnected through GPIO pins. The communication layer of each node is equipped with 10G and 1G communication networks. The 1G network is used for data I / O access with external software systems, and the 10G network is used to connect to the 10G Ethernet interface of other modules, realizing the interconnection operation of a highly scalable multi-module chip array.

[0053] In one of the embodiments, the signal controller is further used to respond to the first synchronization configuration information transmitted by the first Ethernet or the second Ethernet, monitor the synchronization characteristic signal of the corresponding chip to be synchronized on the second data line, and if the synchronization characteristic signal is monitored, respond to the time step synchronization signal sent by the node controller, and control the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line.

[0054] In detail, the synchronization characteristic signal includes at least one of a time step fixed period signal, a standby signal, a first time step separation signal, a second time step separation signal, and a timing delay signal.

[0055] The time step fixed period signal is a time step period estimation result generated after the chip to be synchronized receives the first pulse data or the second pulse data or the third pulse data transmitted by the first data line or the second data line. The signal sensor monitors the time step fixed period signals of all correspondingly connected chips to be synchronized, and confirms that all chips to be synchronized can normally process the pulse data according to the time step period.

[0056] The standby signal is a standby signal generated after the chip to be synchronized or the chip array to be synchronized completes the first pulse data, the second pulse data, or the third pulse data of the previous time step. After the signal controller monitors the standby signals of all correspondingly connected chips to be synchronized, it confirms that all chips to be synchronized are in an idle state. The signal controller can also determine the actual time taken by the chip from the start to the end of the calculation in the previous time step through the standby signal.

[0057] The first time step separation signal is used to separate the calculation data of each time step of the third pulse data. The third pulse data is Gigabit Ethernet data. When the chip to be synchronized receives the third pulse data through the first data line or the second data line for time step calculation, the first time step separation signal is triggered after each time step calculation is completed. The signal controller monitors the first time step separation signal of all chips to be synchronized connected to it, and confirms that the chip to be synchronized has completed the calculation of the previous time step of the third pulse data.

[0058] The second time step separation signal is used to separate the calculation data of each time step of the first pulse data or the second pulse data. The first pulse data or the second pulse data is 10 Gigabit Ethernet data. When the chip to be synchronized receives the first pulse data or the second pulse data through the first data line or the second data line for time step calculation, the second time step separation signal is triggered after each time step calculation is completed. When the signal controller monitors the second time step separation signal of all chips to be synchronized connected to it, it is confirmed that the chip to be synchronized has completed the calculation of the previous time step of the first pulse data or the second pulse data.

[0059] The timing delay signal is a signal generated by the first pulse data or the second pulse data received by the chip to be synchronized via the first data line or the second data line. When the signal controller monitors the timing delay signal, it can confirm the delay time generated by the first pulse data or the second pulse data being transmitted between modules via the first Ethernet.

[0060] Specifically, in the chip topology network of the neuron computer, if the time step synchronization calculation of the chip to be synchronized in the same node or the same module is performed, the signal controller responds to the first synchronization configuration information transmitted by the first Ethernet or the second Ethernet, and after listening to the time step fixed period signal, standby signal, and first time step separation signal of the corresponding chip to be synchronized on the second data line, it can respond to the time step synchronization signal sent by the node controller, and control the corresponding chip to be synchronized to perform the time step synchronization calculation through the signal line.

[0061] If time step synchronization of the chips to be synchronized between modules is to be performed, the signal controller responds to the first synchronization configuration information transmitted by the first Ethernet or the second Ethernet, and after listening to the time step fixed period signal, standby signal, first time step separation signal, second time step separation signal, and timing delay signal of the corresponding chip to be synchronized on the second data line, it can respond to the time step synchronization signal sent by the node controller, and control the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line.

[0062] It should be noted that if it is necessary to perform time step synchronization calculation between two modules, it is necessary to consider the second time step separation signal and the timing delay signal. If it is not necessary to perform time step synchronization calculation between the two modules or to perform time step synchronization calculation of the same node and the same module in one module, it is not necessary to consider the second time step separation signal and the timing delay signal. Therefore, in the chip topology network of the neuron computer of the present application, in addition to supporting time step synchronization calculation within a node, time step synchronization calculation within a module, and time step synchronization calculation between modules, it is also possible to realize asynchronous time step calculation between modules.

[0063] In one embodiment, the first synchronization configuration information includes master channel configuration information and slave channel configuration information. Therefore, in the same node, the signal controller that responds to the master channel configuration information is used as the first signal controller, i.e., the master channel synchronization source of the node, and the signal controller that responds to the slave channel configuration information is used as the second signal controller, i.e., the secondary channel synchronization source of the node.

[0064] The first signal controller is used to respond to the main channel configuration information transmitted by the first Ethernet or the second Ethernet, monitor the first ready signal reported by the second signal controller, and trigger the time step synchronization signal of the second signal controller if the first ready signal is monitored; the second signal controller responds to the time step synchronization signal and controls the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line.

[0065] The second signal controller and the first signal controller are in the same node and respond to the slave channel configuration information transmitted by the first Ethernet or the second Ethernet. The first ready signal is generated after the second signal controller monitors the synchronization characteristic signal of the chip to be synchronized connected to it.

[0066] In this embodiment, by configuring the primary and secondary relationship of the signal controllers in the same node, each signal controller receives the synchronization characteristic signal of the chip to be synchronized connected to it, and at the same time, the first signal controller, i.e., the main channel synchronization source, centrally receives the first ready signal of all the second signal controllers, i.e., the secondary channel synchronization source, and triggers the time step synchronization signal of the second signal controller, so that the time step synchronization signal can be transmitted and identified in an orderly manner among the multiple channels of the same node, thereby realizing the time step synchronization trigger calculation of the chip to be synchronized of each signal controller in the same node.

[0067] In one of the embodiments, in addition to the synchronization of all chips to be synchronized in the same node, the embodiment also proposes the synchronization of all chips to be synchronized in multiple nodes in the same module. The node controller that responds to the master node configuration information transmitted by the first Ethernet or the second Ethernet is used as the first node controller, i.e., the master node synchronization source in the module, and the node controller that responds to the slave node configuration information transmitted by the first Ethernet or the second Ethernet is used as the second node controller, i.e., the secondary node synchronization source in the module.

[0068] The first node controller is used to respond to the master node configuration information transmitted by the first Ethernet or the second Ethernet, monitor the second ready signal reported by the second node controller, and trigger the time step synchronization signal of the second node controller if the second ready signal is monitored; the second node controller responds to the time step synchronization signal to trigger the time step synchronization signal of the third signal controller communicated with it.

[0069] Wherein, the second node controller is in the same module as the first node controller and responds to the slave node configuration information transmitted by the first Ethernet or the second Ethernet. The third signal controller is connected to the second node controller in communication and responds to the master channel configuration information transmitted by the first Ethernet or the second Ethernet. The second ready signal is generated after the second node controller monitors the third ready signal reported by the third signal controller. The third ready signal is generated after the third signal controller monitors the synchronization characteristic signal of the chip to be synchronized connected to it and the fourth ready signal reported by the fourth signal controller. The fourth signal controller is in the same node as the third signal controller and responds to the slave channel configuration information transmitted by the first Ethernet or the second Ethernet. The fourth ready signal is generated after the fourth signal controller monitors the synchronization characteristic signal of the chip to be synchronized connected to it.

[0070] In detail, although the second node controller is a secondary node synchronization source, the third signal controller connected to the second node controller is the main channel synchronization source in the node where the second node controller is located. After the second node controller monitors the third ready signal reported by the third signal controller, it confirms that all chips to be synchronized in the node are ready for time step synchronization calculation and generates a second ready signal. The first node controller monitors the second ready signal of the second signal controller, confirms that all nodes in the same module are ready for time step synchronization calculation, and triggers the time step synchronization signal of the second node controller. The second node controller triggers the time step synchronization signal of the third signal controller. The third signal controller triggers the time step synchronization signal of the chip to be synchronized connected to it and the fourth signal controller. The fourth signal controller triggers the time step synchronization signal of the chip to be synchronized connected to it. In this way, the time step synchronization calculation between multiple nodes in the same module is realized.

[0071] In one of the embodiments, when time step synchronization calculations are performed between multiple nodes in the same module, the first node controller, in addition to monitoring the third ready signal of the second node controller, also needs to monitor the fifth ready signal reported by the fifth signal controller connected to it to confirm whether the chip to be synchronized in the node where the first node controller is located is ready.

[0072] The first node controller is also used to respond to the master node configuration information transmitted by the first Ethernet or the second Ethernet, monitor the fifth ready signal reported by the fifth signal controller connected to it, and if the fifth ready signal is monitored, trigger the time step synchronization signal of the fifth signal controller; the fifth signal controller responds to the time step synchronization signal, controls the corresponding chip to be synchronized through the signal line to perform time step synchronization calculation and trigger the time step synchronization signal of the sixth signal controller.

[0073] The fifth signal controller is located in the same node as the first node controller and responds to the master channel configuration information transmitted by the first Ethernet or the second Ethernet. The sixth signal controller is located in the same node as the first node controller and responds to the slave channel configuration information transmitted by the first Ethernet or the second Ethernet. The fifth ready signal is generated after the fifth signal controller monitors the synchronization characteristic signal reported by the chip to be synchronized connected to it and the sixth ready signal reported by the sixth signal controller. The sixth ready signal is generated after the sixth signal controller monitors the synchronization characteristic signal reported by the chip to be synchronized connected to it.

[0074] In this embodiment, by configuring the primary and secondary relationships of nodes and the primary and secondary relationships of channels in the same module, the first node controller monitors the fifth ready signal reported by the fifth signal controller connected to it, confirms whether the chip to be synchronized in the node where the first node controller is located is ready, thereby triggering the time step synchronization signal of the fifth signal controller; the fifth signal controller triggers the time step synchronization signal of the chip to be synchronized connected to it and the sixth signal controller; the sixth signal controller triggers the time step synchronization signal of the chip to be synchronized connected to it, ensuring that when time step synchronization calculation is required between multiple nodes in the same module, all chips to be synchronized of the primary node synchronization source and all chips to be synchronized of the secondary node synchronization source perform time step calculation at the same time, so that the time step synchronization signal is orderly transmitted and identified between multiple nodes in the same module, thereby improving the accuracy and efficiency of the time step synchronization calculation in the same module.

[0075] In one embodiment, if time step synchronization calculation is required between multiple modules, among the multiple modules, if the third node controller in one of the modules responds to the main module configuration information and the main node configuration information transmitted by the first Ethernet or the second Ethernet, then the module where the third node controller is located is the main module synchronization source among the multiple modules. The remaining modules are the secondary module synchronization sources for this time step synchronization calculation. The fourth node controller in the secondary module synchronization source responds to the secondary module configuration information and the main node configuration information transmitted by the first Ethernet or the second Ethernet.

[0076] The third node controller is used to respond to the main module configuration information transmitted by the first Ethernet or the second Ethernet, monitor the seventh ready signal reported by the fourth node controller, and trigger the time step synchronization signal of the fourth node controller if the seventh ready signal is monitored; the fourth node controller responds to the time step synchronization signal and triggers the time step synchronization signal of the seventh signal controller communicated with it.

[0077] Among them, the seventh signal controller and the fourth node controller are in the same node and respond to the main channel configuration information transmitted by the first Ethernet or the second Ethernet. The seventh ready signal is generated after the fourth node controller monitors the eighth ready signal reported by the seventh signal controller. The eighth ready signal is generated after the seventh signal controller monitors the synchronization characteristic signal of the chip to be synchronized connected to it and the ninth ready signal reported by the ninth signal controller. The ninth signal controller and the seventh signal controller are in the same node and respond to the slave channel configuration information transmitted by the first Ethernet or the second Ethernet. The ninth ready signal is generated after the ninth signal controller monitors the synchronization characteristic signal of the chip to be synchronized connected to it.

[0078] In this embodiment, by configuring the primary and secondary relationships between multiple modules, the time step synchronization trigger calculation of the chip to be synchronized is realized between the synchronization source of the main module and the synchronization source of the secondary module, so that the time step synchronization signal can be transmitted and recognized in an orderly manner among multiple modules, thereby solving the synchronization problem of multi-scale pulse neural networks on neuromorphic hardware.

[0079] In a preferred embodiment, a method based on Figure 2 The specific application scenario of the chip topology network of the neuron computer shown in the figure. Among them, the data controller and signal controller of each node have corresponding channel numbers, and the channel numbers between adjacent modules correspond one to one, which means that the data stream output by the channel will only flow to the channel with the same channel number in the opposite module.

[0080] Assume that the numbering templates of various controllers are (a, b, c, d), where a and b represent the unit numbers of the modules, c is the node number, and d is the channel number. Establish a 4×4 module unit topology network with a numbering range of a∈[0,1], b∈[0,1], c∈[0,3], d∈[1,8]. And deploy applications A, B, C, D, and E on the 4×4 module unit topology network.

[0081] like Figure 3 As shown in the figure, each application has a different synchronization range and control data flow direction. For example, the synchronization signal controllers involved in application A are (1,0,1,1), (1,0,1,2), (1,0,1,3), (1,0,3,1), (1,0,3,2), (1,0,3,3), (1,0,3,4), (1,1,0,1), (1,1,0,2), (1,1,0,3), (1,1,0,4), (1,1,2,3), (1,1,2,4). The synchronization channels controlled by these signal controllers maintain a synchronization relationship during the operation of the application. Figure 3 The one-way arrow in is the transmission direction of the time step synchronization signal. From the transmission direction of the time step synchronization signal in the figure, it can be seen that the module-level synchronization sources of this application are modules (1,0), (0,1), (1,1), among which module (1,1) is the main module synchronization source. In modules (1,0) and (0,1), node controller (1,0,1), node controller (0,1,2), and node controller (1,1,0) are the main node synchronization sources, and the remaining node controllers are secondary node synchronization sources. Furthermore, signal controller (1,0,1,3), signal controller (1,0,3,1), signal controller (0,1,2,1), signal controller (1,1,0,4), and signal controller (1,1,2,2) are the main channel synchronization sources, and the remaining channel controllers are secondary channel synchronization sources.

[0082] Assuming that the current time step is t, the detailed synchronization process is as follows: the Ready signal of the pulse data calculation completed at the t-1 time step is reported by the signal controller (1,1,2,2) to the node controller (1,1,1) connected to it, and the node controller (1,1,1) is passed to the node controller (1,1,0). At the same time, the signal controller (1,1,0,4) also reports the synchronization characteristic signals of all the chips to be synchronized received to the node controller (1,1,0).

[0083] After receiving all Ready signals, node controller (1,1,0) triggers the time step synchronization signal of node controller (1,1,1), and also triggers the time step synchronization signals of signal controller (1,1,0,4), signal controller (1,1,0,1), signal controller (1,1,0,2), and signal controller (1,1,0,3) connected to it.

[0084] The node controller (1,1,1) triggers the time step synchronization signals of all the signal controllers to be synchronized connected to it in turn, thereby triggering all the chips to be synchronized in the module to start calculating the time step t synchronously.

[0085] The pulse data calculated by module (1,1) will be sent to module (1,0) and (0,1) via 10 Gigabit Ethernet. Similarly, after receiving the Ready signal indicating that the pulse data calculation of time step t-1 is completed, the signal controller in module (1,0) and module (0,1) will start waiting for the time step separation signal in the pulse data transmitted by the main module (1,1). When the signal arrives, it can be reported to node controller (1,0,1), node controller (0,1,2), and node controller (1,1,0) in module (1,0) and module (0,1). When each controller in node controller (1,0,1), node controller (0,1,2), and node controller (1,1,0) receives all the signals connected to it, it can trigger the calculation of time step t by the chip to be synchronized in module (1,0) and module (0,1). The synchronization process is the same as that of module (1,1).

[0086] In this preferred embodiment, the channel numbers between adjacent modules correspond one to one, and the channel matching relationship between the adjacent modules is: signal controller (1,0,1,1) and signal controller (1,1,0,1), signal controller (1,0,1,2) and signal controller (1,1,0,2), signal controller (1,0,1,3) and signal controller (1,1,1,3), signal controller (1,0,3,3) and signal controller (1,1,2,3), signal controller (1,0,3,4) and signal controller (1,1,2,4), signal controller (0,1,2,1) and signal controller (1,1,0,4).

[0087] According to the time step synchronization method used in the chip topology network of the neuron computer in this application, Figure 4 The timing relationship of the neuromorphic hardware system calculating multiple time steps at the same time is demonstrated. For the master node, there are generally two synchronization steps in the synchronous calculation process. Step one is to obtain channel resources, that is, to initiate synchronization. This means that the master node controller of the master module synchronization source sends the configuration information of node synchronization to other node controllers within the master module and between modules. Other node controllers read the configuration information and constrain the specified signal controller to the synchronization state according to the configuration information. After the configuration takes effect, it can enter the synchronization stage and pass or wait for the time step synchronization signal. Step two is to release channel resources, that is, to end synchronization. This means that after completing the calculation of all time steps this time, the master node controller will send a configuration clear command to all other node controllers to release channel resources and prepare for the next calculation.

[0088] from Figure 4 It can also be seen that the timing of the third pulse data input to each node by the external software system arriving at the chip topology network of the neuron computer may be different, which will be synchronized by the software scheduler on each node. After the third pulse data calculation is completed, the output timing of each part of the chip topology network may also be inconsistent. The external software system is also used to aggregate and process the output data, thereby realizing the synchronous calculation of time steps within the module and the asynchronous calculation of time steps between modules.

[0089] In this preferred embodiment, multi-scale synchronization across modules, nodes, and channels is divided into three synchronization levels, taking into account multiple synchronization scenarios such as single-chip synchronization, multi-chip synchronization within a single channel, multi-channel synchronization within a node, multi-node synchronization within a module, and multi-module synchronization. This allows synchronized computing signals to be transmitted and identified in an orderly manner among multiple channels, multiple nodes, and multiple modules, thereby solving the synchronization problem of multi-scale pulse data on neuromorphic hardware. The time steps of different synchronization sources are isolated from each other, and multiple network applications can run concurrently.

[0090] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0091] In an exemplary embodiment, Figure 5 As shown, a neuron computer device is provided, which may be a terminal, and includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. The memory contains a chip topology network of the neuron computer as described in the above embodiments.

[0092] Wherein, the processor, memory and input / output interface are connected through a system bus, and the communication interface, display unit and input device are connected to the system bus through the input / output interface. Wherein, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be realized through WIFI, a mobile cellular network, near field communication (Near Field Communication, NFC) or other technologies. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0093] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0094] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A chip topology network of a neuron computer, characterized in that: The chip topology network includes modules of M rows×N columns, adjacent modules are interconnected through a first Ethernet interface, each module is composed of q×k nodes, each node is composed of m×n chips, and adjacent chips are interconnected through a GPIO interface; Each node is provided with a node controller, m data controllers and n signal controllers, and the node controller is communicatively connected with each of the data controllers and the signal controllers; Each node is also provided with m first data lines arranged along the chip column direction and electrically connected to the chip in the column, n second data lines arranged along the chip row direction and electrically connected to the chip in the row, and n signal lines, wherein the first data lines are connected to a data controller, and the second data lines and the signal lines are connected to a signal controller; the data controller is used to send the first pulse data transmitted by the first opposite end module sent by the first Ethernet to the corresponding chip to be synchronized through the first data lines; The signal controller is used to send the second pulse data transmitted by the second opposite end module sent by the first Ethernet to the corresponding chip to be synchronized through the second data line, and in response to the time step synchronization signal sent by the node controller, control the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line.

2. The chip topology network of the neuron computer according to claim 1, characterized in that: A second Ethernet interface is provided between adjacent modules, and the second Ethernet interface is interconnected with the communication interface of the external software system, and is used for transmitting the third pulse data received from the external software system via the second Ethernet to the chip to be synchronized in the module via the first data line or the second data line.

3. The chip topology network of the neuron computer according to claim 2, characterized in that: The signal controller is further used to respond to the first synchronization configuration information transmitted by the first Ethernet or the second Ethernet, monitor the synchronization characteristic signal of the corresponding chip to be synchronized on the second data line, and if the synchronization characteristic signal is monitored, respond to the time step synchronization signal sent by the node controller, and control the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line.

4. The chip topology network of the neuron computer according to claim 3, characterized in that: The first synchronization configuration information includes master channel configuration information and slave channel configuration information; The first signal controller is used to respond to the main channel configuration information transmitted by the first Ethernet or the second Ethernet, monitor the first ready signal reported by the second signal controller, and trigger the time step synchronization signal of the second signal controller if the first ready signal is monitored; the second signal controller controls the corresponding chip to be synchronized to perform time step synchronization calculation through the signal line in response to the time step synchronization signal; wherein the second signal controller is in the same node as the first signal controller and responds to slave channel configuration information transmitted via the first Ethernet or the second Ethernet; The first ready signal is generated after the second signal controller monitors the synchronization characteristic signal of the chip to be synchronized connected to it.

5. The chip topology network of the neuron computer according to claim 4, characterized in that: The first node controller is used to respond to the master node configuration information transmitted by the first Ethernet or the second Ethernet, monitor the second ready signal reported by the second node controller, and trigger the time step synchronization signal of the second node controller if the second ready signal is monitored; the second node controller responds to the time step synchronization signal and triggers the time step synchronization signal of the third signal controller in communication with the second node controller; Wherein, the second node controller is in the same module as the first node controller and responds to slave node configuration information transmitted via the first Ethernet or the second Ethernet; The third signal controller is communicatively connected with the second node controller and responds to the primary channel configuration information transmitted by the first Ethernet or the second Ethernet; The second ready signal is generated after the second node controller monitors the third ready signal reported by the third signal controller; the third ready signal is generated after the third signal controller monitors the synchronization characteristic signal of the chip to be synchronized connected thereto and the fourth ready signal reported by the fourth signal controller; The fourth signal controller and the third signal controller are in the same node and respond to the slave channel configuration information transmitted by the first Ethernet or the second Ethernet; the fourth ready signal is generated after the fourth signal controller monitors the synchronization characteristic signal of the chip to be synchronized connected to it.

6. The chip topology network of the neuron computer according to claim 5, characterized in that: The first node controller is further configured to respond to the master node configuration information transmitted by the first Ethernet or the second Ethernet, monitor the fifth ready signal reported by the fifth signal controller in communication with the first node controller, and trigger the time step synchronization signal of the fifth signal controller if the fifth ready signal is monitored; the fifth signal controller controls the corresponding chip to be synchronized to perform time step synchronization calculation and trigger the time step synchronization signal of the sixth signal controller through the signal line in response to the time step synchronization signal; Wherein, the fifth signal controller is located in the same node as the first node controller and responds to the primary channel configuration information transmitted by the first Ethernet or the second Ethernet; The sixth signal controller is located in the same node as the first node controller and responds to the slave channel configuration information transmitted by the first Ethernet or the second Ethernet; The fifth ready signal is generated after the fifth signal controller monitors the synchronization characteristic signal reported by the chip to be synchronized connected thereto and the sixth ready signal reported by the sixth signal controller; The sixth ready signal is generated after the sixth signal controller monitors the synchronization characteristic signal reported by the chip to be synchronized connected to it.

7. The chip topology network of the neuron computer according to claim 6, characterized in that: The synchronization characteristic signal includes a time step fixed period signal, a standby signal, a first time step separation signal, The time step fixed period signal is a time step period estimation result generated after the chip to be synchronized receives the first pulse data or the second pulse data or the third pulse data transmitted by the first data line or the second data line; The standby signal is a standby signal generated after the chip to be synchronized completes the first pulse data, the second pulse data, or the third pulse data of the previous time step; The first time step separation signal is used to separate the calculation data of each time step of the third pulse data.

8. The chip topology network of the neuron computer according to claim 7, characterized in that: The synchronization characteristic signal also includes: a second time step separation signal, which is used to separate the calculation data of each time step of the first pulse data or the second pulse data.

9. The chip topology network of the neuron computer according to claim 8, characterized in that: The synchronization characteristic signal also includes: a timing delay signal, The timing delay signal is a signal generated by delaying the first pulse data or the second pulse data received by the chip to be synchronized through the first data line or the second data line.

10. The chip topology network of the neuron computer according to claim 1, characterized in that: q=k, m=n.

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