Display panel and display device including same

Abstract

The present disclosure relates to a display panel and a display device including the same, the display panel including: a first mode selection circuit receiving a first mode selection voltage through a first data line to select a first viewing angle as a viewing angle of one or more sub-pixels; and a second mode selection circuit that receives a second mode selection voltage through the second data line to select a second viewing angle as a viewing angle of the one or more sub-pixels.

Description

Technical Field

[0001] The present disclosure relates to a display panel whose viewing angle is variable on a pixel basis and a display device including the display panel. Background Art

[0002] Variable viewing angle technology is being applied to display devices, which can present video content or visual information reproduced on the display device only to users within a narrow viewing angle range, or to multiple users within a wide viewing angle range.

[0003] As the market for future vehicles such as electric vehicles and self-driving cars expands, the demand for in-vehicle display devices is rapidly increasing. A method of dividing the screen of an in-vehicle display device and controlling one part of the screen to have a narrow viewing angle and another part to have a wide viewing angle is currently being studied. This technology can drive pixels with a narrow viewing angle arranged in one area of ​​the screen to display personal content or information that can only be viewed by a specific user, and at the same time drive pixels with a wide viewing angle arranged in another area of ​​the screen to display shared content that can be viewed by multiple users.

[0004] Among vehicle-mounted display devices, display panels for organic light-emitting display devices have attracted much attention. Organic light-emitting display devices include self-luminous organic light-emitting diodes (hereinafter referred to as "OLEDs"), which have the advantages of fast response speed, good luminous efficiency and brightness, and wide viewing angle. The organic light-emitting display device has a fast response speed, is excellent in luminous efficiency, brightness and viewing angle, and provides excellent contrast and color reproducibility due to its black grayscale in full black. Since the display panel of the organic light-emitting display device can be flexibly bent, a curved surface can be easily realized. Due to these advantages, the share of organic light-emitting display devices in the vehicle-mounted display device market is rapidly increasing.

[0005] In order to realize the variable viewing angle technology, wiring for transmitting signals for selecting the viewing angle may be added to the pixels, circuit elements, optical elements, etc. of the display panel. If many wires and circuit elements are added to the display panel, the design of the display panel becomes difficult and the cost of the display device increases. Summary of the invention

[0006] The present disclosure has been made to address the above-mentioned needs and / or deficiencies.

[0007] The present disclosure provides a display device whose viewing angle can be selected on a pixel basis. This can be used to provide a "local" or localized viewing area / range on a pixel basis at which a viewer can view an image in an acceptable manner. For example, a passenger can see a portion of a displayed image while the driver (who has a different viewing angle range) cannot see that portion. The screen image can essentially be segmented locally on a pixel basis.

[0008] Problems or limitations to be solved or addressed by the present disclosure are not limited to those mentioned above, and other problems or limitations not mentioned will be clearly understood by those skilled in the art from the following description.

[0009] According to one embodiment of the present disclosure, a display panel includes: a first mode selection circuit, which receives a first mode selection voltage through a first data line to select a first viewing angle as a viewing angle of one or more sub-pixels; and a second mode selection circuit, which receives a second mode selection voltage through a second data line to select a second viewing angle as a viewing angle of one or more sub-pixels.

[0010] The display panel may further include a plurality of sub-pixels. Each of the sub-pixels may include: a first light emitting element; a second light emitting element; a driving element driving the first light emitting element and the second light emitting element; a compensation circuit including a first capacitor connected to the driving element; a first switching element electrically connected to the driving element and the first light emitting element and driven by the first mode selection voltage; and a second switching element electrically connected to the driving element and the second light emitting element and driven by the second mode selection voltage.

[0011] The first sub-pixel may include the first mode selection circuit. The second sub-pixel may include the second mode selection circuit. The first mode selection circuit is electrically connected to the first data line and the compensation circuit inside the first sub-pixel to provide the first mode selection voltage to the gate electrode of the first switching element arranged in the first sub-pixel and the second sub-pixel. The second mode selection circuit is electrically connected to the second data line and the compensation circuit inside the second sub-pixel to provide the second mode selection voltage to the gate electrode of the second switching element arranged in the first sub-pixel and the second sub-pixel.

[0012] The first mode selection circuit may include a second capacitor to which the first mode selection voltage is applied. The second mode selection circuit may include a third capacitor to which the second mode selection voltage is applied.

[0013] The first mode selection circuit includes: a first mode switch element electrically connected to the first data line; a second capacitor connected to the gate electrode of the first switch element arranged in the first sub-pixel and the second sub-pixel to receive the applied first mode selection voltage; and a second mode switch element connected between the first mode switch element and the second capacitor. The second mode selection circuit may include: a third mode switch element electrically connected to the second data line; a third capacitor connected to the gate electrode of the second switch element arranged in the first sub-pixel and the second sub-pixel to receive the applied second mode selection voltage; and a fourth mode switch element connected between the third mode switch element and the third capacitor.

[0014] When the first switch element is turned on in response to the gate-on voltage of the first mode selection voltage, the first light emitting element may emit light. When the second switch element is turned on in response to the gate-on voltage of the second mode selection voltage, the second light emitting element may emit light. The first switch element may be turned off according to the gate-off voltage of the first mode selection voltage. The second switch element may be turned off according to the gate-off voltage of the second mode selection voltage.

[0015] The display panel may further include: a 1-1MUX switch element connected to the first data line to provide the first mode selection voltage to the first data line; a 1-2MUX switch element connected to the first data line to provide the first data voltage to be charged in the first capacitor of the first sub-pixel to the first data line; a 2-1MUX switch element connected to the second data line to provide the second mode selection voltage to the second data line; and a 2-2MUX switch element connected to the second data line to provide the second data line with the second data voltage to be charged in the first capacitor of the second sub-pixel.

[0016] After the 1-1 MUX switch element and the 2-1 MUX switch element may be simultaneously turned on in response to the gate-on voltage of the first MUX signal, the 1-2 MUX switch element and the 2-2 MUX switch element may be simultaneously turned on in response to the gate-on voltage of the second MUX signal.

[0017] The display panel may further include a third sub-pixel and a fourth sub-pixel. The first mode selection circuit may be connected to the first data line of the first sub-pixel, the compensation circuit of the first sub-pixel, and the gate electrodes of the first switching elements of the first sub-pixel to the fourth sub-pixel. The second mode selection circuit may be connected to the second data line of the second sub-pixel, the compensation circuit of the second sub-pixel, and the gate electrodes of the first switching elements of the first sub-pixel to the fourth sub-pixel.

[0018] Each of the first to fourth sub-pixels may include: a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node; a third switching element including a first electrode connected to a fourth node, a gate electrode to which a first selection signal is applied, and a second electrode connected to a fifth node; a fourth switching element including a first electrode connected to the second node, a gate electrode to which a second selection signal is applied, and a second electrode connected to the third node; a fifth switching element including a first electrode connected to a fourth node, a gate electrode to which a second selection signal is applied, and a second electrode connected to the third node; and a fifth switching element including a gate electrode to which a reference signal is applied. a first electrode to which the reference voltage is applied, a gate electrode to which the second selection signal is applied, and a second electrode connected to a ninth node; a sixth switching element, the sixth switching element comprising a first electrode to which the reference voltage is applied, a gate electrode to which the second selection signal is applied, and a second electrode connected to a tenth node; a seventh switching element, the seventh switching element comprising a first electrode connected to the fifth node, a gate electrode to which the third selection signal is applied, and a second electrode to which the reference voltage is applied; and an eighth switching element, the eighth switching element comprising a first electrode connected to the third node, a gate electrode to which the third selection signal is applied, and a second electrode connected to an eighth node.

[0019] In each of the first to fourth subpixels, the first switching element may include a first electrode connected to the eighth node, a gate electrode connected to the sixth node to which the first mode selection voltage is applied, and a second electrode connected to the ninth node. The second switching element may include a first electrode connected to the eighth node, a gate electrode connected to the seventh node to which the second mode selection voltage is applied, and a second electrode connected to the tenth node. The first light-emitting element may include an anode connected to the ninth node and a cathode to which a cathode voltage is applied. The second light-emitting element may include an anode connected to the tenth node and a cathode to which a cathode voltage is applied. The first capacitor may be connected between the second node and the fifth node.

[0020] The first mode switch element and the second mode switch element may be connected in series between the fourth node and the sixth node. The third mode switch element and the fourth mode switch element may be connected in series between the fourth node and the seventh node. The second capacitor may be connected between the sixth node and the reference voltage or between the sixth node and the pixel drive voltage. The third capacitor may be connected between the seventh node and the reference voltage or between the seventh node and the pixel drive voltage.

[0021] The first mode switching element may include a first electrode connected to the fourth node of the first sub-pixel, a gate electrode to which the third gating signal is applied, and a second electrode connected to the eleventh node of the first sub-pixel. The second mode switching element may include a first electrode connected to the eleventh node of the first sub-pixel, a gate electrode to which the second gating signal is applied, and a second electrode connected to the sixth node. The third mode switching element may include a first electrode connected to the fourth node of the second sub-pixel, a gate electrode to which the third gating signal is applied, and a second electrode connected to the twelfth node of the second sub-pixel. The fourth mode switching element may include a first electrode connected to the twelfth node of the second sub-pixel, a gate electrode to which the second gating signal is applied, and a second electrode connected to the seventh node.

[0022] The 1-1MUX switch element may include a first electrode to which the first mode selection voltage is applied, a gate electrode to which the first MUX signal is applied, and a second electrode connected to the first data line. The 1-2MUX switch element may include a first electrode to which the first data voltage is applied, a gate electrode to which the second MUX signal is applied, and a second electrode connected to the first data line. The 2-1MUX switch element may include a first electrode to which the second mode selection voltage is applied, a gate electrode to which the first MUX signal is applied, and a second electrode connected to the second data line. The 2-2MUX switch element may include a first electrode to which the second data voltage is applied, a gate electrode to which the second MUX signal is applied, and a second electrode connected to the second data line.

[0023] The voltage of the first MUX signal may be a gate-on voltage during the first period, a gate-off voltage during the 2-1 period set after the first period, a gate-off voltage during the 2-2 period set after the 2-1 period, and a gate-off voltage during the third period set after the 2-2 period. The voltage of the second MUX signal may be a gate-off voltage during the first period, a gate-on voltage during the 2-1 period, a gate-off voltage during the 2-2 period, and a gate-off voltage during the third period. The first gating signal may be a gate-off voltage during the first period and the 2-1 period, a gate-on voltage during the 2-2 period, and a gate-off voltage during the third period. The second gating signal may be a gate-on voltage during the first period to the 2-2 period, and a gate-off voltage during the third period. The third gate signal may be a gate-on voltage during the first period, a gate-off voltage during the 2-1 period and the 2-2 period, and a gate-on voltage during the third period.

[0024] According to another embodiment of the present disclosure, a display panel includes: a first sub-pixel connected to a first data line; a second sub-pixel connected to a second data line; a third sub-pixel connected to a third data line; a fourth sub-pixel connected to a fourth data line; a first mode selection circuit, which is configured to receive a first mode selection voltage through one data line from the first data line to the fourth data line to select a first viewing angle as the viewing angle of the first sub-pixel to the fourth sub-pixel; and a second mode selection circuit, which is configured to receive a second mode selection voltage through another data line from the first data line to the fourth data line to select a second viewing angle as the viewing angle of the first sub-pixel to the fourth sub-pixel.

[0025] The display panel may further include: a 1-1MUX switch element connected to the first data line to provide the first mode selection voltage to the first data line; a 1-2MUX switch element connected to the first data line to provide the first data voltage to be applied to the first sub-pixel; a 2-1MUX switch element connected to the second data line to provide the second mode selection voltage to the second data line; and a 2-2MUX switch element connected to the second data line to provide the second data voltage to be applied to the second sub-pixel.

[0026] The display panel may further include: a 1-1MUX switch element connected to the first data line to provide the first mode selection voltage to the first data line; a 1-2MUX switch element connected to the first data line to provide the first data voltage to be applied to the first sub-pixel to the first data line; a 1-3MUX switch element connected to the second data line to provide the second data voltage to be applied to the second sub-pixel to the second data line; a 2-1MUX switch element connected to the third data line to provide the second mode selection voltage to the third data line; a 2-2MUX switch element connected to the third data line to provide the third data line to provide the third data voltage to be applied to the third sub-pixel; and a 2-3MUX switch element connected to the fourth data line to provide the fourth data line to provide the fourth data voltage to be applied to the fourth sub-pixel.

[0027] According to one embodiment of the present disclosure, a display device includes: a display panel, in which a plurality of data lines, a plurality of sub-pixels, a first mode selection circuit, and a second mode selection circuit are arranged, wherein the plurality of sub-pixels are connected to corresponding data lines, the first mode selection circuit applies a first mode selection voltage to one or more sub-pixels through one of the data lines to select a first viewing angle as the viewing angle of the one or more sub-pixels, and the second mode selection circuit applies a second mode selection voltage to the one or more sub-pixels through another data line of the data lines to select a second viewing angle as the viewing angle of the one or more sub-pixels; a data driver, the data driver is configured to provide a data voltage to the data line; and a mode selection voltage power supply, the mode selection voltage power supply is configured to generate the first mode selection voltage and the second mode selection voltage.

[0028] According to another embodiment of the present disclosure, a display device includes: a display panel, in which a first sub-pixel, a second sub-pixel, a third sub-pixel, a fourth sub-pixel, a first mode selection circuit, and a second mode selection circuit are arranged, wherein the first sub-pixel is connected to a first data line, the second sub-pixel is connected to a second data line, the third sub-pixel is connected to a third data line, and the fourth sub-pixel is connected to a fourth data line, the first mode selection circuit receives a first mode selection voltage through one of the first data lines to the fourth data lines to select a first viewing angle as the viewing angle of the first sub-pixel to the fourth sub-pixel, and the second mode selection circuit receives a second mode selection voltage through another data line of the first data line to the fourth data line to select a second viewing angle as the viewing angle of the first sub-pixel to the fourth sub-pixel; a data driver, the data driver is configured to provide a data voltage to the data line; and a mode selection voltage power supply, the mode selection voltage power supply is configured to generate the first mode selection voltage and the second mode selection voltage.

[0029] The mode selection voltage power supply may be embedded in the data driver.

[0030] In the present disclosure, a mode selection voltage can be provided to a pixel through a data line to which a data voltage is applied. Therefore, in the present disclosure, there is no need to add a separate wire for providing the mode selection voltage to the pixel. In addition, in the present disclosure, since the number of wiring lines in the display panel can be reduced, the process of the display panel can be optimized and the yield can be improved.

[0031] In the present disclosure, a separate wiring for supplying a mode selection voltage to a pixel can be minimized, and the viewing angle can be controlled on a pixel basis.

[0032] In the present disclosure, since the viewing angle of pixels arranged in one pixel row can be changed by using a small number of mode selection circuits, the capacitor in the mode selection circuit can be increased.

[0033] The sizes or shapes of the first pixel region driven in the first mode and the second pixel region driven in the second mode may be freely controlled.

[0034] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be apparently understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0036] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0037] Figure 2 is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure;

[0038] Figure 3 is a diagram showing an example of a lens provided on a light emitting element;

[0039] Figure 4 is a circuit diagram showing one embodiment of a pixel circuit in detail;

[0040] Figure 5 is a waveform diagram showing a gating signal and a mode selection voltage generated in a first mode;

[0041] Figure 6 is a waveform diagram showing a strobe signal and a mode selection voltage generated in a second mode;

[0042] 7A to 10B It shows that Figure 5 and Figure 6 The signals shown in the figure are applied to Figure 4 The pixel circuit shown in is a circuit diagram of the step-by-step operation of the pixel circuit;

[0043] Fig.11 is a circuit diagram showing another embodiment of a pixel circuit in detail;

[0044] Fig. 12A and Fig. 12B is a circuit diagram showing an example of first to fourth sub-pixels arranged in one pixel row;

[0045] Fig.13A and Fig. 13B is a circuit diagram showing another example of first to fourth sub-pixels arranged in one pixel row;

[0046] Fig.14 It shows the input to Fig.13A and Fig. 13B , a waveform diagram of an example of a gate signal of a pixel circuit and a MUX signal applied to a MUX switch element;

[0047] Fig.15A and Fig. 15B is a circuit diagram showing an example of a channel in a data driver that outputs a mode selection voltage and a data voltage;

[0048] Fig.16 It is shown from Fig.15A and Fig. 15BAn example waveform diagram of a voltage output by a channel of a data driver shown in ; and

[0049] Fig.17 is a circuit diagram showing a pixel circuit of a sub-pixel supplying a mode selection voltage and a data voltage to a data line without a MUX switching element. DETAILED DESCRIPTION

[0050] According to the embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and the methods for implementing the present disclosure will be more clearly understood. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, the present embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is only limited within the scope of the appended claims.

[0051] The shapes, sizes, ratios, angles, quantities, etc. illustrated in the drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. The same reference numerals generally represent the same elements throughout this specification. In addition, when describing the present disclosure, detailed descriptions of known prior art may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0052] Terms such as “including,” “comprising,” “having,” and “having” used herein are generally intended to allow for the addition of other components unless these terms are used together with the term “only.” Any reference to the singular may include the plural unless expressly stated otherwise.

[0053] Even if not explicitly stated, the components are interpreted as including ordinary error ranges.

[0054] When describing the positional relationship or interconnected relationship between two components, such as "on the top", "above", "below", "beside", "connected or coupled to", "crossing", "intersecting", etc., unless "immediately" or "directly" is used, one or more other components may be inserted between them.

[0055] When describing a temporal precedence relationship, such as "after", "following", "immediately", "before", etc., unless "immediately" or "directly" is used, it may not be continuous on a temporal basis.

[0056] The terms “first”, “second”, etc. may be used to distinguish elements from each other, but the function or structure of a component is not limited by the sequence number preceding the component or the component name.

[0057] The following embodiments may be partially or completely combined or combined with each other, and may be connected and operated in technically different ways. These embodiments may be performed independently or in association with each other.

[0058] The pixel circuit and the gate drive circuit of the display device may include a plurality of transistors. The transistor may be implemented as a thin film transistor (TFT). The transistor may be implemented as an oxide thin film transistor (TFT) including an oxide semiconductor, a low temperature polysilicon TFT (LTPS TFT) including low temperature polysilicon, etc.

[0059] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that provides carriers to the transistor. In a transistor, carriers begin to flow from the source. The drain is the electrode from which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. An n-channel transistor has a direction in which the current flows from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0060] The gating signal swings between a gating on voltage and a gating off voltage. The transistor turns on in response to the gating on voltage and turns off in response to the gating off voltage. In the case of an n-channel transistor, the gating on voltage may be a gating high voltage VGH, and the gating off voltage may be a gating low voltage VGL. In the case of a p-channel transistor, the gating on voltage may be a gating low voltage VGL, and the gating off voltage may be a gating high voltage VGH.

[0061] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0062] Reference Figure 1 , the display device according to the embodiment of the present disclosure includes a display panel 100, and a display panel driving circuit for writing pixel data into pixels of the display panel 100. In addition, the display device includes a power supply 150.

[0063] The display panel 100 may be, but is not limited to, a panel having a rectangular structure having a length along an X-axis direction, a width along a Y-axis direction, and a thickness along a Z-axis direction. For example, the display panel 100 may be a heterogeneous panel at least a portion of which is curved or elliptical.

[0064] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix form. The display panel 100 may also include a power line commonly connected to the pixel. The power line may be commonly connected to the pixel circuit to provide the pixel 101 with a voltage required for driving the pixel 101.

[0065] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel and a blue sub-pixel for color realization. Each pixel can further include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light emitting element. The light emitting element can include an OLED or an inorganic light emitting diode (LED). Each pixel circuit is connected to a data line, a gate line and a power line. In the following description, a pixel can be interpreted as a sub-pixel.

[0066] Pixels may be arranged as real color pixels and P-arranged pixels. P-arranged pixels may achieve a higher resolution than real color pixels by driving two sub-pixels with different colors as one pixel 101 and using a preset pixel rendering algorithm. The pixel rendering algorithm may utilize the color of light emitted from adjacent pixels to compensate for the inadequate color representation in each pixel.

[0067] Each of the pixels may include at least one first light emitting element that emits light in a first mode, and a second light emitting element that emits light in a second mode. Each of the pixels 101 emits light from the first light emitting element at a wide viewing angle in the first mode, while emitting light from the second light emitting element at a narrow viewing angle in the second mode.

[0068] The display area AA includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel row share a gate line 103. Sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0069] The display panel 100 may be implemented with a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and a real object in the background is visible. The display panel 100 may be made of a flexible display panel.

[0070] The power supply 150 receives the input voltage applied from the host system 200, and outputs the voltage required for driving the pixel 101 of the display panel 100 and the display panel driving circuit. To this end, the power supply 150 may include a DC to DC converter (DC-DC converter). The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 150 may output a constant voltage (or DC voltage) through a DC-DC converter, such as a gate-on voltage, a gate-off voltage, a pixel driving voltage, a cathode voltage, a reference voltage, and an IC driving voltage of a display panel driving circuit. The gate-on voltage and the gate-off voltage may be provided to the level shifter 140 and the gate driver 120. Voltages such as the pixel driving voltage, the cathode voltage, and the reference voltage may be provided to the pixel 101 by a power line commonly connected to the pixel 101.

[0071] The power supply 150 may further include a gamma voltage generator. The gamma voltage generator receives a high potential reference voltage and a low potential reference voltage, and outputs a plurality of gamma reference voltages divided at specific intervals on a preset gamma curve (e.g., a 2.2 gamma curve). The gamma reference voltage is provided to the data driver 110. In the data driver 110, the gamma reference voltage is subdivided into grayscale voltages by a voltage divider circuit. The gamma voltage generator may be implemented with a programmable gamma circuit that may adjust the voltage of each of the gamma reference voltages according to digital data. The timing controller 130, the host system 200, or a separate external device may update the digital data stored in the register of the programmable gamma circuit through a communication interface.

[0072] The power supply 150 may include a mode selection voltage generating circuit that outputs a mode selection voltage under the control of the timing controller 130 .

[0073] The display panel driving circuit writes pixel data of an input image into the pixels 101 of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0074] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 1 The data driver 110 and the touch sensor driver may be integrated into one source driver IC.

[0075] The data driver 110 receives pixel data of an input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 may receive a gamma reference voltage through a voltage divider circuit and generate a gamma compensation voltage for each grayscale. The gamma compensation voltage per grayscale is provided to a digital-to-analog converter (hereinafter referred to as a "DAC") provided in each channel of the data driver 110.

[0076] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. In addition, the digital data may include mode selection data for selecting the first mode and the second mode. The DAC converts the pixel data into a gamma compensation voltage and outputs a data voltage of the pixel data. The DAC may convert the mode selection data into a gamma compensation voltage and output a mode selection voltage having different voltage levels in the first mode and the second mode.

[0077] The gate driver 120 may be formed on the display panel 100 together with circuit elements and wiring lines of the display area AA. The gate driver 120 may be disposed in at least one of left and right non-display areas NA outside the display area AA in the display panel 100, or at least a portion thereof may be disposed within the display area AA.

[0078] The gate driver 120 may be disposed in the non-display area NA on both sides of the display panel 100, and provide a gate pulse on both sides of the gate line 103 in a dual-feed manner, wherein the display area AA of the display panel is interposed between the non-display area NA. In another embodiment, the gate driver 120 may be disposed in at least one of the left and right non-display areas NA of the display panel 100, and provide a gate signal to the gate line 103 in a single-feed manner. The gate driver 120 sequentially outputs the pulse of the gate signal to the gate line 103 under the control of the timing controller 130. The gate driver 120 may sequentially provide the gate signal to the gate line 103 by shifting the pulse of the gate signal using a shift register. When a plurality of gate signals are applied to each pixel, the gate driver 120 may include a plurality of shift registers. The gate signal may include a light emitting signal (or an EM signal) and a scan signal input to the pixel circuit through a plurality of gate lines.

[0079] The mode selection voltage may be provided to the data line before the data voltage of the pixel data in each frame period. The mode selection voltage may be generated at different voltage levels in the first mode and the second mode. In the following description, the mode selection voltage indicating the first mode is referred to as the first mode selection voltage, and the mode selection voltage indicating the second mode is referred to as the second mode selection voltage.

[0080] The timing controller 130 receives digital video data of an input image from the host system 200 and a timing signal synchronized with the data. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a cycle of 1 horizontal period (1H). The vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE may be referred to as timing signals Vsync, Hsync, and DE.

[0081] The timing controller 130 may control the display panel driving circuit by generating a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, DE received from the host system 200. The timing controller 130 may synchronize the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0082] The gate timing control signal output from the timing controller 130 may be input to the shift register of the gate driver 120 through the level shifter 140. The level shifter 140 may convert the voltage of the gate timing control signal received from the timing controller 130 into a swing width between a gate-on voltage and a gate-off voltage, and provide it to the gate driver 120.

[0083] The host system 200 may include a mainboard of one of a television system, a set-top box, a navigation system, a personal computer (PC), an in-vehicle system, a mobile terminal, and a wearable terminal. The host system 200 may scale an image signal from a video source according to a resolution of the display panel 100, and may send the image signal together with a timing signal to the timing controller 130.

[0084] The host system 200 may transmit mode signals having different logic values ​​in the first and second modes together with the image signal to the timing controller 130 at least once per frame. The timing controller 130 may control a mode selection voltage output from the power supply 150 or the data driver 110 in response to the mode signal.

[0085] Figure 2 A pixel circuit according to an embodiment of the present disclosure is included.

[0086] Reference Figure 2 , a pixel row of the display panel 100 includes at least one first mode selection circuit 22 and at least one second mode selection circuit 24 .

[0087] A plurality of sub-pixels are disposed on each of the pixel rows L1 to Ln. Each of the sub-pixels may include a plurality of transistors, a plurality of capacitors, and a plurality of light emitting elements. The pixel row may include at least a first sub-pixel PXL1 and a second sub-pixel PXL2.

[0088] The pixel circuit of the first sub-pixel PXL1 includes a first light-emitting element EL1, a second light-emitting element EL2, a driving element DT driving the first light-emitting element EL1 and the second light-emitting element EL2, a compensation circuit 10 connected to the driving element DT, a first switching element M1 connected between the driving element DT and the first light-emitting element EL1, a second switching element M2 connected between the driving element DT and the second light-emitting element EL2, and a first mode selection circuit 22 that receives a first mode selection voltage S to drive the first switching element M1 of the first sub-pixel PXL1 and the second sub-pixel PXL2.

[0089] The pixel circuit of the second sub-pixel PXL2 includes a first light-emitting element EL1, a second light-emitting element EL2, a driving element DT driving the first light-emitting element EL1 and the second light-emitting element EL2, a compensation circuit 10 connected to the driving element DT, a first switching element M1 connected between the driving element DT and the first light-emitting element EL1, a second switching element M2 connected between the driving element DT and the second light-emitting element EL2, and a second mode selection circuit 24 that receives a second mode selection voltage P to drive the second switching element M2 of the first sub-pixel PXL1 and the second sub-pixel PXL2.

[0090] Each of the driving element DT and the switching elements M1 and M2 in the pixel circuit may be implemented with a transistor.

[0091] In each sub-pixel, the driving element DT generates a current according to the gate-source voltage Vgs to drive the first light emitting element EL1 and the second light emitting element EL2. The driving element DT includes a first electrode connected to the first node n1, a gate electrode connected to the second node n2, and a second electrode connected to the third node n3. The pixel driving voltage EVDD may be provided to the first node n1. A switching element (not shown) may be connected between the second electrode of the driving element DT and the third node n3.

[0092] In each sub-pixel, the compensation circuit 10 includes a first capacitor connected to the gate electrode of the driving element DT. The compensation circuit 10 initializes the corresponding pixel circuit and compensates the data voltage Vdata input through the data line DL1 or DL2 by the threshold voltage Vth of the driving element DT.

[0093] The first mode selection circuit 22 includes a second capacitor storing a first mode selection voltage S input through the first data line DL1. The first mode selection circuit 22 drives the first switching element M1 with the first mode selection voltage S. The first mode selection circuit 22 may be connected to two or more or all of the first switching elements M1 arranged on one pixel row to simultaneously turn on the connected switching elements M1.

[0094] The second mode selection circuit 24 includes a third capacitor storing a second mode selection voltage P input through the second data line DL2. The second mode selection circuit 24 drives the second switching element M2 with the second mode selection voltage P. The second mode selection circuit 24 may be connected to two or more or all of the second switching elements M2 arranged on one pixel row to simultaneously turn on the connected switching elements M2.

[0095] Figure 3 2 is a diagram showing an example of a lens provided on a light emitting element.

[0096] Reference Figure 3 , the first lens 32 may be disposed on the first light emitting element EL1. The first lens 32 may be implemented as a semi-cylindrical lens. The first lens 32 may limit the up and down viewing angles and widen the left and right viewing angles. The first lens 32 is longer in the left-right direction (or X-axis direction) of the display panel 100 and narrower in the up and down direction (Y-axis direction), that is, the first lens 32 may be longer in the left-right direction than in the up and down direction.

[0097] The second lens 34 may be disposed on the second light emitting element EL2. The second lens 34 may be a hemispherical lens. The second lens 34 may be thicker in the center and thinner toward the edge, that is, the thickness of the second lens 34 may decrease from the center toward the edge. The second lens 34 may narrow the up-down and left-right viewing angles of the second light emitting element EL2 by focusing the light emitted by the second light emitting element EL2 in the second mode.

[0098] The first lens 32 and the second lens 34 may be implemented by, but not limited to, a transparent medium or a transparent insulating layer pattern disposed in the display panel 100 .

[0099] Figure 4 It is shown in detail Figure 2 A circuit diagram of one embodiment of a pixel circuit is shown. Figure 4 The pixel circuit shown shows a first sub-pixel PXL1 and a second sub-pixel PLX2 arranged on an Nth (N is a natural number) pixel row. Figure 5 is a waveform diagram showing a gate signal and a mode selection voltage generated in a first mode (S mode (SMODE)). Figure 6is a waveform diagram showing a strobe signal and a mode selection voltage generated in the second mode (P mode (PMODE)).

[0100] Reference Figures 4 to 6 , the pixel circuit for each of the sub-pixels PXL1 and PXL2 includes a driving element DT, a first switching element M1, a second switching element M2, a first light emitting element EL1, a second light emitting element EL2, and a compensation circuit 10. It should be noted that the compensation circuit 10 may include, but is not limited to, a first capacitor C1 and third to eighth switching elements M3 to M8.

[0101] The display device of the present disclosure may further include a multiplexer (MUX) connected to the data lines DL1 and DL2. The multiplexer may further include two or more MUX switch elements, for example, a first MUX switch element M9 and a second MUX switch element M10. The first MUX switch element M9 and the second MUX switch element M10 may be disposed in the non-display area NA of the display panel 100, or may be embedded in an integrated circuit (IC) in which a circuit of the data driver 110 is integrated. Figure 4 In the embodiment, the driving element DT and the switching elements M1 to M10 may be implemented by p-channel transistors, but are not limited to p-channel transistors.

[0102] The pixel circuit is connected to the data lines DL1 and DL2 to which the mode selection voltages S and P and the data voltage Vdata are applied, and to the gate lines to which the selection signals SCAN1, SCAN2 and EM are applied. The first subpixel PXL1 receives the first mode selection voltage S and the data voltage Vdata of the pixel data through the first data line DL1. The second subpixel PXL2 receives the second mode selection voltage P and the data voltage Vdata of the pixel data through the second data line DL2.

[0103] The pixel circuits are connected to power lines such as a first power line applied with a pixel driving voltage EVDD, a second power line applied with a cathode voltage EVSS, and a third power line applied with a reference voltage Vref. The power lines on the display panel 100 may be commonly connected to all pixels.

[0104] The pixel driving voltage EVDD is set to a voltage higher than the maximum voltage of the data voltage Vdata, and allows the driving element DT to operate in the saturation region. The pixel driving voltage EVDD is a voltage higher than the cathode voltage EVSS. The reference voltage Vref may be set to a voltage lower than the minimum voltage of the data voltage Vdata and higher than or equal to the cathode voltage EVSS. For example, the reference voltage Vref may be set to, but not limited to, a voltage 1V to 2V higher than the cathode voltage EVSS. The gate-off voltage VGH may be set to a voltage higher than the pixel driving voltage EVDD, and the gate-on voltage VGL may be set to a voltage lower than the cathode voltage EVSS. For example, EVDD=15[V], EVSS=3[V], Vref=3[V], VGH=16[V], VGL=-9[V], but not limited thereto. The data voltage Vdata of the pixel data may have a dynamic range between 2V and 7V. As the grayscale value of the pixel data increases, the voltage level of the data voltage Vdata may be selected to be a low voltage, and the brightness of the light-emitting elements EL1 and EL2 may be increased.

[0105] The mode selection voltages S and P are input to the sub-pixels PXL1 and PXL2 through the data lines DL1 and DL2. The mode selection voltages S and P may swing between a high voltage and a low voltage. In the following description, a low voltage of the mode selection voltage S or P will be described as a gate-on voltage VGL, and a high voltage of the mode selection voltage S or P will be described as a gate-off voltage VGH, but are not limited thereto.

[0106] The first mode selection voltage S and the second mode selection voltage P may be set as shown in Table 1 below.

[0107] [Table 1]

[0108] First Mode Second Mode S On (VGL) Cut-off(VGH) P Cut-off(VGH) On (VGL)

[0109] Each of the first mode selection voltage S and the second mode selection voltage P can be changed in units of one horizontal period (1H). The first mode selection voltage S and the second mode selection voltage P are applied to each of the sub-pixels through the data line 102. To this end, the first pixel area driven in the first mode and the second pixel area driven in the second mode can be freely specified along the X-axis direction (or the gate line direction) and the Y-axis direction (or the data line direction) in the display panel 100. Therefore, the size or shape of the first pixel area and the second pixel area in the display area AA can be freely controlled.

[0110] The selection signals SCAN1, SCAN2, and EM include a first selection signal SCAN1 input to the pixel circuit through a first selection line, a second selection signal SCAN2 input to the pixel circuit through a second selection line, and a third selection signal EM input to the pixel circuit through a third selection line. In this case, the selection driver 120 may include, but is not limited to, a first shift register that sequentially supplies a pulse of the first selection signal SCAN1 to the first selection line, a second shift register that sequentially supplies a pulse of the second selection signal SCAN2 to the second selection line, and a third shift register that sequentially supplies a pulse of the third selection signal EM to the third selection line.

[0111] Pulses of the gate signals SCAN1, SCAN2 and EM swing between a gate-on voltage VGL and a gate-off voltage VGH. The switching elements M1 to M10 and T1 to T4 are turned on by the gate-on voltage VGL applied to the gate electrodes and turned off by the gate-off voltage VGH.

[0112] Each of the first light emitting element EL1 and the second light emitting element EL2 can be implemented with an OLED or an inorganic LED. When the light emitting elements EL1 and EL2 are implemented with OLED, each of the light emitting elements EL1 and EL2 includes an anode, a cathode, and an organic compound layer formed between these electrodes. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The OLED can be implemented in a series structure stacked with a plurality of emitting layers. When each of the first light emitting element EL1 and the second light emitting element EL2 is implemented with an OLED, the OLED may have a stacked structure. The OLED with a series structure can improve the brightness and life of the sub-pixel.

[0113] The anode of the first light emitting element EL1 is connected to the ninth node n9, and the cathode of the first light emitting element EL1 is connected to the second power line to which the cathode voltage EVSS is applied. The anode of the second light emitting element EL2 is connected to the tenth node n10, and the cathode of the second light emitting element EL2 is connected to the second power line.

[0114] The driving element DT generates a current according to the gate-source voltage Vgs to drive the first light emitting element EL1 and the second light emitting element EL2. The driving element DT includes a first electrode connected to a first node n1 to which a pixel driving voltage EVDD is applied, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3. The first capacitor C1 is connected between the second node n2 and a fifth node n5.

[0115] The first switch element M1 is connected between the eighth node n8 and the ninth node n9. The first switch element M1 is turned on according to the gate-on voltage VGL of the first mode selection voltage S to connect the eighth node n8 to the ninth node n9. The first switch element M1 includes a first electrode connected to the eighth node n8, a gate electrode connected to the sixth node n6 to which the first mode selection voltage S is applied, and a second electrode connected to the ninth node n9.

[0116] The second switch element M2 is connected between the eighth node n8 and the tenth node n10. The second switch element M2 is turned on according to the gate-on voltage VGL of the second mode selection voltage P to connect the eighth node n8 to the tenth node n10. The second switch element M2 includes a first electrode connected to the eighth node n8, a gate electrode connected to the seventh node n7 to which the second mode selection voltage P is applied, and a second electrode connected to the tenth node n10.

[0117] The third switching element M3 is connected between the fourth node n4 and the fifth node n5. The third switching element M3 is turned on according to the gate-on voltage VGL of the first selection signal SCAN1 to apply the data voltage Vdata of the pixel data to the first capacitor Cst. The third switching element M3 includes a first electrode connected to the fourth node n4, a gate electrode connected to the first gate line to which the first selection signal SCAN1 is applied, and a second electrode connected to the fifth node n5.

[0118] The fourth switch element M4 is connected between the second node n2 and the third node n3. The fourth switch element M4 is turned on according to the gate-on voltage VGL of the second selection signal SCAN2 to connect the gate electrode and the second electrode of the driving element DT. The fourth switch element M4 includes a first electrode connected to the second node n2, a gate electrode connected to the second selection line to which the second selection signal SCAN2 is applied, and a second electrode connected to the third node n3.

[0119] The fifth switch element M5 is connected between the third power line and the ninth node n9. The fifth switch element M5 is turned on according to the gate-on voltage VGL of the second selection signal SCAN2 to connect the third power line to which the reference voltage Vref is applied to the ninth node n9. The fifth switch element M5 includes a first electrode connected to the third power line, a gate electrode connected to the second selection line to which the second selection signal SCAN2 is applied, and a second electrode connected to the ninth node n9.

[0120] The sixth switch element M6 is connected between the third power line and the tenth node n10. The sixth switch element M6 is turned on according to the gate-on voltage VGL of the second selection signal SCAN2 to connect the third power line applied with the reference voltage Vref to the tenth node n10. The sixth switch element M6 includes a first electrode connected to the third power line, a gate electrode connected to the second selection line applied with the second selection signal SCAN2, and a second electrode connected to the tenth node n10.

[0121] The seventh switch element M7 is connected between the fifth node n5 and the third power line. The seventh switch element M7 is turned on according to the gate-on voltage VGL of the third selection signal EM to connect the fifth node n5 to the third power line. The seventh switch element M7 includes a first electrode connected to the fifth node n5, a gate electrode connected to the third selection line to which the third selection signal EM is applied, and a second electrode connected to the third power line.

[0122] The eighth switch element M8 is connected between the third node n3 and the eighth node n8. The eighth switch element M8 is turned on according to the gate-on voltage VGL of the third selection signal EM to connect the third node n3 to the eighth node n8. The eighth switch element M8 includes a first electrode connected to the third node n3, a gate electrode connected to the third selection line, and a second electrode connected to the eighth node n8.

[0123] The fourth node n4 of the first subpixel PXL1 is connected to the first data line DL1. When the first MUX switch element M9 connected to the first subpixel PXL1 is turned on, the first mode selection voltage S is applied to the first data line DL1. When the second MUX switch element M10 connected to the first channel of the data driver 110 is turned on, the first data voltage Vdata1 charged in the first capacitor C1 of the first subpixel PXL1 is applied to the first data line DL1.

[0124] The first MUX switch element M9 connected to the first subpixel PXL1 includes a first electrode applied with a first mode selection voltage S, a gate electrode applied with a first MUX signal MUX1, and a second electrode connected to the first data line DL1. The first MUX switch element M9 is turned on in response to a gate-on voltage VGL of the first MUX signal MUX1.

[0125] The second MUX switch element M10 connected to the first subpixel PXL1 includes a first electrode applied with a first data voltage Vdata1, a gate electrode applied with a second MUX signal MUX2, and a second electrode connected to the first data line DL1. The second MUX switch element M10 is turned on in response to a gate-on voltage VGL of the second MUX signal MUX2.

[0126] The fourth node n4 of the second subpixel PXL2 is connected to the second data line DL2. When the first MUX switch element M9 connected to the second subpixel PXL2 is turned on, the second mode selection voltage P is applied to the second data line DL2. When the second MUX switch element M10 connected to the second subpixel PXL2 is turned on, the second data voltage Vdata2 charged in the first capacitor C1 of the second subpixel PXL2 is applied to the second data line DL2.

[0127] The first MUX switch element M9 connected to the second subpixel PXL2 includes a first electrode applied with the second mode selection voltage P, a gate electrode applied with the first MUX signal MUX1, and a second electrode connected to the second data line DL2. The first MUX switch element M9 is turned on in response to the gate-on voltage VGL of the first MUX signal MUX1.

[0128] The second MUX switch element M10 connected to the second subpixel PXL2 includes a first electrode to which a second data voltage Vdata2 is applied from the data driver 110, a gate electrode to which a second MUX signal MUX2 is applied, and a second electrode connected to the second data line DL2. The second MUX switch element M10 is turned on in response to the gate-on voltage VGL of the second MUX signal MUX2.

[0129] The timing controller 130 may generate MUX signals MUX1 and MUX2 to control the operation timing of the MUX switch elements M9 and M10. The voltage levels of the MUX signals MUX1 and MUX2 output from the timing controller 130 may be converted by the level shifter 140 and provided to the gate electrodes of the MUX switch elements M9 and M10. When the voltage levels of the MUX signals MUX1 and MUX2 output from the timing controller 130 are a low voltage (0V), the level shifter 140 may output the MUX signals MUX1 and MUX2 as a gate-on voltage VGL. When the voltage levels of the MUX signals MUX1 and MUX2 output from the timing controller 130 are a high voltage (3.3V), the level shifter 140 may output the MUX signals MUX1 and MUX2 as a gate-off voltage VGH.

[0130] The first mode selection circuit 22 may be connected to the fourth node n4 and the sixth node n6 of the first subpixel PXL1, and a third power line to which a reference voltage Vref is applied. The first mode selection circuit 22 may include a first mode switch element T1, a second mode switch element T2, and a second capacitor C2. The first mode switch element T1 and the second mode switch element T2 are connected in series between the fourth node n4 and the sixth node n6.

[0131] The first mode switch element T1 is connected between the fourth node n4 of the first subpixel PXL1 and the second mode switch element T2. The first mode switch element T1 is turned on according to the gate-on voltage VGL of the third selection signal EM to connect the fourth node n4 to the first electrode of the second mode switch element T2. The first mode switch element T1 includes a first electrode connected to the fourth node n4, a gate electrode connected to the third gate line to which the third selection signal EM is applied, and a second electrode connected to the eleventh node n11.

[0132] The second mode switch element T2 is connected between the first mode switch element T1 and the second capacitor C2. The second mode switch element T2 is turned on according to the gate-on voltage VGL of the second selection signal SCAN2 to connect the eleventh node n11 to the second capacitor C2. The second mode switch element T2 includes a first electrode connected to the eleventh node n11, a gate electrode connected to the second gate line to which the second selection signal SCAN2 is applied, and a second electrode connected to the sixth node n6.

[0133] The second capacitor C2 is connected between the sixth node n6 and the third power line, and stores the first mode selection voltage S when the first mode switch element T1 and the second mode switch element T2 are turned on. The first electrode of the second capacitor C2 is connected to the sixth node n6. The second electrode of the second capacitor C2 is connected to the third power line to which the reference voltage Vref is applied. The capacity of the second capacitor C2 may be greater than or equal to the capacity of the first capacitor C1.

[0134] The second mode selection circuit 24 may be connected to the fourth node n4 and the seventh node n7 of the second subpixel PXL2, and a third power line to which a reference voltage Vref is applied. The second mode selection circuit 24 may include a third mode switch element T3, a fourth mode switch element T4, and a third capacitor C3. The third mode switch element T3 and the fourth mode switch element T4 are connected in series between the fourth node n4 and the seventh node n7.

[0135] The third mode switch element T3 is connected between the fourth node n4 of the second subpixel PXL2 and the fourth mode switch element T4. The third mode switch element T3 is turned on according to the gate-on voltage VGL of the third selection signal EM to connect the fourth node n4 to the first electrode of the fourth mode switch element T4. The third mode switch element T3 includes a first electrode connected to the fourth node n4, a gate electrode connected to the third gate line to which the third selection signal EM is applied, and a second electrode connected to the twelfth node n12.

[0136] The fourth mode switch element T4 is connected between the third mode switch element T3 and the third capacitor C3. The fourth mode switch element T4 is turned on according to the gate-on voltage VGL of the second selection signal SCAN2 to connect the twelfth node n12 to the third capacitor C3. The fourth mode switch element T4 includes a first electrode connected to the twelfth node n12, a gate electrode connected to the second selection line to which the second selection signal SCAN2 is applied, and a second electrode connected to the seventh node n7.

[0137] The third capacitor C3 is connected between the seventh node n7 and the third power line, and stores the second mode selection voltage P when the third mode switch element T3 and the fourth mode switch element T4 are turned on. The first electrode of the third capacitor C3 is connected to the seventh node n7. The second electrode of the third capacitor C3 is connected to the third power line to which the reference voltage Vref is applied. The capacity of the third capacitor C3 may be greater than or equal to the capacity of the first capacitor C1, and may be equal to the capacity of the second capacitor C2.

[0138] One frame period of the pixel circuit can be divided into an initialization period INI, a sampling period SAM and a light emitting period EMIS. Figure 5 and Figure 6 The first period may be an initialization period INI, the 2-1 period may be the first half of the sampling period SAM, the 2-2 period may be the second half of the sampling period SAM, and the third period may be a light emitting period EMIS.

[0139] Reference Figure 5 and Figure 6, the voltage of the first MUX signal MUX1 may have a gate-on voltage VGL during the first period, a gate-off voltage VGH during the 2-1 period set after the first period, a gate-off voltage VGH during the 2-2 period set after the 2-1 period, and a gate-off voltage VGH during the third period set after the 2-2 period. The voltage of the second MUX signal MUX2 may have a gate-off voltage VGH during the first period, a gate-on voltage VGL during the 2-1 period, a gate-off voltage VGH during the 2-2 period, and a gate-off voltage VGH during the third period. The first selection signal SCAN1 may have a gate-off voltage VGH during the first period and the 2-1 period, a gate-on voltage VGL during the 2-2 period, and a gate-off voltage VGH during the third period. The second selection signal SCAN2 may have a gate-on voltage VGL during the first period to the 2-2 period, and a gate-off voltage VGH during the third period. The third selection signal EM may have a gate-on voltage VGL during the first period, a gate-off voltage VGH during the 2-1 period and the 2-2 period, and a gate-on voltage VGL during the third period. Here, the first period may be an initialization period. The 2-1 period and the 2-2 period may be sampling periods. The third period may be a light-emitting period.

[0140] exist Figure 5 and Figure 6 In the embodiment, "1H" represents a horizontal period. The sampling period SAM can be divided into a first sampling period t01 and a second sampling period t02. The initialization period INI, the sampling period SAM and the light-emitting period EMIS can be controlled by the waveforms of the selection signals SCAN1, SCAN2 and EM. The selection signals SCAN1, SCAN2 and EM can be generated at the same timing in the first mode and the second mode. The MUX signals MUX1 and MUX2 can be generated at the same timing in the first mode and the second mode.

[0141] 7A to 10B It shows that Figure 5 and Figure 6 The signals shown in the figure are applied to Figure 4 The pixel circuit shown in is a circuit diagram of the step-by-step operation of the pixel circuit. Fig. 7A The operation of the pixel circuit during the first mode initialization period S_INI is shown. Figure 7B The operation of the pixel circuit during the second mode initialization period P_INI is shown. Fig. 8A The operation of the pixel circuit during the first sampling period S_SAM(t01) of the first mode is shown. Figure 8B The operation of the pixel circuit during the second mode first sampling period P_SAM(t01) is shown. Fig. 9AThe operation of the pixel circuit during the first mode second sampling period S_SAM (t02) is shown. Fig. 9B The operation of the pixel circuit during the second sampling period P_SAM(t02) of the second mode is shown. Fig. 10A The operation of the pixel circuit during the first mode light emission period S_EMIS is shown. Fig. 10B The operation of the pixel circuit during the second mode light emission period P_EMIS is shown.

[0142] Reference Figures 5 to 10B During the initialization period S_INI in the first mode, the voltages of the first MUX signal MUX1, the second selection signal SCAN2 and the third selection signal EM have the selection on voltage VGL, and the voltages of the second MUX signal MUX2 and the first selection signal SCAN1 have the selection off voltage VGH. In the first mode, as shown in Tables 1 and Figure 5 As shown, the first mode selection voltage S has a gate-on voltage VGL, and the second mode selection voltage P has a gate-off voltage VGH. Therefore, during the initialization period S_INI in the first mode, as shown in FIG. Fig. 7A As shown, the first switch element M1, the fourth switch element M4 to the eighth switch element M8, the first MUX switch element M9, and the mode switch elements T1 to T4 are turned on, while the second switch element M2, the third switch element M3, and the second MUX switch element M10 are turned off.

[0143] In the initialization period S_INI in the first mode, the gate-on voltage VGL of the first mode selection voltage S is charged in the second capacitor C2, and the gate-off voltage VGH of the second mode selection voltage P is charged in the third capacitor C3. In the initialization period S_INI in the first mode, the voltages of the second node n2, the fifth node n5, the ninth node n9, and the tenth node n10 are initialized to the reference voltage Vref. Due to the voltage of the second capacitor C2 charged during the initialization period S_INI in the first mode, the voltage of the sixth node n6 maintains the gate-on voltage VGL for one frame period. Due to the voltage of the third capacitor C3 charged during the initialization period S_INI in the first mode, the voltage of the seventh node n7 maintains the gate-off voltage VGH for one frame period. Therefore, as Fig. 7A , Fig. 8A , Fig. 9A and Fig. 10A As shown, in the sub-pixels PXL1 and PXL2 driven for one frame period in the first mode, the first switching element M1 is in the on state, and the second switching element M2 is in the off state.

[0144] During the initialization period P_INI in the second mode, the voltages of the first MUX signal MUX1, the second selection signal SCAN2 and the third selection signal EM are the selection on voltage VGL, and the voltages of the second MUX signal MUX2 and the first selection signal SCAN1 are the selection off voltage VGH. In the second mode, as shown in Tables 1 and Figure 6 As shown, the first mode selection voltage S is the gate cut-off voltage VGH, and the second mode selection voltage P is the gate on voltage VGL. Therefore, during the initialization period P_INI in the second mode, as shown in FIG. Figure 7B As shown, the second switch element M2, the fourth switch element M4 to the eighth switch element M8, the first MUX switch element M9, and the mode switch elements T1 to T4 are turned on, while the first switch element M1, the third switch element M3, and the second MUX switch element M10 are turned off.

[0145] In the initialization period P_INI in the second mode, the gate-off voltage VGH of the first mode selection voltage S is charged in the second capacitor C2, and the gate-on voltage VGL of the second mode selection voltage P is charged in the third capacitor C3. In the initialization period P_INI in the second mode, the voltages of the second node n2, the fifth node n5, the ninth node n9, and the tenth node n10 are initialized to the reference voltage Vref. Due to the voltage of the second capacitor C2 charged during the initialization period P_INI in the second mode, the voltage of the sixth node n6 maintains the gate-off voltage VGH for one frame period. Due to the voltage of the third capacitor C3 charged during the initialization period P_INI in the second mode, the voltage of the seventh node n7 maintains the gate-on voltage VGL for one frame period. Therefore, as Figure 7B , Figure 8B , Fig. 9B and Fig. 10B As shown, in the second mode, when the sub-pixels PXL1 and PXL2 are driven for one frame period, the first switching element M1 is in a turned-off state, and the second switching element M2 is in a turned-on state.

[0146] During the first sampling period t01, if Figure 5 and Figure 6 As shown, the voltage of the second MUX signal MUX2 and the second selection signal SCAN2 is the selection on voltage VGL. During the first sampling period t01, the voltage of the first MUX signal MUX1, the first selection signal SCAN1 and the third selection signal EM is the selection off voltage VGH. Therefore, during the first sampling period t01, as shown in FIG. Fig. 8A and Figure 8BAs shown, the fourth switch element M4, the fifth switch element M5 and the sixth switch element M6, the second MUX switch element M10, and the second mode switch element T2 and the fourth mode switch element T4 are turned on. During the first sampling period t01, the third switch element M3, the seventh switch element M7, the eighth switch element M8, the first MUX switch element M9, the first mode switch element T1 and the third mode switch element T3 are turned off.

[0147] During the second sampling period t02, if Figure 5 and Figure 6 As shown, the voltage of the first selection signal SCAN1 and the second selection signal SCAN2 is the selection on voltage VGL. During the second sampling period t02, the voltage of the MUX signals MUX1 and MUX2 and the third selection signal EM is the selection off voltage VGH. Therefore, during the second sampling period t02, as shown in FIG. Fig. 9A and Fig. 9B As shown, the third switch element M3, the fourth switch element M4, the fifth switch element M5 and the sixth switch element M6, the second mode switch element T2 and the fourth mode switch element T4 are turned on. During the second sampling period t02, the seventh switch element M7, the eighth switch element M8, the first MUX switch element M9, the second MUX switch element M10, the first mode switch element T1 and the third mode switch element T3 are turned off.

[0148] During the sampling period SAM, the data voltages Vdata1 and Vdata2 of the pixel data are charged to the data lines DL1 and DL2 through the second MUX switch element M10, and the second node n2 is charged with the pixel drive voltage EVDD through the driving element DT. Parasitic capacitance can be connected to the data lines DL1 and DL2 so that the data voltages Vdata1 and Vdata2 can be charged to the data lines DL1 and DL2. In the first sampling period t01, the driving element DT is turned on. During the sampling period SAM, when the gate voltage of the driving element DT rises and the gate-source voltage Vgs of the driving element DT reaches the threshold voltage Vth, the driving element DT is turned off. When the sampling period SAM ends, the voltages of the data lines DL1 and DL2 are the data voltages Vdata1 and Vdata2 of the pixel data, and the voltage of the second node n2 is EVDD+Vth. Here, "Vth" is the threshold voltage of the driving element DT.

[0149] When the sampling period SAM ends, the voltage of the fifth node n5 is the data voltage Vdata1 or Vdata2, and the voltage of the second node n2 is EVDD+Vth. Therefore, when the sampling period SAM ends, the voltage of the first capacitor C1 is Vdata-(EVDD+Vth). Here, Vdata is Vdata1 or Vdata2.

[0150] When the first sub-pixel PXL1 and the second sub-pixel PXL2 operate in the first mode, during the sampling period SAM, as shown in FIG. Fig. 8A and Fig. 9A As shown, the first switching element M1 maintains a turned-on state due to the gate-on voltage VGL charged in the second capacitor C2, and the second switching element M2 maintains a turned-off state due to the gate-off voltage VGH charged in the third capacitor C3.

[0151] When the first sub-pixel PXL1 and the second sub-pixel PXL2 operate in the second mode, during the sampling period SAM, as shown in FIG. Figure 8B and Fig. 9B As shown, the second switching element M2 maintains a turned-on state due to the gate-on voltage VGL charged in the third capacitor C3, and the first switching element M1 maintains a turned-off state due to the gate-off voltage VGH charged in the second capacitor C2.

[0152] During the emission period EMIS, the voltage of the third selection signal EM is the gate-on voltage VGL, and the voltages of the first selection signal SCAN1 and the second selection signal SCAN2 and the voltages of the MUX signals MUX1 and MUX2 are the gate-off voltage VGH. Fig. 10A and Fig. 10B As shown, the seventh switch element M7, the eighth switch element M8, the first mode switch element T1 and the third mode switch element T3 are turned on. During the light emission period EMIS, the third switch element M3, the fourth switch element M4, the fifth switch element M5 and the sixth switch element M6, the MUX switch elements M9 and M10, the second mode switch element T2 and the fourth mode switch element T4 are turned off.

[0153] When the first subpixel PXL1 and the second subpixel PXL2 operate in the first mode, since the first switch element M1 remains in the on state during the light emission period EMIS, current flows between the pixel driving voltage EVDD and the cathode voltage EVSS, so that the first light emitting element EL1 can emit light. At this time, since the second switch element M2 is in the off state, the second light emitting element EL2 does not emit light.

[0154] During the light emission period S_EMIS in the first mode, the voltage of the fifth node n5 is the reference voltage Vref, and the voltage of the second node n2 is Vref-Vdata+EVDD+Vth. During the light emission period S_EMIS in the first mode, the driving element DT provides the current generated according to the gate-source voltage Vgs to the first light emitting element EL1. During the first mode light emission period S_EMIS, the first light emitting element EL1 emits light having a brightness corresponding to the grayscale value of the pixel data, and the light is emitted at a wide viewing angle through the first lens 32.

[0155] When the first subpixel PXL1 and the second subpixel PXL2 operate in the second mode, since the second switch element M2 remains in the on state during the light emission period EMIS, current flows between the pixel driving voltage EVDD and the cathode voltage EVSS, so that the second light emitting element EL2 can emit light. At this time, since the first switch element M1 is in the off state, the first light emitting element EL1 does not emit light.

[0156] During the light emission period P_EMIS in the second mode, the voltage of the fifth node n5 is the reference voltage Vref, and the voltage of the second node n2 is Vref-Vdata+EVDD+Vth. During the light emission period P_EMIS in the second mode, the driving element DT provides the current generated according to the gate-source voltage Vgs to the second light emitting element EL2. During the second mode light emission period P_EMIS, the second light emitting element EL2 emits light having a brightness corresponding to the grayscale value of the pixel data, and the light is emitted at a narrow viewing angle through the second lens 34.

[0157] Fig.11 is a circuit diagram showing another embodiment of a pixel circuit in detail. Fig.11 In the pixel circuit shown, Figure 4 Elements that are substantially the same as elements in the illustrated pixel circuit will be given the same reference numerals, and a detailed description thereof will be omitted. Fig.11 One frame period of the pixel circuit shown in FIG. 1 can be divided into an initialization period INI, a sampling period SAM and a light emission period EMIS. Figure 5 and Figure 6 As shown. Figure 5 The signal shown is applied to Fig.11 When the pixel circuit is shown, the pixel circuit operates in the first mode. Figure 6 The signal shown is applied to Fig.11 When the pixel circuit is shown, the pixel circuit operates in the second mode.

[0158] Reference Fig.11The pixel circuit of each of the sub-pixels PXL1 and PXL2 includes a driving element DT, a first switching element M1, a second switching element M2, a first light emitting element EL1, a second light emitting element EL2 and a compensation circuit 10. The compensation circuit 10 may include but is not limited to a first capacitor C1 and third to eighth switching elements M3 to M8.

[0159] The display device of the present disclosure may further include MUX switch elements M9 and M10 connected to the data lines DL1 and DL2 .

[0160] The first pixel circuit may further include a first mode selection circuit 22. The first mode selection circuit 22 may be connected to the fourth node n4 and the sixth node n6 of the first subpixel PXL1 and the first power line to which the pixel driving voltage EVDD is applied. The first mode selection circuit 22 may include a first mode switch element T1, a second mode switch element T2, and a second capacitor C2.

[0161] The second capacitor C2 is connected between the sixth node n6 and the first power line, and stores the first mode selection voltage S when the first mode switch element T1 and the second mode switch element T2 are turned on. The first electrode of the second capacitor C2 is connected to the sixth node n6. The second electrode of the second capacitor C2 is connected to the first power line to which the pixel driving voltage EVDD is applied. The capacity of the second capacitor C2 may be greater than or equal to the capacity of the first capacitor C1.

[0162] The second pixel circuit may further include a second mode selection circuit 24. The second mode selection circuit 24 may be connected to the fourth node n4 and the seventh node n7 of the second subpixel PXL2 and the first power line to which the pixel driving voltage EVDD is applied. The second mode selection circuit 24 may include a third mode switch element T3, a fourth mode switch element T4 and a third capacitor C3.

[0163] The third capacitor C3 is connected between the seventh node n7 and the first power line, and stores the second mode selection voltage P when the third mode switch element T3 and the fourth mode switch element T4 are turned on. The first electrode of the third capacitor C3 is connected to the seventh node n7. The second electrode of the third capacitor C3 is connected to the first power line to which the pixel driving voltage EVDD is applied. The capacity of the third capacitor C3 may be greater than or equal to the capacity of the first capacitor C1, and may be equal to the capacity of the second capacitor C2.

[0164] In addition to the reference voltage of the second capacitor C2 and the third capacitor C3 being changed to the pixel driving voltage EVDD, Fig.11 The operation of the pixel circuit shown is similar to 7A to 10B Similar, and its detailed description will be omitted.

[0165] Fig. 12A and Fig. 12B is a circuit diagram showing an example of first to fourth sub-pixels PXL1 to PXL4 arranged on one pixel row. Fig. 12A and Fig. 12B In FIG. 1 , the sixth node n6 of the second subpixel PXL2 and the third subpixel PXL3 are connected at “A”. The seventh node n7 of the second subpixel PXL2 and the third subpixel PXL3 are connected at “B”. Fig. 12A and Fig. 12B In the pixel circuit shown, Figure 4 Elements that are substantially the same as those in the pixel circuit shown in FIG. 1 will be given the same reference numerals, and their detailed description will be omitted. Fig. 12A and Fig. 12B One frame period of the pixel circuit shown in FIG. 1 is divided into an initialization period INI, a sampling period SAM, and a light emission period EMIS. Figure 5 and Figure 6 As shown. Figure 5 The signal shown is applied to Fig. 12A and Fig. 12B When the first to fourth sub-pixels PXL1 to PXL4 are shown, the first to fourth sub-pixels PXL1 to PXL4 operate in the first mode. Figure 6 The signal shown is applied to Fig. 12A and Fig. 12B When the first to fourth sub-pixels PXL1 to PXL4 are shown, the first to fourth sub-pixels PXL1 to PXL4 operate in the second mode.

[0166] Reference Fig. 12A and Fig. 12B The pixel circuit of the first sub-pixel PXL1 includes a first light-emitting element EL1, a second light-emitting element EL2, a driving element DT driving the first light-emitting element EL1 and the second light-emitting element EL2, a compensation circuit 10 connected to the driving element DT, a first switching element M1 connected between the driving element DT and the first light-emitting element EL1, a second switching element M2 connected between the driving element DT and the second light-emitting element EL2, and a first mode selection circuit 22 that receives a first mode selection voltage S to drive the first switching element M1 of the first sub-pixel PXL1 to the fourth sub-pixel PXL4.

[0167] The pixel circuit of the second sub-pixel PXL2 includes a first light-emitting element EL1, a second light-emitting element EL2, a driving element DT driving the first light-emitting element EL1 and the second light-emitting element EL2, a compensation circuit 10 connected to the driving element DT, a first switching element M1 connected between the driving element DT and the first light-emitting element EL1, a second switching element M2 connected between the driving element DT and the second light-emitting element EL2, and a second mode selection circuit 24 that receives a second mode selection voltage P to drive the second switching element M2 of the first sub-pixel PXL1 to the fourth sub-pixel PXL4.

[0168] The pixel circuit of each of the third subpixel PXL3 and the fourth subpixel PXL4 includes a first light emitting element EL1, a second light emitting element EL2, a driving element DT driving the first light emitting element EL1 and the second light emitting element EL2, a compensation circuit 10 connected to the driving element DT, a first switching element M1 connected between the driving element DT and the first light emitting element EL1, and a second switching element M2 connected between the driving element DT and the second light emitting element EL2. The pixel circuit of the third subpixel PXL3 and the fourth subpixel PXL4 can be connected to the mode selection circuit 22 of the first subpixel PXL1 and the mode selection circuit 24 of the second subpixel PXL2 without a separate mode selection circuit.

[0169] The first mode selection circuit 22 may be connected to the sixth node n6 of the first to fourth subpixels PXL1 to PXL4 to drive the first switching element M1. The second mode selection circuit 24 may be connected to the seventh node n7 of the first to fourth subpixels PXL1 to PXL4 to drive the second switching element M2 of the first to fourth subpixels PXL1 to PXL4.

[0170] Fig.13A and Fig. 13B is a circuit diagram showing another example of the first to fourth sub-pixels PXL1 to PXL4 arranged on one pixel row. Fig.13A and Fig. 13B In FIG. 1 , the sixth node n6 of the second subpixel PXL2 and the third subpixel PXL3 are connected at “A”. The seventh node n7 of the second subpixel PXL2 and the third subpixel PXL3 are connected at “B”. Fig.13A and Fig. 13B In the pixel circuit shown, Figure 4 Elements that are substantially the same as elements in the illustrated pixel circuit will be given the same reference numerals, and a detailed description thereof will be omitted. Fig.13A and Fig. 13B One frame period of the pixel circuit shown in FIG. 1 is divided into an initialization period INI, a sampling period SAM, and a light emission period EMIS. Figure 5 and Figure 6 shown. Fig.14 The signals shown can be applied to Fig.13A and Fig. 13B The first to fourth sub-pixels PXL1 to PXL4 are shown in FIG.

[0171] Reference Fig.13A and Fig. 13B , the display device of the present disclosure may further include a first MUX switch element M9, a second MUX switch element M10, and a third MUX switch element M11 connected to the data lines DL1 to DL4. The first MUX switch element M9, the second MUX switch element M10, and the third MUX switch element M11 may be arranged in the non-display area NA of the display panel 100, or may be embedded in an integrated circuit (IC) in which a circuit of the data driver 110 is integrated.

[0172] The first subpixel PXL1 includes a first light-emitting element EL1, a second light-emitting element EL2, a driving element DT driving the first light-emitting element EL1 and the second light-emitting element EL2, a compensation circuit 10 connected to the driving element DT, a first switching element M1 connected between the driving element DT and the first light-emitting element EL1, a second switching element M2 connected between the driving element DT and the second light-emitting element EL2, and a first mode selection circuit 22 that receives a first mode selection voltage S to drive the first switching element M1 of the first subpixel PXL1 to the fourth subpixel PXL4.

[0173] The third sub-pixel PXL3 includes a first light-emitting element EL1, a second light-emitting element EL2, a driving element DT driving the first light-emitting element EL1 and the second light-emitting element EL2, a compensation circuit 10 connected to the driving element DT, a first switching element M1 connected between the driving element DT and the first light-emitting element EL1, a second switching element M2 connected between the driving element DT and the second light-emitting element EL2, and a second mode selection circuit 24 receiving a second mode selection voltage P to drive the second switching element M2 of the sub-pixels PXL1 to PXL4.

[0174] The pixel circuit of each of the second sub-pixel PXL2 and the fourth sub-pixel PXL4 includes a first light emitting element EL1, a second light emitting element EL2, a driving element DT driving the first light emitting element EL1 and the second light emitting element EL2, a compensation circuit 10 connected to the driving element DT, a first switching element M1 connected between the driving element DT and the first light emitting element EL1, and a second switching element M2 connected between the driving element DT and the second light emitting element EL2. Since the pixel circuits of the second sub-pixel PXL2 and the fourth sub-pixel PXL4 share the mode selection circuits 22 and 24 of other sub-pixels arranged in the same pixel circuit, they do not need to be connected to a separate mode selection circuit.

[0175] The first mode selection circuit 22 may be connected to the sixth node n6 of the first to fourth subpixels PXL1 to PXL4 to drive the first switching element M1. The second mode selection circuit 24 may be connected to the seventh node n7 of the first to fourth subpixels PXL1 to PXL4 to drive the second switching element M2.

[0176] The first channel of the data driver 110 may sequentially output a first data voltage Vdata1 and a second data voltage Vdata2. The second channel of the data driver 110 may sequentially output a third data voltage Vdata3 and a fourth data voltage Vdata4.

[0177] The fourth node n4 of the first subpixel PXL1 is connected to the first data line DL1. Fig.13A As shown. When the first MUX switch element M9 connected to the first subpixel PXL1 is turned on, the first mode selection voltage S is applied to the first data line DL1. When the second MUX switch element M10 connected to the first subpixel PXL1 is turned on, the first data voltage Vdata1 is applied to the first data line DL1. When the third MUX switch element M11 connected to the second subpixel PXL2 is turned on, the second data voltage Vdata2 is applied to the second data line DL2.

[0178] The first MUX switch element M9 connected to the first subpixel PXL1 includes a first electrode applied with a first mode selection voltage S, a gate electrode applied with a first MUX signal MUX1, and a second electrode connected to the first data line DL1. The first MUX switch element M9 is turned on in response to a gate-on voltage VGL of the first MUX signal MUX1.

[0179] The second MUX switch element M10 connected to the first subpixel PXL1 includes a first electrode connected to the first channel of the data driver 110, a gate electrode to which the second MUX signal MUX2 is applied, and a second electrode connected to the first data line DL1. The second MUX switch element M10 is turned on in response to the gate-on voltage VGL of the second MUX signal MUX2.

[0180] The third MUX switch element M11 connected to the second subpixel PXL2 includes a first electrode connected to the first channel of the data driver 110, a gate electrode to which the third MUX signal MUX3 is applied, and a second electrode connected to the second data line DL2. The third MUX switch element M11 is turned on in response to the gate-on voltage VGL of the third MUX signal MUX3.

[0181] The fourth node n4 of the third sub-pixel PXL3 is connected to the third data line DL3. Fig. 13B As shown. When the first MUX switch element M9 connected to the third subpixel PXL3 is turned on, the second mode selection voltage P is applied to the third data line DL3. When the second MUX switch element M10 connected to the third subpixel PXL3 is turned on, the third data voltage Vdata3 is applied to the third data line DL3. When the third MUX switch element M11 connected to the fourth subpixel PXL4 is turned on, the fourth data voltage Vdata4 is applied to the fourth data line DL4.

[0182] The first MUX switch element M9 connected to the third subpixel PXL3 includes a first electrode applied with the second mode selection voltage P, a gate electrode applied with the first MUX signal MUX1, and a second electrode connected to the third data line DL3. The first MUX switch element M9 is turned on in response to the gate-on voltage VGL of the first MUX signal MUX1.

[0183] The second MUX switch element M10 connected to the third subpixel PXL3 includes a first electrode connected to the second channel of the data driver 110, a gate electrode to which the second MUX signal MUX2 is applied, and a second electrode connected to the third data line DL3. The second MUX switch element M10 is turned on in response to the gate-on voltage VGL of the second MUX signal MUX2.

[0184] The third MUX switch element M11 connected to the fourth subpixel PXL4 includes a first electrode connected to the second channel of the data driver 110, a gate electrode to which the third MUX signal MUX3 is applied, and a second electrode connected to the fourth data line DL4. The third MUX switch element M11 is turned on in response to the gate-on voltage VGL of the third MUX signal MUX3.

[0185] Fig.13A and Fig. 13B One frame period of the sub-pixels PXL1 to PXL4 shown in FIG. 1 may be divided into an initialization period INI, a sampling period SAM, and a light emission period EMIS. Fig.14 As shown. Fig.14 In the table, "1H" means one horizontal period. Fig.14 As shown, the sampling period SAM can be divided into a first sampling period t01, a second sampling period t02 and a third sampling period t03. The initialization period INI, the sampling period SAM and the light-emitting period EMIS can be controlled by the waveforms of the selection signals SCAN1, SCAN2 and EM. The selection signals SCAN1, SCAN2 and EM can be generated at the same timing in the first mode and the second mode. The selection signals MUX1, MUX2 and MUX3 can be generated at the same timing in the first mode and the second mode.

[0186] Fig.14 It shows the input to Fig.13A and Fig. 13B 2 is a waveform diagram of an example of a selection signal of a pixel circuit and a MUX signal applied to a MUX switch element. Fig.14 , the first mode selection voltage S and the second mode selection voltage P are not shown. The first mode selection voltage S and the second mode selection voltage P can be generated in each mode, as shown in Table 1. In the first mode, the first mode selection voltage S is the gate-on voltage VGL, and the second mode selection voltage P is the gate-off voltage VGH. In the second mode, the first mode selection voltage S is the gate-off voltage VGH, and the second mode selection voltage P is the gate-on voltage VGL.

[0187] Reference Fig.13A , Fig. 13B and Fig.14 During the initialization period, the voltages of the first MUX signal MUX1, the second selection signal SCAN2, and the third selection signal EM have the selection-on voltage VGL, and the voltages of the second MUX signal MUX2 and the third MUX signal MUX3 and the voltage of the first selection signal SCAN1 have the selection-off voltage VGH. Therefore, during the initialization period INI, the fourth to eighth switching elements M4 to M8, the first MUX switching element M9, and the mode switching elements T1 to T4 are turned on, while the third switching element M3 and the second and third MUX switching elements M10 and M11 are turned off.

[0188] In the initialization period INI in the first mode, the first switch element M1 is turned on in response to the gate-on voltage VGL of the first mode selection voltage S, and the second switch element M2 is turned off in response to the gate-off voltage VGH of the second mode selection voltage P. In the initialization period INI in the second mode, the second switch element M2 is turned on in response to the gate-on voltage VGL of the second mode selection voltage P, and the first switch element M1 is turned off in response to the gate-off voltage VGH of the first mode selection voltage S.

[0189] During the sampling period SAM in the first mode, the first mode selection voltage S is the gate-on voltage VGL, and the second mode selection voltage P is the gate-off voltage VGH. Therefore, during the sampling period SAM in the first mode, the first switch element M1 is in the on state, and the second switch element M2 is in the off state. During the sampling period SAM in the second mode, the first mode selection voltage S is the gate-off voltage VGH, and the second mode selection voltage P is the gate-on voltage VGL. Therefore, during the sampling period SAM in the second mode, the first switch element M1 is in the off state, and the second switch element M2 is in the on state.

[0190] During the first sampling period t01, the voltages of the second MUX signal MUX2 and the third MUX signal MUX3 and the voltage of the second selection signal SCAN2 are the selection-on voltage VGL. During the first sampling period t01, the voltages of the first MUX signal MUX1, the first selection signal SCAN1 and the third selection signal EM are the selection-off voltage VGH. Therefore, during the first sampling period t01, the fourth switch element M4, the fifth switch element M5 and the sixth switch element M6, the second MUX switch element M10, the third MUX switch element M11, the second mode switch element T2 and the fourth mode switch element T4 are turned on. During the first sampling period t01, the third switch element M3, the seventh switch element M7, the eighth switch element M8, the first MUX switch element M9, the first mode switch element T1 and the third mode switch element T3 are turned off.

[0191] During the second sampling period t02, the voltages of the third MUX signal MUX3 and the second selection signal SCAN2 are the selection-on voltage VGL. During the second sampling period t02, the voltages of the first MUX signal MUX1, the second MUX signal MUX2, the first selection signal SCAN1 and the third selection signal EM are the selection-off voltage VGH. Therefore, during the second sampling period t02, the fourth switch element M4, the fifth switch element M5 and the sixth switch element M6, the third MUX switch element M11, the second mode switch element T2 and the fourth mode switch element T4 are turned on. During the second sampling period t02, the third switch element M3, the seventh switch element M7, the eighth switch element M8, the first MUX switch element M9, the second MUX switch element M10, the first mode switch element T1 and the third mode switch element T3 are turned off.

[0192] During the third sampling period t03, the voltage of the first selection signal SCAN1 and the second selection signal SCAN2 is the gate-on voltage VGL. During the third sampling period t03, the voltage of the MUX signals MUX1, MUX2 and MUX3 and the third selection signal EM is the gate-off voltage VGH. Therefore, during the third sampling period t03, the third switch element M3, the fourth switch element M4, the fifth switch element M5 and the sixth switch element M6, the second mode switch element T2 and the fourth mode switch element T4 are turned on. During the third sampling period t03, the seventh switch element M7, the eighth switch element M8, the MUX switch elements M9, M10 and M11, the first mode switch element T1 and the third mode switch element T3 are turned off.

[0193] During the sampling period SAM, the data voltages Vdata1 to Vdata4 of the pixel data are charged to the data lines DL1 to DL4 through the second MUX switch element M10 and the third MUX switch element M11, and the second node n2 is charged with the pixel driving voltage EVDD through the driving element DT. During the sampling period SAM, when the gate voltage of the driving element DT rises and the gate-source voltage Vgs of the driving element DT reaches the threshold voltage Vth, the driving element DT is turned off.

[0194] During the light-emitting period EMIS in the first mode, the first mode selection voltage S is the gate-on voltage VGL, and the second mode selection voltage P is the gate-off voltage VGH. Therefore, during the light-emitting period EMIS in the first mode, the first switch element M1 is in the on state, and the second switch element M2 is in the off state. During the light-emitting period EMIS in the second mode, the first mode selection voltage S is the gate-off voltage VGH, and the second mode selection voltage P is the gate-on voltage VGL. Therefore, during the light-emitting period EMIS in the second mode, the first switch element M1 is in the off state, and the second switch element M2 is in the on state.

[0195] During the light emission period EMIS, the voltage of the third selection signal EM is the gate-on voltage VGL, and the voltages of the first selection signal SCAN1 and the second selection signal SCAN2 and the voltages of the MUX signals MUX1 and MUX2 are the gate-off voltage VGH. Therefore, during the light emission period EMIS, the seventh switch element M7, the eighth switch element M8, the first mode switch element T1 and the third mode switch element T3 are turned on. During the light emission period EMIS, the third switch element M3 to the sixth switch element M6, the MUX switch elements M9 and M10, the second mode switch element T2 and the fourth mode switch element T4 are turned off.

[0196] when Fig.13A When the first subpixel PXL1 and the second subpixel PXL2 shown in FIG. 1 are operated in the first mode, since the first switch element M1 remains in the on state during the light emission period EMIS, current flows between the pixel driving voltage EVDD and the cathode voltage EVSS, so that the first light emitting element EL1 can emit light. At this time, since the second switch element M2 is in the off state, the second light emitting element EL2 does not emit light.

[0197] When the first subpixel PXL1 and the second subpixel PXL2 operate in the second mode, since the second switch element M2 remains in the on state during the light emission period EMIS, current flows between the pixel driving voltage EVDD and the cathode voltage EVSS, so that the second light emitting element EL2 can emit light. At this time, since the first switch element M1 is in the off state, the first light emitting element EL1 does not emit light.

[0198] when Fig. 13B When the third sub-pixel PXL3 and the fourth sub-pixel PXL4 shown in FIG. 1 are operated in the first mode, since the first switch element M1 remains in the on state during the light emission period EMIS, current flows between the pixel driving voltage EVDD and the cathode voltage EVSS, so that the first light emitting element EL1 can emit light. At this time, since the second switch element M2 is in the off state, the second light emitting element EL2 does not emit light.

[0199] When the third subpixel PXL3 and the fourth subpixel PXL4 operate in the second mode, since the second switch element M2 remains in the on state during the light emission period EMIS, current flows between the pixel driving voltage EVDD and the cathode voltage EVSS, so that the second light emitting element EL2 can emit light. At this time, since the first switch element M1 is in the off state, the first light emitting element EL1 does not emit light.

[0200] The data driver 110 may sequentially output the mode selection voltages S and P and the data voltage Vdata through a channel electrically connected to the compensation circuit 10 and the mode selection circuits 22 and 24. In this case, since the mode selection voltages S and P and the data voltage Vdata output from the data driver 110 may be directly provided to the data lines, the MUX switching element may be omitted.

[0201] Fig.15A and Fig. 15B is a circuit diagram showing an example of a channel through which a mode selection voltage and a data voltage are output from the data driver 110 . Fig.16 It is shown from Fig.15A and Fig. 15B 2 is a waveform diagram showing an example of a voltage output by a channel of the data driver 110. FIG. 15A to FIG. 16 In FIG. 1 , “OUT” is the output voltage of the data driver 110 .

[0202] Reference Fig.15A and Fig. 15B The data driver 110 includes a DAC 52, a mode selection voltage generator 54, a first output switching element S01, and a second output switching element S02. The mode selection voltage generator 54 can output a first mode selection voltage S and a second mode selection voltage P by using, but not limited to, a level shifter that shifts an input voltage level.

[0203] Figure 1 The timing controller 130 shown may send digital data MDATA indicating the first mode and the second mode and pixel data (digital data) VDATA of the input image to the data driver 110. The logic circuit of the data driver 110 or the timing controller 130 may generate switch control signals SW1 and SW2 to control Fig.15A and Fig. 15B The output switching elements S01 and S02 are shown.

[0204] The DAC 52 of the data driver 110 converts the digital data MDATA received from the timing controller 130 into a gamma compensation voltage. When the dynamic range of the data voltage Vdata output from the data driver 110 is 2V to 7V, if the digital data MDATA indicates a low logic voltage, the DAC may output a first voltage of 2V to 4V, and if the digital data MDATA indicates a high logic voltage, the DAC may output a second voltage of 6V to 7V. When the output voltage of the DAC 52 is the first voltage, the mode selection voltage generator 54 may output a gate-on voltage VGL, and when the output voltage of the DAC 52 is the second voltage, the mode selection voltage generator 54 may output a gate-off voltage VGH.

[0205] The DAC 52 converts the pixel data VDATA received from the timing controller 130 into a gamma compensation voltage. A voltage corresponding to the grayscale value of the pixel data VDATA may be output from the DAC 52 within a dynamic range of 2V to 7V.

[0206] Reference Fig.15A and Fig.16 During the initialization period INI, the first output switching element S01 is turned on in response to the on voltage level of the first switching signal SW1, and the second output switching element S02 is turned off in response to the off voltage level of the second switching signal SW2. Therefore, during the initialization period INI, the mode selection voltages S and P from the mode selection voltage generator 54 can be output from the data driver 110.

[0207] Reference Fig. 15B and Fig.16 During the sampling period SAM and the emission period EMIS, the first output switch element S01 is turned off in response to the cut-off voltage level of the first switch signal SW1, and the second output switch element S02 is turned on in response to the on voltage level of the second switch signal SW2. Therefore, during the sampling period SAM and the emission period EMIS, the data voltage Vdata from the DAC can be output from the data driver 110.

[0208] The mode selection voltages S and P and the data voltage Vdata outputted from the data driver 110 may be directly supplied to the data lines, such as Fig.17 shown.

[0209] Reference Fig.17 , the first subpixel PXL1 is connected to the first data line DL1. The first channel of the data driver 110 may be connected to the first data line DL1. The first mode selection voltage S and the first data voltage Vdata1 outputted from the first channel of the data driver 110 may be sequentially applied to the first data line DL1.

[0210] The first subpixel PXL1 may include a first mode selection circuit 22. The first mode selection circuit 22 charges the second capacitor C2 with the first mode selection voltage S received during the initialization period INI to drive the plurality of first switching elements M1 connected to the sixth node n6. During the sampling period SAM, the first data voltage Vdata1 may be applied to the first capacitor C1 and the gate electrode of the driving element DT through the third switching element M3.

[0211] The second subpixel PXL2 is connected to the second data line DL2. The second channel of the data driver 110 may be connected to the second data line DL2. The second mode selection voltage P and the second data voltage Vdata2 outputted from the second channel of the data driver 110 may be sequentially applied to the second data line DL2.

[0212] The second subpixel PXL2 may include a second mode selection circuit 24. The second mode selection circuit 24 charges the third capacitor C3 with the second mode selection voltage P received during the sampling period SAM to drive the plurality of second switching elements M2 connected to the seventh node n7. During the sampling period SAM, the second data voltage Vdata2 may be applied to the first capacitor C1 and the gate electrode of the driving element DT through the third switching element M3.

[0213] In addition, the mode selection circuits 22 and 24 can be shared not only by a plurality of sub-pixels arranged in one pixel row in the above-described embodiment, but also between pixel rows. For example, the mode selection circuits 22 and 24 can change the viewing angle of two or more sub-pixels arranged on one pixel row, and can also change the viewing angle of two or more sub-pixels arranged on two or more pixel rows.

[0214] According to one or more embodiments of the present disclosure, the display device can be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a bending device, a sliding device, a variable device, an electronic organizer, an electronic book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, a navigation device, a vehicle navigation device, a vehicle display device, a vehicle device, a theater device, a theater display device, a television, a wallpaper device, a sign device, a game device, a notebook computer, a monitor, a camera, a camcorder, and a home appliance, etc. In addition, the display device according to one or more embodiments of the present disclosure can be applied to an organic light emitting lighting device or an inorganic light emitting lighting device.

[0215] The objects to be achieved by the present disclosure, means for achieving the objects, and the effects of the present disclosure described above do not specify essential features of the claims, and therefore, the scope of the claims is not limited to the disclosed contents of the present disclosure.

[0216] Further implementation methods are described in the following clauses:

[0217] 1. A display panel, comprising: a first mode selection circuit, the first mode selection circuit being configured to receive a first mode selection voltage through a first data line to select a first viewing angle as a viewing angle of one or more sub-pixels; and a second mode selection circuit, the second mode selection circuit being configured to receive a second mode selection voltage through a second data line to select a second viewing angle as a viewing angle of one or more sub-pixels.

[0218] 2. According to the display panel described in clause 1, the display panel also includes: a plurality of sub-pixels, wherein each of the sub-pixels includes: a first light-emitting element; a second light-emitting element; a driving element, the driving element driving the first light-emitting element and the second light-emitting element; a compensation circuit, the compensation circuit including a first capacitor connected to the driving element; a first switching element, the first switching element being electrically connected to the driving element and the first light-emitting element and being driven by the first mode selection voltage; and a second switching element, the second switching element being electrically connected to the driving element and the second light-emitting element and being driven by the second mode selection voltage.

[0219] 3. A display panel according to claim 2, wherein: a first sub-pixel includes the first mode selection circuit; a second sub-pixel includes the second mode selection circuit; the first mode selection circuit is electrically connected to the first data line and the compensation circuit inside the first sub-pixel to provide the first mode selection voltage to the gate electrode of the first switching element arranged in the first sub-pixel and the second sub-pixel; and the second mode selection circuit is electrically connected to the second data line and the compensation circuit inside the second sub-pixel to provide the second mode selection voltage to the gate electrode of the second switching element arranged in the first sub-pixel and the second sub-pixel.

[0220] 4. The display panel according to clause 2 or clause 3, wherein: the first mode selection circuit includes a second capacitor to which the first mode selection voltage is applied; and the second mode selection circuit includes a third capacitor to which the second mode selection voltage is applied.

[0221] 5. A display panel according to clause 3, wherein: the first mode selection circuit includes: a first mode switch element, the first mode switch element is electrically connected to the first data line; a second capacitor, the second capacitor is connected to the gate electrode of the first switch element arranged in the first sub-pixel and the second sub-pixel to receive the applied first mode selection voltage; and a second mode switch element, the second mode switch element is connected between the first mode switch element and the second capacitor; and the second mode selection circuit includes: a third mode switch element, the third mode switch element is electrically connected to the second data line; a third capacitor, the third capacitor is connected to the gate electrode of the second switch element arranged in the first sub-pixel and the second sub-pixel to receive the applied second mode selection voltage; and a fourth mode switch element, the fourth mode switch element is connected between the third mode switch element and the third capacitor.

[0222] 6. A display panel according to any one of clauses 2 to 5, wherein: when the first switching element is turned on in response to the on-voltage of the first mode selection voltage, the first light-emitting element emits light; when the second switching element is turned on in response to the on-voltage of the second mode selection voltage, the second light-emitting element emits light; the first switching element is turned off according to the on-off voltage of the first mode selection voltage; and the second switching element is turned off according to the on-off voltage of the second mode selection voltage.

[0223] 7. A display panel according to clause 4 or clause 5 or clause 6 referring to clause 4 or clause 5, wherein the display panel further comprises: a 1-1MUX switch element connected to the first data line to provide the first mode selection voltage to the first data line; a 1-2MUX switch element connected to the first data line to provide the first data voltage to be charged in the first capacitor of the first sub-pixel to the first data line; a 2-1MUX switch element connected to the second data line to provide the second mode selection voltage to the second data line; and a 2-2MUX switch element connected to the second data line to provide the second data line with the second data voltage to be charged in the first capacitor of the second sub-pixel.

[0224] 8. A display panel according to clause 7, wherein after the 1-1MUX switch element and the 2-1MUX switch element are simultaneously turned on in response to the gate-on voltage of the first MUX signal, the 1-2MUX switch element and the 2-2MUX switch element are simultaneously turned on in response to the gate-on voltage of the second MUX signal.

[0225] 9. A display panel according to clause 7 or clause 8, wherein the display panel further includes a third sub-pixel and a fourth sub-pixel, wherein the first mode selection circuit is connected to the first data line of the first sub-pixel, the compensation circuit of the first sub-pixel, and the gate electrodes of the first switching elements of the first sub-pixel to the fourth sub-pixel, and wherein the second mode selection circuit is connected to the second data line of the second sub-pixel, the compensation circuit of the second sub-pixel, and the gate electrodes of the second switching elements of the first sub-pixel to the fourth sub-pixel.

[0226] 10. A display panel according to clause 9, wherein each of the first to fourth sub-pixels comprises: a driving element, the driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node; a third switching element, the third switching element comprising a first electrode connected to a fourth node, a gate electrode to which a first selection signal is applied, and a second electrode connected to a fifth node; a fourth switching element, the fourth switching element comprising a first electrode connected to the second node, a gate electrode to which a second selection signal is applied, and a second electrode connected to the third node; a fifth switching element, the fifth switching element comprising a first electrode connected to the second node, a gate electrode to which a second selection signal is applied, and a second electrode connected to the third node; The element includes a first electrode applied with a reference voltage, a gate electrode applied with the second selection signal, and a second electrode connected to a ninth node; a sixth switching element, the sixth switching element includes a first electrode applied with the reference voltage, a gate electrode applied with the second selection signal, and a second electrode connected to a tenth node; a seventh switching element, the seventh switching element includes a first electrode connected with the fifth node, a gate electrode applied with a third selection signal, and a second electrode applied with the reference voltage; and an eighth switching element, the eighth switching element includes a first electrode connected with the third node, a gate electrode applied with the third selection signal, and a second electrode connected with an eighth node.

[0227] 11. A display panel according to clause 10, wherein: in each of the first to fourth subpixels: the first switching element includes a first electrode connected to the eighth node, a gate electrode connected to the sixth node to which the first mode selection voltage is applied, and a second electrode connected to the ninth node; the second switching element includes a first electrode connected to the eighth node, a gate electrode connected to the seventh node to which the second mode selection voltage is applied, and a second electrode connected to the tenth node; the first light-emitting element includes an anode connected to the ninth node and a cathode to which a cathode voltage is applied; the second light-emitting element includes an anode connected to the tenth node and a cathode to which a cathode voltage is applied; and the first capacitor is connected between the second node and the fifth node.

[0228] 12. A display panel according to clause 10 or 11, wherein: the first mode switch element and the second mode switch element are connected in series between the fourth node and the sixth node; the third mode switch element and the fourth mode switch element are connected in series between the fourth node and the seventh node; the second capacitor is connected between the sixth node and the reference voltage or between the sixth node and the pixel drive voltage; and the third capacitor is connected between the seventh node and the reference voltage or between the seventh node and the pixel drive voltage.

[0229] 13. A display panel according to any one of clauses 10 to 12, wherein: the first mode switching element may include a first electrode connected to the fourth node of the first sub-pixel, a gate electrode to which the third selection signal is applied, and a second electrode connected to the eleventh node of the first sub-pixel; the second mode switching element includes a first electrode connected to the eleventh node of the first sub-pixel, a gate electrode to which the second selection signal is applied, and a second electrode connected to the sixth node; the third mode switching element includes a first electrode connected to the fourth node of the second sub-pixel, a gate electrode to which the third selection signal is applied, and a second electrode connected to the twelfth node of the second sub-pixel; and the fourth mode switching element includes a first electrode connected to the twelfth node of the second sub-pixel, a gate electrode to which the second selection signal is applied, and a second electrode connected to the seventh node.

[0230] 14. A display panel according to clause 8 or any one of clauses 9 to 13 referring to clause 8, wherein: the 1-1MUX switch element includes a first electrode to which the first mode selection voltage is applied, a gate electrode to which the first MUX signal is applied, and a second electrode connected to the first data line; the 1-2MUX switch element includes a first electrode to which the first data voltage is applied, a gate electrode to which the second MUX signal is applied, and a second electrode connected to the first data line; the 2-1MUX switch element includes a first electrode to which the second mode selection voltage is applied, a gate electrode to which the first MUX signal is applied, and a second electrode connected to the second data line; and the 2-2MUX switch element includes a first electrode to which the second data voltage is applied, a gate electrode to which the second MUX signal is applied, and a second electrode connected to the second data line.

[0231] 15. A display panel according to clause 8 or any one of clauses 9 to 14 referring to clause 8, wherein: the voltage of the first MUX signal is the gate-on voltage during the first period, the gate-off voltage during the 2-1 period set after the first period, the gate-off voltage during the 2-2 period set after the 2-1 period, and the gate-off voltage during the third period set after the 2-2 period; the voltage of the second MUX signal is the gate-off voltage during the first period, the gate-on voltage during the 2-1 period, the gate-off voltage during the 2-2 period, and the gate-off voltage during the third time period; the first gate signal is the gate-off voltage during the first time period and the 2-1 time period, the gate-on voltage during the 2-2 time period, and the gate-off voltage during the third time period; the second gate signal is the gate-on voltage during the first time period to the 2-2 time period, and the gate-off voltage during the third time period; and the third gate signal is the gate-on voltage during the first time period, the gate-off voltage during the 2-1 time period and the 2-2 time period, and the gate-on voltage during the third time period.

[0232] 16. A display panel, comprising: a first sub-pixel connected to a first data line; a second sub-pixel connected to a second data line; a third sub-pixel connected to a third data line; a fourth sub-pixel connected to a fourth data line; a first mode selection circuit, the first mode selection circuit being configured to receive a first mode selection voltage through one of the first data line to the fourth data line to select a first viewing angle as the viewing angle of the first sub-pixel to the fourth sub-pixel; and a second mode selection circuit, the second mode selection circuit being configured to receive a second mode selection voltage through another of the first data line to the fourth data line to select a second viewing angle as the viewing angle of the first sub-pixel to the fourth sub-pixel.

[0233] 17. A display panel according to clause 16, wherein the display panel is a display panel according to any one of clauses 1 to 15.

[0234] 18. A display panel according to clause 16 or clause 17, wherein the display panel further comprises: a 1-1MUX switch element, wherein the 1-1MUX switch element is connected to the first data line to provide the first mode selection voltage to the first data line; a 1-2MUX switch element, wherein the 1-2MUX switch element is connected to the first data line to provide the first data voltage to be applied to the first sub-pixel to the first data line; a 2-1MUX switch element, wherein the 2-1MUX switch element is connected to the second data line to provide the second mode selection voltage to the second data line; and a 2-2MUX switch element, wherein the 2-2MUX switch element is connected to the second data line to provide the second data voltage to be applied to the second sub-pixel to the second data line.

[0235] 19. A display panel according to any one of clauses 16 to 18, wherein the display panel further comprises: a 1-1MUX switch element connected to the first data line to provide the first mode selection voltage to the first data line; a 1-2MUX switch element connected to the first data line to provide the first data voltage to be applied to the first sub-pixel to the first data line; a 1-3MUX switch element connected to the second data line to provide the second data voltage to be applied to the second sub-pixel to the second data line; a 2-1MUX switch element connected to the third data line to provide the second mode selection voltage to the third data line; a 2-2MUX switch element connected to the third data line to provide the third data line to provide the third data line with the third data voltage to be applied to the third sub-pixel; and a 2-3MUX switch element connected to the fourth data line to provide the fourth data line with the fourth data voltage to be applied to the fourth sub-pixel.

[0236] 20. A display panel according to any of the preceding clauses, wherein, when each of the one or more sub-pixels includes a first light-emitting element and a second light-emitting element, a first lens is disposed on the first light-emitting element and a second lens is disposed on the second light-emitting element.

[0237] 21. The display panel of clause 20, wherein the first lens is semi-cylindrical and the second lens is hemispherical.

[0238] 22. The display panel according to clause 20 or clause 21, wherein the first lens is longer than the second lens in the left-right direction of the display panel.

[0239] 23. A display panel according to any of the preceding clauses, wherein the first data line is one data line and the second data line is another data line.

[0240] 24. A display device, comprising: a display panel, in which a plurality of data lines, a plurality of sub-pixels, a first mode selection circuit and a second mode selection circuit are arranged, wherein the plurality of sub-pixels are connected to corresponding data lines, the first mode selection circuit applies a first mode selection voltage to one or more sub-pixels through one of the data lines to select a first viewing angle as the viewing angle of the one or more sub-pixels, and the second mode selection circuit applies a second mode selection voltage to the one or more sub-pixels through another of the data lines to select a second viewing angle as the viewing angle of the one or more sub-pixels; a data driver, the data driver being configured to provide a data voltage to the data line; and a mode selection voltage power supply, the mode selection voltage power supply being configured to generate the first mode selection voltage and the second mode selection voltage.

[0241] 25. The display device according to clause 24, wherein the display panel is a display panel according to any one of clauses 1 to 23.

[0242] 26. A display device, comprising: a display panel, in which a first sub-pixel, a second sub-pixel, a third sub-pixel, a fourth sub-pixel, a first mode selection circuit, and a second mode selection circuit are arranged, wherein the first sub-pixel is connected to a first data line, the second sub-pixel is connected to a second data line, the third sub-pixel is connected to a third data line, and the fourth sub-pixel is connected to a fourth data line, the first mode selection circuit receives a first mode selection voltage through one of the first data lines to the fourth data lines to select a first viewing angle as the viewing angle of the first sub-pixel to the fourth sub-pixel, and the second mode selection circuit receives a second mode selection voltage through another of the first data lines to the fourth data lines to select a second viewing angle as the viewing angle of the first sub-pixel to the fourth sub-pixel; a data driver, the data driver is configured to provide a data voltage to the data line; and a mode selection voltage power supply, the mode selection voltage power supply is configured to generate the first mode selection voltage and the second mode selection voltage.

[0243] 27. The display device according to clause 26, wherein the display panel is a display panel according to any one of clauses 1 to 23.

[0244] 28. A display device according to any one of clauses 24 to 27, wherein the mode selection voltage supply is embedded in the data driver.

[0245] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure.

[0246] CROSS-REFERENCE TO RELATED APPLICATIONS

[0247] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0144549, filed on October 26, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display panel, comprising: a first mode selection circuit configured to receive a first mode selection voltage through one of the plurality of data lines to select a first viewing angle as a viewing angle of the one or more sub-pixels; as well as A second mode selection circuit is configured to receive a second mode selection voltage through another data line of the plurality of data lines to select a second viewing angle as a viewing angle of one or more sub-pixels.

2. The display panel according to claim 1, wherein: The one data line is a first data line, and the other data line is a second data line.

3. The display panel according to claim 2, further comprising: A plurality of sub-pixels, wherein each of the sub-pixels comprises: a first light emitting element; a second light emitting element; a driving element, wherein the driving element drives the first light emitting element and the second light emitting element; a compensation circuit comprising a first capacitor connected to the drive element; a first switching element electrically connected to the driving element and the first light emitting element and driven by the first mode selection voltage; and A second switching element is electrically connected to the driving element and the second light emitting element and is driven by the second mode selection voltage.

4. The display panel according to claim 3, wherein: The first sub-pixel includes the first mode selection circuit; The second sub-pixel includes the second mode selection circuit; The first mode selection circuit is electrically connected to the first data line and the compensation circuit inside the first sub-pixel to provide the first mode selection voltage to the gate electrodes of the first switching elements arranged in the first sub-pixel and the second sub-pixel; and The second mode selection circuit is electrically connected to the second data line and the compensation circuit inside the second sub-pixel to provide the second mode selection voltage to the gate electrodes of the second switching elements arranged in the first sub-pixel and the second sub-pixel.

5. The display panel according to claim 3 or claim 4, wherein: The first mode selection circuit includes a second capacitor to which the first mode selection voltage is applied; and The second mode selection circuit includes a third capacitor to which the second mode selection voltage is applied.

6. The display panel according to claim 4, wherein: The first mode selection circuit includes: a first mode switch element electrically connected to the first data line; a second capacitor connected to the gate electrode of the first switch element arranged in the first sub-pixel and the second sub-pixel to receive the applied first mode selection voltage; and a second mode switch element connected between the first mode switch element and the second capacitor; and The second mode selection circuit includes: a third mode switching element, which is electrically connected to the second data line; a third capacitor, which is connected to the gate electrode of the second switching element arranged in the first sub-pixel and the second sub-pixel to receive the applied second mode selection voltage; and a fourth mode switching element, which is connected between the third mode switching element and the third capacitor.

7. The display panel according to claim 6, wherein: When the first switch element is turned on in response to the gate-on voltage of the first mode selection voltage, the first light emitting element emits light; When the second switch element is turned on in response to the gate-on voltage of the second mode selection voltage, the second light emitting element emits light; The first switch element is turned off according to the gate-off voltage of the first mode selection voltage; and The second switching element is turned off according to a gate-off voltage of the second mode selection voltage.

8. The display panel according to claim 7, further comprising: a 1-1MUX switch element, the 1-1MUX switch element being connected to the first data line to provide the first mode selection voltage to the first data line; a 1-2MUX switch element connected to the first data line to provide a first data voltage to be charged in the first capacitor of the first sub-pixel to the first data line; a 2-1MUX switch element, the 2-1MUX switch element being connected to the second data line to provide the second mode selection voltage to the second data line; as well as A 2-2MUX switching element is connected to the second data line to provide the second data line with a second data voltage to be charged in the first capacitor of the second sub-pixel.

9. The display panel according to claim 8, wherein: After the 1-1 MUX switch element and the 2-1 MUX switch element are simultaneously turned on in response to the gate-on voltage of the first MUX signal, the 1-2 MUX switch element and the 2-2 MUX switch element are simultaneously turned on in response to the gate-on voltage of the second MUX signal.

10. The display panel according to claim 9, further comprising a third sub-pixel and a fourth sub-pixel, in, The first mode selection circuit is connected to the first data line of the first sub-pixel, the compensation circuit of the first sub-pixel, and gate electrodes of the first switching elements of the first to fourth sub-pixels, and The second mode selection circuit is connected to the second data line of the second sub-pixel, the compensation circuit of the second sub-pixel, and the gate electrodes of the second switching elements of the first to fourth sub-pixels.

11. The display panel according to claim 10, wherein: Each of the first to fourth sub-pixels includes: a driving element, the driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node; a third switching element including a first electrode connected to the fourth node, a gate electrode to which the first gating signal is applied, and a second electrode connected to the fifth node; a fourth switching element, the fourth switching element including a first electrode connected to the second node, a gate electrode to which a second gating signal is applied, and a second electrode connected to the third node; a fifth switching element, the fifth switching element including a first electrode to which a reference voltage is applied, a gate electrode to which the second gating signal is applied, and a second electrode connected to a ninth node; a sixth switching element, the sixth switching element including a first electrode to which the reference voltage is applied, a gate electrode to which the second gating signal is applied, and a second electrode connected to a tenth node; a seventh switching element including a first electrode connected to the fifth node, a gate electrode to which a third gating signal is applied, and a second electrode to which the reference voltage is applied; and An eighth switching element includes a first electrode connected to the third node, a gate electrode to which the third gate signal is applied, and a second electrode connected to an eighth node.

12. The display panel according to claim 11, wherein: In each of the first to fourth sub-pixels: The first switching element includes a first electrode connected to the eighth node, a gate electrode connected to a sixth node to which the first mode selection voltage is applied, and a second electrode connected to the ninth node; the second switching element includes a first electrode connected to the eighth node, a gate electrode connected to a seventh node to which the second mode selection voltage is applied, and a second electrode connected to the tenth node; The first light emitting element includes an anode connected to the ninth node and a cathode to which a cathode voltage is applied; The second light emitting element includes an anode connected to the tenth node and a cathode to which a cathode voltage is applied; and The first capacitor is connected between the second node and the fifth node.

13. The display panel according to claim 12, wherein: The first mode switch element and the second mode switch element are connected in series between the fourth node and the sixth node; The third mode switch element and the fourth mode switch element are connected in series between the fourth node and the seventh node; The second capacitor is connected between the sixth node and the reference voltage or between the sixth node and the pixel driving voltage; and The third capacitor is connected between the seventh node and the reference voltage or between the seventh node and the pixel driving voltage.

14. The display panel according to claim 12 or 13, wherein: The first mode switching element includes a first electrode connected to the fourth node of the first sub-pixel, a gate electrode to which the third gate signal is applied, and a second electrode connected to the eleventh node of the first sub-pixel; The second mode switching element includes a first electrode connected to the eleventh node of the first sub-pixel, a gate electrode to which the second gate signal is applied, and a second electrode connected to the sixth node; The third mode switching element includes a first electrode connected to the fourth node of the second sub-pixel, a gate electrode to which the third gate signal is applied, and a second electrode connected to the twelfth node of the second sub-pixel; and The fourth mode switching element includes a first electrode connected to the twelfth node of the second sub-pixel, a gate electrode to which the second gate signal is applied, and a second electrode connected to the seventh node.

15. The display panel according to claim 9, wherein: The 1-1MUX switch element includes a first electrode to which the first mode selection voltage is applied, a gate electrode to which the first MUX signal is applied, and a second electrode connected to the first data line; The 1-2MUX switch element includes a first electrode applied with the first data voltage, a gate electrode applied with the second MUX signal, and a second electrode connected with the first data line; The 2-1MUX switch element includes a first electrode to which the second mode selection voltage is applied, a gate electrode to which the first MUX signal is applied, and a second electrode connected to the second data line; and The 2-2 MUX switch element includes a first electrode to which the second data voltage is applied, a gate electrode to which the second MUX signal is applied, and a second electrode connected to the second data line.

16. The display panel according to claim 11, wherein: The voltage of the first MUX signal is the gate-on voltage during a first period, the gate-off voltage during a 2-1 period set after the first period, the gate-off voltage during a 2-2 period set after the 2-1 period, and the gate-off voltage during a third period set after the 2-2 period; The voltage of the second MUX signal is the gate-off voltage during the first period, the gate-on voltage during the 2-1 period, the gate-off voltage during the 2-2 period, and the gate-off voltage during the third period; The first gating signal is the gating cut-off voltage during the first period and the 2-1 period, the gating on voltage during the 2-2 period, and the gating cut-off voltage during the third period; The second gating signal is the gating on voltage during the first period to the 2-2 period, and the gating off voltage during the third period; and The third gate signal is the gate-on voltage during the first period, the gate-off voltage during the 2-1 period and the 2-2 period, and the gate-on voltage during the third period.

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