Method for reducing write-in power consumption of nonvolatile memory

Abstract

The invention provides a method for reducing write-in power consumption of a nonvolatile memory. The method comprises the following steps of: 1, applying a write-in pulse to a grid electrode of a storage unit in the nonvolatile memory according to a preset write-in pulse width; step 2, performing current detection on the drain electrode of the storage unit in the application process of the write-in pulse; step 3, judging whether the detected current value of the drain electrode is greater than a specified current monitoring threshold value or not; and 4, on the basis of the judgment result, carrying out the step of judging whether the operation of writing the pulse is completed or not.

Description

Technical Field

[0001] The invention belongs to the technical field of non-volatile memory, and relates to a method for reducing writing power consumption of a non-volatile memory. Background Art

[0002] With the advancement of technology, the performance requirements for non-volatile memory (NOR FLASH) are constantly increasing. However, new developments have also brought new technical challenges, especially in the data writing process, NOR FLASH applies voltage to the selected word line and bit line according to address decoding, and then injects electrons into the floating layer of the storage unit through the write pulse (Program Pulse). By increasing the number of electrons in the floating layer and changing the threshold voltage (Vth) of the storage unit, the write pulse operation is realized. This method is called hot electron injection.

[0003] However, due to differences in manufacturing processes, the efficiency of write pulses of different memory cells in the same array varies. In order to ensure that the written data can be completely and correctly written into the memory cell, the traditional method is to set the width of the write pulse by taking the memory cell with the worst write efficiency as a consideration for the single write pulse width configuration to ensure that the data can be completely and correctly written. In addition, when the write phase is completed, a reference voltage is used to determine whether the threshold voltage Vth of the memory cell has reached the target value to determine whether to write again, but this method will affect the overall performance of the chip. In addition, the memory cell with the worst write efficiency mentioned above, for example, the memory cell that requires two write operations to complete has the worst efficiency relative to the memory cell that can be completed with one write operation. Summary of the invention

[0004] Technical problem to be solved by the invention

[0005] Since the corresponding fixed write pulse width is configured according to the storage unit with poor write efficiency, the write-detection state is repeatedly switched to complete the write operation, which will lead to the problem of reduced overall chip write speed and increased power consumption of write operation.

[0006] Therefore, the purpose of the present invention is to provide a method for reducing the write power consumption of a non-volatile memory. During the writing process, the width of the write pulse is dynamically adjusted according to the current feedback during the actual writing process, thereby avoiding the overall write speed of the chip from being reduced due to the chip repeatedly performing the write-detection stage, and reducing the power consumption of the chip write operation.

[0007] Technical solutions to technical problems

[0008] One aspect of the present invention provides a method for reducing write power consumption of a non-volatile memory, comprising the following steps: Step 1, applying a write pulse with a predetermined write pulse width to the gate of a storage unit in the non-volatile memory; Step 2, performing current detection on the drain of the storage unit during the application of the write pulse; Step 3, judging whether the detected current value of the drain is above a specified current monitoring threshold; Step 4, determining whether the operation of the write pulse is completed based on the result of the judgment.

[0009] Furthermore, in step 3, when it is determined that the current value of the drain is greater than the current monitoring threshold, the write pulse width is extended, and then the current detection of the drain of the storage unit is performed again.

[0010] Furthermore, in the step 3, when it is determined that the current value of the drain is less than the current monitoring threshold, the operation of the write pulse is completed.

[0011] Furthermore, before performing step 3, it is determined whether the number of times the write pulse width is extended reaches a specified number of times.

[0012] Furthermore, when the number of times the write pulse width is extended reaches the number of extensions, the write pulse operation is completed without determining whether the current value of the drain is greater than a specified current monitoring threshold.

[0013] Furthermore, when the number of times the write pulse width is extended is less than the number of extensions, and when it is determined that the current value of the drain is greater than or equal to the predetermined current monitoring threshold, the write pulse width is extended.

[0014] Furthermore, the number of times the write pulse width is extended is increased by 1, and then the current of the drain of the storage unit is detected again.

[0015] Further, when the number of times the write pulse width is extended is less than the number of extensions, and when it is determined that the current value of the drain is less than the current monitoring threshold, the operation of the write pulse is completed.

[0016] Furthermore, the extension times is 4 times.

[0017] Furthermore, when the application of the write pulse is nearly finished, the current of the drain of the memory cell is detected.

[0018] Effects of the Invention

[0019] According to the present invention, a method for reducing the write power consumption of a non-volatile memory can be obtained. During the writing process, the width of the write pulse is dynamically adjusted according to the current feedback during the actual writing process, thereby avoiding a reduction in the overall writing speed of the chip due to repeated writing-detection stages of the chip and reducing the power consumption of the chip writing operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present disclosure may be better understood by describing exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, in which:

[0021] Description of reference numerals: 100 nonvolatile memory, 10 memory cell, 11 floating layer, G gate, D drain, S source.

[0022] Figure 1A is a general schematic diagram of a storage array of a non-volatile memory.

[0023] Figure 1B is a general schematic diagram of a selected memory cell in a non-volatile memory.

[0024] Figure 2 This is a flowchart of a method for reducing write power consumption according to the first embodiment of the present invention.

[0025] Figure 3 This is a flowchart of a method for reducing write power consumption according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0026] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0027] In the description of the present disclosure, it should be noted that, unless otherwise specified, "multiple" means more than two; the terms "upper", "lower", "left", "right", etc. indicate directions or positional relationships only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present disclosure. In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. "Vertical" is not strictly vertical, but is within the allowable error range. "Parallel" is not strictly parallel, but is within the allowable error range.

[0028] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the present disclosure. In the description of the present disclosure, it should also be noted that, unless otherwise clearly specified and limited, the terms "assemble", "connect", "connect", "relative", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances.

[0029] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present disclosure. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0030] by Figure 1A , Figure 1B The memory cell in the general nonvolatile memory is taken as an example to illustrate the method for reducing the write power consumption of the present invention. Figure 1A is a general schematic diagram of a storage array of a non-volatile memory. Figure 1B 1 is a general schematic diagram of a selected memory cell in a nonvolatile memory. The nonvolatile memory 100 is sometimes referred to as a "NORFLASH" below.

[0031] The general method of writing pulses is described below. Figure 1A As shown, a plurality of storage cells 10 (three are shown in the figure) in NOR FLASH are taken as an example for explanation. Figure 1A 1 shows a memory array in which a plurality of memory cells 10 are arranged in a row. The memory cells 10 are assumed to be NPN type non-volatile memories, but are not limited thereto. The gate G of each memory cell 10 is connected to a word line, the drain D is connected to a bit line, and the source S is connected to a source line. According to address decoding, a word line voltage V is applied to the word line and the bit line connected to the selected memory cell 10. 字线 and the bit line voltage V 位线 , the source S is grounded. Before the write pulse operation is formally started, the word line voltage V 字线The voltage source (not shown) located on the word line is charged, and the voltage source acts on the gate and is charged to a target voltage value that can perform a write pulse operation. When the voltage source is charged, the channel between the voltage source and the gate G of the memory cell 10 is opened, and the voltage source acts on the gate G, that is, a write pulse (Program Pulse) is applied to the gate of the memory cell 10 with a predetermined write pulse width, thereby generating electrons that are injected into the floating layer of the memory cell 10, thereby increasing the number of electrons in the floating layer and changing the threshold voltage (Vth) of the memory cell 10 to achieve the write pulse operation (i.e., hot electron injection method).

[0032] During the above-mentioned write pulse process, we expect that the threshold voltage Vth of the memory cell 10 will also rise to a certain target value before the write pulse is about to end. However, if a memory cell 10 with poor write efficiency appears, its threshold voltage Vth does not reach the above-mentioned target value, which will cause the voltage difference between its gate G and the floating layer 11 to increase, thereby causing a corresponding increase in the drain current.

[0033] Therefore, the embodiments of the present invention are described in combination with the above situation.

[0034] <Example 1>

[0035] Figure 2 This is a flowchart of a method for reducing write power consumption according to the first embodiment of the present invention.

[0036] In view of the above situation that the drain current will increase, we can set a current monitoring threshold and perform real-time current detection on the drain. Among them, the above current monitoring threshold can be adjustable, because after the chip is used for a long time, the internal storage unit will have a performance degradation. At this time, if it is required according to the standard when the chip is just produced, it will affect the writing efficiency of the chip. Therefore, by adjusting the current monitoring threshold, the writing efficiency of the chip can be guaranteed. When the gate voltage of the selected storage unit 10 is constant, when the current of the drain D reaches or exceeds the specified current monitoring threshold, it means that the threshold voltage Vth has not reached the above target value, and the chip needs to extend the width of the write pulse to wait for the threshold voltage Vth of the storage unit to rise to the above target value, so as to complete the write pulse operation. In addition, when the current of the drain D is less than the specified current monitoring threshold, it means that the threshold voltage Vth reaches the above target value, and the operation of this write pulse can be completed.

[0037] Current sensing of the drain current may be performed, for example, on a bit line connected to the drain by a current sensor.

[0038] Refer to the following Figure 2 Provide specific instructions.

[0039] In step S1, a write pulse is applied to the gate G of the selected memory cell 10 in the nonvolatile memory 100 with a predetermined write pulse width T. This step is the starting point of the write process, indicating the start of the write pulse operation.

[0040] In step S2 , during the application of the write pulse, the current of the drain D of the memory cell 10 is detected.

[0041] In step S3, it is determined whether the current value of the detected drain D is above the specified current monitoring threshold. When it is determined that the current value of the detected drain is above the specified current monitoring threshold, proceed to step S5. Extend the write pulse width T, then return to step S2, re-detect the current of the drain D of the storage unit 10, and then repeat step S3 until it is determined that the current value of the detected drain D is less than the specified current monitoring threshold, then proceed to step S4 to complete the operation of this write pulse. When it is determined that the current value of the detected drain D is less than the specified current monitoring threshold, proceed to step S4.

[0042] In step S4, based on the result of the judgment, the step of whether the write pulse operation is completed is performed. That is, when it is determined in step S3 that the current value of the drain D detected is less than the specified current monitoring threshold, the write pulse operation is completed.

[0043] In addition, when the application of the write pulse is close to the end, the current detection can also be performed on the drain D of the selected storage cell 10. When it is determined that the current value of the detected drain D is above the specified current monitoring threshold, the write pulse width T is extended until the threshold voltage Vth rises to the target value, thereby completing the write pulse operation. When it is determined that the current value of the detected drain is less than the specified current monitoring threshold, the operation of this write pulse is completed. Here, extending the write pulse width T is to extend a certain width based on the write pulse width T, and the certain width can be the same length as the above T, or it can be different.

[0044] Embodiment 1 of the present invention realizes that during the write pulse process, the width of the write pulse is dynamically adjusted according to the current feedback during the actual write process, thereby significantly improving the overall write speed of the chip, reducing the write power consumption of the chip, and improving the overall performance of the chip.

[0045] <Example 2>

[0046] Figure 3 This is a flowchart of a method for reducing write power consumption according to the second embodiment of the present invention.

[0047] The difference from Example 1 is that a detection of the number of times the write pulse is extended is added. During the write pulse process, sometimes there is a storage unit that cannot be written. If the write pulse is extended to the storage unit at this time, the write operation will be looped infinitely, resulting in a delay in the overall write speed of the chip. By adding the detection of the number of extensions, an infinite loop can be prevented.

[0048] Refer to the following Figure 3 Specific instructions.

[0049] Similar to the first embodiment, in step S1, a write pulse is applied to the gate G of the memory cell 10 in the nonvolatile memory 100 with a predetermined write pulse width T. This step is the starting point of the write process and indicates the start of the write pulse operation.

[0050] In step S2 , during the application of the write pulse, current detection is performed on the drain D of the memory cell 10 .

[0051] Afterwards, before performing step S3 , step S21 is performed to determine whether the number of times the write pulse width T is extended reaches a limited number of extensions.

[0052] When the number of times the write pulse width is extended reaches the limited number of extensions, that is, when the limited number of extensions is reached, the current write pulse operation is completed without determining whether the current value of the drain D is equal to or greater than a predetermined current monitoring threshold.

[0053] When the limited number of extension times has been reached, it means that the storage unit may not be able to be written, that is, the storage unit may be unable to be written due to damage or other reasons. Therefore, by limiting the number of delays, an infinite loop can be prevented.

[0054] In addition, when the number of times the write pulse width T is extended is less than the extension number in step S21, the process proceeds to step S3, and when it is determined that the current value of the drain D is greater than the specified current monitoring threshold, the write pulse width T is extended in step S5, and then in step S51, the number of times the write pulse width T is extended is added by 1, and then the process returns to step S2 to re-detect the current of the drain D of the storage unit 10. That is, after each detection during the execution of a write pulse, the value of the "extension number" is increased by 1, in order to record how many times the write pulse extension has been attempted at the current position.

[0055] In addition, when it is determined in the above step S3 that the drain current value is less than the current monitoring threshold, the process proceeds to step S4 to complete the operation of the write pulse this time.

[0056] Furthermore, the above-mentioned extension frequency is preferably 4 times.

[0057] In addition, when the application of the write pulse is close to the end, the current of the drain D of the selected memory cell 10 can be detected. When it is determined that the current value of the detected drain D is above the specified current monitoring threshold, the write pulse width T is extended until the threshold voltage Vth rises to the target value, thereby completing the write pulse operation. When it is determined that the current value of the detected drain D is less than the specified current monitoring threshold, the write pulse operation is completed.

[0058] Embodiment 2 of the present invention realizes that during the write pulse process, the width of the write pulse is dynamically adjusted according to the current feedback during the actual write process, and the number of delays is limited, thereby significantly improving the overall write speed of the chip, reducing the write power consumption of the chip, and improving the overall performance of the chip.

[0059] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of the present invention, many modifications can be made to adapt specific conditions or materials to the teachings of various embodiments of the present invention. Although the size and type of materials described herein are used to define the parameters of various embodiments of the present invention, the various embodiments are not meant to be restrictive, but exemplary embodiments. In the case of reading the above description, many other embodiments are obvious to those skilled in the art. Therefore, the scope of various embodiments of the present invention should be determined with reference to the attached claims, and the full range of equivalent forms claimed by these claims.

Claims

1. A method for reducing write power consumption of a non-volatile memory, characterized in that: The steps include: Step 1, applying a write pulse with a predetermined write pulse width to the gate of a memory cell in the non-volatile memory; Step 2, during the application of the write pulse, performing current detection on the drain of the memory cell; Step 3, determining whether the detected current value of the drain is above a specified current monitoring threshold; Step 4, based on the result of the judgment, a step is performed to determine whether the operation of the write pulse is completed.

2. The method for reducing write power consumption according to claim 1, characterized in that: In the step 3, when it is determined that the current value of the drain is greater than the current monitoring threshold, the write pulse width is extended, and then the current detection of the drain of the memory cell is performed again.

3. The method for reducing write power consumption according to claim 1, characterized in that: In the step 3, when it is determined that the current value of the drain is less than the current monitoring threshold, the operation of the write pulse is completed.

4. The method for reducing write power consumption according to claim 1, characterized in that: Before performing step 3, it is also determined whether the number of times the write pulse width is extended reaches a specified number of extensions.

5. The method for reducing write power consumption as claimed in claim 4, characterized in that: When the number of times the write pulse width is extended reaches the number of extensions, the write pulse operation is completed without determining whether the drain current value is equal to or greater than a predetermined current monitoring threshold.

6. The method for reducing write power consumption as claimed in claim 5, characterized in that: In the case where the number of times the write pulse width is extended is less than the number of extensions, When it is determined that the current value of the drain is equal to or greater than the predetermined current monitoring threshold, the write pulse width is extended.

7. The method for reducing write power consumption according to claim 6, characterized in that: The number of times the write pulse width is extended is increased by 1, and then the current of the drain of the memory cell is detected again.

8. The method for reducing write power consumption as claimed in claim 6, characterized in that: In the case where the number of times the write pulse width is extended is less than the number of extensions, When it is determined that the current value of the drain is less than the current monitoring threshold, the operation of the write pulse is completed.

9. The method for reducing write power consumption according to any one of claims 4 to 8, characterized in that: The extension times is 4 times.

10. The method for reducing write power consumption according to any one of claims 1 to 8, characterized in that: When the application of the write pulse is nearly completed, current detection is performed on the drain of the memory cell.

Images