Self-detection method and self-detection circuit of storage device, storage device and system

Abstract

The embodiment of the invention provides a self-detection method and a self-detection circuit of a storage device, the storage device and a system, and relates to the technical field of storage detection. The self-detection method of the storage device comprises the following steps: after entering a self-detection mode of the storage device, sending a self-detection enable signal to a clock generation module, and sending self-detection command data to each distributed detection unit; the clock generation module generates a self-detection clock signal and sends the self-detection clock signal to the self-detection module and each distributed detection unit; and on the basis of the self-checking command data, obtaining test related data for testing the corresponding target storage module, and carrying out fault testing on the target storage module on the basis of the test related data to obtain fault information of the target storage module. The self-detection power consumption is reduced, and the self-detection efficiency of the storage module is improved.

Description

Technical Field

[0001] The present invention relates to the field of storage detection technology, and in particular to a self-detection method, a self-detection circuit, a storage device and a system for a storage device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. DRAM consists of multiple sub-storage modules (Banks), and each Bank consists of multiple storage cells (Cells) arranged in rows and columns. The circuit structure of DRAM is complex and highly integrated. As the process advances, problems such as poor contact of the DRAM circuit structure or unqualified storage cells may occur during the manufacturing process, causing some storage cells in the DRAM to fail to work properly, resulting in data errors when the DRAM reads and writes failed storage cells.

[0003] In order to avoid the above data errors and improve the yield of DRAM, it is necessary to use fault detection technology to find and mark the faulty storage cells in DRAM, avoid reading and writing operations on the faulty storage cells in DRAM, and facilitate subsequent redundant repair operations. However, the commonly used fault detection schemes for DRAM have problems such as narrow applicability, long detection time, and high detection power consumption. Summary of the invention

[0004] The purpose of the present invention is to provide a self-detection method, a self-detection circuit, a storage device and a system for a storage device. After the self-detection of the self-detection circuit is completed, the clock generation module no longer generates a self-detection clock signal, thereby reducing the power consumption of the self-detection; thus, when the storage device is in a normal working state, the internal clock will be in a closed mode, avoiding increasing the power consumption overhead of normal reading and writing of the storage device; and achieving distributed self-detection of multiple storage modules in parallel in the storage device, thereby shortening the self-detection time of the storage device and improving the self-detection efficiency of the storage module.

[0005] To achieve the above-mentioned purpose, the present invention provides a self-detection method for a storage device, which is applied to a self-detection circuit of the storage device, wherein the self-detection circuit comprises: a clock generation module, a self-detection module, and a plurality of distributed detection units; the plurality of distributed detection units correspond one to one to a plurality of storage modules in the storage device; the method comprises: after entering a self-detection mode of the storage device, the self-detection module sends a self-detection enable signal to the clock generation module, and sends self-detection command data to each of the distributed detection units; after receiving the self-detection enable signal, the clock generation module generates a self-detection clock signal and sends it to the self-detection module and each of the distributed detection units; The distributed detection unit; the distributed detection unit obtains test related data for testing the corresponding target storage module based on the self-test command data, and performs a fault test on the target storage module based on the test related data to obtain fault information of the target storage module, and sends the fault information to the self-test module; wherein the test related data includes test data for writing the corresponding storage module and a test unit address corresponding to the test data; after the self-test of all the storage modules is completed, the self-test module sends a self-test end signal to the clock generation module to shut down the clock generation module.

[0006] The present invention also provides a self-detection circuit for a storage device, the storage device includes multiple storage modules, and the self-detection circuit includes: a clock generation module, a self-detection module, and multiple distributed detection units; the multiple distributed detection units correspond to the multiple storage modules one by one; the self-detection module is used to send a self-detection enable signal to the clock generation module after entering the self-detection mode of the storage device, and send self-detection command data to each of the distributed detection units; the clock generation module is used to generate a self-detection clock signal after receiving the self-detection enable signal and send it to the self-detection module and each of the distributed detection units; the distributed detection unit is used to: based on the self-detection command data, obtain test-related data for testing the corresponding target storage module, the test-related data includes test data for writing the corresponding storage module and the test unit address corresponding to the test data; based on the test-related data, perform a fault test on the target storage module to obtain fault information of the target storage module, and send the fault information to the self-detection module; the self-detection module is also used to send a self-detection end signal to the clock generation module after all the storage modules have completed self-detection, so as to shut down the clock generation module.

[0007] The present invention also provides a storage device, comprising: a plurality of storage modules and the above-mentioned self-detection circuit.

[0008] The present invention also provides a storage system, comprising: a controller and the above storage device.

[0009] In one embodiment, the method further includes: the self-detection module sends the received fault information of each of the storage modules to an external controller so that the external controller can store the fault information of each of the storage modules; before entering the self-detection mode of the storage device, it also includes: after the storage device is powered on, when the self-detection module does not receive the fault information of the storage module in the storage device sent by the external controller, entering the self-detection mode; after the storage device is powered on, when the self-detection module receives the fault information of the storage module sent by the external controller, storing the fault information of the storage module and skipping the self-detection.

[0010] In one embodiment, the distributed detection unit acquires test related data for testing the corresponding target storage module based on the self-test command data, including: The distributed detection unit selects a target test item from a plurality of pre-stored test items based on the self-test command data, and the target test item includes test data for writing into the target storage module and a test unit address corresponding to the test data.

[0011] In one embodiment, the self-detection module is further used to send the fault information of each storage module to an external controller, so that the external controller can store the fault information of each storage module; The self-detection module is used to enter the self-detection mode after the storage device is powered on: if a self-detection start signal sent by the external controller is received; If a control instruction instructing external writing of fault information sent by the external controller is received, self-detection is skipped, and the fault information of the storage module is obtained from the external controller and stored.

[0012] In one embodiment, the distributed detection unit includes: a test command circuit and a comparison circuit; The test command circuit is used to: Based on the self-test command data, selecting a target test item from a plurality of pre-stored test items, the target test item including test data for writing into a corresponding target storage module and a test unit address corresponding to the test data; Writing the test data into a corresponding test unit address in a target storage module, and sending the test data to the comparison circuit; The comparison circuit is used to read detection data from the target storage module, compare the detection data with data corresponding to the same storage unit address in the test data, and record the address and fault type of the storage unit where the fault occurs in the storage module; the fault information of the storage module includes: the address and fault type of each storage unit where the fault occurs in the storage module.

[0013] In one embodiment, each of the storage modules includes a storage cell array formed by a plurality of storage cells; the comparison circuit is used to compare the detection data with the test data row by row according to the storage cell array in the storage module; for each row of the storage cell array, if the detection data and the test data are inconsistent in data in some storage cells among all the storage cells included in the row, then the addresses of the storage cells with inconsistent data and the fault type are recorded as single-bit faults; if the detection data and the test data are inconsistent in data in all the storage cells included in the row, then the address of the row and the fault type are recorded as word line faults.

[0014] In one embodiment, the self-detection module includes: a detection state control unit and an address storage unit; The detection state control unit is used to send a self-test enable signal to the clock generation module after entering the self-test mode of the storage device; and send self-test command data to each of the distributed detection units; The distributed detection unit is used to send the fault information to the address storage unit for storage.

[0015] In one embodiment, the clock generation module includes: an enable status register, an oscillation circuit and a frequency multiplier; The enable status register is used to activate the oscillation circuit and the frequency multiplier to start working after receiving the self-test enable signal; The oscillation circuit is used to generate a clock signal of a preset reference clock frequency, and send the clock signal of the reference clock frequency to the frequency multiplier; The frequency multiplier is used to amplify the reference clock frequency of the clock signal to obtain the self-test clock signal.

[0016] In one embodiment, the clock generation module further includes: a temperature compensation circuit; The enable status register is also used to activate the temperature compensation circuit to start working after receiving the self-test enable signal; The temperature compensation circuit is used to perform temperature compensation on the oscillation circuit so that the oscillation circuit outputs a stable clock signal of the reference clock frequency.

[0017] In one embodiment, the self-detection circuit further includes: a first multiplexer, a second multiplexer and a third multiplexer, wherein one input end of the first multiplexer is connected to an external clock signal and another input end is connected to the clock generation module, one input end of the second multiplexer is connected to an external command signal and another input end is connected to the self-detection module, and one input end of the third multiplexer is connected to an external data signal bus and another input end is connected to the self-detection module; The self-test module is used to send a self-test enable signal to the first multiplexer, the second multiplexer and the third multiplexer respectively after entering the self-test mode of the storage device; The clock generation module is used to send the self-test clock signal to the first multiplexer, wherein the first multiplexer selects to transmit the self-test clock signal to each of the distributed detection units when enabled by the self-test enable signal; The self-test module is used to send the self-test command data to the second multiplexer, wherein the second multiplexer selects to send the self-test command data to each of the distributed detection units when the self-test enable signal is enabled; The distributed detection unit is used to send the fault information of the target storage module to the third multiplexer, wherein the third multiplexer selects to send the fault information of the target storage module to the self-detection module when the self-detection enable signal is enabled; The first multiplexer is further configured to select to switch the external clock signal to an internal clock source of the storage device when the self-test enable signal is not received. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a specific flow chart of the self-detection method of the storage device according to the first embodiment of the present invention; Figure 2 is a schematic structural diagram of a self-detection circuit for a storage device according to a second embodiment of the present invention; Figure 3 is a schematic diagram of the structure of an address storage table of a self-detection module according to a second embodiment of the present invention; Figure 4 is a schematic diagram of connecting a storage device and an external controller according to a second embodiment of the present invention; Figure 5 is a schematic diagram of the structure of a distributed detection unit in a self-detection circuit according to a second embodiment of the present invention; Figure 6 is a schematic structural diagram of a clock generation module in a self-detection circuit according to a second embodiment of the present invention; Figure 7 is a schematic diagram of a storage device using a self-detection circuit according to a second embodiment of the present invention; Figure 8 FIG. 4 is a schematic structural diagram of a stacked memory according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will be described in detail with reference to the accompanying drawings to provide a clearer understanding of the purpose, features and advantages of the present invention. It should be understood that the embodiments shown in the accompanying drawings are not intended to limit the scope of the present invention, but are only intended to illustrate the essential spirit of the technical solution of the present invention.

[0020] In the following description, certain specific details are set forth for the purpose of illustrating various disclosed embodiments to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the embodiments may be practiced without one or more of these specific details. In other cases, well-known devices, structures, and techniques associated with the present application may not be shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0021] Unless the context requires otherwise, throughout the specification and claims, the word "comprise" and variations such as "include" and "have" should be construed in an open, inclusive sense, ie, should be interpreted as "including, but not limited to."

[0022] References throughout the specification to "one embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any manner in one or more embodiments.

[0023] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It should be noted that the term "or" is generally employed in its sense including "or / and" unless the context clearly dictates otherwise.

[0024] In the following description, in order to clearly show the structure and working mode of the present invention, many directional words will be used for description, but the words "front", "back", "left", "right", "outside", "inside", "outward", "inward", "up", "down", etc. should be understood as convenient terms and should not be understood as restrictive terms.

[0025] The first embodiment of the present invention relates to a self-detection method for a storage device, which is applied to a self-detection circuit of the storage device. The self-detection circuit includes: a clock generation module, a self-detection module, and multiple distributed detection units; the multiple distributed detection units correspond one-to-one to multiple storage modules in the storage device.

[0026] The specific process of the self-test method of the storage device in this embodiment is as follows: Figure 1 shown.

[0027] Step 101, after entering the self-test mode of the storage device, the self-test module sends a self-test enable signal to the clock generation module, and sends self-test command data to each distributed detection unit.

[0028] Step 102: After receiving the self-test enable signal, the clock generation module generates a self-test clock signal and sends it to the self-test module and each distributed detection unit.

[0029] Step 103, the distributed detection unit obtains test-related data for testing the corresponding target storage module based on the self-test command data, and performs a fault test on the target storage module based on the test-related data to obtain fault information of the target storage module, and sends the fault information to the self-test module; wherein the test-related data includes test data for writing the corresponding storage module and a test unit address corresponding to the test data.

[0030] Step 104: After all storage modules have completed self-testing, the self-testing module sends a self-testing completion signal to the clock generating module to shut down the clock generating module.

[0031] Furthermore, the self-detection method further includes: the self-detection module sends the received fault information of each storage module to the external controller, so that the external controller stores the fault information of each storage module.

[0032] Before entering the self-detection mode of the storage device, it also includes: after the storage device is powered on, when the self-detection module does not receive the fault information of the storage module in the storage device sent by the external controller, entering the self-detection mode; after the storage device is powered on, when the self-detection module receives the fault information of the storage module sent by the external controller, storing the fault information of the storage module and skipping the self-detection.

[0033] The distributed detection unit obtains test-related data for testing the corresponding target storage module based on the self-test command data, including: the distributed detection unit selects a target test item from multiple test items based on the self-test command data, and the target test item includes test data for writing the corresponding storage module and a test unit address corresponding to the test data.

[0034] In the present embodiment, a self-detection circuit is configured in the storage device. After the storage device enters the self-detection mode, the self-detection module sends a self-detection enable signal to the clock generation module. After receiving the self-detection enable signal, the clock generation module can generate a self-detection clock signal. The self-detection clock signal is sent to the self-detection module and the distributed detection unit as an internal clock, thereby providing a precise delay for the self-detection. After the self-detection is completed, the clock generation module no longer generates a self-detection clock signal, thereby reducing the power consumption of the self-detection. Therefore, when the storage device is in normal working state, the internal clock will be in the off mode, thereby avoiding increasing the power consumption overhead of normal reading and writing of the storage device.

[0035] The self-detection circuit includes distributed detection units corresponding to multiple storage modules in the storage device. During the self-detection process, each distributed detection unit can perform fault tests on the corresponding storage modules respectively, record the fault information of each storage module and send it to the self-detection module; that is, each storage module is equipped with an independent distributed detection unit, so the self-detection module only needs to send self-detection command data to each distributed detection unit respectively, and each distributed detection unit independently completes the distributed self-test, thereby realizing distributed self-detection of multiple storage modules in parallel, shortening the self-detection time of the storage device, and improving the self-detection efficiency of the storage module.

[0036] Furthermore, the clock, control, test and other signals required in the self-test process are all derived from the inside of the storage device, so that even if the storage device has been shipped, the user can perform the self-test of the storage device.

[0037] The second embodiment of the present invention relates to a self-detection circuit for a storage device. Figure 2 The storage device includes multiple storage modules (BANK), the number of storage modules in Figure 2 is P (P is an integer greater than 1), namely BANK1 to BANKP; each storage module includes a storage cell array formed by multiple storage cells (Cell), such as a storage module with m rows and n columns, and a row decoder and a column decoder, the row decoder is connected to all rows of storage cells, the column decoder is connected to all columns of the storage cell array, and each storage cell (Cell) includes a capacitor and a transistor. The applicable scenario of the storage device is, for example, to be assembled on a test computer before leaving the factory, or to be assembled on a personal computer by an individual user.

[0038] The storage device is, for example, a dynamic random access memory DRAM, and its basic working method is: the opening or closing of the transistor is controlled by a voltage signal input to the word line of the storage cell array (a row of the storage cell array), and then the data information stored in the storage cell capacitor is read through the bit line (a column of the storage cell array), or the data information is written into the capacitor of the storage cell through the bit line for storage; each storage cell represents a binary bit (bit) of 1 or 0 by the amount of charge stored in the capacitor.

[0039] The self-detection circuit includes: a clock generation module 1, a self-detection module 2, and multiple distributed detection units 3; the multiple distributed detection units 3 correspond one-to-one to the multiple storage modules, that is, the number of distributed detection units 3 is also P, the P distributed detection units 3 correspond one-to-one to the P storage modules (BANK1 to BANKP) and are communicatively connected, the self-detection module (MBIST module) 2 is communicatively connected to each distributed detection unit 3 and the clock generation module 1, wherein two signal transmission lines are formed between the self-detection module 2 and the multiple distributed detection units 3, one is an instruction transmission line, and the other is a data transmission line, for example, the multiple distributed detection units 3 are respectively connected to the instruction transmission bus CMD_BUS and the data transmission bus DATA_BUS, and the self-detection module 2 can be directly or indirectly connected to the instruction transmission bus CMD_BUS and the data transmission bus DATA_BUS, respectively.

[0040] The following is a detailed description of the self-test process after the storage device is powered on, as follows: After entering the self-test mode of the storage device, the self-test module 2 sends a self-test enable signal MBIST_EN to the clock generation module 1, and sends the self-test command data to each distributed detection unit 3. Wherein, the self-test command data includes: a self-test trigger signal MBIST_TRIG and a self-test command set CMDSET. After entering the self-test mode, the self-test module 2 first sends a self-test trigger signal MBIST_TRIG to the command transmission bus CMD_BUS, and then sends a self-test command set CMDSET to the command transmission bus CMD_BUS, thereby broadcasting the self-test trigger signal MBIST_TRIG and the self-test command set CMDSET to each distributed detection unit 3.

[0041] After receiving the self-test enable signal MBIST_EN, the clock generation module 1 generates a self-test clock signal MBIST_CLK and sends it to the self-test module 2 and each distributed detection unit 3. Thus, in the self-test process, the self-test module 2 and the distributed detection unit 3 use the self-test clock signal MBIST_CLK as the self-test internal clock, which is the precise delay required for read / write / data refresh in the subsequent self-test process, and also provides the working clock of the self-test module.

[0042] For each distributed detection unit 3 corresponding to each storage module, based on the self-test command data, the test-related data for testing the corresponding target storage module is obtained, and the test-related data includes the test data for writing the corresponding target storage module and the test unit address corresponding to the test data; based on the test-related data, the target storage module is tested for faults, the fault information of the target storage module is obtained, and the fault information is sent to the self-test module. The fault information of the target storage module includes the address and fault type of the storage unit in the target storage module where the fault occurs; for each distributed detection unit 3, if the corresponding target storage module does not have a fault, there is no need to send the fault information to the self-test module 2.

[0043] The self-test module 2 is also used to send a self-test completion signal to the clock generation module 1 after all storage modules have completed self-test, so as to shut down the clock generation module 1. That is to say, after all storage modules of the storage device have completed self-test, the self-test module 2 can receive the fault information sent by any distributed detection unit 3 for storage, and send a self-test completion signal to the clock generation module 1 to shut down the clock generation module 1. The shut down clock generation module 1 stops outputting the self-test clock signal, and at this time the storage device can use the external clock signal as the clock source to perform normal reading and writing of the storage device.

[0044] After completing the above process, the self-test module 2 exits the self-test mode.

[0045] In one example, the self-detection module 2 includes: a detection state control unit 21 and an address storage unit 22. The detection state control unit 21 is connected to each distributed detection unit 3 for communication, and the address storage unit 22 is connected to each distributed detection unit 3 for communication.

[0046] The detection state control unit 21 is used to send a self-detection enable signal to the clock generation module 1 after entering the self-detection mode of the storage device; and send self-detection command data to each distributed detection unit 3.

[0047] The distributed detection unit 3 is used to send fault information to the address storage unit 22 for storage. The address storage unit 22 is an address storage table (AST). Each distributed detection unit 3 sends the fault information of the corresponding target storage module to the address storage table (AST) for storage via the data transmission bus DATA_BUS.

[0048] The structure of the address storage table is as follows Figure 3As shown, the address storage table includes multiple storage table entries, each storage table entry includes 2 fault information identification bits and 2 fault addresses, and the 2-bit fault information identification bit indicates the fault type. When the fault information identification bit is 01, it indicates a single storage unit fault, and the fault address stores the row address (Row_ADDR) and bit address (Col_ADDR) of the faulty unit respectively; when the fault information identification bit is 00, it indicates a storage cell array word line fault, and the fault address stores the row start address (Row_ADDR) and row end address (Row_ADDR) of the faulty word line respectively; when the fault information identification bit is 00, it indicates a storage cell array bit line fault, and the fault address stores the column start address (Col_ADDR) and column end address (Col_ADDR) of the faulty word line respectively; in order to save storage space, each storage table entry can also store two different word line faults and / or bit line faults at the same time, which can be identified by using the address of one of the storage cells in the row where the word line is located or the column where the bit line is located.

[0049] In one example, the storage device is further connected to an external controller, which may be a processor of a detection computer dedicated to detecting the storage device, or a processor of a user's personal computer.

[0050] The self-detection module 2 is also used to send the fault information of each storage module to the external controller, so that the external controller can store the fault information of each storage module.

[0051] The self-detection module 2 is used to enter the self-detection mode after the storage device is powered on: if a self-detection start signal is received from an external controller, the self-detection mode is entered; if a control instruction indicating external writing of fault information is received from an external controller, the self-detection mode is skipped, and the fault information of the storage module is obtained from the external controller and stored.

[0052] For details, please refer to Figure 4 The external controller may include: a fault detection control unit, a memory controller (MC) and a fault external storage table which are communicatively connected in sequence, the fault detection control unit is communicatively connected to the fault external storage table; the memory controller is communicatively connected to the detection state control unit 21 in the self-detection module 2 via the external command transmission bus CMD1, and the memory controller is communicatively connected to the address storage unit 22 via the external data transmission bus DQ1.

[0053] Each time the self-detection module 2 completes the self-detection, the fault information of each storage module received is sent to the memory controller through the external data transmission bus, so that the memory controller stores the fault information of each storage module in the fault external storage table. The specific structure of the fault external storage table is similar to the aforementioned address storage table and will not be repeated here.

[0054] After the storage device is powered on each time, the fault detection control unit in the external controller queries whether the fault information of the storage module in the storage device is stored in the fault external storage table; If the fault detection control unit determines through query that the fault external storage table does not store the fault information of the storage module in the storage device, the fault detection control unit sends a self-detection start signal to the detection status control unit 21 via the memory controller using the external command transmission bus CMD1, triggering the detection status control unit 21 to enter the self-detection mode.

[0055] If the fault detection control unit determines through query that the fault information of the storage module in the storage device has been stored in the fault external storage table, the fault detection control unit sends a control instruction indicating the external writing of the fault information to the detection status control unit 21 via the memory controller using the external instruction transmission bus CMD1. After receiving the control instruction, the detection status control unit 21 skips the self-detection link, and reads the fault information of the storage device from the fault external storage table via the external data transmission bus DQ1 and stores it in the address storage unit 22.

[0056] The detection status control unit 21 can start timing after the storage device is powered on. If a self-detection start signal sent by the memory controller is received before the timing reaches a preset time, it will trigger the entry into the self-detection mode; or if a self-detection start signal sent by the memory controller is still not received after the timing reaches the preset time, it will trigger the entry into the self-detection mode.

[0057] From the above, the present invention proposes an external recording mechanism for the fault information of the storage device. After the storage device completes self-detection, the fault information of the storage device obtained by the detection can be transmitted and stored in an external controller, so that the fault information of the storage device can be directly read from the external controller when the storage device is powered on next time, avoiding repeated self-detection of the storage device after each power-on.

[0058] For an example, see Figure 5 The distributed detection unit 3 includes: a test command circuit 31 and a comparison circuit 32 connected to each other; the test command circuit 31 is connected to the command transmission bus CMD_BUS, and the comparison circuit 32 is connected to the data transmission bus DATA_BUS. The test command circuit 31 is connected to the row decoder and column decoder of the corresponding target storage module, and the comparison circuit 32 is connected to the column decoder of the corresponding target storage module.

[0059] For each distributed detection unit 3, the test command circuit 31 of the distributed detection unit 3 selects a target test item from multiple pre-stored test items based on the self-test command data, and the target test item includes test data for writing into the corresponding target storage module and a test unit address corresponding to the test data; the test data is then written into the corresponding test unit address in the target storage module, and the test data is sent to the comparison circuit, the comparison circuit is used to read the detection data from the target storage module, compare the detection data with the data at the same address in the test data, and store the address and fault type of the storage unit where the fault occurs in the storage module; the fault information of the storage module includes: the address and fault type of each storage unit where the fault occurs in the storage module.

[0060] Specifically, the test command circuit 31 may be a state machine, and a plurality of test project files required for the test are pre-stored in the state machine register. Each test project file includes: test data used in the test and a test cell address of a storage cell array corresponding to the test data.

[0061] After receiving the self-test trigger signal MBIST_TRIG from the command transmission bus CMD_BUS, the test command circuit 31 triggers the test of the target storage module; the self-test command set CMDSET received from the command transmission bus CMD_BUS includes test instructions (such as start detection instructions, stop detection instructions) and test items selected for the test. The test command circuit 31 selects the target test item from the pre-stored multiple test items, obtains the test data for writing into the target storage module and the test cell address of the storage cell array corresponding to the test data, the test cell address corresponding to the test data includes the word line address and the bit line address of the storage cell array, thereby locating the data to be written in each storage cell of the storage cell array, and then the test data can be written into the corresponding storage cells in the storage module in sequence.

[0062] The test data may be selected from a plurality of test item data preset in the test command circuit 31. In one example, the test data included in the test item data is, for example, a test pattern, which may include various test patterns for detecting specific faults and structural defects and has a high fault coverage; the test pattern may include a random test pattern, a pseudo-random test pattern (which is similar to a random test pattern except that its test vector sequence is repeated), or a test pattern for parallel bit testing (PBT) including the same data (e.g., "0" or "1").

[0063] The corresponding test command circuit 31 will also send the test data written into each storage unit to the comparison circuit 32. After a specific time interval, the comparison circuit 32 reads data from each storage unit of the storage module to obtain the detection data; wherein the specific time interval is related to the type of storage device. For example, if the storage device is DRAM, the specific time interval is usually set to just reach the refresh time interval specified by the DRAM standard.

[0064] Then, the comparison circuit 32 uses the test data sent by the test command circuit 31 as the reference data, compares the test data with the detection data read from the storage cell array, compares the detection data with the data corresponding to the same storage cell address in the test data, and records the address and fault type of the storage cell where the fault occurs in the storage module; the fault information of the storage module includes: the address and fault type of each storage cell where the fault occurs in the storage module.

[0065] For each storage cell, if the test data written into the storage cell is consistent with the detection data read from the storage cell, it means that the storage cell does not have a fault; if the test data written into the storage cell is inconsistent with the detection data read from the storage cell, it means that the storage cell has a fault. Specifically, the detection data and the test data are compared row by row according to the storage cell array in the storage module. For each row of the storage cell array, if the detection data and the test data are inconsistent in the data of some storage cells in all the storage cells included in the row, the addresses of the storage cells with inconsistent data and the fault type are recorded as single-bit faults, wherein the addresses of the storage cells with inconsistent data include the row address of the row where the storage cell is located and the column address of the column where the storage cell is located; if the detection data and the test data are inconsistent in the data of all the storage cells included in the row, the address of the row and the fault type are recorded as word line faults; if the detection data and the test data are consistent in the data of all the storage cells included in the row, it means that the storage cells in the row do not have a fault. In one example, if the detection data and the test data are inconsistent in data of all memory cells included in a column of the memory cell array, the address of the column and the failure type are recorded as a bit line failure.

[0066] In one example, the comparison circuit 32 is, for example, an exclusive OR (XOR) logic circuit or an exclusive OR (XNOR) logic circuit; for each storage unit in the storage module, if the logic states of the detection data and the test data are consistent, the comparison circuit 32 can output, for example, a comparison signal of a logic low level to indicate that the storage unit has no fault; conversely, if the logic states of the detection data and the test data are inconsistent, the comparison circuit 32 can output, for example, a comparison signal of a logic high level to indicate that the storage unit has a fault.

[0067] In addition, in this embodiment, the area overhead of the distributed detection unit separately configured for each storage module is smaller than that of a single storage module, and will not increase the area overhead of the storage module.

[0068] In one embodiment, please refer to Figure 6 The clock generation module 1 includes: an enable state register 11, an oscillating circuit 12 and a frequency multiplier 13; further, the clock generation module 1 also includes a temperature compensation circuit 14. The enable state register 11 is electrically connected to the oscillating circuit 12, the frequency multiplier 13 and the temperature compensation circuit 14 respectively, the oscillating circuit 12 is electrically connected to the frequency multiplier 13, and the temperature compensation circuit 14 is electrically connected to the oscillating circuit 12.

[0069] The enable state register 11 is used to activate the oscillation circuit 12, the frequency multiplier 13 and the temperature compensation circuit 14 to start working after receiving the self-test enable signal. Specifically, the enable state register 11 is connected to the self-test module 2, and the self-test module 2 sends a high-level self-test enable signal to the enable state register 11, and the enable state register 11 activates the oscillation circuit 12, the frequency multiplier 13 and the temperature compensation circuit 14 to start working.

[0070] The oscillator circuit 12 is used to generate a clock signal of a preset reference clock frequency, and send the clock signal of the reference clock frequency to the frequency multiplier 13. The oscillator circuit 12 may be composed of an inverter chain, and may generate a clock signal of a preset reference clock frequency.

[0071] The frequency multiplier 13 is used to amplify the reference clock frequency of the clock signal to obtain a self-test clock signal. Among them, the reference clock frequency of the clock signal sent by the oscillation circuit 12 is lower than the operating frequency of the core device of the storage device (DRAM). Therefore, in order to provide the high-frequency clock frequency required by the core device of the storage device (for example, the storage device is DRAM, DDR / DDR2 / DDR3 / DDR4 is up to 200M, and DDR5 / LPDDR5 is up to 400M), the frequency multiplier 13 can amplify the reference clock frequency of the clock signal sent by the oscillation circuit 12 to obtain a self-test clock signal that can meet the high-frequency clock frequency required by the core device of the storage device. The frequency multiplier 13 outputs the self-test clock signal to the self-test module 2 and each distributed detection unit 3.

[0072] The temperature compensation circuit 14 is used to perform temperature compensation on the oscillation circuit 12 so that the oscillation circuit 12 outputs a clock signal with a stable reference clock frequency, thereby preventing the read and write timing of the storage device from being affected by temperature.

[0073] After the self-test is completed, the self-test module 2 sends a low-level self-test completion signal to the enable status register 11, the oscillation circuit 12, the frequency multiplier 13 and the temperature compensation circuit 14 stop working, and the clock generation module 1 no longer outputs the self-test clock signal, thereby reducing power consumption.

[0074] In this embodiment, please refer to Figure 7 The self-detection circuit also includes: a first multiplexer MUX1, a second multiplexer MUX2, a third multiplexer MUX3 and a fourth multiplexer MUX4.

[0075] One input end of the first multiplexer MUX1 is connected to the external clock signal CLK, the other input end is connected to the clock generation module 1, and the output end of the first multiplexer MUX1 is respectively connected to the self-detection module 2 and each distributed detection unit 3; One input end of the second multiplexer MUX2 is connected to the external command signal source CMD / ADDR through the external command bus, the other input end is connected to the self-detection module 2, and the output end of the second multiplexer MUX2 is connected to the test command circuit 31 of the distributed detection unit 3 through the command transmission bus CMD_BUS; One input end of the third multiplexer MUX3 is connected to the external data signal source DQ through the external data signal bus, the other input end is connected to the self-detection module 2, and the output end of the third multiplexer MUX3 is connected to the comparison circuit 32 of the distributed detection unit 3. Specifically, one input end of the third multiplexer MUX3 is connected to the fourth multiplexer MUX4, the other input end of the fourth multiplexer MUX4 is connected to the self-detection module 2, and the output end of the fourth multiplexer MUX4 is connected to the external data signal source DQ through the external data signal bus.

[0076] The self-detection module 2 is also connected to the control terminals of the first multiplexer MUX1, the second multiplexer MUX2, the third multiplexer MUX3 and the fourth multiplexer MUX4 respectively; The self-test module 2 is used to send a self-test enable signal MBIST_EN to the control terminals of the first multiplexer MUX1 , the second multiplexer MUX2 , the third multiplexer MUX3 and the fourth multiplexer MUX4 respectively after entering the self-test mode of the storage device.

[0077] The clock generation module 1 is used to send the self-test clock signal MBIST_CLK to the first multiplexer MUX1, wherein the first multiplexer switches the clock source to the internal self-test clock signal when the self-test enable signal MBIST_EN is enabled, and selects to transmit the self-test clock signal MBIST_CLK to each distributed detection unit 3; wherein the clock generation module 1 also sends the self-test clock signal MBIST_CLK directly to the self-test module 2.

[0078] The self-test module 2 is also used to send self-test command data to the second multiplexer MUX2; wherein the second multiplexer MUX2 switches the command signal source to the self-test command data when the self-test enable signal MBIST_EN is enabled, and selects to send the self-test command data to the test command circuit 31 of each distributed detection unit 3 through the command transmission bus CMD_BUS.

[0079] The distributed detection unit 3 is used to send the fault information of the target storage module to the third multiplexer MUX3, wherein the third multiplexer MUX3 selects to send the fault information of the target storage module to the address storage unit 22 of the self-detection module 2 for storage when the self-detection enable signal MBIST_EN is enabled.

[0080] Furthermore, the data signal source of the third multiplexer MUX3 is switched to the self-test test data input by the self-test module 2, that is, the self-test module 2 sends the self-test test data to the distributed detection unit 3 through the third multiplexer MUX3, so that the distributed detection unit 3 can use the latest test data (self-test test data) to test the target storage module.

[0081] The self-detection module 2 sends the fault information of each storage module in the storage device to the fourth multiplexer MUX4. When the self-detection enable signal MBIST_EN is enabled, the fourth multiplexer MUX4 switches the signal output to the external data signal source DQ to the fault information of the storage module input by the self-detection module 2, that is, selects to send the fault information of each storage module to the external controller for storage.

[0082] As described above, by adding four multiplexers in the storage device, the switching between the internal clock signal and the external clock signal, the internal command signal and the external command signal, and the internal data signal source and the external data signal source is realized.

[0083] A third embodiment of the present invention relates to a storage device, comprising: a plurality of storage modules and the self-detection circuit in the second embodiment.

[0084] The storage device may be any one of the volatile memory devices: synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), low power double data rate SDRAM (LPDDR SDRAM), graphic double data rate SDRAM (GDDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, wide input / output (I / O) DRAM, high bandwidth memory (HBM), and hybrid memory cube (HMC). The storage module in the storage device may be implemented by an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small outline DIMM (SODIMM), etc. In addition, the storage device may also be any one of the following non-volatile memory devices: flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0085] For other embodiments, please refer to Figure 8 The storage device in this embodiment may further include a first group of dies and a second group of dies, the first group of dies including at least one buffer die, the second group of dies including K memory dies, K being an integer greater than 1; the second group of dies are stacked on top of the first group of dies, each memory die in the second dies exchanges control signals and / or data with the first group of dies through a plurality of through silicon via (TSV) lines, such as the TSV lines being electrically connected to micro bumps MCB formed between the K memory dies, respectively, each memory die includes at least one storage module, the storage module includes a storage cell array, and each storage cell includes an access transistor and a storage capacitor.

[0086] The buffer die may be configured with a clock generation module and a self-detection module in the self-detection circuit. The clock generation module generates an internal high-speed clock (i.e., a self-detection clock signal) required for self-detection. The self-detection module may include a detection state control unit and an address storage table (AST), and each memory die is provided with a number of distributed detection units corresponding to the storage modules one by one; wherein the address storage table is used to record fault information (fault type and fault address), or to store fault information read from an external controller.

[0087] The detection state control unit sends a self-detection test command and instructs the distributed detection units in the K memory dies to perform a fault test.

[0088] Among them, the specific functions of the self-detection module, the clock generation module and the distributed detection unit are similar to those in the first embodiment. Please refer to the first embodiment for details and will not be repeated here.

[0089] Since the first and second embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the first and second embodiments. The relevant technical details mentioned in the first and second embodiments are still valid in this embodiment, and the technical effects that can be achieved in the first and second embodiments can also be achieved in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the first and second embodiments.

[0090] The fourth embodiment of the present invention relates to a storage system, comprising: a controller and the storage device of the third embodiment, wherein the controller is an external controller connected to the storage device.

[0091] Preferred embodiments of the present invention have been described above in detail, but it should be understood that aspects of the embodiments can be modified, if necessary, to employ aspects, features and concepts of the various patents, applications and publications to provide further embodiments.

[0092] These and other changes can be made to the embodiments in light of the above detailed description.In general, in the claims, the terms used should not be considered limited to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which these claims are entitled.

Claims

1. A self-detection method for a storage device, characterized in that: A self-detection circuit applied to a storage device, the self-detection circuit comprising: a clock generation module, a self-detection module, and a plurality of distributed detection units; the plurality of distributed detection units correspond one-to-one to a plurality of storage modules in the storage device; the method comprising: After entering the self-test mode of the storage device, the self-test module sends a self-test enable signal to the clock generation module, and sends self-test command data to each of the distributed detection units; After receiving the self-test enable signal, the clock generation module generates a self-test clock signal and sends it to the self-test module and each of the distributed detection units; The distributed detection unit acquires test-related data for testing the corresponding target storage module based on the self-test command data, performs a fault test on the target storage module based on the test-related data, obtains fault information of the target storage module, and sends the fault information to the self-test module; wherein the test-related data includes test data for writing into the corresponding storage module and a test unit address corresponding to the test data; After all the storage modules have completed self-test, the self-test module sends a self-test completion signal to the clock generation module to shut down the clock generation module.

2. A self-detection circuit for a storage device, characterized in that: The storage device includes a plurality of storage modules, and the self-detection circuit includes: a clock generation module, a self-detection module, and a plurality of distributed detection units; the plurality of distributed detection units correspond to the plurality of storage modules one by one; The self-detection module is used to send a self-detection enable signal to the clock generation module and send self-detection command data to each of the distributed detection units after entering the self-detection mode of the storage device; The clock generation module is used to generate a self-test clock signal after receiving the self-test enable signal and send it to the self-test module and each of the distributed detection units; The distributed detection unit is used for: Based on the self-test command data, acquiring test-related data for testing the corresponding target storage module, the test-related data including test data for writing the corresponding storage module and a test unit address corresponding to the test data; Performing a fault test on the target storage module based on the test-related data to obtain fault information of the target storage module, and sending the fault information to the self-detection module; The self-detection module is further configured to send a self-detection completion signal to the clock generation module after all the storage modules have completed self-detection, so as to shut down the clock generation module.

3. The self-detection circuit for a storage device according to claim 2, characterized in that: The self-detection module is also used to send the fault information of each storage module to the external controller, so that the external controller can store the fault information of each storage module; The self-detection module is used to enter the self-detection mode after the storage device is powered on: if a self-detection start signal sent by the external controller is received; If a control instruction instructing external writing of fault information sent by the external controller is received, self-detection is skipped, and the fault information of the storage module is obtained from the external controller and stored.

4. The self-detection circuit for a storage device according to claim 2, characterized in that: The distributed detection unit includes: a test command circuit and a comparison circuit; The test command circuit is used to: Based on the self-test command data, selecting a target test item from a plurality of pre-stored test items, the target test item including test data for writing into a corresponding target storage module and a test unit address corresponding to the test data; Writing the test data into a corresponding test unit address in a target storage module, and sending the test data to the comparison circuit; The comparison circuit is used to read detection data from the target storage module, compare the detection data with data corresponding to the same storage unit address in the test data, and record the address and fault type of the storage unit where the fault occurs in the storage module; the fault information of the storage module includes: the address and fault type of each storage unit where the fault occurs in the storage module.

5. The self-detection circuit for a storage device according to claim 4, characterized in that: Each of the memory modules includes a memory cell array formed by a plurality of memory cells; The comparison circuit is used to compare the detection data with the test data row by row according to the storage cell array in the storage module. For each row of the storage cell array, if the detection data and the test data are inconsistent in data in some storage cells among all the storage cells included in the row, the addresses of the storage cells with inconsistent data and the fault type are recorded as single-bit faults; if the detection data and the test data are inconsistent in data in all the storage cells included in the row, the address of the row and the fault type are recorded as word line faults.

6. The self-detection circuit for a storage device according to claim 2, characterized in that: The self-detection module includes: a detection state control unit and an address storage unit; The detection state control unit is used to send a self-test enable signal to the clock generation module after entering the self-test mode of the storage device; and send self-test command data to each of the distributed detection units; The distributed detection unit is used to send the fault information to the address storage unit for storage.

7. The self-detection circuit for a storage device according to claim 2, characterized in that: The clock generation module includes: an enable status register, an oscillation circuit and a frequency multiplier; The enable status register is used to activate the oscillation circuit and the frequency multiplier to start working after receiving the self-test enable signal; The oscillation circuit is used to generate a clock signal of a preset reference clock frequency, and send the clock signal of the reference clock frequency to the frequency multiplier; The frequency multiplier is used to amplify the reference clock frequency of the clock signal to obtain the self-test clock signal.

8. The self-detection circuit for a storage device according to claim 2, characterized in that: The self-detection circuit further comprises: a first multiplexer, a second multiplexer and a third multiplexer, wherein one input end of the first multiplexer is connected to an external clock signal and another input end is connected to the clock generation module, one input end of the second multiplexer is connected to an external command signal and another input end is connected to the self-detection module, and one input end of the third multiplexer is connected to an external data signal bus and another input end is connected to the self-detection module; The self-test module is used to send a self-test enable signal to the first multiplexer, the second multiplexer and the third multiplexer respectively after entering the self-test mode of the storage device; The clock generation module is used to send the self-test clock signal to the first multiplexer, wherein the first multiplexer selects to transmit the self-test clock signal to each of the distributed detection units when enabled by the self-test enable signal; The self-test module is used to send the self-test command data to the second multiplexer, wherein the second multiplexer selects to send the self-test command data to each of the distributed detection units when the self-test enable signal is enabled; The distributed detection unit is used to send the fault information of the target storage module to the third multiplexer, wherein the third multiplexer selects to send the fault information of the target storage module to the self-detection module when the self-detection enable signal is enabled; The first multiplexer is further configured to select to switch the external clock signal to an internal clock source of the storage device when the self-test enable signal is not received.

9. A storage device, characterized in that: include: A plurality of storage modules and the self-detection circuit according to any one of claims 2 to 8.

10. A storage system, characterized in that: include: A controller and the storage device as claimed in claim 9.

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