Packaging method and packaging structure of gallium nitride cascade device

Abstract

The invention relates to a packaging method and a packaging structure of a gallium nitride cascade device. The method comprises the following steps: carrying out electrode position transfer on at least one of an original gallium nitride chip and an original low-voltage enhancement chip; providing a packaging frame; mounting a gallium nitride chip and a low-voltage enhancement chip on the base island; electrical interconnection including electrically connecting a drain electrode of the gallium nitride chip and a device drain electrode region of the packaging frame; the device gate region is electrically connected with the gate of the low-voltage enhancement chip and the packaging frame; the source electrode of the gallium nitride chip is electrically connected with the drain electrode of the low-voltage enhancement chip; and carrying out plastic packaging and cutting on the connecting rib to obtain a single gallium nitride cascade device. According to the invention, the production cost is reduced, the packaging process flow of the gallium nitride cascade device is simplified, and the performance and reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a packaging method and a packaging structure of a gallium nitride cascade device. Background Art

[0002] A GaN cascode device is a device structure that combines GaN high electron mobility transistors (HEMTs) and low voltage transistors. Low voltage transistors are, for example, field effect transistors and triodes, where the field effect transistors can be metal-oxide-semiconductor field-effect transistors (MOS) or junction field-effect transistors (JEFT). In the following description, the MOS structure is used as an example. See Figure 1 , Figure 1 This is an electrical schematic diagram of a gallium nitride cascade device in the prior art. The MOS drain D2 of MOS Q2 is connected to the HEMT source S1 of HEMT Q1, the MOS source S2 is connected to the HEMT gate G1 and serves as the source S of the gallium nitride cascade device, the HEMT drain D1 serves as the drain D of the gallium nitride cascade device, and the MOS gate G2 serves as the gate G of the gallium nitride cascade device. By cascading the high-voltage HEMT with the low-voltage MOS and using the low-voltage MOS to provide a driving interface, the high requirements of the GaN device on the gate driving circuit are avoided.

[0003] Among them, the chip structure of conventional low-voltage silicon-based MOS is usually that the gate and source are located on the front of the chip, and the drain is located on the back of the chip, that is, the back of the substrate. The chip structure of conventional HEMT is usually that the gate, source and drain are located on the front of the chip. Therefore, the packaging structure of GaN Cascode in the prior art is as follows Figure 2 As shown, Figure 2The device packaging structure of GaN Cascode in the prior art is schematically shown. The device packaging of GaN Cascode in the prior art includes a packaging frame 1, a HEMT chip U1, a MOS chip U2 and a substrate U3. The backs of the HEMT chip U1 and the substrate U3 are fixed to the conductive area of ​​the base island 11 of the packaging frame 1 through an insulating layer. The conductive area of ​​the base island 11 can be used as the device source S of the GaN cascode. The MOS drain D2 on the back of the MOS chip U2 is attached to the conductive metal area 21 on the front of the substrate U3 through conductive adhesive, etc. The conductive metal area 21 is connected to the HEMT source S1 of the HEMT chip U1 through bonding wires. The MOS source S2 on the front of the MOS chip U2 is electrically connected to the conductive area of ​​the base island 11 of the package frame 1 through bonding wires. The MOS gate G2 on the front of the MOS chip U2 is connected to the gate area 12 of the package frame 1 through bonding wires. The HEMT drain D1 of the HEMT chip U1 is connected to the drain area 13 of the package frame 1 through bonding wires. The HEMT gate G1 of the HEMT chip U1 is connected to the conductive area of ​​the base island 11 of the package frame 1 through bonding wires, thereby achieving electrical connection with the MOS source S2.

[0004] pass Figure 2 It can be seen from the package structure shown that since the electrode layout structure of the MOS chip U2 is not very compatible with the electrode layout structure of the HEMT chip U1, it is necessary to add a substrate U3 to the package structure, so that the GaN Cascode needs to be loaded three times during the packaging process, which takes a long time; in addition, since the substrate U3 needs to be insulated from the source region of the device, the insulating layer structure of the substrate U3 is relatively complex; and there are too many bonding wires in the package structure, and the parasitic inductance / resistance is large, which will reduce the reliability and other performances of the GaN Cascode; in addition, the large area of ​​the substrate U3 makes it impossible for the GaN Cascode to adopt a traditional small package structure, resulting in a high packaging cost of the GaN Cascode and limiting the miniaturization of the GaN Cascode. Summary of the invention

[0005] In view of the technical problems existing in the prior art, the present invention proposes a packaging method and a packaging structure of a gallium nitride cascade device, which are suitable for various packaging methods and can improve the performance of the gallium nitride cascade device.

[0006] In order to solve the above technical problem, according to one aspect of the present invention, the present invention provides a packaging method of a gallium nitride cascade device, comprising the following steps:

[0007] performing electrode position transfer on at least one of the original gallium nitride chip and the original low-voltage enhancement chip;

[0008] Providing a packaging frame, the packaging frame comprising a plurality of frame units connected together by connecting ribs, each frame unit comprising a base island for mounting a chip, a device gate region, a device drain region and a device source region;

[0009] Mount the GaN chip and low voltage enhancement chip on the base island;

[0010] Conducting electrical interconnection, including: electrically connecting the drain of the gallium nitride chip and the device drain region of the frame unit; electrically connecting the gate of the gallium nitride chip and the device source region of the frame unit; electrically connecting the gate of the low-voltage enhancement chip and the device gate region of the frame unit; electrically connecting the source of the gallium nitride chip and the drain of the low-voltage enhancement chip; and

[0011] Plastic encapsulation and cutting of connecting ribs to obtain a single GaN cascade device.

[0012] Preferably, when transferring the electrode position of the target chip, the target electrode is rearranged from the original position to the preset position through the redistribution layer based on the RDL process, and the target electrode is one or more of the drain, source and gate, wherein the target chip is the original gallium nitride chip and / or the original low-voltage enhancement chip.

[0013] Preferably, when the relative areas of the original position electrode surface and the preset position electrode surface of the target electrode are relatively large, the redistribution layer is obtained by planting balls or electroplating metal columns between the original position electrode surface and the preset position electrode surface of the target electrode.

[0014] Preferably, when transferring the electrode position of the target chip, when the original position and the preset position of the target electrode are respectively located on the front and back sides of the chip, an electrode hole is provided in the secondary plastic package, and the redistribution layers respectively located on the front and back sides of the chip are connected to the electrode hole.

[0015] Preferably, when transferring the electrode position of the target chip, when the chip surface where the target electrode is originally located also includes a second electrode, after rearranging the target electrode to the opposite surface through the redistribution layer and the electrode hole, it further includes: thickening the electrode surface of the second electrode; fanning out the electrode surface of the second electrode to a preset position on the current chip surface.

[0016] Preferably, the step of fanning out the electrode surface of the second electrode to a preset position on the surface of the current chip includes: fanning out the electrode surface of the second electrode to the entire surface of the current chip; and patterning the electrode surface of the entire surface to be staggered with the internal redistribution layer.

[0017] Preferably, the target chip is a wafer-level chip or a finished chip; when the target chip is a wafer-level chip, the back side of the wafer is thinned before performing the RDL process.

[0018] Preferably, when transferring the electrode position of at least one of the original gallium nitride chip and the original low-voltage enhancement chip, the source electrode of the gallium nitride chip for packaging and the drain electrode of the low-voltage enhancement chip for packaging are located on the same surface of the respective chips;

[0019] Correspondingly, the gallium nitride chip and the low-voltage enhancement chip are mounted in parallel on the base island; when electrically interconnected, when the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the front side of their respective chips, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are electrically connected through metal connectors; when the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the back side of their respective chips, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are respectively in contact with and electrically connected to the conductive area on the base island.

[0020] Preferably, when transferring the electrode position of the original gallium nitride chip, the gallium nitride gate is rearranged from the original position on the front side to the back side, so as to increase the source electrode surface of the gallium nitride electrode;

[0021] Correspondingly, when mounting the gallium nitride chip and the low-voltage enhancement chip on the base island, the gallium nitride chip is mounted on the conductive area of ​​the base island, and the original low-voltage enhancement chip is mounted on the gallium nitride source electrode surface; wherein the gate on the back of the gallium nitride chip is electrically connected to the conductive area of ​​the base island; and the drain on the back of the original low-voltage enhancement chip is electrically connected to the gallium nitride source electrode surface.

[0022] The present invention also provides a packaging structure of a gallium nitride cascade device, comprising:

[0023] A packaging frame, the packaging frame comprising a base island for mounting a chip, a device gate region, a device drain region and a device source region;

[0024] Gallium nitride chip;

[0025] Low voltage enhancement chip; and

[0026] Plastic sealing body;

[0027] The gallium nitride chip and the low-voltage enhancement chip are mounted on the base island of the packaging frame; the gallium nitride chip is an original gallium nitride chip or a chip obtained by transferring the electrode position of the original gallium nitride chip, and the low-voltage enhancement chip is an original low-voltage enhancement chip or a chip obtained by transferring the electrode position of the original low-voltage enhancement chip;

[0028] The drain of the gallium nitride chip is electrically connected to the device drain region of the packaging frame; the gate of the gallium nitride chip and the source of the low-voltage enhancement chip are electrically connected to the device source region of the packaging frame respectively; the gate of the low-voltage enhancement chip is electrically connected to the device gate region of the packaging frame; the source of the gallium nitride chip is electrically connected to the drain of the low-voltage enhancement chip.

[0029] Optionally, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the same surface of their respective chips; the gallium nitride chip and the low-voltage enhancement chip are mounted side by side on a base island of a packaging frame; when the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the front sides of their respective chips, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are electrically connected through metal connectors; when the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the back sides of their respective chips, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are respectively in contact with and electrically connected to the conductive areas on the base island.

[0030] Optionally, the gallium nitride chip is an original gallium nitride chip, whose drain, source and gate are distributed on the front side of the chip, and the low-voltage enhancement chip is a chip obtained by transferring the electrode position of the original low-voltage enhancement chip, the drain and gate of the low-voltage enhancement chip are distributed on the front side of the chip, and the source is distributed on the back side of the chip, and the source of the low-voltage enhancement chip is in contact with and electrically connected to the conductive area on the base island; the gate of the gallium nitride chip is electrically connected to the conductive area on the base island via a metal connector.

[0031] Optionally, the gallium nitride chip is an original gallium nitride chip, whose drain, source and gate are distributed on the front side of the chip, and the low-voltage enhancement chip is a chip obtained by transferring the electrode position of the original low-voltage enhancement chip, the source, drain and gate of the low-voltage enhancement chip are distributed on the front side of the chip, and the gate of the gallium nitride chip is electrically connected to the conductive area on the base island through a metal connector; the source of the low-voltage enhancement chip is electrically connected to the conductive area on the base island through a metal connector.

[0032] Preferably, the low-voltage enhancement chip is an original low-voltage enhancement chip, whose drain is distributed on the back of the chip, and the source and gate are distributed on the front of the chip; the gallium nitride chip is a chip obtained by transferring the electrode position of the original gallium nitride chip, the gate and drain of the gallium nitride chip are located on the front of the chip, and the source is located on the back of the chip; the drain on the back of the low-voltage enhancement chip and the source of the gallium nitride chip are respectively in contact and electrically connected with the conductive area on the base island; the source on the back of the low-voltage enhancement chip and the gate of the gallium nitride chip are respectively electrically connected to the source area of ​​the device through metal connectors.

[0033] Preferably, the gallium nitride chip is a chip obtained by transferring the electrode position of the original gallium nitride chip, the drain, source and gate of the original gallium nitride chip are distributed on the front side of the chip, the drain and source of the gallium nitride chip obtained after the electrode position transfer are located on the front side of the chip, and the gate is located on the back side of the chip; the low-voltage enhancement chip is a chip obtained by transferring the electrode position of the original low-voltage enhancement chip, the drain of the original low-voltage enhancement chip is distributed on the back side of the chip, the source and gate are distributed on the front side of the chip, and the drain and gate of the low-voltage enhancement chip obtained after the electrode position transfer are located on the front side of the chip; the gate of the gallium nitride chip is electrically connected to the conductive area on the base island; the drain of the low-voltage enhancement chip and the source of the gallium nitride chip are electrically connected through a metal connector.

[0034] Preferably, the source, drain and gate of the low-voltage enhancement chip obtained after the electrode position transfer are all located on the front side of the chip, and the source of the low-voltage enhancement chip and the conductive area on the base island are electrically connected through a metal connector.

[0035] Preferably, the source electrode of the low-voltage enhancement chip obtained after the electrode position transfer is located on the back side of the chip, and the source electrode of the low-voltage enhancement chip is in contact with and electrically connected to the conductive area on the base island.

[0036] Preferably, the gallium nitride chip is a chip obtained by transferring the electrode position of the original gallium nitride chip, the drain, source and gate of the original gallium nitride chip are distributed on the front side of the chip, the drain and gate of the gallium nitride chip obtained after the electrode position transfer are located on the front side of the chip, and the source is located on the back side of the chip; the low-voltage enhancement chip is a chip obtained by transferring the electrode position of the original low-voltage enhancement chip, the drain, source and gate of the original low-voltage enhancement chip are distributed on the front side of the chip, and the drain, source and gate of the low-voltage enhancement chip obtained after the electrode position transfer are located on the front side of the chip; the gate of the gallium nitride chip is electrically connected to the source region of the device through a metal connector, and the drain of the low-voltage enhancement chip is electrically connected to the conductive region on the base island through a metal connector; the source of the low-voltage enhancement chip is electrically connected to the source region of the device through a metal connector.

[0037] Preferably, the metal connecting member is a bonding wire used in a wire bonding process, a metal strip used in a strip bonding process, or a metal sheet used in a pressure welding bridging process.

[0038] Preferably, the target chip after the electrode position transfer includes an original chip, a redistribution layer and a secondary plastic package, wherein the original chip and the redistribution layer are located in the secondary plastic package; the redistribution layer rearranges the target electrode from the original position to a preset position; the target electrode is one or more of a drain, a source and a gate, and the target chip is an original gallium nitride chip and / or an original low-voltage enhancement chip.

[0039] Preferably, electrode holes are provided in the secondary plastic package, and the redistribution layer includes a first redistribution layer and a second redistribution layer, the first redistribution layer is connected to the electrode surface and the electrode hole of the preset position of the target electrode, and the second redistribution layer is connected to the electrode surface and the electrode hole of the original position of the target electrode, and the original position and the preset position of the target electrode are respectively arranged on the front and back sides of the chip.

[0040] Preferably, the original position electrode surface and the preset position electrode surface of the target electrode are located on the same surface of the chip, and the redistribution layer is obtained between the original position and the preset position of the target electrode by ball planting or electroplating metal columns.

[0041] Preferably, the redistribution layer in the secondary plastic package is staggered with the electrode surface on the surface of the secondary plastic package, and the electrode surface on the surface of the secondary plastic package is a drain, a source or a gate.

[0042] Preferably, the gallium nitride chip is a chip obtained by transferring the electrode position of the original gallium nitride chip, the gallium nitride gate is located on the back of the chip, and the gallium nitride drain and gallium nitride source are located on the front of the chip; the low-voltage enhancement chip is the original chip, the source and gate of the low-voltage enhancement chip are located on the front of the chip, and the drain is located on the back of the chip;

[0043] The gallium nitride chip is mounted on the conductive area of ​​the base island, and the gallium nitride gate on the back of the gallium nitride chip is electrically connected to the conductive area of ​​the base island; the low-voltage enhancement chip is mounted on the gallium nitride source electrode surface; the drain on the back of the low-voltage enhancement chip is electrically connected to the gallium nitride source electrode surface.

[0044] The present invention transforms the electrode layout position by shifting the electrode position of the MOS chip and / or HEMT chip used, reduces the number of bonding wires, and can also eliminate the large substrate used in the package to adapt to a small package structure, thereby reducing costs and simplifying the packaging process of the gallium nitride cascade device, improving the performance of the device, and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The preferred embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:

[0046] Figure 1 It is an electrical schematic diagram of a gallium nitride cascade device in the prior art;

[0047] Figure 2 It is a schematic diagram of the device packaging structure of GaN Cascode in the prior art;

[0048] Figure 3 is a schematic diagram of a device packaging structure of a GaN Cascode according to Embodiment 1 of the present invention;

[0049] Figure 4is a flow chart of a GaN Cascode packaging method according to Embodiment 1 of the present invention;

[0050] Figure 5 1 is a schematic diagram of the side structure of the device packaging structure of the GaN Cascode after the patch and interconnection are completed according to the first embodiment of the present invention;

[0051] Figure 6 is a schematic diagram of the structure of a MOS chip during the process of transferring the electrode position of the MOS chip according to an embodiment of the present invention;

[0052] Figure 7 is a schematic cross-sectional view of a chip structure obtained after the position of electrodes of an original MOS chip is transferred according to another embodiment of the present invention;

[0053] Figure 8 is a schematic diagram of a device packaging structure of a GaN Cascode according to Embodiment 2 of the present invention;

[0054] Fig. 9 is a schematic diagram of the structure of a MOS chip during the process of transferring the electrode position of the MOS chip according to another embodiment of the present invention;

[0055] Fig.10 is a schematic diagram of a device packaging structure of a GaN Cascode according to Embodiment 3 of the present invention;

[0056] Fig.11 A schematic cross-sectional view of a chip structure obtained after transferring the electrode position of a HEMT chip according to an embodiment of the present invention;

[0057] Fig.12 is a schematic diagram of a device packaging structure of a GaN Cascode according to a fourth embodiment of the present invention;

[0058] Fig.13 is a schematic cross-sectional view of a chip structure obtained after transferring the electrode position of a HEMT chip according to another embodiment of the present invention;

[0059] Fig.14 is a schematic diagram of a device packaging structure of a GaN Cascode according to Embodiment 5 of the present invention;

[0060] Fig.15 is a schematic diagram of a device packaging structure of a GaN Cascode according to a sixth embodiment of the present invention;

[0061] Fig.16 A schematic diagram of a GaN Cascode packaging structure according to Embodiment 7 of the present invention; and

[0062] Fig.17Schematic diagram of the GaN Cascode packaging structure according to Embodiment 8 of the present invention. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0065] The present invention provides a packaging method and packaging structure of a gallium nitride cascade device, wherein the gallium nitride cascade device is a composite switch composed of a high-voltage gallium nitride chip and a low-voltage enhancement chip, wherein the high-voltage gallium nitride chip is, for example, a HEMT, and the low-voltage enhancement chip is, for example, a MOS, a JEFT, or a triode. In the following description, a cascode composed of a HEMT and a MOS is taken as an example, but it can be known that the following packaging method and corresponding structure are also applicable to a cascode in which the low-voltage chip is a JEFT or a triode.

[0066] Since the drain of conventional MOS chips is located on the back of the chip, the source and gate are located on the front of the chip, and the drain, source and gate of conventional HEMT chips are located on the front of the chip, in order to achieve Figure 1 The electrical connection relationship shown in the figure is as follows: Figure 2 As shown, it is necessary to use the substrate U3 and to wire the HEMT gate G1 of the HEMT chip U1, and to electrically connect it to the base island conductive area on the packaging frame through the bonding wire. In view of this packaging structure, the present invention transfers the electrode position of at least one of the conventional HEMT chip and the conventional MOS chip to change the distribution position of the electrode, thereby achieving the purpose of reducing wire bonding and simplifying the packaging process. In addition, in the present invention, the chip surface that is used to contact the base island or substrate of the packaging frame in the chip mounting step during the packaging process is called the back side, and the opposite side is called the front side.

[0067] In addition, the packaging forms that can be used for the GaN Cascode in the present invention include but are not limited to QFN, DFN, TO, CSP, BGA, SOP, FOPLP and FOWLP. Therefore, in the following description, the packaging frame used in the packaging structure can be in any form. The packaging frame in the following embodiment is only used as an example for simple explanation. In actual production, any packaging frame suitable for a given packaging form and the corresponding subsequent packaging process flow can be used as needed.

[0068] Embodiment 1

[0069] Figure 3 Schematic diagram of the device packaging structure of GaN Cascode according to the first embodiment of the present invention. The device packaging structure of GaN Cascode in the first embodiment includes a packaging frame 1, a HEMT chip U1 and a MOS chip U2. The HEMT chip U1 in this embodiment is a conventional HEMT chip, and three electrodes are distributed on the front of the chip, including a long strip of HEMT drain D1, a long strip of HEMT source S1 and two square HEMT gates G1. The MOS chip U2 is a chip after the electrode position of the conventional MOS chip is transferred. The MOS drain D2 and MOS gate G2 of the MOS chip U2 are located on the front of the chip, and the MOS source S2 is located on the back of the chip.

[0070] See also Figure 4 , Figure 4 : is a flow chart of a GaN Cascode packaging method according to Embodiment 1 of the present invention, wherein the packaging method comprises the following steps:

[0071] Step S1, providing a HEMT chip U1 and a MOS chip U2, wherein the HEMT chip U1 is a conventional HEMT chip, and the MOS chip U2 is a chip obtained after the electrode position is transferred.

[0072] Step S2, providing a packaging frame 1. According to the packaging category determined by specific needs, a corresponding packaging frame is adopted. The packaging frame includes a plurality of frame units connected together by connecting ribs, and each frame unit includes at least a base island 11 for mounting a chip, a device gate region 12, and a device drain region 13. In the present embodiment, the base island 11 is also a device source region. In addition, according to the packaging category of the application, the device gate region 12, the device drain region 13, and the device source region in the packaging frame in the present embodiment can also be deformed into corresponding pins, so that a person of ordinary skill in the art can understand that the device gate region 12, the device drain region 13, and the device source region in the present invention can have the same function as the pins in other packages. In order to correspond to the structure in a single device, each frame unit is referred to as a packaging frame 1 in the following description.

[0073] Step S3, mounting the HEMT chip U1 and the MOS chip U2 on the base island in parallel. Figure 5 ) The back side of the HEMT chip U1 is mounted on a predetermined position on the base island, and the back side of the MOS chip U2 is mounted on the base island 11 by using a conductive adhesive, in parallel with the HEMT chip U1. Since the MOS source S2 is located on the back side of the chip and is mounted by a conductive adhesive, the MOS source S2 is electrically connected to the conductive area on the base island in a contact manner (referred to as contact electrical connection).

[0074] Step S4, electrical interconnection, that is, completing the electrical connection between the two chip electrodes and between the electrodes and the packaging frame. In the present invention, the electrical connection in the interconnection step can be in any form. In the present embodiment, the interconnection is performed by wire bonding. For example, a wire is bonded between the HEMT drain D1 and the device drain region 13 through a wire bonding process to electrically connect the HEMT drain D1 and the device drain region 13. Similarly, a wire is bonded between the HEMT source S1 and the MOS drain D2 to electrically connect the HEMT source S1 and the MOS drain D2. A wire is bonded between the HEMT gate G1 and the base island 11 to electrically connect the HEMT gate G1 and the base island 11. Since the MOS source S1 is electrically connected to the base island 11, the electrical connection between the HEMT gate G1 and the MOS source S1 is achieved. A wire is bonded between the MOS gate G2 and the device gate region 12 to electrically connect the MOS gate G2 and the device gate region 12. See. Figure 3 , the base island 11, the device gate area 12 and the device drain area 13 of the packaging frame 1 are solid areas, and the area between the device gate area 12 and the device drain area 13 and the base island 11 is a hollow area. However, it can be known that in addition to using the wire bonding process to achieve electrical interconnection, a strip bonding process can also be used, such as bonding a metal strip by ultrasonic wedge bonding, and the metal strip can be an aluminum strip. A pressure welding bridging process can also be used to directly press-weld the metal sheet to the electrode surface of the chip and the pin or electrode area of ​​the device. The specific interconnection process can be flexibly selected according to actual conditions.

[0075] See also Figure 5 , Figure 5 1 is a schematic diagram of the side structure of the device packaging structure of the GaN Cascode after the patch and interconnection according to the first embodiment of the present invention. In this embodiment, the interconnection uses a bonding wire 41, such as a copper wire or an aluminum wire, but it can be known that when the device needs to be used in a high current scenario, copper tape, aluminum tape, copper sheet, etc. can also be used for interconnection.

[0076] Step S5, plastic encapsulation. For example, a plastic molding process is used to encapsulate plastic encapsulation materials such as epoxy resin around the chip, welding wire, etc., thereby protecting them. According to actual scenarios such as production equipment and production lines, transfer molding, compression molding, etc. can be used. This step can also include a step of surface grinding of the plastic encapsulation material to expose a flat electrode surface.

[0077] Step S6, electroplating or chemically plating Ag, Au or sputtering aluminum or other metals that can be used for wire bonding on the electrode surface.

[0078] Step S7, marking the surface of the plastic package of the device, for example, printing chip information such as brand, model, batch, production cycle, version, place of origin, etc. on the chip surface by laser or ink.

[0079] Step S8, cutting the entire plastic package body, removing the connecting ribs, flash, etc., to obtain a single GaN Cascode.

[0080] In this embodiment, after the electrode position of the MOS chip U2 is transferred, the MOS drain D2 and the HEMT source S1 to be interconnected are both located on the front of their respective chips, so the two can be directly interconnected by wire bonding and other methods, and no substrate is needed for transfer. Therefore, this embodiment does not require a substrate during packaging, and only needs to load the chip twice during chip loading, which shortens the packaging cycle and reduces the difficulty of packaging chip mounting and wire bonding. Figure 2 In comparison, this embodiment significantly reduces the number of wire bonds (can be reduced by more than 30%), and relatively reduces the parasitic inductance / resistance (experiments have shown that the parasitic inductance and resistance are reduced by more than 20%, respectively), so the performance of the packaged GaN cascade device is improved. At the same time, the packaging material used in this embodiment is small, which reduces the packaging cost. In addition, the solution provided by the present invention can effectively reduce the size of the device, so that it can be compatible with packaging frames of more forms and sizes, solving the problem that the original GaN cascade device is delaminated due to its large area or cannot be installed in packaging frames of other sizes and forms.

[0081] Figure 6 FIG. 1 is a schematic diagram of a MOS chip structure in a process of transferring the electrode position of a MOS chip according to an embodiment of the present invention. In this embodiment, a silicon wafer that has not been cut after the preparation of each semiconductor layer of the MOS and the source and gate is completed is used as the electrode position transfer processing target. To simplify the drawings, Figure 6 Only one conventional MOS die on a silicon wafer is shown. Specifically, the following steps are included:

[0082] Step S11, adding a UBM (Under-Bump Metallurgy) metal layer with a thickness of 1 to 10 um on the electrode surface of the front side of the wafer. The adding method is, for example, electroplating, evaporation or sputtering. The metal that can be used for UBM is, for example, titanium copper, nickel gold, nickel palladium gold, titanium nickel silver, etc. Figure 6 , Figure 6 The first figure is a conventional MOS grain on a wafer, and the second figure is a schematic diagram of the MOS grain structure after step S11.

[0083] Step S12, thinning the back of the wafer. This step is optional, and the silicon substrate on the back of the wafer is ground to a certain thickness to reduce the thickness of the original MOS grain, so as to avoid the MOS chip being too thick after the electrode position transfer.

[0084] Step S13, back-coating the back of the wafer with silver, gold or copper. The back of the conventional MOS is used as the drain. After the processing in step S13, a layer of metal is added at the original drain position, which is beneficial to the heat dissipation of the device. The thickness range is 1-10um.

[0085] Step S14, providing a metal layer for convenient metal electroplating on the back of the wafer or brushing on a conductive glue that can be used for metal electroplating, the thickness of which is greater than or equal to 10um.

[0086] Step S15, cutting the wafer to obtain a single MOS crystal, hereinafter referred to as MOS chip.

[0087] Step S16, flip-chipping a plurality of MOS chips onto a temporary bonding film at a certain interval, and performing back-side plastic sealing on the MOS chips, wherein the temporary bonding film is located on a temporary substrate / carrier.

[0088] Step S17, thinning the plastic package 51 on the back side of the MOS chip until the metal layer or glue layer on the back side of the MOS chip is exposed.

[0089] Step S18, drilling a hole in the package body next to the MOS chip body to form a G electrode hole. In an optional solution, the distance between the G electrode hole and the MOS chip body is small enough to reduce the length of the connection metal layer between the original gate on the front of the MOS chip and the metal at the G electrode hole, thereby reducing the parasitic parameters generated between the connection metal layer and the nearest source S electrode surface.

[0090] Step S19, electroplating a layer of copper on the upper surface of the current structure (i.e. the back of the MOS chip), and then etching to form a first redistribution layer RDL1, thereby forming a separated MOS drain D and a new MOS gate G, and the new gate G extends to the back of the plastic package through the G electrode hole.

[0091] Step S110, remove the carrier and temporary bonding film, expose the electrodes on the front of the MOS, that is, the source S and the original gate G, attach the back of the MOS to the temporary bonding film, electroplate the metal on the front of the MOS, and etch the electroplated metal layer to obtain the second redistribution layer RDL2. The second redistribution layer includes a thickened source S, a thickened original gate, and a connecting metal layer between the original gate and the G electrode hole, so that the original gate of the MOS is electrically connected to the new gate G. Preferably, when etching the electroplated metal layer, the area of ​​the connecting metal layer between the original gate and the G electrode hole is minimized. It can be seen that the electrode surface of the gate G of the original MOS chip of this embodiment and the electrode surface of the source S are located on the front of the chip, and the preset position electrode surface of the gate is located on the back of the chip. The original position of the gate G is transferred to the back of the chip through the second redistribution layer RDL2, the G electrode hole and the first redistribution layer RDL1 on the front. The G electrode hole is located in the secondary plastic package.

[0092] Step S111 , plastic-encapsulating the front side of the MOS chip, and grinding the upper surface of the plastic-encapsulating body 52 to expose the flat gate G electrode surface and the source S electrode surface.

[0093] Step S112, electroplating metal, such as copper, on the source S electrode surface on the front side of the MOS chip to raise the source S. In one embodiment, the height of the raised source S electrode surface is ≥15 um.

[0094] Step S113, plastic-encapsulating the front side of the MOS chip again, and grinding the upper surface of the plastic-encapsulating material to expose a flat source electrode S.

[0095] Step S114, fanning out the source S electrode surface to the entire surface of the current plastic package body to serve as the source S of the finished MOS, and then removing the carrier board and the temporary bonding film.

[0096] After the above steps, the gate G on the front side of the original MOS chip is rearranged to the back side of the chip, and the front side of the original MOS chip is the source S arranged on the entire surface. Therefore, the front side of the original MOS chip becomes the back side of the repackaged MOS chip, and the back side of the original MOS chip becomes the front side of the repackaged MOS chip.

[0097] Step S115, the electrode surface of the gate G and the drain D of the repackaged MOS are plated or electroplated with Ag, Au or sputtered with aluminum or other metals that can be used for wire bonding; the electrode surface of the source S of the repackaged MOS is plated or sputtered with Ag, Au or other metals that can be used for chip bonding.

[0098] Step S116, cutting and shaping, thereby obtaining a plurality of single MOS chips after the electrode positions are transferred.

[0099] pass Figure 6It can be seen from the electrode position transfer process shown that the present embodiment uses the RDL process to rearrange the gate of the original MOS chip to the back of the original chip, and fans out the source on the front of the original chip to the size of the current chip, so that the front and back of the MOS chip after the electrode position transfer are exactly opposite to the front and back of the original MOS chip. When the present invention repackages the MOS chip, the electrode area of ​​the MOS gate can be expanded through the RDL process, which can not only meet the needs of using aluminum wires, copper strips or aluminum strips with larger cross-sectional areas to achieve interconnection in high current scenarios, but also does not require additional increase in the area of ​​the original chip. In the prior art, for high current scenarios, in order to enable the chips to be interconnected using large-diameter welding wires when interconnected, the electrode area of ​​the chip is required to be larger, so the chip area is usually increased during wafer processing, so that the number of chips that can be made with a wafer of the same area is reduced, resulting in a waste of chip area, and the MOS chip used in the present invention does not need to increase the chip area during wafer processing, thereby avoiding the waste of chip area and also improving the wafer utilization rate, with significant cost advantages. In addition, the present invention performs secondary packaging of the chip. When a large electrode area is required, there is no need to prepare a large-sized chip on the wafer. The electrode surface can be transferred out only through the RDL process. Since the packaging cost is much smaller than the wafer processing cost, the present invention reduces the production cost relatively.

[0100] In the above-mentioned embodiment, the rearranged electrode is a MOS gate, and there is also a source S on the chip surface at its original position. Figure 6 As can be seen from the electrode schematic diagram of the finally completed MOS chip, the finally completed source S electrode surface fans out to the back of the entire chip, and the original position electrode surface of the gate and the metal layer connected to the electrode hole are encapsulated inside the plastic package. In order to reduce the parasitic inductance that may be caused by the new source electrode surface and the internal gate metal surface (which is part of the second redistribution layer RDL2), in one embodiment, after the source S electrode surface is fanned out to the back of the entire chip, it is patterned so that the source S electrode surface on the back of the chip is staggered with the internal gate metal surface, for example, the electrode surface on the back of the chip opposite to the internal gate metal surface is etched away.

[0101] Figure 7 It is a schematic cross-sectional view of a chip structure obtained after secondary packaging of an original MOS chip according to another embodiment of the present invention. In this embodiment, when the relative area of ​​the electrode surface at the original position of the source S and the electrode surface at the preset position is large, during rewiring, the rewiring layer is obtained by using a ball planting method or a metal column electroplating method between the original position and the preset position of the source S. That is, corresponding to step S110, electroplating metal on the front side of the MOS, and using a ball planting method or a metal column electroplating method to obtain a second rewiring layer RDL2, thereby saving metal materials and reducing costs.

[0102] Although this embodiment uses the silicon wafer that has completed the preparation of each MOS semiconductor layer and the source and gate but has not been cut as the secondary packaging processing target, it can be known that a single MOS chip that has been packaged and cut can also be used as the packaging processing target.

[0103] Embodiment 2

[0104] Figure 8 : is a schematic diagram of the device packaging structure of the GaN Cascode according to the second embodiment of the present invention. The GaN Cascode packaging structure in the second embodiment includes a packaging frame 1, a HEMT chip U1 and a MOS chip U2. For example, the HEMT chip U1 in this embodiment is a conventional HEMT chip, and three electrodes are distributed on the front of the chip, including a long strip of HEMT drain D1, a long strip of HEMT source S1 and two square HEMT gates G1. The MOS chip U2 is a chip after secondary packaging of a conventional MOS chip, and the MOS drain D2, MOS source S2 and MOS gate G2 of the MOS chip U2 are located on the front of the chip.

[0105] The packaging process in this embodiment is the same as that in the first embodiment, and will not be described in detail here. In this embodiment, the MOS chip U2 is a conventional MOS chip that has undergone electrode position transfer and secondary packaging. After the electrode position transfer and packaging, the MOS drain D2 originally on the back of the chip is transformed to the front of the chip.

[0106] Fig. 9 FIG. 1 is a schematic diagram of a MOS chip structure in a process of transferring the electrode position of a MOS chip U2 according to another embodiment of the present invention. In this embodiment, a single conventional MOS chip is used as a processing object, and specifically includes the following steps:

[0107] Step S21, multiple MOS chips are mounted upside down on a temporary carrier, and a UBM (Under-Bump Metallurgy) metal layer with a thickness of 1 to 10 um is added to the drain electrode D surface on the back of the MOS chip. The adding method is, for example, electroplating, evaporation or sputtering, and the UBM metal is, for example, titanium copper or nickel gold or nickel palladium gold or titanium nickel silver for electroplating. The electrodes on the front of a single conventional MOS chip are the source and gate, and the back is the drain.

[0108] Step S22, plastic-encapsulating the back side of the MOS chip, and grinding the plastic-encapsulated body to expose the drain electrode D surface on the back side of the MOS chip.

[0109] Step S23, drilling a hole beside the MOS chip body to form a D electrode hole. In an optional solution, the D electrode hole can be made into a long strip, which is approximately the same size as the front source S.

[0110] Step S24, electroplating a metal layer on the back of the current MOS chip to obtain a first redistribution layer (RDL1). The D electrode hole is connected to the MOS drain D, so that the MOS drain D extends to the front of the plastic package through the D electrode hole.

[0111] Step S25, plastic-sealing the current structure.

[0112] Step S26, then remove the temporary carrier, flip the current structure, and grind the front side of the plastic package to expose the front drain D, source S and gate G electrode surfaces, and then obtain the drain D, source S and gate G of the finished MOS.

[0113] Step S27, Ag, Au or aluminum, etc., metals that can be used for wire bonding are plated or sputtered on the gate G, drain D and source S of the finished MOS, and Ag or Au, etc., metals that can be used for chip bonding are plated or sputtered on the back of the package.

[0114] Step S28, cutting and shaping, thereby obtaining a plurality of MOS chips after secondary packaging.

[0115] Embodiment 3

[0116] Fig.10 : is a schematic diagram of the device packaging structure of the GaN Cascode according to the third embodiment of the present invention. The GaN Cascode packaging structure in the third embodiment includes a packaging frame 1, a HEMT chip U1 and a MOS chip U2, wherein the MOS chip U2 is an original chip, the MOS drain D2 (not shown) is distributed on the back of the chip, and the MOS source S2 and the MOS gate G2 are distributed on the front of the chip. When the MOS chip U2 is mounted, the MOS drain D2 is fixed to the base island 11 through a conductive adhesive, and is thus electrically connected to it. The HEMT chip U1 is a chip that has been packaged twice, the HEMT gate G1 and the HEMT drain D1 are located on the front of the chip, and the HEMT source S1 is located on the back of the chip. When the HEMT chip U1 is mounted, the HEMT source S1 is fixed to the base island 11 through a conductive adhesive, and is thus electrically connected to it. Therefore, the HEMT source S1 and the MOS drain D2 are both located on the back of their respective chips, and are electrically connected to the base island 11, respectively, thereby achieving electrical connection between the two. In this embodiment, the HEMT gate G1 and the MOS source S2 are electrically connected to the device source region 14 by wire bonding. The HEMT drain D1 is electrically connected to the device drain region 13 by wire bonding. The MOS gate G2 is electrically connected to the device gate region 12 by wire bonding.

[0117] The packaging method of this embodiment is similar to that of the first embodiment and will not be described again here.

[0118] Fig.11The schematic diagram of the cross-sectional structure of the chip is obtained after secondary packaging of the HEMT chip according to an embodiment of the present invention. The secondary packaging process is similar to the secondary packaging of the MOS chip in the first and second embodiments, and will not be described in detail here.

[0119] Embodiment 4

[0120] Fig.12 : is a schematic diagram of the device packaging structure of the GaN Cascode according to the fourth embodiment of the present invention. The GaN Cascode packaging structure in the fourth embodiment includes a packaging frame 1, a HEMT chip U1 and a MOS chip U2, wherein the HEMT chip U1 and the MOS chip U2 are chips that have undergone secondary packaging; wherein the drain D1 and the source S1 of the HEMT chip U1 obtained after the secondary packaging are located on the front side of the chip, and the gate G1 is located on the back side of the chip, and when mounted on the base island 11 of the packaging frame, they are electrically connected to the conductive area on the base island 11. The source S2, the drain D2 and the gate G2 of the MOS chip U2 obtained after the secondary packaging are all located on the front side of the chip; when mounted on the base island 11 of the packaging frame, they are electrically insulated from the conductive area on the base island 11 by insulating glue. The drain D2 of the MOS chip U2 and the source S1 of the HEMT chip U1 are electrically connected by wire bonding. The source S2 of the MOS chip U2 is electrically connected to the conductive area on the base island 11 by wire bonding, thereby achieving electrical connection with the gate G1 of the HEMT chip U1.

[0121] The packaging method of this embodiment is similar to that of the first embodiment and will not be described again here.

[0122] Fig.13 The schematic diagram of the cross-sectional structure of the chip is obtained after secondary packaging of the HEMT chip according to another embodiment of the present invention. The secondary packaging process is similar to the secondary packaging of the MOS chip in the first embodiment, and will not be described in detail here.

[0123] Embodiment 5

[0124] Fig.14: is a schematic diagram of the device packaging structure of the GaN Cascode according to the fifth embodiment of the present invention. The GaN Cascode packaging structure in the fifth embodiment includes a packaging frame 1, a HEMT chip U1 and a MOS chip U2, wherein the HEMT chip U1 and the MOS chip U2 are chips that have undergone secondary packaging; wherein the drain D1 and the source S1 of the HEMT chip U1 obtained after the secondary packaging are located on the front of the chip, and the gate G1 is located on the back of the chip, and when mounted on the base island 11 of the packaging frame, the gate G1 of the HEMT chip U1 is electrically connected to the conductive area on the base island 11. The drain D2 and the gate G2 of the MOS chip U2 obtained after the secondary packaging are located on the front of the chip, and the source S2 is located on the back of the chip. When mounted on the base island 11 of the packaging frame, the source S2 of the MOS chip U2 is electrically connected to the conductive area on the base island 11. The drain D2 of the MOS chip U2 and the source S1 of the HEMT chip U1 are electrically connected by wire bonding.

[0125] The packaging method of this embodiment is similar to that of the first embodiment and will not be described again here.

[0126] Embodiment 6

[0127] Fig.15 : This is a schematic diagram of the device packaging structure of the GaN Cascode according to the sixth embodiment of the present invention. The GaN Cascode packaging structure in the sixth embodiment includes a packaging frame 1, a HEMT chip U1 and a MOS chip U2. The MOS chip U2 is a chip after secondary packaging after the original chip electrode is modified. The MOS source S2, the MOS gate G2 and the MOS drain D2 are distributed on the front of the chip. When the MOS chip U2 is mounted, the MOS chip U2 is mounted on the base island 11 by insulating glue. The MOS drain D2 is electrically connected to the conductive area on the base island 11 by wire bonding. The HEMT chip U1 is a chip that has been secondary packaged. The HEMT gate G1 and the HEMT drain D1 are located on the front of the chip, and the HEMT source S1 is located on the back of the chip. When the HEMT chip U1 is mounted, the HEMT source S1 is fixed to the base island 11 by conductive glue, thereby realizing the electrical connection between the HEMT source S1 and the MOS drain D2. In this embodiment, the HEMT gate G1 and the MOS source S2 are electrically connected to the device source region 14 by wire bonding. The HEMT drain D1 is electrically connected to the device drain region 13 by wire bonding. The MOS gate G2 is electrically connected to the device gate region 12 by wire bonding.

[0128] Embodiment 7

[0129] Fig.16Schematic diagram of GaN Cascode packaging structure according to Embodiment 7 of the present invention. The GaN Cascode packaging structure in Embodiment 7 includes a packaging frame 1, a HEMT chip U1, a MOS chip U2 and a substrate U3, wherein the MOS chip U2 is an original chip, the MOS drain D2 is located on the back of the chip, and the MOS source S2 and the MOS gate G2 are located on the front of the chip. The HEMT chip U1 is a HEMT chip that has been packaged twice; wherein the drain, source and gate of the original HEMT chip are distributed on the front of the chip, and the HEMT drain D1 and HEMT source S1 of the HEMT chip U1 obtained after the secondary packaging are located on the front of the chip, and the HEMT gate G1 is located on the back of the chip.

[0130] The packaging method includes: firstly, providing a secondary packaged HEMT chip U1. Then, the HEMT chip U1 and the substrate U3 are mounted in parallel on the base island 11 of the packaging frame 1, and the gate of the HEMT chip is in contact with and electrically connected to the conductive area on the base island; the front side of the substrate includes a conductive area, and the substrate is mounted insulated from the base island. Then, the MOS chip U2 is mounted on the conductive area on the front side of the substrate U3, and is electrically connected to the MOS drain D2 on the back side of the MOS chip U2. Then, interconnection is performed. In this embodiment, a wire bonding method is used to electrically connect the MOS source S2 and the conductive area on the base island 11, the HEMT source S2 and the conductive area on the front side of the substrate U3, the HEMT drain D2 and the device drain area 13 of the packaging frame; and the MOS gate G2 and the device gate area 12 of the packaging frame 1 are electrically connected.

[0131] pass Fig.16 It can be seen that although the substrate is still used in this embodiment, the number of bonding wires is reduced by modifying the HEMT electrodes, thereby reducing the parasitic inductance / resistance and improving the overall performance of the device.

[0132] Embodiment 8

[0133] Fig.17 Schematic diagram of GaN Cascode packaging structure according to Embodiment 8 of the present invention. The GaN Cascode packaging structure in Embodiment 8 includes a packaging frame 1, a HEMT chip U1 and a MOS chip U2, wherein the MOS chip U2 is an original chip, the MOS drain D2 is located on the back of the chip, and the MOS source S2 and the MOS gate G2 are located on the front of the chip. The HEMT chip U1 is a HEMT chip after electrode position transfer and secondary packaging, the drain, source and gate of the original HEMT chip are distributed on the front of the chip, the HEMT drain D1 and the HEMT source S1 of the HEMT chip U1 obtained after the electrode position transfer are located on the front of the chip, the HEMT gate G1 is transferred to the back of the chip through the redistribution layer and the electrode hole, and the original HEMT source S1 electrode located on the front of the chip is fanned out to increase the electrode area.

[0134] During the packaging process, when mounting the HEMT chip U1 and the MOS chip U2 on the base island, the HEMT chip U1 is first mounted on the conductive area of ​​the base island. Since the back of the HEMT chip U1 is the gate G1, a conductive adhesive is used during mounting to electrically connect the gate G1 to the conductive area of ​​the base island 11. Then the MOS chip U2 is mounted on the electrode surface of the HEMT source S1 through the conductive adhesive; then during the electrical interconnection process, the HEMT drain D1 and the device drain area 13 are electrically connected by wire bonding, and the source S2 of the MOS chip U2 is electrically connected to the conductive area of ​​the base island 11 by wire bonding. In this embodiment, the conductive area of ​​the base island 11 serves as the device source area, and the gate G1 of the MOS chip U2 is electrically connected to the device gate area 12 by wire bonding.

[0135] In addition, in some embodiments, in order to improve the performance of the GaN Cascode, boosting devices such as resistors, capacitors, and inductors may be added therein. These boosting devices may be integrated in the MOS or HEMT device body, or mounted on the base island or the MOS or HEMT chip, and then packaged together.

[0136] By changing the electrode layout of the original chip, the present invention can reduce the use of large substrates, reduce the number of wire bonds, reduce costs and process difficulties, and improve product performance and reliability. The present invention can also effectively reduce the actual use area of ​​the packaged chip, achieve a more reasonable chip layout, and thus be able to adapt to a smaller package form. When the present invention modifies the electrode surface of the original chip, an arbitrary wiring layout can be achieved through the RDL process, so that the shape of the electrode surface can be compatible with the traditional frame, and is more compatible with thick bonding wires, aluminum strips, copper sheets, etc., which is more conducive to high-power devices.

[0137] The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.

Claims

1. A method for packaging a gallium nitride cascade device, characterized in that: include: performing electrode position transfer on at least one of the original gallium nitride chip and the original low-voltage enhancement chip; Providing a packaging frame, the packaging frame comprising a plurality of frame units connected together by connecting ribs, each frame unit comprising a base island for mounting a chip, a device gate region, a device drain region and a device source region; Mount the GaN chip and low voltage enhancement chip on the base island; Conducting electrical interconnection, including: electrically connecting the drain of the gallium nitride chip and the device drain region of the frame unit; electrically connecting the gate of the gallium nitride chip and the device source region of the frame unit; electrically connecting the gate of the low-voltage enhancement chip and the device gate region of the frame unit; electrically connecting the source of the gallium nitride chip and the drain of the low-voltage enhancement chip; and Plastic encapsulation and cutting of connecting ribs to obtain a single GaN cascade device.

2. The packaging method of the gallium nitride cascade device according to claim 1, characterized in that: When transferring the electrode position of the target chip, the target electrode is rearranged from the original position to the preset position through the redistribution layer based on the RDL process, and the target electrode is one or more of the drain, source and gate, wherein the target chip is the original gallium nitride chip and / or the original low-voltage enhancement chip.

3. The packaging method of the gallium nitride cascade device according to claim 2, characterized in that: When the relative areas of the original position electrode surface and the preset position electrode surface of the target electrode are relatively large, the redistribution layer is obtained by planting balls or electroplating metal columns between the original position electrode surface and the preset position electrode surface of the target electrode.

4. The packaging method of the gallium nitride cascade device according to claim 2, characterized in that: When transferring the electrode position of the target chip, when the original position and the preset position of the target electrode are respectively located on the front and back sides of the chip, an electrode hole is set in the secondary plastic package of the target chip, and the redistribution layers respectively located on the front and back sides of the chip are connected to the electrode hole.

5. The packaging method of the gallium nitride cascade device according to claim 4, characterized in that: When transferring the electrode position of the target chip, when the chip surface where the target electrode is originally located also includes a second electrode, after rearranging the target electrode to the opposite surface through the redistribution layer and the electrode hole, it further includes: thickening the electrode surface of the second electrode; and fanning out the electrode surface of the second electrode to a preset position on the current chip surface.

6. The packaging method of the gallium nitride cascade device according to claim 5, characterized in that: The step of fanning out the electrode surface of the second electrode to a preset position on the current chip surface includes: fanning out the electrode surface of the second electrode to the entire surface of the current chip; and patterning the electrode surface of the entire surface to be staggered with the internal redistribution layer.

7. The packaging method of the gallium nitride cascade device according to claim 2, characterized in that: The target chip is a wafer-level chip or a finished chip; when the target chip is a wafer-level chip, the back side of the wafer is thinned before the RDL process is performed.

8. The packaging method of a gallium nitride cascade device according to any one of claims 1 to 7, characterized in that: When transferring the electrode position of at least one of the original gallium nitride chip and the original low-voltage enhancement chip, the source electrode of the gallium nitride chip and the drain electrode of the low-voltage enhancement chip are located on the same surface of the respective chips; Correspondingly, the gallium nitride chip and the low-voltage enhancement chip are mounted in parallel on the base island; when electrically interconnected, when the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the front side of their respective chips, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are electrically connected through metal connectors; when the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the back side of their respective chips, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are respectively in contact with and electrically connected to the conductive area on the base island.

9. The method for packaging a gallium nitride cascade device according to any one of claims 1 to 7, characterized in that: The gate, drain and source of the original GaN chip are located on the front side of the chip. When the electrode position of the original GaN chip is transferred, the GaN gate is rearranged from the original position on the front side of the chip to the back side of the chip, and the GaN source electrode surface on the front side of the chip is enlarged; Correspondingly, when mounting the gallium nitride chip and the low-voltage enhancement chip on the base island, the gallium nitride chip is mounted on the conductive area of ​​the base island, and the original low-voltage enhancement chip is mounted on the gallium nitride source electrode surface; wherein the gate on the back of the gallium nitride chip is electrically connected to the conductive area of ​​the base island; and the drain on the back of the original low-voltage enhancement chip is electrically connected to the gallium nitride source electrode surface.

10. A packaging structure of a gallium nitride cascade device, characterized in that: include: A packaging frame, the packaging frame comprising a base island for mounting a chip, a device gate region, a device drain region and a device source region; Gallium nitride chip; Low voltage enhancement chip; as well as Plastic sealing body; The gallium nitride chip and the low-voltage enhancement chip are mounted on the base island of the packaging frame; the gallium nitride chip is an original gallium nitride chip or a chip obtained by transferring the electrode position of the original gallium nitride chip, and the low-voltage enhancement chip is an original low-voltage enhancement chip or a chip obtained by transferring the electrode position of the original low-voltage enhancement chip; The drain of the gallium nitride chip is electrically connected to the device drain region of the packaging frame; the gate of the gallium nitride chip and the source of the low-voltage enhancement chip are electrically connected to the device source region of the packaging frame respectively; the gate of the low-voltage enhancement chip is electrically connected to the device gate region of the packaging frame; the source of the gallium nitride chip is electrically connected to the drain of the low-voltage enhancement chip.

11. The packaging structure of the gallium nitride cascade device according to claim 10, characterized in that: The source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the same surface of their respective chips; the gallium nitride chip and the low-voltage enhancement chip are mounted side by side on the base island of the packaging frame; when the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the front of their respective chips, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are electrically connected through a metal connector; when the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are located on the back of their respective chips, the source of the gallium nitride chip and the drain of the low-voltage enhancement chip are respectively in contact with and electrically connected to the conductive area on the base island.

12. The packaging structure of the gallium nitride cascade device according to claim 11, characterized in that: The gallium nitride chip is an original gallium nitride chip, and its drain, source and gate are distributed on the front side of the chip. The low-voltage enhancement chip is a chip obtained by transferring the electrode position of the original low-voltage enhancement chip. The drain and gate of the low-voltage enhancement chip are distributed on the front side of the chip, and the source is distributed on the back side of the chip. The source of the low-voltage enhancement chip is in contact with and electrically connected to the conductive area on the base island; the gate of the gallium nitride chip is electrically connected to the conductive area on the base island through a metal connector.

13. The packaging structure of the gallium nitride cascade device according to claim 11, characterized in that: The gallium nitride chip is an original gallium nitride chip, and its drain, source and gate are distributed on the front of the chip. The low-voltage enhancement chip is a chip obtained by transferring the electrode position of the original low-voltage enhancement chip. The source, drain and gate of the low-voltage enhancement chip are distributed on the front of the chip. The gate of the gallium nitride chip is electrically connected to the conductive area on the base island through a metal connector; the source of the low-voltage enhancement chip is electrically connected to the conductive area on the base island through a metal connector.

14. The packaging structure of the gallium nitride cascade device according to claim 11, characterized in that: The low-voltage enhancement chip is an original low-voltage enhancement chip, whose drain is located on the back of the chip, and whose source and gate are located on the front of the chip; the gallium nitride chip is a chip obtained by transferring the electrode position of the original gallium nitride chip, whose gate and drain are located on the front of the chip, and whose source is located on the back of the chip; The drain electrode on the back of the low-voltage enhancement chip and the source electrode of the gallium nitride chip are respectively in contact and electrically connected with the conductive area on the base island; the source electrode on the back of the low-voltage enhancement chip and the gate electrode of the gallium nitride chip are respectively electrically connected with the device source area through metal connectors.

15. The packaging structure of the gallium nitride cascade device according to claim 11, characterized in that: The gallium nitride chip is a chip obtained by transferring the electrode positions of the original gallium nitride chip. The drain, source and gate of the original gallium nitride chip are distributed on the front side of the chip. The drain and source of the gallium nitride chip obtained after the electrode position transfer are located on the front side of the chip, and the gate is located on the back side of the chip. The low-voltage enhancement chip is a chip obtained by transferring the electrode position of the original low-voltage enhancement chip. The drain of the original low-voltage enhancement chip is distributed on the back of the chip, and the source and gate are distributed on the front of the chip. The drain and gate of the low-voltage enhancement chip obtained after the electrode position transfer are located on the front of the chip; the gate of the gallium nitride chip is in contact and electrically connected with the conductive area on the base island; the drain of the low-voltage enhancement chip and the source of the gallium nitride chip are electrically connected through a metal connector.

16. The packaging structure of the gallium nitride cascade device according to claim 15, characterized in that: The source, drain and gate of the low-voltage enhancement chip obtained after the electrode position transfer are all located on the front side of the chip, and the source of the low-voltage enhancement chip is electrically connected to the conductive area on the base island through a metal connector.

17. The packaging structure of the gallium nitride cascade device according to claim 15, characterized in that: The source electrode of the low-voltage enhancement chip obtained after the electrode position transfer is located on the back of the chip, and the source electrode of the low-voltage enhancement chip is in contact with and electrically connected to the conductive area on the base island.

18. The packaging structure of the gallium nitride cascade device according to claim 11, characterized in that: The gallium nitride chip is a chip obtained by transferring the electrode positions of the original gallium nitride chip. The drain, source and gate of the original gallium nitride chip are distributed on the front side of the chip. The drain and gate of the gallium nitride chip obtained after the electrode position transfer are located on the front side of the chip, and the source is located on the back side of the chip. The low-voltage enhancement chip is a chip obtained by transferring the electrode position of the original low-voltage enhancement chip. The drain, source and gate of the original low-voltage enhancement chip are distributed on the front side of the chip, and the drain, source and gate of the low-voltage enhancement chip obtained after the electrode position transfer are located on the front side of the chip; the gate of the gallium nitride chip is electrically connected to the source region of the device through a metal connector, and the drain of the low-voltage enhancement chip is electrically connected to the conductive region on the base island through a metal connector; the source of the low-voltage enhancement chip is electrically connected to the source region of the device through a metal connector.

19. The packaging structure of the gallium nitride cascade device according to any one of claims 10 to 18, characterized in that: The metal connecting piece is a bonding wire, a metal strip or a metal sheet.

20. The packaging structure of the gallium nitride cascade device according to claim 10, characterized in that: The target chip after the electrode position transfer includes an original chip, a rewiring layer and a secondary plastic package, wherein the original chip and the rewiring layer are located in the secondary plastic package; the rewiring layer rearranges the target electrode from the original position to the preset position; The target electrode is one or more of a drain, a source and a gate, and the target chip is an original gallium nitride chip and / or an original low-voltage enhancement chip.

21. The packaging structure of the cascade device according to claim 20, characterized in that: Electrode holes are provided in the secondary plastic package, and the redistribution layer includes a first redistribution layer and a second redistribution layer. The first redistribution layer is connected to the electrode surface and the electrode hole of the preset position of the target electrode, and the second redistribution layer is connected to the electrode surface and the electrode hole of the original position of the target electrode. The original position and the preset position of the target electrode are respectively arranged on the front and back sides of the chip.

22. The packaging structure of the cascade device according to claim 20, characterized in that: The original position electrode surface and the preset position electrode surface of the target electrode are located on the same surface of the chip, and the redistribution layer is obtained by ball planting or electroplating metal columns between the original position electrode surface and the preset position electrode surface of the target electrode.

23. The packaging structure of the cascade device according to claim 20, characterized in that: The redistribution layer in the secondary plastic package is staggered with the electrode surface on the surface of the secondary plastic package, and the electrode surface on the surface of the secondary plastic package is a drain, a source or a gate.

24. The packaging structure of the cascade device according to claim 10, characterized in that: The gallium nitride chip is a chip obtained by transferring the electrode position of the original gallium nitride chip, the gallium nitride gate is located on the back of the chip, and the gallium nitride drain and gallium nitride source are located on the front of the chip; the low-voltage enhancement chip is the original chip, the source and gate of the low-voltage enhancement chip are located on the front of the chip, and the drain is located on the back of the chip; The gallium nitride chip is mounted on the conductive area of ​​the base island, and the gallium nitride gate on the back of the gallium nitride chip is electrically connected to the conductive area of ​​the base island; the low-voltage enhancement chip is mounted on the gallium nitride source electrode surface; the drain on the back of the low-voltage enhancement chip is electrically connected to the gallium nitride source electrode surface.

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