TSV through hole morphology process for 3D packaging

Abstract

The invention discloses a TSV through hole morphology process for 3D packaging, and relates to the technical field of integrated circuit packaging. According to the technical scheme, on one hand, two-sided repeated secondary through hole etching trapezoidal hole patterns are connected to form an X-type through hole structure, discontinuity of deposition of an insulating layer and sputtering of a barrier layer and a seed layer is reduced, and the step coverage rate is increased; the integrity and continuity of the electroplating process are improved; meanwhile, through the optimized morphology of the through hole, the integrity of electroplating hole filling is improved, and generation of holes is reduced; on the basis, the aperture of the top and the aperture of the bottom are enlarged, the line width of a redistribution line (RDL) is increased, RC delay and signal crosstalk are reduced, the return loss and insertion loss performance of high-frequency signal transmission is improved, finally, compared with laser drilling, the wet etching process is simple, the cost is low, and the production efficiency is improved.

Description

Technical Field

[0001] The present invention specifically relates to the field of integrated circuit packaging, and in particular to a TSV through-hole morphology process for 3D packaging. Background Art

[0002] In modern electronic devices, with the increasing demand for high performance, miniaturization and low power consumption, three-dimensional integrated circuit (3D IC) technology has emerged. 3D IC significantly improves integration density and performance by vertically stacking multiple layers of chips and using through silicon vias (TSVs) to achieve electrical connections between layers. However, the common TSV process currently has many challenges, such as the use of different plasmas such as C4F8 and SF6 in the deep silicon etching process of the Bosch process, which alternately uses etching to form a scallop morphology with rough sidewalls of the through hole, resulting in uneven CVD insulation layer, PVD barrier layer and seed layer during sputtering deposition of thin films, low step coverage, and affecting the integrity of subsequent electroplating hole filling, resulting in poor surface uniformity, easy generation of voids (void / seam) during the hole filling process, reducing the electrical performance of signal transmission and affecting product reliability. The large aperture of laser drilling technology is not conducive to the manufacture of high-density and high-precision packaging structures, and has low production efficiency. These problems seriously affect the reliability and electrical performance of 3DIC. Therefore, we propose a TSV through-hole morphology process for 3D packaging to solve the above problems. Summary of the invention

[0003] The purpose of the present invention is to provide a TSV through-hole morphology process for 3D packaging. By setting a screen with a specific aperture under the crushing tooth plate, the crushed raw material is screened by the screen, and the particles that do not meet the particle size requirements continue to remain in the crushing chamber and are repeatedly crushed until they reach the specified particle size and are discharged through the screen. In this way, the particle size of the crushed raw material is accurately controlled to ensure that the output raw material particle size is uniform and meets the strict requirements of all links in chemical production, thereby improving the overall quality and performance of the product; at the same time, the dust removal mechanism can effectively reduce the emission of dust in the working environment, purify the air in the workplace, protect the health of operators, and at the same time reduce the adverse effects of dust on equipment, ensuring stable operation of equipment; so as to solve the technical problems raised in the above background technology.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] A TSV through-hole morphology process for 3D packaging includes the following steps:

[0006] S1: Prepare materials and complete silicon wafers;

[0007] S2: wet etching, using HF solution with a specific patterned mask to selectively chemically etch the silicon substrate until a predetermined depth is reached;

[0008] S3: Deposit an insulating layer, using chemical vapor deposition (CVD) technology to cover the entire wafer with a thin and uniform layer of dielectric material;

[0009] S4: sputtering a barrier layer and a seed layer, depositing a titanium Ti barrier layer and a copper Cu seed layer on the insulating layer in sequence through a physical vapor deposition (PVD) process;

[0010] S5: electroplating copper filling, after PVD deposition is completed, electroplating Cu filling is performed;

[0011] S6: Repeat the operation on the back side. After flipping the sample, repeat steps 1 to 4 at the same position on the other side to ensure that the holes formed on both sides are accurately aligned and connected to form an X-shaped through-hole structure.

[0012] S7: Planarization: Chemical mechanical polishing (CMP) is applied to remove excess metal residues, leaving a smooth and flat pad surface for subsequent RDL wiring or solder bump implantation.

[0013] As a further technical solution of the present invention, in step S2, due to the isotropic property of wet etching, this process will form a trapezoidal hole that is wide outside and narrow inside on the silicon substrate.

[0014] As a further technical solution of the present invention, the function of the Ti barrier layer in step S4 is to prevent Cu atoms from diffusing into the insulating layer, while the Cu seed layer provides a basis for the subsequent electroplating process.

[0015] As a further technical solution of the present invention, during the electroplating process in step S5, the Cu seed layer serves as a cathode, and Cu ions are deposited into the through hole under the action of the electric field, gradually filling the entire through hole.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1. The novel through-hole morphology of the present invention reduces the discontinuity of the deposited insulating layer, the sputtered barrier layer and the seed layer, improves the integrity of the electroplated hole filling, and reduces the generation of voids;

[0018] 2. The present invention enlarges the apertures at the top and bottom, increases the width of the redistribution wiring (RDL) line, reduces RC delay and signal crosstalk, and improves the return loss and insertion loss performance of high-frequency signal transmission;

[0019] 3. The present invention increases the aperture of the through hole, so that the contact area between the surface pad and the solder bump is larger, thereby enhancing the bonding force;

[0020] 4. Compared with laser drilling, the wet etching process of the present invention is simple and has low cost, thereby improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of a complete silicon wafer of the present invention.

[0022] Figure 2 The present invention Figure 1 Schematic diagram after wet etching.

[0023] Figure 3 The present invention Figure 2 Schematic diagram after chemical vapor deposition.

[0024] Figure 4 The present invention Figure 3 Schematic diagram after physical vapor deposition.

[0025] Figure 5 The present invention Figure 4 Schematic diagram after electroplated copper filling.

[0026] Figure 6 The present invention Figure 5 Schematic diagram of the operation being repeated after reversal.

[0027] Figure 7 The present invention Figure 6 Schematic diagram after chemical mechanical polishing. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] See also Figure 1-7 In an embodiment of the present invention, the following steps are included:

[0030] S1: Prepare materials and complete silicon wafers;

[0031] S2: wet etching, using HF solution with a specific patterned mask to selectively chemically etch the silicon substrate until a predetermined depth is reached;

[0032] S3: Deposit an insulating layer, using chemical vapor deposition (CVD) technology to cover the entire wafer with a thin and uniform layer of dielectric material;

[0033] S4: sputtering a barrier layer and a seed layer, depositing a titanium Ti barrier layer and a copper Cu seed layer on the insulating layer in sequence through a physical vapor deposition (PVD) process;

[0034] S5: electroplating copper filling, after PVD deposition is completed, electroplating Cu filling is performed;

[0035] S6: Repeat the operation on the back side. After flipping the sample, repeat steps 1 to 4 at the same position on the other side to ensure that the holes formed on both sides are accurately aligned and connected to form an X-shaped through-hole structure.

[0036] S7: Planarization: Chemical mechanical polishing (CMP) is applied to remove excess metal residues, leaving a smooth and flat pad surface for subsequent RDL wiring or solder bump implantation.

[0037] As a further technical solution of the present invention, in step S2, due to the isotropic property of wet etching, this process will form a trapezoidal hole that is wide outside and narrow inside on the silicon substrate.

[0038] As a further technical solution of the present invention, the function of the Ti barrier layer in step S4 is to prevent Cu atoms from diffusing into the insulating layer, while the Cu seed layer provides a basis for the subsequent electroplating process.

[0039] As a further technical solution of the present invention, during the electroplating process in step S5, the Cu seed layer serves as a cathode, and Cu ions are deposited into the through hole under the action of the electric field, gradually filling the entire through hole.

[0040] The above-mentioned TSV side barrier layer is mainly formed by CVD chemical vapor deposition and PVD physical vapor deposition. It will cause insulation failure due to thickness or delamination, forming another current leakage path, which will have a great impact on the product reliability Rc delay. Multi TSVs mainly consists of multiple separate TSVs that conduct current at the same time, reducing the reliability problem caused by a single TSV failure, and adding grounding I / O in I / O design to reduce the parasitic current generation of two adjacent I / Os, while also reducing Rc delay and improving reliability;

[0041] Due to the increased hole density of Multi TSV, TSV etch must use Bosch process, 1000sccm MFC, 13.56MHz source power. CVD Plasma Enhance TEOS, PVD uses electromagnets to absorb secondary electrons to increase the target sputtering rate, increase the distance from the target to the wafer to increase the mean free path, and increase the thickness of the bottom side of the TSV hole.

[0042] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0043] In addition, it should be understood that although this specification is described according to implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Technicians with this skill should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A TSV through-hole morphology process for 3D packaging, characterized in that: The following steps are involved: S1: Prepare materials and complete silicon wafers; S2: wet etching, using HF solution with a specific patterned mask to selectively chemically etch the silicon substrate until a predetermined depth is reached; S3: Deposit an insulating layer, using chemical vapor deposition (CVD) technology to cover the entire wafer with a thin and uniform layer of dielectric material; S4: sputtering a barrier layer and a seed layer, depositing a titanium Ti barrier layer and a copper Cu seed layer on the insulating layer in sequence through a physical vapor deposition (PVD) process; S5: electroplating copper filling, after PVD deposition is completed, electroplating Cu filling is performed; S6: Repeat the operation on the back side. After flipping the sample, repeat steps 1 to 4 at the same position on the other side to ensure that the holes formed on both sides are accurately aligned and connected to form an X-shaped through-hole structure. S7: Planarization: Chemical mechanical polishing (CMP) is applied to remove excess metal residues, leaving a smooth and flat pad surface for subsequent RDL wiring or solder bump implantation.

2. The TSV through-hole morphology process for 3D packaging according to claim 1, characterized in that: In step S2, due to the isotropic property of wet etching, this process will form a trapezoidal hole that is wide outside and narrow inside on the silicon substrate.

3. The TSV through-hole morphology process for 3D packaging according to claim 1, characterized in that: The function of the Ti barrier layer in step S4 is to prevent Cu atoms from diffusing into the insulating layer, while the Cu seed layer provides a basis for the subsequent electroplating process.

4. The TSV through-hole morphology process for 3D packaging according to claim 3, characterized in that: During the electroplating process in step S5, the Cu seed layer serves as a cathode, and Cu ions are deposited into the through hole under the action of the electric field, gradually filling the entire through hole.

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