Drive circuit, plasma power supply circuit and plasma system

Abstract

This application provides a driving circuit, a plasma power supply circuit, and a plasma system, comprising: a driving branch; the driving branch includes a driving module, a filtering module, and a power conversion module; a first terminal of the driving module receives a first control signal, a second terminal of the driving module is electrically connected to the first terminal of the power conversion module, a third terminal of the driving module is electrically connected to the second terminal of the power conversion module, a fourth terminal of the driving module receives a first power signal, and an output terminal of the driving module is electrically connected to the filtering module; the driving module is used to sense and generate a second control signal based on the first control signal and the first power signal, and output a driving signal based on the second control signal; the filtering module is used to filter the driving signal; the third terminal of the power conversion module is used to receive the second power signal, and the power conversion module is used to convert the second power signal into a third power signal and output it. This is used to improve the common-mode transient immunity of the driving circuit.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, specifically to a drive circuit, a plasma power supply circuit, and a plasma system. Background Technology

[0002] With the rapid development of modern power electronics technology, inverters, as key devices for energy conversion and control, play a vital role in power systems. Especially in the application field of plasma generators, the performance and efficiency of inverters directly affect the stability and efficiency of the entire system.

[0003] Please see Figure 1 The schematic diagram of the three-level inverter topology shown indicates that the first bus capacitor Cbus1 and the second bus capacitor Cbus2 are connected in series between the positive DC bus BUS+ and the negative DC bus BUS-. The common node of the first bus capacitor Cbus1 and the second bus capacitor Cbus2 forms the midpoint b of the DC bus. The first switching unit 110 is connected between the first terminal a and the positive DC bus BUS+. The second switching unit 120 is connected between the first terminal a and the negative DC bus BUS-. The third switching unit 130 is connected between the first terminal a and the midpoint b of the DC bus. The first terminal a is used to form the output terminal of the three-level inverter to output AC power Vac. A DC voltage source can be connected between the positive DC bus BUS+ and the negative DC bus BUS-.

[0004] Typically, an inverter system also includes a switching control circuit and a switching drive circuit. The switching control circuit outputs a PWM control signal based on a sampled and / or given signal. The PWM control signal, via the switching drive circuit, outputs a switching drive signal that controls the on or off of the switching transistors within the three-level inverter, enabling the three-level inverter to achieve the desired inverter function. In some technologies, the drive circuit uses a non-isolated topology. Such drive circuits have low common-mode transient immunity, are prone to false turn-on and false turn-off errors, and reduce circuit reliability. Summary of the Invention

[0005] In view of this, this application provides a driving circuit, a plasma power supply circuit, and a plasma system to help solve the problem of low common-mode transient immunity of driving circuits in the prior art.

[0006] In a first aspect, embodiments of this application provide a driving circuit, including:

[0007] At least two drive branches; for each drive branch, the drive branch includes a drive module, a filter module, and a power conversion module;

[0008] The first terminal of the drive module is used to receive a first control signal, the second terminal of the drive module is electrically connected to the first terminal of the power conversion module, the third terminal of the drive module is electrically connected to the second terminal of the power conversion module, the fourth terminal of the drive module is used to receive a first power signal, and the output terminal of the drive module is electrically connected to the filter module; the drive module is used to generate a second control signal based on the first power signal under the control of the first control signal, and output the signal obtained by the second terminal of the drive module as a drive signal under the control of the second control signal.

[0009] The filtering module is used to filter the driving signal and output the filtered driving signal.

[0010] The third terminal of the power conversion module is used to receive the second power signal. The power conversion module is used to convert the second power signal into a third power signal and output it through the first terminal of the power conversion module. The power conversion module provides the reference ground signal of the third power signal to the drive module through the second terminal of the power conversion module.

[0011] In one possible implementation of the first aspect, the driving module includes a first switch submodule and a driving submodule;

[0012] The first terminal of the first switch submodule is electrically connected to the first terminal of the drive submodule, the second terminal of the first switch submodule is electrically connected to the first ground terminal, and the control terminal of the first switch submodule is used to receive a first control signal; the first switch submodule is used to turn on and off under the control of the first control signal.

[0013] The second terminal of the driving submodule is electrically connected to the first terminal of the power conversion module, and the third terminal of the driving submodule is electrically connected to the second terminal of the power conversion module; the fourth terminal of the driving submodule is used to receive a first power signal, and the driving submodule is used to generate second control information based on the first power signal when the first switch submodule is in the on state, and output a driving signal under the control of the second control signal.

[0014] In one possible implementation of the first aspect, the power conversion module includes a power conversion submodule and a first isolation submodule;

[0015] The first terminal of the power conversion submodule is electrically connected to the second terminal of the drive submodule, and the second terminal of the power conversion submodule is electrically connected to the third terminal of the drive submodule. The third terminal of the power conversion submodule is used to receive a second power signal, and the fourth terminal of the power conversion submodule is used to receive a reference ground signal of the second power signal. The power conversion submodule is used to convert the second power signal into a third power signal, and output the third power signal through the first terminal of the power conversion submodule, and output the reference ground signal of the third power signal through the second terminal of the power conversion submodule.

[0016] One end of the first isolation submodule is electrically connected to the fourth end of the power conversion submodule, and the other end of the first isolation submodule is electrically connected to the second end of the power conversion submodule; the first isolation submodule is used to isolate the reference ground signal of the second power signal from the reference ground signal of the third power signal.

[0017] In one possible implementation of the first aspect, the first isolation submodule includes a first capacitor.

[0018] In one possible implementation of the first aspect, the power conversion module further includes a second capacitor, a third capacitor, a fourth capacitor, and a first inductor; a first terminal of the first inductor is electrically connected to a first terminal of the second capacitor, a second terminal of the first inductor and a first terminal of the third capacitor are electrically connected to a third terminal of the power conversion submodule, and a second terminal of the second capacitor and a second terminal of the third capacitor are electrically connected to a fourth terminal of the power conversion submodule; one terminal of the fourth capacitor is electrically connected to a first terminal of the power conversion submodule, and the other terminal of the fourth capacitor is electrically connected to a second terminal of the power conversion submodule.

[0019] In one possible implementation of the first aspect, the driving module further includes: a first resistor, a fifth capacitor, a sixth capacitor, and a second resistor;

[0020] One end of the first resistor is electrically connected to the control terminal of the first switch submodule, and the other end of the first resistor is electrically connected to the second terminal of the first switch submodule.

[0021] The fifth capacitor and the sixth capacitor are connected in parallel. One end of the fifth capacitor and the sixth capacitor is electrically connected to the second terminal of the drive submodule, and the other end of the fifth capacitor and the sixth capacitor is electrically connected to the second terminal of the power conversion submodule.

[0022] One end of the second resistor is electrically connected to the output terminal of the driving submodule, and the other end of the second resistor is electrically connected to the filtering module.

[0023] In one possible implementation of the first aspect, the filtering module includes a seventh capacitor and a third resistor; the seventh capacitor and the third resistor are connected in parallel, and one end of the seventh capacitor and the third resistor is electrically connected to the output terminal of the driving submodule, and the other end of the seventh capacitor and the third resistor is electrically connected to the second terminal of the power conversion submodule.

[0024] Secondly, embodiments of this application provide a plasma power supply circuit, including the driving circuit described in any of the first aspects, a three-level high-frequency inverter circuit, and a high-frequency voltage conversion circuit;

[0025] The driving circuit is electrically connected to the first terminal of the three-level high-frequency inverter circuit, and the second terminal of the three-level high-frequency inverter circuit is electrically connected to the input terminal of the high-frequency voltage conversion circuit; the third terminal of the three-level high-frequency inverter circuit is used to receive DC power; the output terminal of the high-frequency voltage conversion circuit is used to connect to the plasma load.

[0026] The driving circuit is used to send a driving signal to the three-level high-frequency inverter circuit;

[0027] The three-level high-frequency inverter circuit is used to convert the DC power supply into three levels of power signals under the action of the drive signal and output them.

[0028] The high-frequency voltage conversion circuit is used to boost the power signal output by the three-level high-frequency inverter circuit and output the boosted power signal to the plasma load.

[0029] In one possible implementation of the second aspect, the switching devices in the three-level high-frequency inverter circuit are SiC switching devices.

[0030] In one possible implementation of the second aspect, the high-frequency voltage conversion circuit includes a high-frequency transformer; the high-frequency transformer satisfies preset conditions;

[0031] The preset conditions include: the wire diameter of the high-frequency transformer is 0.015cm. 2 (square centimeters) -0.02cm 2 Within the specified range, the window utilization rate of the high-frequency transformer is within the range of 80%-85%, and the area of ​​the high-frequency transformer is within 19cm². 2 -21cm 2 Within the specified ranges, the operating frequency of the high-frequency transformer is 25 kHz, the magnetic flux density of the high-frequency transformer is in the range of 0.35-0.45, the voltage regulation rate is in the range of 1-5, and the cross-sectional area of ​​the magnetic core in the high-frequency transformer is 3.4 cm². 2 -3.6cm 2The high-frequency transformer has at least one of the following characteristics: the number of primary turns is in the range of 14-18; wherein the area of ​​the high-frequency transformer includes the product of the maximum cross-sectional area of ​​the transformer core and the area of ​​the window.

[0032] Thirdly, embodiments of this application provide a plasma system, including: the plasma power supply circuit and plasma load described in any of the second aspects above.

[0033] In one possible implementation of the third aspect, the plasma load includes at least one of a plasma rotary spray gun and a loaded plasma direct injection spray gun.

[0034] The driving circuit using the solution provided in this application includes at least two driving branches. Each driving branch includes a driving module, a filtering module, and a power conversion module. The first terminal of the driving module receives a first control signal. The second terminal of the driving module is electrically connected to the first terminal of the power conversion module. The third terminal of the driving module is electrically connected to the second terminal of the power conversion module. The fourth terminal of the driving module receives a first power signal. The output terminal of the driving module is electrically connected to the filtering module. The driving module, under the control of the first control signal, senses and generates a second control signal based on the first power signal. Under the control of the second control signal, it outputs the signal acquired by the second terminal of the driving module as a driving signal. The filtering module filters the driving signal and outputs the filtered driving signal. The third terminal of the power conversion module receives the second power signal. The power conversion module converts the second power signal into a third power signal and outputs it through the first terminal of the power conversion module. The power conversion module also provides a first reference ground signal to the driving module through its second terminal. The first reference ground signal is the reference ground signal of the third power signal. In this embodiment, the driving module in each driving branch of the driving circuit can generate a second control signal based on the first power signal under the control of the first control signal, and output a driving signal based on the second control signal. That is, the driving circuit does not directly output a driving signal based on the received first control signal, but rather generates a second control signal under the control of the first control signal and outputs a driving signal based on the second control signal. This achieves isolation between the driving signal output by the driving circuit and the first control signal, reducing the influence of the first control signal on the driving signal, thereby improving the common-mode transient immunity of the driving circuit. Furthermore, in this embodiment, the power conversion module can achieve isolation between the driving signals and the reference ground signal of the driving signals between at least two driving sub-modules, reducing interference between at least two driving sub-modules, thereby further improving the common-mode transient immunity of the driving circuit. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a three-level inverter topology provided in the prior art;

[0037] Figure 2 This is a schematic diagram of a driving circuit provided in an embodiment of this application;

[0038] Figure 3 for Figure 2 A schematic diagram of the structure of one type of drive circuit in the drive circuit shown;

[0039] Figure 4 This is a schematic diagram of another driving branch provided in an embodiment of this application;

[0040] Figure 5 Provided for the embodiments of this application Figure 4 A schematic diagram of the power conversion module in the drive branch shown;

[0041] Figure 6 This is a schematic diagram of another driving branch provided in an embodiment of this application;

[0042] Figure 7 This is a schematic diagram of another driving branch provided in an embodiment of this application;

[0043] Figure 8 This is a schematic diagram of another driving branch provided in an embodiment of this application;

[0044] Figure 9a This is a schematic diagram of another driving branch provided in an embodiment of this application;

[0045] Figure 9b This is a schematic diagram of the structure of a driver submodule provided in an embodiment of this application;

[0046] Figure 10 This is a schematic diagram of a plasma power supply circuit provided in an embodiment of this application;

[0047] Figure 11a for Figure 10 A schematic diagram of a three-level high-frequency inverter circuit in the plasma power supply circuit described above;

[0048] Figure 11b for Figure 10Another schematic diagram of the three-level high-frequency inverter circuit in the plasma power supply circuit described above.

[0049] Figure 12 Schematic diagrams of simulation models of some high-frequency transformers provided for embodiments of this application;

[0050] Figure 13 A schematic diagram illustrating the simulation results of the bus current of a high-frequency transformer provided in this application embodiment;

[0051] Figure 14 A schematic diagram illustrating the simulation results of the bus voltage of a high-frequency transformer provided in an embodiment of this application;

[0052] Figure 15 This is a schematic diagram of another plasma power supply circuit provided in an embodiment of this application;

[0053] Figure 16 A schematic diagram illustrating the generation of drive signals for a three-level high-frequency inverter circuit provided in an embodiment of this application;

[0054] Figure 17 A schematic diagram of the drive signal for a three-level high-frequency inverter circuit provided in an embodiment of this application;

[0055] Figure 18 A schematic diagram of the drive signal for another three-level high-frequency inverter circuit provided in an embodiment of this application;

[0056] Figure 19 The bus voltage U of a high-frequency transformer provided in this application embodiment P-P Simulation diagram;

[0057] Figure 20 A voltage simulation diagram of the midpoint b of a three-level high-frequency inverter circuit provided in an embodiment of this application;

[0058] Figure 21 The bus current I of a high-frequency transformer provided in this application embodiment P-P Simulation diagram;

[0059] Figure 22 A simulation diagram of the current at point b, the midpoint of a three-level high-frequency inverter circuit, provided for an embodiment of this application;

[0060] Figure 23 The peak-to-peak value of the secondary current I of a high-frequency transformer provided in this application embodiment PP-S Simulation diagram;

[0061] Figure 24 This is a schematic diagram of the structure of a plasma system provided in an embodiment of this application. Detailed Implementation

[0062] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0063] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0064] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0065] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0066] refer to Figure 2 This is a schematic diagram of a driving circuit provided in an embodiment of this application. Figure 2 As shown, the drive circuit includes at least two drive branches 20. For each drive branch 20, the drive branch 20 includes a drive module 21, a filter module 22, and a power conversion module 23.

[0067] The first terminal of the drive module 21 is used to receive a first control signal. The second terminal of the drive module 21 is electrically connected to the first terminal of the power conversion module 23. The third terminal of the drive module 21 is electrically connected to the second terminal of the power conversion module 23. The fourth terminal of the drive module 21 is used to receive a first power signal. The output terminal of the drive module 21 is electrically connected to the filter module 22. The drive module 21 is used to generate a second control signal based on the first power signal under the control of the first control signal, and output the signal acquired by the second terminal of the drive module 21 as a drive signal under the control of the second control signal.

[0068] The filtering module 22 is used to filter the drive signal and output the filtered drive signal.

[0069] The third terminal of the power conversion module 23 is used to receive the second power signal. The power conversion module 23 is used to convert the second power signal into a third power signal and output it through the first terminal of the power conversion module 23. The power conversion module 23 provides a reference ground signal of the third power signal to the drive module 21 through the second terminal of the power conversion module 23.

[0070] In this embodiment, a three-level high-frequency inverter circuit can convert DC to three-level AC. When the three-level high-frequency inverter circuit is operating, a drive circuit needs to input a drive signal to control the operation of the switching devices in the circuit, thereby converting DC to three-level AC. Since a three-level high-frequency inverter circuit typically contains at least two switching devices, and a drive signal is required for each device, the drive circuit contains at least two drive branches 20. Each drive branch 20 includes a drive module 21, a filter module 22, and a power conversion module 23. The first terminal of the drive module 21 is used to receive a first control signal. The second terminal of the drive module 21 is electrically connected to the first terminal of the power conversion module 23, the third terminal of the drive module 21 is electrically connected to the second terminal of the power conversion module 23, and the fourth terminal of the drive module 21 is used to receive a first power signal. The third terminal of the power conversion module 23 is used to receive a second power signal. In this way, the power conversion module 23 can receive the second power signal, convert it into the third power signal required by the drive module 21, and output it through the first terminal of the power conversion module 23. At this time, the drive module 21 can receive the third power signal through its second terminal. Furthermore, the second terminal of the power conversion module 23 can output a reference ground signal for the third power signal. The third terminal of the drive module 21 is electrically connected to the second terminal of the power conversion module 23, meaning the third terminal of the drive module 21 is electrically connected to the reference ground terminal of the third power signal. This allows the third terminal of the drive module 21 to receive the reference ground signal for the third power signal, enabling the drive module 21 to accurately acquire the third power signal. The first terminal of the drive module 21 receives the first control signal. To isolate the drive signal output by the drive module 21 from the first control signal, the drive module 21 does not directly output the drive signal based on the first control signal. Instead, under the control of the first control signal, the drive module 21 senses and generates a second control signal based on the first power signal received at its fourth terminal. After generating the second control signal, the third power signal received at the second terminal of the drive module 21 can be used as the drive signal based on the second control signal to output the drive signal. In this way, the drive signal output by the drive module 21 will not be affected by the first control signal, which can improve the reliability of the drive signal and thus improve the common-mode transient immunity of the drive circuit.

[0071] To improve the reliability of the drive signal, the drive branch 20 also includes a filter module 22. The filter module 22 can filter the drive signal output by the drive module 21 and output the filtered drive signal to reduce interference signals in the drive signal.

[0072] Furthermore, in this embodiment, each drive branch 20 includes a power conversion module 23. That is, the third power signal and the reference ground signal of the third power signal generated by the power conversion module 23 in each drive branch 20 are isolated from each other and will not interfere with each other. In this way, the drive signals generated by the drive module 21 in each drive branch 20 are also isolated from each other and will not interfere with each other, further improving the common-mode transient immunity of the drive circuit.

[0073] It should be noted that, for ease of illustration, Figure 2 The image is only shown in the middle. Figure 1 The structure of the driving branch 20 is the same as that of the driving branch 20 shown in the diagram.

[0074] As one possible implementation, such as Figure 3 As shown, the drive module 21 includes a first switch submodule 211 and a drive submodule 212. The first terminal of the first switch submodule 211 is electrically connected to the first terminal of the drive submodule 212. The second terminal of the first switch submodule 211 is electrically connected to a first ground terminal. The control terminal of the first switch submodule 211 is used to receive a first control signal. The first switch submodule 211 is used to turn on and off under the control of the first control signal.

[0075] The second terminal of the drive submodule 212 is electrically connected to the first terminal of the power conversion module 23, and the third terminal of the drive submodule 212 is electrically connected to the second terminal of the power conversion module 23; the fourth terminal of the drive submodule 212 is used to receive the first power signal. The drive submodule 212 is used to generate second control information based on the first power signal when the first switch submodule is in the on state, and output a drive signal under the control of the second control signal.

[0076] In this embodiment, the driving module 21 includes a first switch submodule 211 and a driving submodule 212. A first terminal of the first switch submodule 211 is electrically connected to a first terminal of the driving submodule 212, and a second terminal of the first switch submodule 211 is electrically connected to a first ground terminal. The control terminal of the first switch submodule 211 receives a first control signal, which controls the switching on and off of the first switch submodule 211. When the first switch submodule 211 is on, its first and second terminals are connected, and the first terminal of the driving submodule 212 is electrically connected to the first ground terminal, meaning its first terminal is grounded. When the first switch submodule 211 is off, its first and second terminals are disconnected, and the branch between the first terminal of the driving submodule 212 and the first ground terminal is broken. The first ground terminal is the reference ground terminal for the first power signal.

[0077] The fourth terminal of the drive submodule 212 receives a first power signal. When the first switch submodule 211 is turned on, the branch between the fourth terminal and the first terminal of the drive submodule 212 is connected. Thus, the drive submodule 212 can generate a second control signal by sensing the first power signal received at its fourth terminal, and control the output of the drive signal through the second control signal. The second terminal of the drive submodule 212 is electrically connected to the first terminal of the power conversion module 23, and the third terminal of the drive submodule 212 is electrically connected to the second terminal of the power conversion module 23. The power conversion module 23 can convert the second power signal into a third power signal and output it through its first terminal. The second terminal of the power conversion module 23 serves as the reference ground terminal for the third power signal and can output the reference ground signal for the third power signal. The second terminal of the drive submodule 212 receives the third power signal. The third terminal of the drive submodule 212 receives the reference ground signal for the third power signal. Thus, under the control of the second control signal, the drive submodule 212 can output the third power signal as a drive signal. When the driver submodule 212 does not output a drive signal, it can output a reference ground signal of the third power supply signal received at the third terminal.

[0078] In some embodiments, the aforementioned driver submodule 212 may be a CA-IS3211 chip. The CA-IS3211 chip is an optocoupler-compatible single-channel isolated gate driver that can be used to drive switching devices, such as MOSFETs (metal-oxide semiconductor FETs), IGBTs (Insulated-Gate Bipolar Transistors), and SiC devices. It achieves an isolation level of 5.7 kVRMS (kilovolt effective value) and can provide a peak output current capability of 5 A and a sink current of 6 A. Key performance features of this chip include high common-mode transient immunity (CMTI), low propagation delay, and low pulse width distortion, enabling it to effectively drive high-voltage side power transistors. Of course, the driver submodule 212 can also be other chips capable of achieving the above functions, and this application does not limit its application to such applications.

[0079] As one possible implementation, such as Figure 4 As shown, the power conversion module 23 includes a power conversion submodule 231 and a first isolation submodule 232.

[0080] The first terminal of the power conversion submodule 231 is electrically connected to the second terminal of the drive submodule 212, and the second terminal of the power conversion submodule 231 is electrically connected to the third terminal of the drive submodule 212. The third terminal of the power conversion submodule 231 is used to receive the second power signal, and the fourth terminal of the power conversion submodule 231 is used to receive the reference ground signal of the second power signal. The power conversion submodule 231 is used to convert the second power signal into a third power signal, and output the third power signal through the first terminal of the power conversion submodule 231, and output the reference ground signal of the third power signal through the second terminal of the power conversion submodule 231.

[0081] One end of the first isolation submodule 232 is electrically connected to the fourth terminal of the power conversion submodule 231, and the other end of the first isolation submodule 232 is electrically connected to the second terminal of the power conversion submodule 231. The first isolation submodule 232 is used to isolate the reference ground signal of the second power signal from the reference ground signal of the third power signal.

[0082] In this embodiment, the power conversion module 23 provides a third power signal and a reference ground signal for the third power signal to the drive submodule 212. The power conversion module 23 includes a power conversion submodule 231 and a first isolation submodule 232. The first terminal of the power conversion submodule 231 is electrically connected to the second terminal of the drive submodule 212, and the second terminal of the power conversion submodule 231 is electrically connected to the third terminal of the drive submodule 212. The third terminal of the power conversion submodule 231 can receive the second power signal, and the fourth terminal of the power conversion submodule 231 receives the reference ground signal of the second power signal. In this embodiment, the magnitude of the drive signal to be generated in the drive submodule 212 is usually different from the magnitude of the second power signal, requiring adjustment of the second power signal before it can be input to the second terminal of the drive submodule 212. Therefore, the power conversion submodule 231 is needed. To ensure that the power conversion submodule 231 can accurately identify the second power signal, the fourth terminal of the power conversion submodule 231 receives the reference ground signal of the second power signal. The power conversion submodule 231 converts the received second power signal into a third power signal with the same signal magnitude as the drive signal required by the drive submodule 212. The third power signal is transmitted from the first terminal of the power conversion submodule 231 to the second terminal of the drive submodule 212. To ensure that the drive submodule 212 can accurately acquire the third power signal, the power conversion submodule 231 also needs to transmit a reference ground signal of the third power signal to the drive submodule 212. In this case, the power conversion submodule 231 can use its second terminal as the reference ground terminal for the third power signal, thereby providing a reference ground signal for the third power signal to the drive submodule 212; that is, the second terminal of the power conversion submodule 231 is electrically connected to the third terminal of the drive submodule 212. In this way, the drive submodule 212 can receive the third power signal through its second terminal and connect to the reference ground terminal of the third power signal through its third terminal. Under the control of the second control signal, the third power signal is output as a drive signal. Furthermore, when no drive signal is output, the reference ground signal of the third power signal can be output.

[0083] It should be noted that since the second terminal of the power conversion submodule 231 outputs the reference ground signal of the third power signal, that is, the second terminal of the power conversion submodule 231 is the reference ground terminal of the third power signal. For ease of illustration, the second terminal of the power conversion submodule 231 will be represented by the reference ground of the third power signal in the following figures.

[0084] To prevent interference between the reference ground signal of the third power signal and the reference ground signal of the second power signal, which could cause signal inaccuracy, the power conversion module 23 also includes a first isolation submodule 232. The first terminal of the first isolation submodule 232 is electrically connected to the fourth terminal of the power conversion submodule 231, and the other terminal of the power isolation submodule 232 is electrically connected to the second terminal of the power conversion submodule 231. In this way, the first isolation submodule 232 can isolate the reference ground signal of the second power signal from the reference ground signal of the third power signal, preventing interference between them.

[0085] In some embodiments, to facilitate circuit implementation and reduce the circuit footprint, the first isolation submodule 232 can be a first capacitor C1. That is, the first capacitor C1 is used to isolate the reference ground signal of the third power supply signal from the reference ground signal of the second power supply signal. Figure 9a As shown.

[0086] As one possible implementation, refer to Figure 5 As shown, the power conversion module 23 further includes: a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a first inductor L1. The first end of the first inductor L1 is electrically connected to the first end of the second capacitor C2. The second ends of the first inductor L1 and the first end of the third capacitor C3 are electrically connected to the third end of the power conversion submodule 231. The second ends of the second capacitor C2 and the second ends of the third capacitor C3 are electrically connected to the fourth end of the power conversion submodule 231. One end of the fourth capacitor C4 is electrically connected to the first end of the power conversion submodule 231, and the other end of the fourth capacitor C4 is electrically connected to the second end of the power conversion submodule 231.

[0087] In this embodiment, the second capacitor C2, the first inductor L1, and the third capacitor C3 constitute a filtering circuit for the second power signal. Specifically, the first end of the first inductor L1 is electrically connected to the first end of the second capacitor C2, the second end of the first inductor L1 is electrically connected to the first end of the third capacitor C3, the first end of the third capacitor C3 is electrically connected to the third end of the power conversion submodule 231, and the second ends of the second capacitors C2 and C3 are electrically connected to the fourth end of the power conversion submodule 231. Thus, the second power signal can be filtered by the second capacitor C2, the first inductor L1, and the third capacitor C3, and the filtered second power signal is transmitted to the third end of the power conversion submodule 231. To improve the signal quality of the third power signal, one end of the fourth capacitor C4 is electrically connected to the first end of the power conversion submodule 231, and the other end of the fourth capacitor C4 is electrically connected to the second end of the power conversion submodule 231. Thus, the fourth capacitor C4 can filter the third power signal output by the power conversion submodule 231, improving the signal quality of the third power signal.

[0088] As one possible implementation, such as Figure 6 As shown, the driving module 21 also includes: a first resistor R1, a fifth capacitor C5, a sixth capacitor C6, and a second resistor R2.

[0089] One end of the first resistor R1 is electrically connected to the control terminal of the first switch submodule 211, and the other end of the first resistor R1 is electrically connected to the second terminal of the first switch submodule 211.

[0090] The fifth capacitor C5 and the sixth capacitor C6 are connected in parallel. One end of the fifth capacitor C5 and the sixth capacitor C6 is electrically connected to the second end of the drive submodule 212, and the other end of the fifth capacitor C5 and the sixth capacitor C6 is electrically connected to the second end of the power conversion submodule 231.

[0091] One end of the second resistor R2 is electrically connected to the output terminal of the driver submodule 212, and the other end of the second resistor R2 is electrically connected to the filter module 22.

[0092] In this embodiment, to improve the safety of the drive module 21, a first resistor R1 is also included. One end of the first resistor R1 is electrically connected to the control terminal of the first switch submodule 211, and the other end is electrically connected to the second terminal of the first switch submodule 211. Thus, the first resistor R1 not only limits current but also controls the charging and discharging speed of the control terminal of the first switch submodule 211, preventing damage to the first switch submodule 211 and improving the safety of the drive module 21. Furthermore, the drive module 21 also includes a fifth capacitor C5 and a sixth capacitor C6, which are connected in parallel. One end of each capacitor is electrically connected to the second terminal of the drive submodule 212, and the other end is electrically connected to the second terminal of the power conversion submodule 231. In the accompanying drawings, the second terminal of the power conversion submodule 231 is represented by the reference ground of the third power signal. Thus, the fifth capacitor C5 and the sixth capacitor C6 can be the filtering circuit for the third power signal. Interference signals, such as AC signals, in the third power signal output by the power conversion submodule 231 can be transmitted to the reference ground terminal of the third power signal through the fifth capacitor C5 and the sixth capacitor C6. The filtered third power signal can be transmitted to the second terminal of the drive submodule 212.

[0093] The aforementioned drive module 21 also includes a second resistor R2. One end of the second resistor R2 is electrically connected to the output terminal of the drive submodule 212, and the other end is electrically connected to the filter module 22. In this way, the second resistor R2 can limit the current of the drive signal output by the drive submodule 212, preventing the drive signal from damaging the subsequent three-level high-frequency inverter module and improving circuit safety.

[0094] As one possible implementation, such as Figure 7 As shown, the filter module 22 includes a seventh capacitor C7 and a third resistor R3. The seventh capacitor C7 and the third resistor R3 are connected in parallel, and one end of the seventh capacitor C7 and the third resistor R3 is electrically connected to the output terminal of the drive submodule 212, and the other end of the seventh capacitor C7 and the third resistor R3 is electrically connected to the second terminal of the power conversion submodule 231.

[0095] In order to reduce interference signals in the drive signal, a filter module 22 is electrically connected to the output terminal of the drive submodule 212. To improve filtering efficiency and reduce circuit complexity, the filter module 22 can be an RC filter circuit. Specifically, the filter module 22 includes a seventh capacitor C7 and a third resistor R3. The seventh capacitor C7 and the third resistor R3 are connected in parallel. One end of the seventh capacitor C7 and the third resistor R3 is electrically connected to the output terminal of the drive submodule 212, and the other end of the seventh capacitor C7 and the third resistor R3 is electrically connected to the second terminal of the power conversion submodule 231. In the attached figure, the second terminal of the power conversion submodule 231 is represented by the reference ground of the third power supply signal. In this way, one end of the seventh capacitor C7 and the third resistor R3 is electrically connected to the output terminal of the drive submodule 212, and the other end of the seventh capacitor C7 and the third resistor R3 is electrically connected to the reference ground terminal of the drive signal. This can filter out interference signals, such as AC signals, in the drive signal and improve the accuracy of the drive signal.

[0096] As one possible implementation, such as Figure 8 As shown, the driving module 21 further includes a first freewheeling submodule 213 and a second freewheeling submodule 214, and the filtering module 22 further includes a protection submodule 223. The positive terminal of the first freewheeling submodule 213 is electrically connected to the control terminal of the first switching submodule 211, and the negative terminal of the first freewheeling submodule 213 is used to receive the first control signal. The positive terminal of the second freewheeling submodule 214 is electrically connected to the filtering module 22, and the negative terminal of the second freewheeling submodule 214 is electrically connected to the output terminal of the driving submodule 212. The protection submodule 223 is connected in parallel with the seventh capacitor C7 and the third resistor R3.

[0097] In this way, the first freewheeling submodule 213 and the second freewheeling submodule 214 can prevent reverse current from damaging the drive submodule 212, thereby improving the safety of the drive module 21. The protection submodule 223 can reduce the probability of instantaneous surges damaging various components in the drive circuit.

[0098] Furthermore, the aforementioned first freewheeling submodule 213 can be a first diode D1 and a fourth resistor R4 connected in parallel. In this case, the positive terminal of the first diode D1 and one end of the fourth resistor R4 are electrically connected to the control terminal of the first switching submodule 211. The negative terminal of the first diode D1 and the other end of the fourth resistor R4 are used to receive the first control signal.

[0099] The aforementioned second freewheeling submodule 214 can be a second diode D2 connected in parallel. In this case, the positive terminal of the second diode D2 is electrically connected to the filter module 22. The negative terminal of the second diode D2 is electrically connected to the output terminal of the drive submodule 212.

[0100] The aforementioned protection submodule 223 can be a TVS (Transient Voltage Suppressor) diode.

[0101] As one possible implementation, the aforementioned drive circuit includes four drive branches. The structure of each drive branch can refer to the structure of the drive branch described above.

[0102] For example, assume the above driving circuit includes four driving branches, all of which have the same structure. For ease of illustration, the following description uses any one of these driving branches as an example. The driving branch includes a driving module 21, a filtering module 22, and a power conversion module 23. Driving module 21 includes a first switching submodule 211, a driving submodule 212, a first resistor R1, a fifth capacitor C5, a sixth capacitor C6, a second resistor R2, a first freewheeling submodule 213, and a second freewheeling submodule 214. Assume driving submodule 212 is a CA-IS3211 chip, represented by U1 in the diagram. The pin structure of the CA-IS3211 chip is as follows... Figure 9b As shown. Reference Figure 9a As shown, the first switching submodule 211 is an N-type MOSFET, represented by Q1 in the diagram. The first freewheeling submodule 213 includes a first diode D1 and a fourth resistor R4 connected in parallel. The second freewheeling submodule 214 includes a second diode D2. The filter module 22 includes a seventh capacitor C7, a third resistor R3, and a TVS diode D3 connected in parallel. The power conversion module 23 includes a power conversion submodule 231, a first isolation submodule 232, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a first inductor L1. Assuming that the power conversion submodule 231 is an F2415S-2WR2 chip, represented by U2 in the diagram. The first isolation submodule 232 is the first capacitor C1.

[0103] Thus, in Figure 9aIn this configuration, the first inductor L1 is connected between the first terminal of the second capacitor C2 and the first terminal of the third capacitor C3. The first terminal of the first inductor L1 and the first terminal of the second capacitor C2 are electrically connected to receive the second power supply. The second terminal of the second capacitor C2 is electrically connected to the second pin of U2. The second pin of U2 is the reference ground pin of U2 and is electrically connected to the ground terminal of the second power supply. The second terminal of the first inductor L1 and the first terminal of the third capacitor C3 are electrically connected to the first pin of U2, where the first pin of U2 is the power supply pin. The second terminal of the third capacitor C3 is electrically connected to the second pin of U2. The seventh pin of U2 is the output pin of U2, and the fifth pin of U2 serves as the 0V level signal output pin. The fifth pin of U2 serves as the reference ground terminal for the third power supply signal. The seventh pin of U2 outputs the third power supply signal. One end of the first capacitor C1 is electrically connected to the second pin of U2, and the other end is electrically connected to the fifth pin of U2 to isolate the reference ground signal of the second power supply signal and the reference ground signal of the third power supply signal. One end of the fourth capacitor C4 is electrically connected to pin 7 of U2, and the other end of the fourth capacitor C4 is electrically connected to pin 5 of U2. The fourth capacitor C4 can filter the third power supply signal output by U2.

[0104] The anode of the first diode D1 and one end of the fourth resistor R4 are electrically connected to the control terminal of the first switch submodule Q1. The cathode of the first diode D1 and the other end of the fourth resistor R4 are used to receive the first control signal. One end of the first resistor R1 is electrically connected to the control terminal of the first switch submodule Q1, and the other end of the first resistor R1 is electrically connected to the source of the first switch submodule Q1. The source of the first switch submodule Q1 is electrically connected to the first ground terminal. The drain of the first switch submodule Q1 is electrically connected to the third pin of U1, where the third pin of U1 is the cathode. The first power supply is electrically connected to the second pin of U1 via the sixth resistor R6, where the second pin of U1 is the anode. One end of the fifth capacitor C5 and the sixth capacitor C6 are electrically connected to the eighth pin of U1, where the eighth pin of U1 is the positive terminal of the power supply of U1. The eighth pin of U1 is electrically connected to the seventh pin of U2. The other end of the fifth capacitor C5 and the sixth capacitor C6 is electrically connected to the reference ground terminal of the third power supply signal. Pin 5 of U1 is electrically connected to the reference ground of the third power supply signal, which is also electrically connected to pin 5 of U2. Pin 5 of U1 is the negative power supply terminal of U1. Pin 6 of U1 is electrically connected to the negative terminal of the second diode D2. Pin 6 of U1 is the output terminal of U1. The positive terminal of the second diode D2 is electrically connected to one end of the seventh capacitor C7, one end of the third resistor R3, and one end of the TVS diode D3. The other end of the seventh capacitor C7, the other end of the third resistor R3, and the other end of the TVS diode D3 are electrically connected to the reference ground of the third power supply signal. Assuming the first power supply is 5V, the second power supply is 24V, and the third power supply signal is 15V. The 24V power supply signal is filtered by the first inductor L1, the second capacitor C2, and the third capacitor C3, and then transmitted to pin 1 of U2. U2 steps down the 24V power supply signal, converting it into a 15V third power supply signal, and outputs it through pin 7 of U2. The 15V third power supply signal is filtered by the fifth capacitor C5 and the sixth capacitor C6 before being transmitted to the eighth pin of U1. A seventh resistor R7 is electrically connected between the first terminal of the first switch submodule Q1 and the third pin of U1 to prevent excessive current from damaging U1. A sixth resistor R6 is electrically connected between the second pin of U1 and the first power supply to prevent damage to U1.

[0105] The control terminal of the first switch submodule Q1 can receive a first control signal. When the first switch submodule Q1 is turned on according to the first control signal, the branch between the third pin of U1 and the first ground terminal is connected, and the circuit between the second pin and the third pin of U1 is connected. U1 can generate a second control signal based on the first power supply signal. When U1 receives the second control signal, it can control the circuit between the sixth pin and the eighth pin to be connected. At this time, the 15V third power supply signal can be output as a drive signal at the sixth pin of U1. When the first switch submodule Q1 is turned off according to the first control signal, the branch between the third pin of U1 and the first ground terminal is disconnected, and U1 does not generate a second control signal. When U1 does not receive the second control signal, the circuit between its sixth pin and the fifth pin is connected. At this time, the sixth pin of U1 outputs a reference ground signal of the 15V third power supply signal. This example uses the above scenario for illustration.

[0106] After the seventh capacitor C7 and the third resistor R3 filter the output drive signal, the drive branch can output the drive signal.

[0107] In this embodiment, each drive branch in the drive circuit outputs a drive signal, and the drive signals and their reference ground signals are mutually isolated, reducing mutual interference between drive signals and improving the common-mode transient immunity of the drive circuit. Furthermore, for each drive branch, after generating a second control signal based on the first control signal, the output of the drive signal is controlled based on the second control signal. This ensures that the output drive signal is also isolated from the first control signal, reducing the influence of the first control signal on the drive signal and further improving the common-mode transient immunity of the drive circuit.

[0108] refer to Figure 10 This is a schematic diagram of a plasma power supply circuit provided in an embodiment of this application. Figure 10 As shown, the circuit includes a drive circuit 101, a three-level high-frequency inverter circuit 102, and a high-frequency voltage conversion circuit 103. The drive circuit 101 is the drive circuit described in the above embodiment.

[0109] The drive circuit 101 is electrically connected to the first terminal of the three-level high-frequency inverter circuit 102, and the second terminal of the three-level high-frequency inverter circuit 102 is electrically connected to the input terminal of the high-frequency voltage conversion circuit 103. The third terminal of the three-level high-frequency inverter circuit 102 is used to receive DC power. The output terminal of the high-frequency voltage conversion circuit 103 is used to connect to a plasma load.

[0110] The drive circuit 101 is used to send drive signals to the three-level high-frequency inverter circuit 102.

[0111] The three-level high-frequency inverter circuit 102 is used to convert DC power supply into three levels of power signals under the action of a drive signal and output them.

[0112] The high-frequency voltage conversion circuit 103 is used to boost the power signal output by the three-level high-frequency inverter circuit 102 and output the boosted power signal to the plasma load.

[0113] In this embodiment, the three-level high-frequency inverter circuit 102, as a mainstream multi-level inverter topology, offers significant advantages in output voltage quality and efficiency. It divides the DC voltage of the power supply into three levels, rather than the two levels found in a full-bridge inverter, using two intermediate capacitors and two switching devices. This design enables the three-level inverter to generate a higher quality output voltage with lower current harmonics and higher efficiency. Simultaneously, it reduces switching device losses and EMI noise, making it particularly suitable for high-power applications.

[0114] In comparison, while full-bridge inverters offer advantages such as lower cost and simpler structure, their output voltage quality is inferior to that of the three-level high-frequency inverter circuit 102, and their efficiency is also relatively lower. Full-bridge inverters use four switching devices to convert DC voltage to AC voltage. Although widely used in low-power applications such as household appliances and small electronic devices, their performance is inferior to the three-level high-frequency inverter circuit 102 in applications requiring high power and high quality.

[0115] In some embodiments, the three-level high-frequency inverter circuit 102 employs a diode-clamped NPC three-level inverter, see reference. Figure 11aAs shown, the circuit includes a first power switch Q2, a second power switch Q3, a third power switch Q4, a fourth power switch Q5, a first clamping diode D4, a second clamping diode D5, a first bus capacitor C11, and a second bus capacitor C12. Q3, Q4, D4, and D5 form a clamping midpoint type circuit. The first bus capacitor C11 and the second bus capacitor C12 are connected in series between the positive DC bus BUS+ and the negative DC bus BUS-. The common node of the first bus capacitor C11 and the second bus capacitor C12 forms the DC bus midpoint b. The first terminal of the first power switch Q2 is electrically connected to the positive DC bus BUS+, the second terminal of the first power switch Q2 is electrically connected to the first terminal of the second power switch Q3, and the second terminal of the second power switch Q3 is electrically connected to the output terminal a. The first terminal of the third power switch Q4 is electrically connected to the output terminal a. The second terminal of the third power switch Q4 is electrically connected to the first terminal of the fourth power switch Q5. The second terminal of the fourth power switch Q5 is electrically connected to the negative DC bus BUS-. The positive terminal of the first clamping diode D4 and the negative terminal of the second clamping diode D5 are electrically connected to the midpoint b of the DC bus. The negative terminal of the first clamping diode D4 is electrically connected to the first terminal of the second power switch Q3. The positive terminal of the second clamping diode D5 is electrically connected to the first terminal of the fourth power switch Q5.

[0116] In this configuration, the first power switch Q2, the second power switch Q3, the third power switch Q4, and the fourth power switch Q5 can be N-type MOSFETs. In this case, the first terminal of each of the four power switches Q2, Q3, Q4, and Q5 is the drain, and the second terminal of each is the source. Figure 11a As shown.

[0117] It should be understood that the first power switch Q2, the second power switch Q3, the third power switch Q4, and the fourth power switch Q5 can also be P-type MOSFETs. In this case, the first terminal of each of the four power switches Q2, Q3, Q4, and Q5 is the source, and the second terminal is the drain. Of course, the first power switch Q2, Q3, Q4, and Q5 can also be other types of power switches, and this application embodiment does not limit this.

[0118] The control terminals of the first power switch Q2, the second power switch Q3, the third power switch Q4, and the fourth power switch Q5 are electrically connected to the output terminals of the four drive branches in the drive circuit 101, respectively. Thus, each drive branch in the drive circuit 101 can drive its corresponding power switch to turn on or off, and different drive branches drive different power switches. Therefore, when the first power switch Q2 and the second power switch Q3 are simultaneously turned on, and the third power switch Q4 and the fourth power switch Q5 are simultaneously turned off, the voltage level at output terminal a relative to point b is +U. dc / 2, where U dc This represents the voltage between the positive DC bus BUS+ and the negative DC bus BUS-. When the second power switch Q3 and the third power switch Q4 are both on, and the first power switch Q2 and the fourth power switch Q5 are both off, the voltage level at point a relative to point b is 0V. When the first power switch Q2 and the second power switch Q3 are both off, and the third power switch Q4 and the fourth power switch Q5 are both on, the voltage level at point a relative to point b is +U. dc The switching states and output levels of the / 2 three-level high-frequency inverter circuit 102 can be referenced in Table 1 below.

[0119] Table 1

[0120]

[0121] In Table 1, 1 indicates that the power switch is on, and 0 indicates that the power switch is off.

[0122] For ease of representation, the switching function Si can be defined using Table 1 as follows:

[0123]

[0124] Where Sa represents the state of the bridge arm. Based on the defined ideal switching function Si, Figure 11a The diode-clamped three-level high-frequency inverter circuit 102 shown can be equivalent to: Figure 11b The equivalent circuit shown has the fifth resistor R5 and the second inductor L2 forming the equivalent load between points a and b. According to the above formula, the bridge arm has three equivalent states: 1, 0, and -1. Switch S can be used to activate different branches, thus controlling the state of different bridge arms and outputting different voltages. Figure 11bIn this circuit, the second inductor L2 is connected in series with the fifth resistor R5. One end of the fifth resistor R5 is electrically connected to one end of the second inductor L2, and the other end of the fifth resistor R5 is connected to the first terminal of switch S. The second terminal of switch S is electrically connected to the first terminal of the first bus capacitor C11 and the positive DC bus BUS+. The third terminal of switch S is electrically connected to the second terminal of the second bus capacitor C12 and the negative DC bus BUS-. The first bus capacitor C11 and the second bus capacitor C12 are connected in series between the positive DC bus BUS+ and the negative DC bus BUS-. The fourth terminal of switch S is electrically connected to the second terminal of the first bus capacitor C11, and the other end of the second inductor L2 is electrically connected to the first terminal of the second bus capacitor C12. Thus, by controlling the conduction of different terminals of switch S (the first terminal and its second, third, and fourth terminals), different bridge arm states are achieved, resulting in different output voltages.

[0125] right Figure 11b Applying KVL's law to the equivalent circuit shown, we can obtain: Where i represents the current value, R represents the resistance of the fifth resistor R5, L represents the inductance of the second inductor L2, and S represents the state of the bridge arm, where S = (-1, 0, 1). U dc This represents the voltage between the positive DC bus BUS+ and the negative DC bus BUS-.

[0126] From the voltage and capacitance relationship between C11 and C12, we can obtain:

[0127]

[0128] The mathematical model of the three-level high-frequency inverter circuit 102 can be expressed as:

[0129]

[0130] Therefore, the state equation of the three-level high-frequency inverter circuit 102 is as follows:

[0131]

[0132] Assuming the above formula is passed through If it means:

[0133]

[0134] Compared to a two-level structure, the three-level structure requires only half the DC switching voltage under the same bus voltage, bringing many advantages, mainly including the following:

[0135] (1) Better output waveform

[0136] Because the voltage level of a three-level bridge arm changes from positive or negative to the midpoint potential during commutation, adding an extra step, the waveform change is smoother and closer to a sine wave when converted to phase voltage. The waveform of a three-level bridge is much smoother than that of a two-level bridge. Typically, the total harmonic distortion (THD) of a two-level output voltage is around 50%, while at the same switching frequency, the THD of a three-level bridge is only around 26%. This reduction of nearly half significantly helps to reduce harmonic injection into the power grid.

[0137] (2) Improve electromagnetic interference (EMI) problems

[0138] In a three-level structure, the switching voltage of the power switch is reduced by half. The rate of change of voltage (dv / dt) is a major source of electromagnetic interference (EMI) in power electronic systems. During switching, the rate of change of voltage (dv / dt) of the power switch is significantly reduced, which translates to a reduction and improvement in system EMI. Furthermore, in inverter applications, it can reduce shaft current, effectively mitigating the inverter's impact on motor lifespan.

[0139] (3) Reduced losses, higher efficiency, and increased switching frequency

[0140] During the switching process, the decrease in DC voltage during the turn-on and turn-off of the power switch significantly reduces the switching losses of the chip. Based on empirical values, the relationship between DC voltage and switching losses is as follows:

[0141] Among them, E SW V represents switching losses. ref Indicates the reference voltage, V dc This indicates DC voltage.

[0142] Calculations show that when the switching DC voltage is reduced to 50%, the loss decreases to about 40% of its original value. This reduction in loss translates to higher efficiency and a higher switching frequency. The increased switching frequency greatly benefits the design of LC filters, allowing for smaller reactor sizes and volume, and facilitating more reliable resonant point design.

[0143] refer to Figure 11a As shown, the DC power supply between the positive DC bus BUS+ and the negative DC bus BUS- can output a DC voltage of 310V after the 220V AC power is rectified by a bridge rectifier.

[0144] In some embodiments, the switching devices in the above-described three-level high-frequency inverter circuit 102 are SiC switching devices.

[0145] Among them, silicon carbide power semiconductor devices have many advantages, such as high temperature resistance, low impedance, fast switching speed, and high operating frequency, exhibiting significant performance advantages. Especially in applications such as plasma generators and high-power motor control, silicon carbide power semiconductor devices can effectively improve the power density and efficiency of the system, reduce heat loss, and perform even better under extreme conditions such as high frequency, high voltage, and high temperature, making them an ideal choice for achieving high efficiency and integration.

[0146] In some embodiments, the DC input voltage of 310V in the three-level high-frequency inverter circuit 102 is clamped by clamping diodes. During normal system operation, each power switch transistor withstands a DC voltage of 155V. In general, sudden power quality issues must be considered, as exceeding the withstand voltage of the switch transistors could burn them out. Therefore, a certain voltage margin must be maintained. In this embodiment, the four power switch transistors can be selected as GC2M0040120D SiC MOSFETs in a TO-247-3 package, with a drain-source withstand voltage U... DS 1200V, leakage current I D It is 55A.

[0147] In some embodiments, during normal operation, the voltage across each bus capacitor on the DC side of the three-level high-frequency inverter circuit 102 is 155V. Considering a margin of 2, its rated voltage must be at least 310V. This is because there is a potential shift at the midpoint of the two bus capacitors on the DC side of the three-level high-frequency inverter circuit 102. A larger capacitance value results in higher voltage stability for the system and better suppression of the midpoint shift. Therefore, in this embodiment, the impact of the midpoint potential shift on the target output voltage is minimized, and the capacitance value is chosen to be as large as possible while still meeting the target output voltage requirements.

[0148] Generally, non-polar capacitors are used as voltage divider capacitors in NPC (Neutral Point Clamped) circuits to prevent reverse voltage from affecting the capacitors and causing failure or damage. Considering both voltage withstand capability and stability, bus capacitors typically withstand higher voltages, especially in high-power applications. Non-polar capacitors (such as ceramic or film capacitors) offer advantages in voltage withstand capability and stability, making them suitable for continuously withstanding high voltages in DC or AC environments without easily failing. Finally, considering the high requirements of NPC circuits for the frequency response and loss tangent (ESR) of bus capacitors, non-polar capacitors such as ceramic and film capacitors exhibit better high-frequency characteristics and lower losses, making them suitable for the operating requirements of high-frequency circuits.

[0149] The magnitudes of the voltage dividers in an NPC circuit can be estimated using the following formula. The bus capacitor is primarily used to balance the voltage, maintain a stable neutral point voltage, and withstand voltage fluctuations caused by switching operations.

[0150] Assuming the three-level high-frequency inverter circuit 102 uses two bus capacitors C11 and C12, and the goal is to ensure a stable midpoint voltage, the basic formula for calculating the capacitor size is:

[0151]

[0152] Δv=u P-P *(1%–2%); (3)

[0153] Where: C is the bus capacitance (unit: farad, F). DC Δv is the effective value of the DC bus current (unit: ampere, A), which is the DC side current of the three-level high-frequency inverter circuit 102. f is the switching frequency (unit: hertz, Hz), referring to the switching operating frequency of the three-level high-frequency inverter circuit 102. Δv is the allowable midpoint voltage ripple (unit: volt, V), typically 1% to 2% of the bus voltage.

[0154] Assume I P-P 45A, f is 25KHz, U P-P Since the voltage is 310V, substituting it into formulas (1)-(3) yields C = 25.7uF. Considering the margin, C is selected as 30uF. Therefore, a welding machine capacitor with a rated voltage of 400V and a capacitance of 30μF is selected.

[0155] In some embodiments, the three-level high-frequency inverter circuit 102 receives a 310V DC input voltage on the DC side. Due to the clamping effect of the clamping diodes, each clamping diode withstands a 155V DC voltage during normal system operation. When using this circuit, it is generally necessary to consider sudden power quality issues and allow for a certain margin. Therefore, a SiC diode of model GC4D30120H, packaged in TO-247-2, is selected, with a DC reverse withstand voltage U... RRM The voltage is 1.2KV, and the rectified current I is... F It is 94A.

[0156] Assuming that, in the embodiments of this application, the bus current I in the plasma power supply circuit... P-P Bus voltage U P-P The design parameters for load voltage U, load power P, and frequency f are shown in Table 2 below.

[0157] parameter Design maximum value <![CDATA[Busbar current I P-P > 50A <![CDATA[Bus voltage U P-P > 320V Load voltage U 25KV Load power P 500W Frequency f 25KHz

[0158] The aforementioned three-level high-frequency inverter circuit 102 converts the three-level output voltage signal with a peak-to-peak value of 310V into a high-voltage signal of 18kV, which is then transmitted to the high-frequency high-voltage conversion circuit 103.

[0159] The high-frequency voltage conversion circuit 103 includes a high-frequency transformer; the high-frequency transformer meets preset conditions. These preset conditions include: the wire diameter of the high-frequency transformer is 0.015 cm. 2 (square centimeters) -0.02cm 2 Within the specified range, the window utilization rate in high-frequency transformers is within the range of 80%-85%, and the area of ​​high-frequency transformers is within 19cm². 2 -21cm 2 Within the specified range, the operating frequency of the high-frequency transformer is 25 kHz, the magnetic flux density in the high-frequency transformer is in the range of 0.35-0.45, the voltage regulation rate is in the range of 1-5, and the cross-sectional area of ​​the magnetic core in the high-frequency transformer is 3.4 cm². 2 -3.6cm 2 Within the range of 14-18, at least one of the following: the area of ​​the high-frequency transformer includes the product of the maximum cross-sectional area of ​​the transformer core and the window area.

[0160] Based on preset conditions, the wire diameter of the high-frequency transformer can be set to 0.017cm. 2 Within the specified range, the window utilization rate in the high-frequency transformer is 80%, and the area of ​​the high-frequency transformer is 20 cm². 2 Within the specified range, the operating frequency of the high-frequency transformer is 25 kHz, the magnetic flux density in the high-frequency transformer is 0.4, the voltage regulation rate is 1, and the cross-sectional area of ​​the magnetic core in the high-frequency transformer is 3.54 cm². 2 A high-frequency transformer with 16 primary turns was simulated.

[0161] When performing simulation, such as Figure 12 As shown in (1), the waveform coefficient K can be used to determine the waveform coefficient K. f Calculate the electrical state coefficient K using frequency f and magnetic flux density B. e ,

[0162] like Figure 12 As shown in (2), according to the electrical state coefficient K e Voltage regulation rate a and core geometric parameters K g Calculate the apparent power P t ,

[0163] like Figure 12 As shown in (3), the derivation of Faraday's law of electromagnetic induction is based on the waveform coefficient K. f Magnetic flux density B, frequency f, number of turns Np and the cross-sectional area A of the magnetic core c Given the given information, calculate the bus voltage V. Wherein, (turns).

[0164] like Figure 12 As shown in (4), based on the waveform coefficient K f Window utilization rate K u Area A p Frequency f, magnetic flux density B, and apparent power P t Calculate the current density J. Where,

[0165] like Figure 12 As shown in (5), based on the known wire diameter A wp The bus current I passing through the conductor is obtained by multiplying the current density J by the current density J.

[0166] After simulating the high-frequency transformer, refer to Figure 13 This is a schematic diagram showing the simulation results of the bus current of a high-frequency transformer. The effective value of the bus current (IF) is shown. RMS It is 24.5A. (Reference) Figure 14 This is a schematic diagram showing the simulation results of the bus voltage of a high-frequency transformer. The effective value of the bus voltage, U... RMS It is 251.5V.

[0167] In some embodiments, the magnetic core material of the high-frequency transformer is ferrite, PC40, iron-nickel alloy, or nanocrystalline alloy, and the output wire is multi-strand wire with a cross-sectional area of ​​3.14 mm². 2 The UY16 type ferrite transformer has a high-temperature outer film that can withstand temperatures up to 180 degrees Celsius.

[0168] refer to Figure 15 This is a schematic diagram of another plasma power supply circuit provided in an embodiment of this application. The circuit includes a rectifier bridge circuit, a drive circuit 101, a three-level high-frequency inverter circuit 102, and a high-frequency voltage conversion circuit 103.

[0169] refer to Figure 16 This is a schematic diagram of the generation of drive signals in a three-level high-frequency inverter circuit 102. The drive circuit 101 includes four drive branches, each outputting a drive signal to one of the four power switching transistors in the three-level high-frequency inverter circuit 102.

[0170] refer to Figure 17 This is a schematic diagram of the drive signals for the three-level high-frequency inverter circuit 102. Figure 17The drive signals are 4-channel PWM waves with a frequency of 25KHz, adjustable duty cycle, and fixed phase shift.

[0171] In some embodiments, to avoid the risk of shoot-through in the bridge arm of the three-level high-frequency inverter circuit 102, which could lead to excessive heat loss in the power switching transistors and even damage to the transistors, the heating and temperature rise of the power switching transistors are effectively reduced. For example... Figure 18 This diagram illustrates a complementary PWM signal with a 500ns (nanosecond) dead time. The dead times of all complementary PWM signals are set to 500ns. The first power switch Q2 and the third power switch Q4 are complementary, as are the second power switch Q3 and the fourth power switch Q5. Both the first power switch Q2 and the third power switch Q4 have a 500ns dead time.

[0172] refer to Figure 19 U is the bus voltage of the high-frequency transformer. P-P A simulation diagram. In Figure 19 Three-level voltage peak-to-peak value U PP-P It is 312V.

[0173] refer to Figure 20 This is a simulation diagram of the voltage at point b, the midpoint of the three-level high-frequency inverter circuit 102. (See diagram for example.) Figure 20 As shown, the upper half peak voltage is 156V, and the lower half peak voltage is also 156V. A three-level high-frequency inverter circuit 102 with all SiC is used to achieve midpoint potential balance, ensuring a stable and accurate output voltage waveform, thereby improving output power quality. This also reduces voltage stress on the capacitors, extending their lifespan; and lowers voltage stress on the inverter switching transistors, improving system reliability. Furthermore, reducing harmonic generation helps protect load equipment such as motors.

[0174] refer to Figure 21 , is the bus current I of the high-frequency transformer. P-P A simulation diagram. In Figure 21 Intermediate bus current I P-P It is 43A.

[0175] refer to Figure 22 This is a simulation diagram of the current at point b, the midpoint of the three-level high-frequency inverter circuit 102. (See diagram for example.) Figure 22 As shown, the peak current in the upper half is 21.5A and the peak current in the lower half is 21.5A.

[0176] refer to Figure 23 I is the peak-to-peak value of the secondary current of the high-frequency transformer. PP-S A simulation diagram. (For example...) Figure 23 As shown, the peak-to-peak value I of the secondary current of the high-frequency transformer PP-SIt is 0.638A. Because... Figure 21 The bus current I is displayed in the middle. P-P It is 43A. This can be calculated according to the formula. Calculate the secondary voltage value U of the high-frequency transformer. PP-S It is 21.03KV.

[0177] Simulation results show that the output of the high-frequency transformer in this embodiment is basically the same as the target values ​​of each parameter of the plasma power supply circuit preset in Table 2. Therefore, the plasma power supply circuit in this embodiment can provide an accurate power supply voltage for the plasma load. Specifically, the plasma power supply circuit in this embodiment can use a single-phase AC power supply as the power input, and rectify the 220V AC voltage into a DC output voltage signal with a peak-to-peak value of 310V through a diode full-bridge rectifier circuit. The SiC-based three-level high-frequency inverter circuit 102 converts the 310V DC voltage into a three-level output voltage signal. In the drive circuit, a dual-channel complementary PWM drive signal with a high frequency of 25KHz SiC power switching transistor drives the power switching transistor of the three-level high-frequency inverter circuit 102, realizing the system's inverter function. Furthermore, the input terminal of the high-frequency transformer is electrically connected to the output terminal of the three-level high-frequency inverter circuit 102. The three-level output voltage signal is connected to the primary side of a high-frequency transformer, which is composed of a ferrite PL-13U core. On the secondary side of the high-frequency transformer, the three-level output voltage signal with a peak-to-peak value of 310V is converted into a high voltage of 21.03KV. The output terminal of the high-frequency transformer is connected to a plasma load, for example, to a plasma direct injection gun, in which gas forms plasma under a high voltage of 21.03KV.

[0178] Furthermore, silicon carbide (SiC) has garnered significant attention in high-frequency and high-voltage applications, particularly in the design and implementation of plasma generators. All-SiC high-frequency, high-voltage plasma generators leverage the superior characteristics of SiC devices, which exhibit low on-resistance and high switching speeds, enabling efficient operation at high frequencies. All-SiC devices also perform exceptionally well in high-temperature and high-voltage environments, making them suitable for the harsh operating conditions of plasma generators.

[0179] The core of an all-SiC high-frequency high-voltage plasma generator lies in its highly efficient power conversion capability. This system typically employs a three-level topology, which effectively reduces switching losses and increases the system's power density. Specifically, the three-level topology can provide a higher voltage level during the switching process of the switching devices, thereby reducing voltage stress and improving overall efficiency. This design is particularly suitable for high-frequency applications because it can operate stably at higher frequencies, meeting the instantaneous high voltage requirements for plasma generation.

[0180] refer to Figure 24This is a plasma system provided in an embodiment of this application. For example... Figure 24 As shown, the system includes a plasma power supply circuit 2401 and a plasma load 2402. The plasma power supply circuit 2401 is the plasma power supply circuit described in the above embodiment.

[0181] In some embodiments, the plasma load 2402 includes at least one of a plasma rotary spray gun and a load plasma direct injection spray gun.

[0182] Corresponding to the above embodiments, this application provides an electronic device that includes the driving circuit described in the above embodiments, or the plasma power supply circuit described in the above embodiments, or the plasma system described in the above embodiments.

[0183] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0184] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

Claims

1. A driving circuit, characterized in that, include: At least two drive branches; For each drive branch, the drive branch includes a drive module, a filter module, and a power conversion module; The first terminal of the drive module is used to receive a first control signal, the second terminal of the drive module is electrically connected to the first terminal of the power conversion module, the third terminal of the drive module is electrically connected to the second terminal of the power conversion module, the fourth terminal of the drive module is used to receive a first power signal, and the output terminal of the drive module is electrically connected to the filter module; the drive module is used to generate a second control signal based on the first power signal under the control of the first control signal, and output the signal obtained by the second terminal of the drive module as a drive signal under the control of the second control signal. The filtering module is used to filter the driving signal and output the filtered driving signal. The third terminal of the power conversion module is used to receive the second power signal. The power conversion module is used to convert the second power signal into a third power signal and output it through the first terminal of the power conversion module. The power conversion module provides the reference ground signal of the third power signal to the drive module through the second terminal of the power conversion module.

2. The circuit according to claim 1, characterized in that, The drive module includes a first switch submodule and a drive submodule; The first terminal of the first switch submodule is electrically connected to the first terminal of the drive submodule, the second terminal of the first switch submodule is electrically connected to the first ground terminal, and the control terminal of the first switch submodule is used to receive a first control signal; the first switch submodule is used to turn on and off under the control of the first control signal. The second terminal of the driving submodule is electrically connected to the first terminal of the power conversion module, and the third terminal of the driving submodule is electrically connected to the second terminal of the power conversion module; the fourth terminal of the driving submodule is used to receive a first power signal, and the driving submodule is used to generate second control information based on the first power signal when the first switch submodule is in the on state, and output a driving signal under the control of the second control signal.

3. The circuit according to claim 2, characterized in that, The power conversion module includes a power conversion submodule and a first isolation submodule; The first terminal of the power conversion submodule is electrically connected to the second terminal of the drive submodule, and the second terminal of the power conversion submodule is electrically connected to the third terminal of the drive submodule. The third terminal of the power conversion submodule is used to receive a second power signal, and the fourth terminal of the power conversion submodule is used to receive a reference ground signal of the second power signal. The power conversion submodule is used to convert the second power signal into a third power signal, and output the third power signal through the first terminal of the power conversion submodule, and output the reference ground signal of the third power signal through the second terminal of the power conversion submodule. One end of the first isolation submodule is electrically connected to the fourth end of the power conversion submodule, and the other end of the first isolation submodule is electrically connected to the second end of the power conversion submodule; the first isolation submodule is used to isolate the reference ground signal of the second power signal from the reference ground signal of the third power signal.

4. The circuit according to claim 3, characterized in that, The first isolation submodule includes a first capacitor.

5. The circuit according to claim 4, characterized in that, The power conversion module further includes a second capacitor, a third capacitor, a fourth capacitor, and a first inductor; a first end of the first inductor is electrically connected to a first end of the second capacitor, a second end of the first inductor and a first end of the third capacitor are electrically connected to a third end of the power conversion submodule, a second end of the second capacitor and a second end of the third capacitor are electrically connected to a fourth end of the power conversion submodule; one end of the fourth capacitor is electrically connected to a first end of the power conversion submodule, and the other end of the fourth capacitor is electrically connected to a second end of the power conversion submodule.

6. The circuit according to any one of claims 3-5, characterized in that, The driving module further includes: a first resistor, a fifth capacitor, a sixth capacitor, and a second resistor; One end of the first resistor is electrically connected to the control terminal of the first switch submodule, and the other end of the first resistor is electrically connected to the second terminal of the first switch submodule. The fifth capacitor and the sixth capacitor are connected in parallel. One end of the fifth capacitor and the sixth capacitor is electrically connected to the second terminal of the drive submodule, and the other end of the fifth capacitor and the sixth capacitor is electrically connected to the second terminal of the power conversion submodule. One end of the second resistor is electrically connected to the output terminal of the driving submodule, and the other end of the second resistor is electrically connected to the filtering module.

7. The circuit according to claim 6, characterized in that, The filtering module includes a seventh capacitor and a third resistor; the seventh capacitor and the third resistor are connected in parallel, and one end of the seventh capacitor and the third resistor is electrically connected to the output terminal of the driving submodule, and the other end of the seventh capacitor and the third resistor is electrically connected to the second terminal of the power conversion submodule.

8. A plasma power supply circuit, characterized in that, Includes the driving circuit, three-level high-frequency inverter circuit and high-frequency voltage conversion circuit as described in any one of claims 1-7; The driving circuit is electrically connected to the first terminal of the three-level high-frequency inverter circuit, and the second terminal of the three-level high-frequency inverter circuit is electrically connected to the input terminal of the high-frequency voltage conversion circuit; the third terminal of the three-level high-frequency inverter circuit is used to receive DC power; the output terminal of the high-frequency voltage conversion circuit is used to connect to the plasma load. The driving circuit is used to send a driving signal to the three-level high-frequency inverter circuit; The three-level high-frequency inverter circuit is used to convert the DC power supply into three levels of power signals under the action of the drive signal and output them. The high-frequency voltage conversion circuit is used to boost the power signal output by the three-level high-frequency inverter circuit and output the boosted power signal to the plasma load.

9. The circuit according to claim 8, characterized in that, The switching devices in the three-level high-frequency inverter circuit are SiC switching devices.

10. A plasma system, characterized in that, include: The plasma power supply circuit and plasma load according to any one of claims 8-9.

11. The system according to claim 10, characterized in that, The plasma load includes at least one of a plasma rotary spray gun and a plasma direct injection spray gun.

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