Control circuit and control method of power factor correction circuit

Abstract

The invention discloses a control circuit and a control method of a power factor correction circuit, and relates to the field of power converters. The control circuit comprises a current reference signal generation circuit, a current sampling circuit, a first subtracter, a first calculation unit, a current loop and a control signal generation circuit. The current reference signal generation circuit generates a current reference signal, the current sampling circuit outputs a current sampling signal, the first subtracter generates a first error signal according to the current sampling signal and the current reference signal, and the first calculation unit generates a first parameter and a second parameter according to the current reference signal. The current loop generates a current loop control signal according to the first error signal, the first parameter and the second parameter, and the control signal generation circuit generates a driving control signal according to the current loop control signal. According to the control circuit, the contradiction between the ITHD and the peak oscillation of the input current can be overcome through the gradual change control over the first parameter and the second parameter, and the problem of peak oscillation is avoided while the ITHD is improved.

Description

Technical Field

[0001] The present invention relates to the field of power converters such as server power supplies, and in particular to a control circuit and a control method of a power factor correction circuit. Background Art

[0002] Figure 1 Figure 1 shows a schematic diagram of the structure of a traditional bridge rectifier circuit. Figure 1 As shown, the input side of the bridge rectifier circuit receives alternating current AC, and the output side thereof is connected to capacitor C1, wherein the bridge rectifier circuit is composed of four diodes D1, D2, D3 and D4. When the alternating current AC is filtered by the bridge rectifier circuit and capacitor C1 and output to the load R1, the input current is seriously distorted, that is, the input current cannot follow the input voltage change, resulting in poor input current total harmonic distortion (ITHD) and power factor (PF), which seriously pollutes the power grid. Power factor correction (PFC) circuits that can effectively improve the power factor have emerged, which are divided into active PFC and passive PFC. Among them, active PFC is widely used in the field of switching power supplies. Its control circuit generates a pulse width modulation (PWM) signal through sampling signals and loop calculations to control the conduction and disconnection of the switch tube, so that the input current follows the input voltage change, thereby realizing power factor correction.

[0003] Figure 2 Figure 2 shows the schematic diagram of the classic Boost PFC circuit. Figure 2 As shown, the Boost circuit includes an inductor L2, a power switch tube Q21, a diode D21, an output capacitor C21, and a control circuit 20. One end of the inductor L2 is connected to the anode of the diode D21 and the first end of the power switch tube Q21, the cathode of the diode D21 is connected to one end of the output capacitor C21, the second end of the power switch tube Q21 is connected to the other end of the output capacitor C21, the other end of the inductor L2 is used to connect to one end of the power supply AC, the second end of the power switch tube Q21 is used to connect to the other end of the power supply AC, the output capacitor C21 is used to connect to the load R21, and the output end of the control circuit 20 is connected to the control end of the power switch tube Q21. The control circuit 20 includes a voltage outer loop and a current inner loop, wherein the voltage outer loop is a slow loop and the current inner loop is a fast loop. The voltage outer loop is used to generate a current reference signal according to the output voltage of the PFC circuit, and the current inner loop is used to generate the control signal according to the input current of the PFC and the current reference signal to control the conduction or disconnection of the power switch tube Q21. The input current changes with the input voltage by controlling the charging and discharging of the inductor L2.

[0004] However, the inductance will show different degrees of attenuation characteristics depending on the input current, that is, the larger the input current, the smaller the inductance, and the larger the corresponding hardware open-loop gain. Figure 3The relationship between the inductance and the input current is shown in Figure 2. Figure 3 As shown in the figure, when the input current is 0A, the inductance is about 620uH. As the input current increases, the inductance decreases. When the input current increases to 30A, the inductance drops to about 50uH. For the inductor L2 with a faster attenuation characteristic, the difference in gain under light load and full load conditions increases. At the same time, the gain at the input voltage peak is much greater than the gain at the input voltage zero crossing. If the constant loop parameters are still used for gain compensation, the contradiction between the input current total harmonic distortion (ITHD) and the input peak current is difficult to adjust, and the performance of high-order harmonics is also difficult to meet. In addition, for the connection to the line impedance stabilization network (LISN) and weak power grid test, the inductive device at the input end is easy to cause the secondary crossing of the PFC circuit gain curve, which in turn causes insufficient phase margin, the input current will oscillate, and the ITHD will deteriorate, especially under heavy load, which may cause damage to the PFC circuit.

[0005] Therefore, the industry urgently needs to develop a power factor correction control circuit and control method that can overcome the inherent contradiction between ITHD and input peak current oscillation, while meeting the performance requirements of weak power grids and high-order harmonics. Summary of the invention

[0006] The contradiction between ITHD and input peak current mentioned above is difficult to adjust, and high-order harmonic performance is difficult to meet.

[0007] The present invention proposes a control circuit of a power factor correction circuit, wherein the power factor correction circuit includes an inductor and a power switch tube, and the control circuit includes:

[0008] A current reference signal generating circuit, used for generating a current reference signal according to an input voltage of the power factor correction circuit, an output voltage of the power factor correction circuit, a voltage reference signal and a proportionality coefficient;

[0009] A current sampling circuit, used for sampling the input current of the power factor correction circuit and outputting a current sampling signal representing the input current;

[0010] A first subtractor, configured to generate a first error signal according to the current sampling signal and the current reference signal;

[0011] A first calculation unit, configured to generate a first parameter and a second parameter according to the current reference signal;

[0012] a current loop, configured to generate a current loop control signal according to the first error signal, the first parameter and the second parameter; and

[0013] The control signal generating circuit is used to generate a driving control signal according to the current loop control signal to control the on or off of the power switch tube.

[0014] Optionally, the current reference signal generating circuit includes:

[0015] A first voltage sampling circuit, used for sampling the output voltage of the power factor correction circuit and outputting a first voltage sampling signal representing the output voltage;

[0016] a second subtractor, configured to generate a second error signal according to the first voltage sampling signal and the voltage reference signal;

[0017] a voltage loop, configured to generate a first reference signal according to the second error signal;

[0018] A second voltage sampling signal, used for sampling the input voltage of the power factor correction circuit and outputting a second voltage sampling signal representing the input voltage;

[0019] A second calculation unit, configured to generate a second reference signal according to the second voltage sampling signal;

[0020] a first multiplier, configured to generate a third reference signal according to the second voltage sampling signal, the second reference signal and the proportional coefficient;

[0021] A second multiplier is used to generate the current reference signal according to the third reference signal and the first reference signal.

[0022] Optionally, in each power frequency cycle, the inductance of the inductor decreases as the current reference signal increases, and the inductance of the inductor increases as the current reference signal decreases, wherein when the current reference signal is a maximum value, the inductance of the inductor is a minimum value, and when the current reference signal is a minimum value, the inductance of the inductor is a maximum value.

[0023] Optionally, the waveform of the first parameter is consistent with the inductance waveform of the inductor; the waveform of the second parameter is consistent with the inductance waveform of the inductor.

[0024] Optionally, the first parameter is a first initial value minus a product of the current reference signal and a first attenuation factor.

[0025] Optionally, the second parameter is a second initial value minus a product of the current reference signal and a second attenuation factor.

[0026] Optionally, the phase angle of the current reference signal is the same as the phase angle of the input voltage of the power factor correction circuit.

[0027] The present invention also proposes another control method for a power factor correction circuit, wherein the power factor correction circuit includes an inductor and a power switch tube, and the control method includes:

[0028] Generate a current reference signal according to an input voltage of the power factor correction circuit, an output voltage of the power factor correction circuit, a voltage reference signal and a proportionality coefficient;

[0029] Sampling the input current of the power factor correction circuit and outputting a current sampling signal representing the input current;

[0030] Generate a first error signal according to the current sampling signal and the current reference signal;

[0031] generating a first parameter and a second parameter according to the current reference signal;

[0032] generating a current loop control signal according to the first error signal, the first parameter and the second parameter; and

[0033] A driving control signal is generated according to the current loop control signal to control the on or off of the power switch tube.

[0034] Optionally, in each power frequency cycle, the inductance of the inductor decreases as the current reference signal increases, and the inductance of the inductor increases as the current reference signal decreases, wherein when the current reference signal is a maximum value, the inductance of the inductor is a minimum value, and when the current reference signal is a minimum value, the inductance of the inductor is a maximum value.

[0035] Optionally, the waveform of the first parameter is consistent with the inductance waveform of the inductor; the waveform of the second parameter is consistent with the inductance waveform of the inductor.

[0036] Optionally, the first parameter is a first initial value minus a product of the current reference signal and a first attenuation factor; and the second parameter is a second initial value minus a product of the current reference signal and a second attenuation factor.

[0037] Optionally, generating a current reference signal according to an input voltage of the power factor correction circuit, an output voltage of the power factor correction circuit, a voltage reference signal and a proportionality coefficient specifically includes:

[0038] Sampling the output voltage of the power factor correction circuit and outputting a first voltage sampling signal representing the output voltage;

[0039] generating a second error signal according to the first voltage sampling signal and the voltage reference signal;

[0040] generating a first reference signal according to the second error signal;

[0041] Sampling the input voltage of the power factor correction circuit and outputting a second voltage sampling signal representing the input voltage;

[0042] generating a second reference signal according to the second voltage sampling signal;

[0043] Generate a third reference signal according to the second voltage sampling signal, the second reference signal and the proportional coefficient;

[0044] The current reference signal is generated according to the third reference signal and the first reference signal.

[0045] The present invention can achieve the following beneficial effects:

[0046] The control circuit of the present invention includes a current reference signal generating circuit, a current sampling circuit, a first subtractor, a first calculation unit, a current loop and a control signal generating circuit. The current reference signal generating circuit is used to generate a current reference signal according to the input voltage of the power factor correction circuit, the output voltage of the power factor correction circuit, a voltage reference signal and a proportional coefficient. The current sampling circuit is used to sample the input current of the power factor correction circuit and output a current sampling signal representing the input current. The first subtractor is used to generate a first error signal according to the current sampling signal and the current reference signal. The first calculation unit 33 is used to generate a first parameter and a second parameter according to the current reference signal. The current loop is used to generate a current loop control signal according to the first error signal, the first parameter and the second parameter. The control signal generating circuit is used to generate a drive control signal according to the current loop control signal to control the conduction or disconnection of the power switch tube in the power factor correction circuit. Based on the real-time calculation of the current reference signal, the first parameter and the second parameter required for different phases are fitted, the current loop response performance is improved, the high-order harmonic performance is improved, the inductor with faster attenuation characteristics can be adapted, and the production cost is reduced. By gradually controlling the first and second parameters, the contradiction between ITHD and the oscillation at the peak of the input current can be overcome, and the problem of oscillation at the peak of the input current can be avoided while improving ITHD. In addition, the test performance of its access to LISN and weak power grid is improved, the required loop gain is fitted, the phase margin of the secondary crossing is improved, and the problem of loop oscillation caused by phase loss is avoided.

[0047] The above is a fairly broad overview of the features and technical advantages of the present application, so that the following detailed description of the present application can be better understood. The additional features and advantages of the present application will be described below, and they form the subject matter of the claims of the present application. It will be appreciated by those skilled in the art that the disclosed concepts and specific embodiments can be easily utilized as the basis for modifying or designing other structures or processes for realizing the same purpose of the present application. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present application as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more fully understand the present application and its advantages, reference is now made to the following description in conjunction with the accompanying drawings:

[0049] In the figure:

[0050] Figure 1 The schematic diagram of the structure of a traditional bridge rectifier circuit is shown;

[0051] Figure 2 The schematic diagram of the structure of the classic Boost PFC circuit is shown;

[0052] Figure 3 shows the relationship between the inductance and the input current;

[0053] Figure 4 A schematic diagram showing the structure of a control circuit of a power factor correction circuit according to an embodiment of the present invention is shown;

[0055] Figure 5 The waveform diagram of the inductance and the current reference signal of the embodiment of the present invention is shown;

[0056] Figure 6 A waveform diagram of a first parameter and a second parameter of an embodiment of the present invention is shown;

[0057] Figure 7 A flow chart of a control method of a power factor correction circuit according to an embodiment of the present invention is shown.

[0058] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0059] Various exemplary embodiments, features and aspects of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0060] The word "exemplary" is used herein to mean "serving as an example, embodiment or illustration". Any embodiment described herein as "exemplary" is not necessarily to be construed as being superior or better than other embodiments. The terms "first", "second", "third", etc. (if any) in the specification and claims of the present invention and the drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence.

[0061] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "coupled", "connected", and "connected" should be understood in a broad sense. For example, it can be an electrical connection or mutual communication, it can be a direct connection, it can also be an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0062] In addition, in order to better illustrate the present invention, numerous specific details are provided in the following specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0063] As the power range of the power factor correction circuit increases, the input current will become larger, making the inductor's ability to resist attenuation poor. Figure 3 As shown, when the load is light, the inductance can be maintained. When the load increases, the inductance will decay faster, and the current loop will not adjust with the decay, resulting in oscillation at the peak value of the input current. The present invention mainly solves the problem that the inductance decays with the increase of the input current, thereby causing oscillation at the peak value of the input current.

[0064] Figure 4 FIG. 2 is a schematic diagram showing a structure of a control circuit of a power factor correction circuit according to an embodiment of the present invention. Figure 4As shown, the power factor correction circuit includes an inductor L2 and a power switch tube Q21. The input end of the power factor correction circuit is connected to the power supply AC for receiving the input voltage Vin, and the output end of the power factor correction circuit is connected to the load R21 to provide it with an output voltage Vout. The control circuit includes a current reference signal generating circuit 30, a current sampling circuit 34, a first subtractor 41, a first calculation unit 33, a current loop 35 and a control signal generating circuit 36. The current reference signal generating circuit 30 is used to generate a current reference signal Iref according to the input voltage Vin of the power factor correction circuit, the output voltage Vout of the power factor correction circuit, the voltage reference signal Vref and the proportional coefficient Km. The current sampling circuit 34 samples the input current Iin of the power factor correction circuit and outputs a current sampling signal representing the input current. The first subtractor 41 receives the current sampling signal and the current reference signal Iref respectively and generates a first error signal according to the current sampling signal and the current reference signal Iref. The first calculation unit 33 receives the current reference signal Iref and generates a first parameter and a second parameter according to the current reference signal Iref. The current loop 35 receives the first error signal, the first parameter and the second parameter, and generates a current loop control signal according to the first error signal, the first parameter and the second parameter. The first parameter and the second parameter are the current loop parameters currently required, such as kp and ki. The control signal generating circuit 36 ​​receives the current loop control signal, and generates a drive control signal, such as a PWM signal, according to the current loop control signal to control the on or off of the power switch tube Q21.

[0065] Further, the current reference signal generating circuit 30 includes a first voltage sampling circuit 31, a second subtractor 42, a voltage loop 32, a second voltage sampling circuit 43, a second calculation unit 39, a first multiplier 37 and a second multiplier 38. The first voltage sampling circuit 31 is connected to the output end of the power factor correction circuit, and is used to sample the output voltage Vout of the power factor correction circuit and output a first voltage sampling signal representing the output voltage Vout. The second subtractor 42 receives the first voltage sampling signal and the voltage reference signal Vref respectively, and generates a second error signal according to the first voltage sampling signal and the voltage reference signal Vref. The voltage loop 32 receives the second error signal and generates a first reference signal according to the second error signal. The second voltage sampling circuit 43 is connected to the input end of the power factor correction circuit, and is used to sample the input voltage Vin of the power factor correction circuit and output a second voltage sampling signal representing the input voltage Vin. The second calculation unit 39 receives the second voltage sampling signal and generates a second reference signal according to the second voltage sampling signal, wherein the second reference signal may be the reciprocal of the square of the root mean square value of the input voltage Vin. The first multiplier 37 receives the second voltage sampling signal, the second reference signal and the proportional coefficient Km respectively and generates a third reference signal according to the second voltage sampling signal, the second reference signal and the proportional coefficient Km. The second multiplier 38 receives the third reference signal and the first reference signal and generates the current reference signal Iref according to the third reference signal and the first reference signal.

[0066] In this embodiment, the first multiplier 37 and the second multiplier 38 can be replaced by one multiplier, that is, the multiplier generates the current reference signal Iref according to the received first reference signal, the second reference signal, the second voltage sampling signal and the proportional coefficient Km.

[0067] The control circuit of this embodiment can prevent the power factor correction circuit from oscillating at the peak of the input current when operating under heavy load or weak power grid conditions, and also effectively reduce the total harmonic distortion (ITHD) of the input current.

[0068] In this embodiment, the current reference signal Iref is calculated based on the first voltage sampling signal and the second voltage sampling signal sampled in real time, has the same phase angle as the input voltage Vin, and presents a sinusoidal shape within one power frequency cycle.

[0069] Figure 5 FIG. 2 shows a waveform diagram of the inductance and current reference signal of an embodiment of the present invention. Figure 5As shown, the dotted line represents the waveform of the current reference signal Iref, and the solid line represents the waveform of the inductance L of the inductor. In each power frequency cycle, the inductance L of the inductor decreases as the current reference signal Iref increases, and the inductance L of the inductor increases as the current reference signal Iref decreases, wherein when the current reference signal Iref is the maximum value, the inductance L of the inductor is the minimum value, and when the current reference signal Iref is the minimum value, the inductance L of the inductor is the maximum value, which can well fit the loop gain required by the inductor at different phases, improve the phase margin of the secondary crossing, and avoid the problem of current loop oscillation caused by phase loss.

[0070] Based on the attenuation characteristics of the inductance, the first calculation unit 33 generates a first parameter kp and a second parameter ki according to the current reference signal Iref. The first parameter kp is the first initial value A1 minus the product of the current reference signal Iref and the first attenuation factor B1, that is, Kp=A1-B1*Iref. The second parameter ki is the second initial value A2 minus the product of the current reference signal Iref and the second attenuation factor B2, that is, Kp=A2-B2*Iref. The first parameter Kp and the second parameter Ki are different values. The first initial value A1 and the second initial value A2, as well as the first attenuation factor B1 and the second attenuation factor B2 can be empirical values. The corresponding first parameter kp and the second parameter ki can be obtained by adjusting the first initial value A1 and the second initial value A2, as well as the first attenuation factor B1 and the second attenuation factor B2. In this embodiment, the required first initial value A1 and the second initial value A2, as well as the first attenuation factor B1 and the second attenuation factor B2 can be adjusted at any time according to different load specifications. Through the real-time calculation of the current reference signal Iref, the first parameter and the second parameter kp and ki required for different phases are fitted to improve the current loop response performance and the high-order harmonic performance. In addition, the control circuit can adapt to inductors with faster attenuation characteristics to reduce production costs. In this embodiment, the first initial value A1 and the second initial value A2 may be the same or different, and the first attenuation factor B1 and the second attenuation factor B2 may be the same or different. It is only necessary to ensure that the first parameter Kp and the second parameter Ki are different values. The values ​​of the first initial value A1 and the second initial value A2, as well as the first attenuation factor B1 and the second attenuation factor B2 are selected according to actual needs.

[0071] Figure 6 FIG. 2 shows a waveform diagram of the first parameter and the second parameter of an embodiment of the present invention. Figure 6As shown, the waveform of the first parameter kp is consistent with the waveform of the inductance L of the inductor; the waveform of the second parameter ki is consistent with the waveform of the inductance L of the inductor. It can be seen that when the input current reaches a peak value, the first parameter kp and the second parameter ki are adjusted to a smaller value, so that the loop response becomes slower, ensuring that there is no oscillation problem at the peak value of the input current. When the input current is at a minimum, the first parameter kp and the second parameter ki are adjusted to a larger value, so that the loop response becomes faster, and a good power factor correction can be achieved. The first calculation unit 33 realizes a gradual control of the first parameter kp and the second parameter ki through the current reference signal Iref, which avoids the oscillation problem at the peak value of the input current Iin while improving ITHD, and is also well adapted to applications with a larger power range.

[0072] In this embodiment, if Figure 4 As shown, the power factor correction circuit is explained by taking the Boost circuit as an example. The Boost circuit includes an inductor L2, a power switch tube Q21, a diode D21, an output capacitor C21 and a control circuit. One end of the inductor L2 is connected to the anode of the diode D21 and the first end of the power switch tube Q21, the cathode of the diode D21 is connected to one end of the output capacitor C21, the second end of the power switch tube Q21 is connected to the other end of the output capacitor C21 and one end of the power supply AC, and the other end of the inductor L2 is used to connect the other end of the power supply AC. The output end of the control circuit is connected to the control end of the power switch tube Q21 to control the conduction or disconnection of the power switch tube Q21. It should be noted that the power factor correction circuit is not limited to the Boost circuit, and can also be other topological structures including inductors and power switch tubes, which will not be illustrated one by one here.

[0073] In this embodiment, the first calculation unit 33 generates the first parameter kp and the second parameter ki according to the current reference signal Iref, wherein the first parameter kp and the second parameter ki are gradual, and the current loop gain required by the inductor at different phases can be fitted, the loop response performance can be improved, the high-order harmonic performance can be improved, and at the same time, the inductor with faster attenuation characteristics can be adapted to reduce costs, and the oscillation problem at the peak of the input current can be avoided while improving ITHD.

[0074] Figure 7 FIG. 2 is a flow chart showing a control method of a power factor correction circuit according to an embodiment of the present invention. Figure 7 As shown, the present invention provides another control method for a power factor correction circuit, wherein the power factor correction circuit includes an inductor and a power switch tube, and the control method includes:

[0075] Step S71: Generate a current reference signal according to the input voltage of the power factor correction circuit, the output voltage of the power factor correction circuit, a voltage reference signal and a proportionality coefficient.

[0076] Specifically, Figure 4 As shown, the current reference signal generating circuit 30 is used to generate a current reference signal Iref according to the input voltage Vin of the power factor correction circuit, the output voltage Vout of the power factor correction circuit, the voltage reference signal Vref and the proportionality coefficient Km.

[0077] Step S72: sampling the input current of the power factor correction circuit and outputting a current sampling signal representing the input current.

[0078] Specifically, Figure 4 As shown, the current sampling circuit 34 samples the input current Iin of the power factor correction circuit and outputs a current sampling signal representing the input current.

[0079] Step S73: Generate a first error signal according to the current sampling signal and the current reference signal.

[0080] Specifically, Figure 4 As shown, the first subtractor 41 receives the current sampling signal and the current reference signal Iref respectively and generates a first error signal according to the current sampling signal and the current reference signal Iref.

[0081] Step S74: generating a first parameter and a second parameter according to the current reference signal.

[0082] Specifically, Figure 4 As shown, the first calculation unit 33 receives the current reference signal Iref, and generates a first parameter kp and a second parameter ki according to the current reference signal Iref.

[0083] Step S75: generating a current loop control signal according to the first error signal, the first parameter and the second parameter.

[0084] Specifically, Figure 4 As shown, the current loop 35 receives the first error signal, the first parameter kp and the second parameter ki, and generates a current loop control signal according to the first error signal, the first parameter and the second parameter.

[0085] Step S76: Generate a drive control signal according to the current loop control signal to control the on or off of the power switch tube.

[0086] Specifically, Figure 4 As shown, the control signal generating circuit 36 ​​receives the current loop control signal, and generates a driving control signal, such as a PWM signal, according to the loop control signal to control the on or off of the power switch tube.

[0087] The control circuit of this embodiment can prevent the power factor correction circuit from oscillating at the peak of the input current when operating under heavy load or weak power grid conditions, and also effectively reduce the total harmonic distortion (ITHD) of the input current.

[0088] In this embodiment, the current reference signal Iref is calculated based on the first voltage sampling signal and the second voltage sampling signal sampled in real time, has the same phase angle as the input voltage Vin, and presents a sinusoidal shape within one power frequency cycle.

[0089] Further, if Figure 5 As shown, in each power frequency cycle, the inductance L of the inductor decreases as the current reference signal Iref increases, and the inductance L of the inductor increases as the current reference signal Iref decreases, wherein when the current reference signal Iref is the maximum value, the inductance L of the inductor is the minimum value, and when the current reference signal Iref is the minimum value, the inductance L of the inductor is the maximum value, which can well fit the loop gain required by the inductor at different phases, improve the phase margin of the secondary crossing, and avoid the problem of phase loss causing the current loop 35 to oscillate.

[0090] Further, based on the attenuation characteristics of the inductance, the first calculation unit 33 generates a first parameter kp and a second parameter ki according to the current reference signal Iref. The first parameter kp is the product of the current reference signal Iref and the first attenuation factor B1 minus the first initial value A1, that is, Kp=A1-B1*Iref. The second parameter ki is the product of the current reference signal Iref and the second attenuation factor B2 minus the second initial value A2, that is, Kp=A2-B2*Iref. The first parameter Kp and the second parameter Ki can be different values. The first initial value A1 and the second initial value A2, as well as the first attenuation factor B1 and the second attenuation factor B2 can be empirical values. By adjusting the first initial value A1 and the second initial value A2, as well as the first attenuation factor B1 and the second attenuation factor B2, the corresponding kp and ki can be obtained. In this embodiment, the required first initial value A1 and the second initial value A2, as well as the first attenuation factor B1 and the second attenuation factor B2 can also be adjusted at any time according to different load specifications. Through the real-time calculation of the current reference signal Iref, the first parameter and the second parameter kp and ki required for different phases are fitted to improve the current loop response performance and the high-order harmonic performance. In addition, the control circuit can adapt to inductors with faster attenuation characteristics to reduce production costs. In this embodiment, the first initial value A1 and the second initial value A2 may be the same or different, and the first attenuation factor B1 and the second attenuation factor B2 may be the same or different. It is only necessary to ensure that the first parameter Kp and the second parameter Ki can be different values. The values ​​of the first initial value A1 and the second initial value A2, as well as the first attenuation factor B1 and the second attenuation factor B2 are selected according to actual needs.

[0091] Further, generating a current reference signal according to the input voltage of the power factor correction circuit, the output voltage of the power factor correction circuit, the voltage reference signal and the proportional coefficient specifically includes:

[0092] Step S710: sampling the output voltage of the power factor correction circuit and outputting a first voltage sampling signal representing the output voltage.

[0093] Specifically, Figure 4 As shown, the first voltage sampling circuit 31 is connected to the output end of the power factor correction circuit, and is used to sample the output voltage Vout of the power factor correction circuit and output a first voltage sampling signal representing the output voltage Vout.

[0094] Step S711: Generate a second error signal according to the first voltage sampling signal and the voltage reference signal.

[0095] Specifically, Figure 4As shown, the second subtractor 42 receives the first voltage sampling signal and the voltage reference signal Vref respectively, and generates a second error signal according to the first voltage sampling signal and the voltage reference signal Vref.

[0096] Step S712: Generate a first reference signal according to the second error signal.

[0097] Specifically, Figure 4 As shown, the voltage loop 32 receives the second error signal and generates a first reference signal according to the second error signal.

[0098] Step S713: sampling the input voltage of the power factor correction circuit and outputting a second voltage sampling signal representing the input voltage.

[0099] Specifically, Figure 4 As shown, the second voltage sampling circuit 43 is connected to the input end of the power factor correction circuit, and is used to sample the input voltage Vin of the power factor correction circuit and output a second voltage sampling signal representing the input voltage Vin.

[0100] Step S714: Generate a second reference signal according to the second voltage sampling signal.

[0101] Specifically, Figure 4 As shown, the second calculation unit 39 receives the second voltage sampling signal and generates a second reference signal according to the second voltage sampling signal, wherein the second reference signal may be the inverse of the square of the root mean square value of the input voltage Vin.

[0102] Step S715: Generate a third reference signal according to the second voltage sampling signal, the second reference signal and the proportional coefficient.

[0103] Specifically, Figure 4 As shown, the first multiplier 37 receives the second voltage sampling signal, the second reference signal and the proportional coefficient Km respectively and generates a third reference signal according to the second voltage sampling signal, the second reference signal and the proportional coefficient Km.

[0104] Step S716: Generate the current reference signal according to the third reference signal and the first reference signal.

[0105] Specifically, Figure 4 As shown, the second multiplier 38 receives the third reference signal and the first reference signal and generates the current reference signal Iref according to the third reference signal and the first reference signal.

[0106] Further, if Figure 6As shown, the waveform of the first parameter kp is consistent with the waveform of the inductance L of the inductor; the waveform of the second parameter ki is consistent with the waveform of the inductance L of the inductor. The first parameter kp and the second parameter ki are gradually controlled by the current reference signal Iref, so that the oscillation problem at the peak of the input current Iin is avoided while improving ITHD.

[0107] In this embodiment, the first calculation unit 33 generates the first parameter kp and the second parameter ki according to the current reference signal Iref, wherein the first parameter kp and the second parameter ki are gradual, and the current loop gain required by the inductor at different phases can be fitted, the loop response performance can be improved, the high-order harmonic performance can be improved, and at the same time, the inductor with faster attenuation characteristics can be adapted to reduce costs, and the oscillation problem at the peak of the input current can be avoided while improving ITHD.

[0108] Although the embodiments of the present application and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application as defined by the appended claims.

[0109] In addition, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, modes, methods, and steps described in this specification. Those skilled in the art will readily understand from the disclosure of the present application that, according to the present application, currently existing or later to be developed processes, machines, manufactures, material compositions, modes, methods, or steps that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein may be utilized. Therefore, it is intended that the appended claims include such processes, machines, manufactures, material compositions, modes, methods, or steps within their scope.

Claims

1. A control circuit of a power factor correction circuit, the power factor correction circuit comprising an inductor and a power switch tube, characterized in that: The control circuit comprises: A current reference signal generating circuit, used for generating a current reference signal according to an input voltage of the power factor correction circuit, an output voltage of the power factor correction circuit, a voltage reference signal and a proportionality coefficient; A current sampling circuit, used for sampling the input current of the power factor correction circuit and outputting a current sampling signal representing the input current; A first subtractor, configured to generate a first error signal according to the current sampling signal and the current reference signal; A first calculation unit, configured to generate a first parameter and a second parameter according to the current reference signal; a current loop, configured to generate a current loop control signal according to the first error signal, the first parameter and the second parameter; and The control signal generating circuit is used to generate a driving control signal according to the current loop control signal to control the on or off of the power switch tube.

2. The control circuit of the power factor correction circuit according to claim 1, characterized in that: The current reference signal generating circuit comprises: A first voltage sampling circuit, used for sampling the output voltage of the power factor correction circuit and outputting a first voltage sampling signal representing the output voltage; a second subtractor, configured to generate a second error signal according to the first voltage sampling signal and the voltage reference signal; a voltage loop, configured to generate a first reference signal according to the second error signal; A second voltage sampling signal, used for sampling the input voltage of the power factor correction circuit and outputting a second voltage sampling signal representing the input voltage; A second calculation unit, configured to generate a second reference signal according to the second voltage sampling signal; a first multiplier, configured to generate a third reference signal according to the second voltage sampling signal, the second reference signal and the proportional coefficient; A second multiplier is used to generate the current reference signal according to the third reference signal and the first reference signal.

3. The control circuit of the power factor correction circuit according to claim 1, characterized in that: In each power frequency cycle, the inductance of the inductor decreases as the current reference signal increases, and the inductance of the inductor increases as the current reference signal decreases, wherein when the current reference signal is a maximum value, the inductance of the inductor is a minimum value, and when the current reference signal is a minimum value, the inductance of the inductor is a maximum value.

4. The control circuit of the power factor correction circuit according to claim 3, characterized in that: The waveform of the first parameter is consistent with the inductance waveform of the inductor; the waveform of the second parameter is consistent with the inductance waveform of the inductor.

5. The control circuit of the power factor correction circuit according to claim 1, characterized in that: The first parameter is a first initial value minus a product of the current reference signal and a first attenuation factor.

6. The control circuit of the power factor correction circuit according to claim 1, characterized in that: The second parameter is a second initial value minus a product of the current reference signal and a second attenuation factor.

7. The control circuit of the power factor correction circuit according to claim 1, characterized in that: The phase angle of the current reference signal is the same as the phase angle of the input voltage of the power factor correction circuit.

8. A control method for a power factor correction circuit, wherein the power factor correction circuit comprises an inductor and a power switch tube, characterized in that: The control method comprises: Generate a current reference signal according to an input voltage of the power factor correction circuit, an output voltage of the power factor correction circuit, a voltage reference signal and a proportionality coefficient; Sampling the input current of the power factor correction circuit and outputting a current sampling signal representing the input current; Generate a first error signal according to the current sampling signal and the current reference signal; generating a first parameter and a second parameter according to the current reference signal; generating a current loop control signal according to the first error signal, the first parameter and the second parameter; and A driving control signal is generated according to the current loop control signal to control the on or off of the power switch tube.

9. The control method of the power factor correction circuit according to claim 8, characterized in that: In each power frequency cycle, the inductance of the inductor decreases as the current reference signal increases, and the inductance of the inductor increases as the current reference signal decreases, wherein when the current reference signal is a maximum value, the inductance of the inductor is a minimum value, and when the current reference signal is a minimum value, the inductance of the inductor is a maximum value.

10. The control method of the power factor correction circuit according to claim 9, characterized in that: The waveform of the first parameter is consistent with the inductance waveform of the inductor; the waveform of the second parameter is consistent with the inductance waveform of the inductor.

11. The control method of the power factor correction circuit according to claim 8, characterized in that: The first parameter is a first initial value minus a product of the current reference signal and a first attenuation factor; the second parameter is a second initial value minus a product of the current reference signal and a second attenuation factor.

12. The control method of the power factor correction circuit according to claim 8, characterized in that: Generating a current reference signal according to the input voltage of the power factor correction circuit, the output voltage of the power factor correction circuit, a voltage reference signal and a proportional coefficient specifically includes: Sampling the output voltage of the power factor correction circuit and outputting a first voltage sampling signal representing the output voltage; generating a second error signal according to the first voltage sampling signal and the voltage reference signal; generating a first reference signal according to the second error signal; Sampling the input voltage of the power factor correction circuit and outputting a second voltage sampling signal representing the input voltage; generating a second reference signal according to the second voltage sampling signal; Generate a third reference signal according to the second voltage sampling signal, the second reference signal and the proportional coefficient; The current reference signal is generated according to the third reference signal and the first reference signal.

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