Active discharge control in fail-safe states

Abstract

An inverter circuit includes: a first phase circuit, the first phase circuit including: a first transistor; a first gate driver configured to control the first transistor; a second transistor connected in series with the first transistor; and a second gate driver configured to control the second transistor; a microcontroller unit (MCU) configured to generate a first control signal and a second control signal to control operations of the first gate driver and the second gate driver, respectively; and a power management circuit configured to: detect a fault in operation of the MCU; and generate a third control signal and a fourth control signal to control the operation of the first gate driver and the second gate driver when the fault in the operation of the MCU is detected, thereby controlling the discharging of the charging capacitor.

Description

Technical Field

[0001] Various exemplary embodiments disclosed herein relate to active discharge control in fail-safe conditions of inverters and other systems. Background Art

[0002] In electric vehicles, inverters are used that include a direct current (DC) link that includes charged capacitors. When the system is powered off or placed in a safe state, the capacitors need to be discharged. These systems may be subject to time requirements for capacitor discharge: for example, 2s. Summary of the invention

[0003] A summary of various exemplary embodiments is presented below.

[0004] Various embodiments relate to an inverter circuit, comprising: a first phase circuit, the first phase circuit comprising: a first transistor; a first gate driver, which is configured to control the first transistor; a second transistor, which is connected in series with the first transistor; and a second gate driver, which is configured to control the second transistor; a microcontroller unit (MCU), the MCU is configured to generate a first control signal and a second control signal to control the operation of the first gate driver and the second gate driver, respectively, wherein the first control signal and the second control signal are configured to control the discharge of a charging capacitor connected to the first phase circuit; and a power management circuit, the power management circuit is configured to: detect a fault in the operation of the MCU; and generate a third control signal and a fourth control signal to control the operation of the first gate driver and the second gate driver when a fault in the operation of the MCU is detected, thereby controlling the discharge of the charging capacitor.

[0005] Various embodiments are described wherein the power management circuit is configured to send a third control signal to the first gate driver and the second gate driver to indicate a failure of the MCU.

[0006] Various embodiments are described wherein the second gate driver is configured to turn on the second transistor when the third control signal indicates a failure of the MCU.

[0007] Various embodiments are described in which the power management circuit is configured to send a fourth control signal to the first gate driver having an entry mode indicating a start of discharge of the charging capacitor.

[0008] Various embodiments are described wherein the entry mode is signaled after a first delay time period following an indication of a failure of the MCU.

[0009] Various embodiments are described in which the first delay period is configurable.

[0010] Various embodiments are described wherein the first gate driver is configured to drive the first transistor with a pulse width modulated signal after the first gate driver receives a fourth control signal having an entry mode.

[0011] Various embodiments are described wherein the power management circuit is configured to send a fourth control signal having an exit mode indicating an end of discharge of a charging capacitor to the first gate driver after a second delay time, wherein the exit mode is different from the entry mode.

[0012] Various embodiments are described wherein entering the mode comprises a first number of pulses and exiting the mode comprises a second number of pulses.

[0013] Various embodiments are described wherein the second delay time is configurable.

[0014] Various embodiments are described wherein the MCU is configured to override the third control signal and the fourth control signal when asserted by the power management circuit.

[0015] Various embodiments are described, additionally including: a second phase circuit, the second phase circuit including: a third transistor; a third gate driver configured to control the third transistor; a fourth transistor connected in series with the third transistor; and a fourth gate driver configured to control the fourth transistor; wherein the first control signal and the second control signal are configured to control the operation of the third gate driver and the fourth gate driver, respectively, and wherein the third control signal and the fourth control signal are configured to control the operation of the third gate driver and the fourth gate driver to control the discharge of the charging capacitor when a fault in the operation of the MCU is detected.

[0016] Various other embodiments relate to an inverter circuit comprising: first, second and third phase circuits, wherein each phase circuit comprises: a first transistor; a first gate driver configured to control the first transistor; a second transistor connected in series with the first transistor; a second gate driver configured to control the second transistor; a microcontroller unit (MCU) configured to generate a first control signal and a second control signal to control operations of the first gate driver and the second gate driver, respectively, wherein the first control signal and the second control signal are configured to control the discharge of a charging capacitor connected to the first phase circuit; and a power management circuit configured to: detect a fault in the operation of the MCU; and generate a third control signal and a fourth control signal to control operations of the first gate driver and the second gate driver when a fault in the operation of the MCU is detected, thereby controlling the discharge of the charging capacitor.

[0017] Various embodiments are described in which the power management circuit is configured to send a third control signal to the first gate driver and the second gate driver to indicate a failure of the MCU.

[0018] Various embodiments are described wherein the second gate driver is configured to turn on the second transistor when the third control signal indicates a failure of the MCU.

[0019] Various embodiments are described in which the power management circuit is configured to send a fourth control signal to the first gate driver having an entry mode indicating a start of discharge of the charging capacitor.

[0020] Various embodiments are described wherein the entry mode is signaled after a first delay time period following an indication of a failure of the MCU.

[0021] Various embodiments are described wherein the first gate driver is configured to drive the first transistor with a pulse width modulated signal after the first gate driver receives a fourth control signal having an entry mode.

[0022] Various embodiments are described wherein the power management circuit is configured to send a fourth control signal having an exit mode indicating an end of discharge of a charging capacitor to the first gate driver after a second delay time, wherein the exit mode is different from the entry mode.

[0023] Various embodiments are described wherein the MCU is configured to override the third control signal and the fourth control signal when asserted by the power management circuit.

[0024] The foregoing has been fairly extensively summarized according to the features and technical advantages of the examples of the present disclosure so that the following specific embodiments can be better understood. Additional features and advantages will be described below. The disclosed concepts and specific examples can be easily used as the basis for modifying or designing other structures for the same purpose of implementing the present disclosure. Such equivalent constructions do not deviate from the scope of the appended claims. When considered in conjunction with the accompanying drawings, the characteristics of the concepts disclosed herein (both their organization and method of operation) together with the associated advantages will be better understood from the following description. Each of the figures is provided for the purpose of illustration and description and is not intended to define the limits of the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order that the above-mentioned features of the present disclosure may be understood in detail, a more specific description briefly summarized above may be made by reference to various aspects, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show certain typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure, as the specification may allow for other equally effective aspects. The same reference numerals in different figures may identify the same or similar elements.

[0026] Figure 1 An inverter is shown for use with an electric motor.

[0027] Figure 2 An embodiment of an inverter taking into account a failure of an MCU is shown.

[0028] Figure 3 The control signals for entering and exiting the discharge mode are shown.

[0029] Figure 4 An example of a DC link entry mode is shown.

[0030] Figure 5 An example of a DC link exit mode is shown. DETAILED DESCRIPTION

[0031] Various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to any specific structure or function presented throughout the present disclosure. In fact, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings herein, those skilled in the art should understand that the scope of the present disclosure is intended to cover any aspect of the present disclosure disclosed herein, whether implemented independently of any other aspect of the present disclosure or implemented in combination with it. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover this device or method practiced using other structures, functionality, or structure and functionality other than the various aspects of the present disclosure set forth herein or different from the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the present disclosure disclosed herein can be embodied by one or more elements of the claims.

[0032] Several aspects of methods and systems for active discharge control during a fail-safe state will now be presented with reference to various devices and techniques. These devices and techniques will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using hardware, software, or a combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0033] An electric vehicle (EV) may include an inverter with three phases to drive an electric motor. The inverter may include a DC link with a charging capacitor that collects energy and then provides the energy to the electric motor as needed during operation. When the inverter is to be placed in a safe state or powered off, this charging capacitor needs to be discharged to prevent the risk of electric shock. Various regulatory agencies have set regulations that specify the discharge time of this charging capacitor when the system is shut down or enters a safe state. For example, this time can be 2s to avoid electric shock. Today, this discharge is achieved by expensive and large passive components (large resistors and switches controlled by a microcontroller unit (MCU)), or by MCU pulse width modulation (PWM) control of the three branches of the inverter through gate drivers. The problem with these solutions is that if the MCU or logic controller fails, the active DC link discharge cannot be activated, and then the system maintains a high voltage (HV) potential on the charging capacitor, and this leads to a dangerous situation in which the charging capacitor continues to hold a charge, which prevents the system from entering a safe state.

[0034] A discharge control system and method are disclosed herein, which use existing features of gate drivers to implement discharge, even when the MCU is no longer working. The inverter includes a system basis chip (SBC), which is a power management circuit that supplies power to the MCU and gate driver. It may also include other logic. In the case where some intelligent logic is integrated in the SBC and when an MCU fault or failure is detected, the SBC can set all high-side (HS) gate drivers to discharge mode (where the gate driver can automatically select the gate voltage to limit the discharge current by acting as a resistor), while all low-side (LS) gate drivers are turned on. Because this is done on all branches of the inverter, each branch in the branch experiences a lower current and also provides increased fault tolerance. In other embodiments, the LS transistor can be set to act as a resistor and the HS transistor is always turned on. If necessary, the SBC can directly control the gate driver to activate the DC link discharge mode after a delay.

[0035] When the SBC detects a microcontroller failure, the SBC will then begin forcing an active short circuit during a preprogrammed duration to release motor energy, and then automatically send a dedicated mode signal to the gate driver to enter discharge mode. To maintain safety while the battery contactor is still closed, the SBC may also have a preprogrammed maximum duration to exit the DC link discharge, and will send the exit mode to the gate driver to ensure that the discharge is terminated.

[0036] Figure 1An inverter for use with an electric motor is shown. The inverter 100 includes an SBC 102, an MCU 104, a phase U 114, a phase V 116, a phase W 118, and a charging capacitor 126. The inverter 100 is connected to a +DC link 128 and a -DC link 130. Each phase of the inverter 100 includes two gate drivers 120, as well as a HS drive transistor 122 and a LS drive transistor 124. The MCU 104 may include an interface 106 connected to each of the gate drivers 120. The MCU 104 generates control signals including a HS control signal 108, a LS control signal 110, and a PWM control signal 112. The HS control signal 108 and the LS control signal 110 are used to turn on and off the HS drive transistor 122 and the LS drive transistor 124, respectively. In addition, the PWM control signal 112 can be used to control the on and off time of the LS drive transistor 124. The SBC 102 is a power management integrated circuit that supplies power to the MCU and the gate drivers.

[0037] During normal operation, the MCU 104 provides a control signal to the gate driver 120 to control the state of the HS drive transistor 122 and the LS drive transistor 124 in sequence to drive the electric motor. During this operation, the charging capacitor 126 can store and release energy to drive the electric motor. When the MCU 104 receives a command to place the inverter in a safe state, there may be a charge remaining on the charging capacitor 126. As described above, this charging capacitor 126 needs to be discharged safely and quickly to prevent harm to personnel. This can be achieved by the MCU 104 supplying the HS PWM control signal 108 to close the HS drive transistor 122. Then, the MCU 104 also applies a signal 112 to the LS drive transistor 124 to enable the DC link discharge mode, so that the LS drive transistor 124 acts as a resistor to discharge and dissipate the charge on the charging capacitor 126. PWM is used to control the LS drive transistor 124 so as to control the discharge rate of the charging capacitor 126, and thereby limit the current flowing through the different phases of the inverter 100. It should be noted that all three phases of the inverter 100 can be used to dissipate the charge on the charging capacitor 126. As a result, the amount of current handled by each phase is reduced. In addition, the use of all three phases provides redundant discharge capability, allowing discharge to occur even if one of the phases fails. In alternative embodiments, fewer phases (including one phase) can be used to discharge the charging capacitor 126. Moreover, in alternative embodiments, the HS drive transistor 122 can act as a resistor controlled by the PWM control signal 112, and the LS drive transistor 124 can be a switch that is disconnected during the discharge mode.

[0038] Figure 1A problem with the inverter 100 is that if the MCU 104 fails, the inverter 100 cannot perform a safe discharge of the charging capacitor 126 . Figure 2 An embodiment of an inverter taking into account a failure of an MCU is shown. Figure 2 The inverter 200 includes Figure 1 1. The inverter 200 will include the same gate driver 120, HS drive transistor 122, and LS drive transistor 124 as the inverter 100 in FIG. 1. The inverter 200 will include an SBC 202, which includes additional functionality to provide control signals to the gate driver 120 to perform the discharge of the charging capacitor 126. The MCU 204 may be the same as the MCU 104 or may be different so as to provide an interface to the SBC 202 to detect failures of the MCU 204.

[0039] The SBC 202 may have two outputs, DCLINK_OUT and FSOB, which output signals FSSTATE HS control signal 232 and FSENB control signal 234, respectively. The FSSTATE HS control signal 232 is provided to the HS gate driver 120. The FSSTATE HS control signal 232 may be used to control the operation of the HS driver transistor 122 when the MCU 204 experiences a fault. The FSENB control signal 234 is provided to the HS gate driver 120 to indicate that the HS gate driver 120 should use the input signal FSSTATE HS control signal 232 to control the HS driver transistor 122. The FSENB control signal 234 is also provided to the LS gate driver 120 to indicate that the LS gate driver 120 should use the input signal FSSTATE LS control signal 236 to control the LS driver transistor 124. The FSSTATE LS control signal 236 may simply remain in a state (a high state in this example) that will indicate that the LS gate driver 120 should close the LS driver transistor 124.

[0040] Typically, the SBC 202 monitors the operation of the MCU 204. This monitoring can be used to determine whether the MCU 204 has failed. For example, the SBC 202 can use a watchdog signal and protocol to determine whether the MCU 204 has failed. In addition, the MCU 204 can output an error code indicating that the operation of the MCU 204 has failed in some way. In another example, the MCU 204 can have the ability to detect the presence of the FSSTATE HS control signal 232 and the FSENB control signal 234, and the MCU 204 can override these signals by sending an override control signal to the gate driver 120. And, at the gate driver 120, the control signal from the MCU 104 can have a higher priority than the control signal from the SBC 102. Due to this functionality, the SBC 202 may occasionally send the FSSTATE HS control signal 232 and the FSENB control signal 234 signals and determine whether they are aborted by the MCU 204. If so, the MCU 204 is operating properly, and if not, the MCU 204 is not operating properly.

[0041] Figure 3 204 , the control signals for entering and exiting the discharge mode are shown. Sometimes, the SBC 202 detects an MCU fault 302. When the MCU 204 fails, the FSENB control signal 234 changes from high to low (it should be noted that this logic can also be reversed). And at this time, the FSSTATE HS control signal 232 remains low (it should be noted that this logic can also be reversed). As a result, the inverter 100 enters an initial delay phase 304 of operation. This initial delay phase 304 can be configurable and can be on the order of a few ms to hundreds of ms to a few seconds depending on the specific application and requirements. This initial delay can be set to allow the electric motor driven by the inverter 100 to stop completely. During the initial delay phase 304, the phase is set to be in an active short circuit by turning on the LS drive transistor 124 and turning off the HS drive transistor 122. In addition, during this initial delay phase 302, the MCU 204 can override or abort any control signal output by the SBC 202 that will cause the inverter 100 to enter the discharge mode.

[0042] After the initial delay phase 304, the inverter 100 enters the discharge entry phase 306. During the discharge entry phase 306, the FSSTATE HS control signal 232 transmits the DC link entry mode 312. The DC link entry mode 312 is the only signal indicating that the inverter is entering the discharge phase. The mode is selected so that random noise or other unintentional signals do not accidentally start the discharge phase of the inverter 100. Figure 4An example of a DC link entry pattern 312 is shown. In this case, it is a series of 8 pulses with specific timing. The duty cycle is shown as 50% with a period of 1 μs. Other duty cycles, periods, number of pulses, and patterns may also be used as long as the DC link entry pattern 312 is unique and resistant to random noise. Additionally, the pattern selection may be made based on filtering of the signal at the gate driver 120.

[0043] After the discharge entry phase 306, the discharge phase 308 begins in response to the DC link entry mode 312. During the discharge phase 308, the LS drive transistor 124 is turned on, and the HS drive transistor 122 is driven by the PWM signal to discharge the charging capacitor 126. PWM is used to cause a controlled discharge of the charging capacitor 126 so that the amount of current flowing through the HS drive transistor 122 and the LS drive transistor 124 is controlled and limited. At this time, the HS drive transistor 122 acts as a resistor to dissipate the energy released from the charging capacitor 126. In addition, the length of the discharge phase 308 can be configurable. The length of the discharge phase 308 can be set to meet any discharge requirements that may be imposed on the inverter 100. And, the length of the discharge phase 308 is a configurable timeout that limits the length of the discharge mode.

[0044] After the discharge phase 308, the inverter 100 enters the discharge exit phase 310. During the discharge exit phase 310, the FSSTATE HS control signal 232 transmits a DC link exit mode 314. The DC link exit mode 314 is the only signal indicating that the inverter is exiting the discharge phase. The mode is selected so that random noise or other unintentional signals do not accidentally initiate the discharge phase of the inverter 100. Figure 5 An example of a DC link exit pattern 314 is shown. In this case, it is a series of 4 pulses with specific timing. The duty cycle is shown as 50% with a period of 1 μs. Other duty cycles, periods, number of pulses, and patterns may also be used as long as the DC link exit pattern 314 is unique and resistant to random noise. Additionally, the pattern selection may be made based on filtering of the signal at the gate driver 120.

[0045] In the above description, the HS driver transistor 122 is driven by the PWM signal during the discharge phase 308, and the LS driver transistor 124 is driven by a constant value to be turned on. In other embodiments, this may be reversed, i.e., the LS driver transistor 124 is driven by the PWM signal during the discharge phase 308, and the HS driver transistor 122 is driven by a constant value to be turned on.

[0046] in addition, Figure 2The embodiment of FIG. 1 shows that all three phases are used to discharge the charging capacitor 126. It is also possible to use only two phases to spread the current discharge and provide some redundancy in case one of the phases fails during the discharge phase. Even only one phase can be used as long as it can handle the maximum discharge current and the system can tolerate no redundancy in the discharge system. In addition, the inverter 100 can also have more than three phases, and then any number of these phases can be used to discharge the charging capacitor 126.

[0047] Although Figure 2 The embodiments are described as being applied to electric motors, but the embodiments may also be used in other phasing systems.

[0048] The above disclosure provides illustration and description, but is not intended to be exhaustive or to limit the aspects to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure, or may be acquired from practice of the various aspects.

[0049] As used herein, the term "component" is intended to be broadly interpreted as hardware, firmware, and / or a combination of hardware and software. As used herein, a processor is implemented in hardware, firmware, and / or a combination of hardware and software.

[0050] As used herein, satisfying a threshold value may refer to a value being greater than a threshold value, greater than or equal to a threshold value, less than a threshold value, less than or equal to a threshold value, equal to a threshold value, not equal to a threshold value, etc., depending on the context. It will be apparent that the systems and / or methods described herein may be implemented in various forms of hardware, firmware, and / or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods does not limit the aspects. Thus, the operation and behavior of the systems and / or methods are described herein without reference to specific software code - it should be understood that software and hardware may be designed to implement the systems and / or methods based, at least in part, on the description herein.

[0051] As used herein, the term "non-transitory machine-readable storage medium" will be understood to exclude transitory propagating signals but include all forms of volatile and non-volatile memory. When software is implemented on a processor, the combination of software and processor becomes a specific special purpose machine.

[0052] Because the data processing to implement the embodiments described herein is largely comprised of electronic components and circuits known to those skilled in the art, circuit details will not be explained to any greater extent than deemed necessary as described above in order to understand and appreciate the basic concepts of the aspects described herein and in order not to confuse or deviate from the teachings of the aspects described herein.

[0053] Unless otherwise stated, terms such as "first" and "second," etc., are used to arbitrarily distinguish between the elements such terms describe. Therefore, these terms are not necessarily intended to indicate temporal or other priority of such elements.

[0054] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative hardware embodying the principles of the various aspects.

[0055] Although each of the embodiments is described above in terms of its structural arrangement, it should be understood that the aspects also encompass the associated methods of using the above-described embodiments.

[0056] Although the specific combination of features is described in the claims and / or disclosed in this specification, these combinations are not intended to limit the disclosure of various aspects. In fact, many of these features can be combined in a manner that is not specifically described in the claims and / or disclosed in the specification. Although each dependent claim listed below can directly depend on only one claim, the disclosure of various aspects includes each dependent claim in combination with each other claim in the claim set. The phrase "at least one" mentioned in the list of items refers to any combination of these items, including single members. As an example, "at least one of the following: a, b or c" is intended to cover a, b, c, ab, ac, bc and abc, and any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc and ccc, or any other ordering of a, b and c).

[0057] Unless so clearly described, the elements, actions or instructions used herein should not be interpreted as critical or necessary. And, as used herein, the article "one" is intended to include one or more items and can be used interchangeably with "one or more". In addition, as used herein, the terms "set" and "group" are intended to include one or more items (e.g., related items, unrelated items, combinations of related items and unrelated items, etc.), and can be used interchangeably with "one or more". In the case of only one item expected, the phrase "only one" or similar language is used. And, as used herein, the terms "has", "have", "having" and / or similar terms are intended to be open terms. In addition, unless otherwise clearly stated, the phrase "based on" is intended to mean "based at least in part on".

Claims

1. An inverter circuit, characterized in that: include: A first phase circuit, the first phase circuit comprising: a first transistor; a first gate driver configured to control the first transistor; a second transistor connected in series with the first transistor; and a second gate driver configured to control the second transistor; a microcontroller unit (MCU) configured to generate a first control signal and a second control signal to control operations of the first gate driver and the second gate driver, respectively, wherein the first control signal and the second control signal are configured to control the discharge of a charging capacitor connected to the first phase circuit; and A power management circuit, the power management circuit being configured to: detecting a fault in the operation of the MCU; and A third control signal and a fourth control signal are generated to control the operation of the first gate driver and the second gate driver when the failure in the operation of the MCU is detected, thereby controlling the discharge of the charging capacitor.

2. The inverter circuit according to claim 1, characterized in that: The power management circuit is configured to send the third control signal to the first gate driver and the second gate driver to indicate the fault of the MCU.

3. The inverter circuit according to claim 2, characterized in that: The second gate driver is configured to turn on the second transistor when the third control signal indicates the fault of the MCU.

4. The inverter circuit according to claim 3, characterized in that: The power management circuit is configured to send the fourth control signal having an entry mode indicating initiation of the discharging of the charging capacitor to the first gate driver.

5. The inverter circuit according to claim 4, characterized in that: The entry mode is sent after a first delay time period after the indication of the fault of the MCU.

6. The inverter circuit according to any one of claims 4 to 5, characterized in that: The first gate driver is configured to drive the first transistor with a pulse width modulation signal after the first gate driver receives the fourth control signal having the entry mode.

7. The inverter circuit according to claim 6, characterized in that: The power management circuit is configured to send the fourth control signal having an exit mode indicating an end of the discharging of the charging capacitor to the first gate driver after a second delay time, wherein the exit mode is different from the entry mode.

8. An inverter circuit according to any one of the preceding claims, characterized in that The MCU is configured to override the third control signal and the fourth control signal when asserted by the power management circuit.

9. An inverter circuit according to any one of the preceding claims, characterized in that Also includes: A second phase circuit, the second phase circuit comprising: A third transistor; a third gate driver configured to control the third transistor; a fourth transistor connected in series with the third transistor; and a fourth gate driver configured to control the fourth transistor; wherein the first control signal and the second control signal are configured to control the operation of the third gate driver and the fourth gate driver, respectively, and Wherein the third control signal and the fourth control signal are configured to control the operation of the third gate driver and the fourth gate driver when the fault in the operation of the MCU is detected, thereby controlling the discharge of the charging capacitor.

10. The inverter circuit according to any one of claims 1 to 9, characterized in that: additionally including a second phase circuit and a third phase circuit, wherein each of the first phase circuit and the third circuit includes the same components as the first phase circuit; wherein the MCU is configured to generate a first control signal and a second control signal to control operations of the first gate driver and the second gate driver, respectively, wherein the first control signal and the second control signal are configured to control the discharge of a charging capacitor connected to the first phase circuit; and The power management circuit is configured to: detecting a fault in the operation of the MCU; and A third control signal and a fourth control signal are generated to control the operation of the first gate driver and the second gate driver when the failure in the operation of the MCU is detected, thereby controlling the discharge of the charging capacitor.

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