High-speed level conversion circuit and chip

Abstract

The present invention relates to the field of integrated circuits, and discloses a high-speed level conversion circuit and a chip. The circuit includes: a same-phase and inverted signal output circuit, configured to output a first output signal in phase and a second output signal in inverted phase during the rising edge of an input signal; a level boosting circuit, configured to enter a charging state and boost the first output signal in response to the first and second output signals V BS ; a substrate voltage regulation circuit, configured to generate a positive pulse differential waveform to quickly turn on a first NMOS transistor of the conversion circuit and generate a negative pulse differential waveform to quickly turn off a second NMOS transistor in response to the first and second output signals; a conversion circuit, configured to pull an output voltage to a low level in response to the actions of the first and second NMOS transistors; an inverted output buffer circuit, configured to invert its output voltage to convert the low level into a target level. The level conversion circuit of the present invention can achieve high speed and a wide level conversion range.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a high-speed level conversion circuit and a chip. Background Art

[0002] Level conversion circuits are widely used in mixed-signal circuits with multiple power supply voltage domains. In the field of mixed-signal design, in order to reduce the power consumption of the circuit and improve the operating speed of the circuit, a mixed voltage domain design is often adopted. Among them, key performance modules adopt high-voltage design, high-speed and low-power modules adopt low-voltage design, and at the interface between the two, a large number of level conversion circuits are required. Therefore, how to implement a high-speed and low-cost level conversion circuit has always been a widely concerned issue.

[0003] There are two basic structures of voltage converter circuits, Figure 1a AND Figure 1b For the existing design one, where Figure 1a is the circuit, Figure 1b is the signal waveform diagram. Figure 1a The circuit 100 shown includes an input inverter circuit 110, a level conversion circuit 120 based on a cross-coupled structure, and an inverting output buffer circuit 130. Among them, the input inverter circuit 110 operates in a low voltage domain of 1.8V, and the level conversion circuit 120 and the inverting output buffer circuit 130 operate in a high voltage domain of 5V. The input inverter circuit 110 inverts the input signal to provide an inverted input signal. The level conversion circuit 120 includes: a cross-coupled structure composed of PMOS transistors 123 and 124 as a pull-up network to pull up the output signal to a high voltage; a pull-down network composed of NMOS transistors 121 and 122 to pull down the output signal to ground. The cross-coupled pull-up network has a positive feedback characteristic, which strengthens the voltage difference between Q1 and Q2, thereby performing level switching faster. The signal waveform during operation is as Figure 1b shown. During the rising edge of the input signal V iL NMOS transistor 121 is turned on and NMOS transistor 122 is turned off. At this time, the voltage at Q1 gradually decreases, and PMOS transistor 124 gradually turns on, pulling Q2 towards the high power supply voltage ( V ddH ), which helps to turn off PMOS transistor 123, resulting in faster discharge of Q1; the pull-up speed of the inverting output buffer circuit 130 from low level to high level is also faster. This architecture has very low power consumption in the standby mode because neither of the two circuit branches consumes static power. However, when the low power supply voltage ( V ddLWhen it is relatively low, the overdrive voltages of the pull - down transistors NMOS 121 and 122 are relatively low and cannot easily overcome the pull - up transistors PMOS 123 and 124. Therefore, in order to improve the pull - down network, the sizes of NMOS transistors 121 and 122 are often large, which reduces the overall efficiency and brings greater delay and power consumption.

[0004] Figure 2a And Figure 2b For existing design two, where Figure 2a Is a circuit, Figure 2b Is a signal waveform diagram. Figure 2a The circuit 200 shown includes an input inverter circuit 210, a level - conversion circuit 220 based on a current - mirror structure, and a cascaded output buffer circuit 230. Among them, the input inverter circuit 210 operates in a low - voltage domain of 1.8V, and the level - conversion circuit 220 and the cascaded output buffer circuit 230 operate in a high - voltage domain of 5V. The input inverter circuit 210 inverts the input signal to provide an inverted input signal. The level - conversion circuit 220 includes: a current - mirror structure composed of PMOS transistors 223 and 224 as the pull - up network to pull up the output signal to a high voltage; a pull - down network composed of NMOS transistors 221 and 222 to pull down the output signal to ground. Finally, the output signal of the level converter is output through the cascaded output buffer circuit 223. The signal waveform during operation is as Figure 2b Shown, during the rising edge of the input signal V iL NMOS transistor 221 turns on and NMOS transistor 222 turns off. At this time, the voltage at Q1 gradually decreases, and PMOS transistor 224 gradually turns on, pulling Q2 towards the high - power supply voltage ( V ddH ), and finally, after passing through the cascaded output buffer 223, the low voltage is converted to a high voltage. In this circuit structure, although there is no competition relationship between the pull - down network and the pull - up network, there is almost no regenerative interaction between the upper and lower pull - down networks and between the left and right branches of the circuit. Therefore, the conversion speed is relatively low. In addition, it has relatively large static power, which is mainly due to the existence of static current in one of the circuit branches according to the input state. Summary of the Invention

[0005] The object of the present invention is to provide a high - speed level - conversion circuit and a chip, which can increase the overdrive voltage of the pull - down network of the level - conversion circuit, increase the strength of the pull - down network without sacrificing the strength of the pull - up network, achieve high - speed level conversion, and have the characteristics of high speed and wide level - conversion range compared with the existing design when the circuit size and load size are equivalent.

[0006] To achieve the above object, a first aspect of the present invention provides a high-speed level conversion circuit, which includes: a same-phase and anti-phase signal output circuit, a level boost circuit, a substrate voltage regulation circuit, a level conversion circuit based on a cross-coupled structure, and an inverting output buffer circuit. Among them, the same-phase and anti-phase signal output circuit is used to output a first output signal in phase with the input signal and a second output signal in anti-phase with the input signal during the rising edge of the input signal; the level boost circuit is used to enter a charging state and boost the first output signal in response to the first output signal and the second output signal V BS , where the V BS is an external bias voltage for controlling the level boost circuit; the substrate voltage regulation circuit is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal to quickly turn on the first NMOS transistor in the level conversion circuit, and generate a negative pulse differential waveform to quickly turn off the second NMOS transistor in the level conversion circuit, where the V BS is less than the threshold voltages of the first NMOS transistor and the second NMOS transistor; the level conversion circuit is used to pull the output voltage to the low level 0 in response to the first NMOS transistor being quickly turned on and the second NMOS transistor being quickly turned off; and the inverting output buffer circuit is used to invert the output voltage to convert the low level 0 into a target level.

[0007] Preferably, the same-phase and anti-phase signal output circuit is used to output a first output signal in phase with the input signal and a second output signal in anti-phase with the input signal during the falling edge of the input signal; the level boost circuit is used to enter a charging state and boost the second output signal in response to the first output signal and the second output signal V BS ; the substrate voltage regulation circuit is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal to quickly turn on the second NMOS transistor in the level conversion circuit, and generate a negative pulse differential waveform to quickly turn off the first NMOS transistor in the level conversion circuit; the level conversion circuit is used to pull the output voltage to the target level in response to the second NMOS transistor being quickly turned on and the first NMOS transistor being quickly turned off; and the inverting output buffer circuit is used to invert the output voltage to convert the target level into the low level 0.

[0008] Preferably, the in-phase and anti-phase signal output circuit is a clock edge adjustment circuit, and the clock edge adjustment circuit is further configured to align the center point of the rising edge of the first output signal with the center point of the falling edge of the second output signal, and align the center point of the falling edge of the first output signal with the center point of the rising edge of the second output signal.

[0009] Preferably, the level boosting circuit includes: a first circuit configured to enter a charging state in response to the first output signal and the second output signal during the rising edge of the input signal, or boost the second output signal in response to the first output signal and the second output signal during the falling edge of the input signal V BS ; and a second circuit configured to boost the first output signal in response to the first output signal and the second output signal during the rising edge of the input signal V BS , or enter a charging state in response to the first output signal and the second output signal during the falling edge of the input signal.

[0010] Preferably, the first circuit includes: a third NMOS transistor, the gate of the third NMOS transistor is connected to the first output signal, and the source of the third NMOS transistor is connected to the external bias voltage; a first capacitor, the first end of the first capacitor is connected to the drain of the third NMOS transistor, and the second end of the first capacitor is connected to the second output signal. The second circuit includes: a fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the second output signal, and the source of the fourth NMOS transistor is connected to the external bias voltage; a second capacitor, the first end is connected to the drain of the fourth NMOS transistor, and the second end is connected to the first output signal.

[0011] Preferably, the first circuit further includes: a fifth NMOS transistor, the source of the fifth NMOS transistor is connected to the drain of the third NMOS transistor, and the drain of the fifth NMOS transistor is connected to the first end of the first capacitor. The second circuit further includes: a sixth NMOS transistor, the source of the sixth NMOS transistor is connected to the drain of the fourth NMOS transistor, and the drain of the sixth NMOS transistor is connected to the first end of the second capacitor.

[0012] Preferably, the first circuit further includes: a first resistor, the first end of the first resistor is connected to the drain of the third NMOS transistor, and the second end of the first resistor is connected to the first end of the first capacitor. The second circuit further includes: a second resistor, the first end of the second resistor is connected to the drain of the fourth NMOS transistor, and the second end of the second resistor is connected to the first end of the second capacitor.

[0013] Preferably, the first end of the second capacitor is connected to the gate of the first NMOS transistor in the level conversion circuit; the first end of the first capacitor is connected to the gate of the second NMOS transistor in the level conversion circuit.

[0014] Preferably, the substrate voltage regulation circuit includes: a first micro-branch circuit, the input end of the first micro-branch circuit is connected to the first output signal, and the output end of the first micro-branch circuit is connected to the substrate of the first NMOS transistor in the level conversion circuit; and a second micro-branch circuit, the input end of the second micro-branch circuit is connected to the second output signal, and the output end of the second micro-branch circuit is connected to the substrate of the second NMOS transistor in the level conversion circuit.

[0015] By the above technical solution, the present invention creatively provides a same-phase and anti-phase signal output circuit, a level boosting circuit, a substrate voltage regulation circuit, a level conversion circuit based on a cross-coupled structure, and an inverting output buffer circuit in the high-speed level conversion circuit. Among them, the same-phase and anti-phase signal output circuit is used to output a first output signal in phase with the input signal and a second output signal opposite to the input signal during the rising edge of the input signal; the level boosting circuit is used to respond to the first output signal and the second output signal, enter a charging state and boost the first output signal V BS , where the V BS is an external bias voltage for controlling the level boosting circuit; the substrate voltage regulation circuit is used to respond to the first output signal and the second output signal, generate a positive pulse differential waveform to quickly turn on the first NMOS transistor in the level conversion circuit, and generate a negative pulse differential waveform to quickly turn off the second NMOS transistor in the level conversion circuit, where the V BS is less than the threshold voltages of the first NMOS transistor and the second NMOS transistor; the level conversion circuit is used to respond to the first NMOS transistor being quickly turned on and the second NMOS transistor being quickly turned off, and pull the output voltage to the low level 0; and the inverting output buffer circuit is used to invert the output voltage to convert the low level 0 into a target level. Thus, the present invention uses an auxiliary level boosting circuit and a substrate voltage regulation circuit to increase the overdrive voltage of the pull-down network of the level conversion circuit. Without sacrificing the strength of the pull-up network, the strength of the pull-down network is increased, realizing high-speed level conversion. Compared with the existing design, it has the characteristics of high speed and wide level conversion range when the circuit size and load size are comparable.

[0016] The second aspect of the present invention provides a chip, and the chip includes the above-mentioned high-speed level conversion circuit.

[0017] Other features and advantages of the present invention will be described in detail in the following specific implementation part. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the specification. Together with the following specific implementation manners, they are used to explain the embodiments of the present invention, but do not constitute a limitation to the embodiments of the present invention. In the accompanying drawings:

[0019] Figure 1a is a schematic structural diagram of an existing level conversion circuit design one;

[0020] Figure 1b is Figure 1a the signal waveform diagram corresponding to the level conversion circuit in;

[0021] Figure 2a is a schematic structural diagram of an existing level conversion circuit design two;

[0022] Figure 2b is Figure 2a the signal waveform diagram corresponding to the level conversion circuit in;

[0023] Figure 3 is a schematic structural diagram of a high-speed level conversion circuit provided by an embodiment of the present invention; and

[0024] Figure 4 is provided by an embodiment of the present invention Figure 3 the signal waveform diagram corresponding to the high-speed level conversion circuit in. SPECIFIC IMPLEMENTATION MANNERS

[0025] The following will describe in detail the specific implementation manners of the present invention with reference to the accompanying drawings. It should be understood that the specific implementation manners described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0026] Figure 3 is a schematic structural diagram of a high-speed level conversion circuit provided by an embodiment of the present invention. As Figure 3 shown, the high-speed level conversion circuit 500 includes: a same-phase and anti-phase signal output circuit 510, a level boosting circuit 520, a substrate voltage regulation circuit 530, a level conversion circuit 540 based on a cross-coupled structure, and an inverting output buffer circuit 550.

[0027] This embodiment proposes a high-speed level conversion circuit applicable to low latency and a wide voltage conversion range. The main idea is to use an auxiliary level boosting circuit and a substrate voltage regulation circuit (such as a differential circuit composed of capacitors and resistors) to increase the overdrive voltage of the pull-down NMOS network in the level conversion circuit. Without sacrificing the strength of the pull-up network, the strength of the pull-down network is increased, achieving high-speed level conversion.

[0028] For the rising edge of the input signal V iL during (as shown in Figure 4 ), a high-speed level conversion circuit 500 can be used to achieve high-speed level conversion with low latency and a wide voltage conversion range. The specific implementation details are described below.

[0029] The inverting and non-inverting signal output circuit 510 is used to output a first output signal in phase with the input signal and a second output signal inverted with respect to the input signal during the rising edge of the input signal.

[0030] The level boosting circuit 520 is used to enter a charging state in response to the first output signal and the second output signal and boost the first output signal V BS . Wherein, the V BS is an external bias voltage used to control the level boosting circuit.

[0031] The substrate voltage regulation circuit 530 is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal to quickly turn on the first NMOS transistor (e.g., NMOS transistor 541) in the level conversion circuit 540, and generate a negative pulse differential waveform to quickly turn off the second NMOS transistor (e.g., NMOS transistor 542) in the level conversion circuit 540. Wherein, the V BS is less than the threshold voltages of the first NMOS transistor (e.g., NMOS transistor 541) and the second NMOS transistor (e.g., NMOS transistor 542). By the above level boosting circuit 520 entering the charging state, the overdrive voltage of the NMOS transistor 541 can be increased, making the NMOS transistor 541 conduct faster.

[0032] The level conversion circuit 540 is used to pull the output voltage to the low level 0 in response to the first NMOS transistor (e.g., NMOS transistor 541) quickly turning on and the second NMOS transistor (e.g., NMOS transistor 542) quickly turning off.

[0033] The inverting output buffer circuit 550 is used to invert the output voltage to convert the low level 0 to the target level.

[0034] Among them, the common and inverted signal output circuit 510 (e.g., clock edge adjustment circuit), the level boost circuit 520, and the substrate voltage adjustment circuit 530 operate at a low level (e.g., 1.8V); the level conversion circuit 540 and the inverted output buffer circuit 550 operate at a high level / target level (e.g., 5V).

[0035] Specifically, taking Figure 3 and Figure 4 as an example, the working process of the high-speed level conversion circuit is described.

[0036] When the input signal V iL rises from the power supply ground (0V) to V ddL (e.g., 1.8V) (i.e., during the rising edge of Figure 4 ), the common and inverted signal output circuit 510 outputs a first output signal V iL in phase with V iLC and a second output signal iL inverted with V V iNLC .

[0037] When the input signal V iL converts from the power supply ground 0V to V ddL ( V iLC is at a low level and V iNLC is at a high level), the level boost circuit 520 enters the charging state; and raises the input signal V iL / the first output signal V iLC by a voltage magnitude of V BS (as shown in Figure 4 of V iLC_BS ), where V BS is less than the threshold voltages of the NMOS transistors 541 and 542, thereby increasing the overdrive voltage of the input NMOS transistor and enhancing the pull-down ability of the NMOS transistor.

[0038] The substrate voltage adjustment circuit 530 generates a positive pulse differential waveform when the NMOS transistor 541 is turned on (e.g., Figure 4 in V sub1), reducing the threshold voltage of the NMOS transistor 541, thereby increasing the overdrive voltage of the NMOS transistor 541 and enabling the NMOS transistor 541 to turn on faster; while when the NMOS transistor 542 is turned off, a negative pulse differential waveform is generated (for example Figure 4 in V sub2 ), increasing the threshold voltage of the NMOS transistor 542, enabling the NMOS transistor 542 to turn off faster.

[0039] In response to the NMOS transistor 541 turning on quickly and the NMOS transistor 542 turning off quickly, the level conversion circuit 540, as the core circuit of the entire level conversion circuit system, outputs a signal at Q1 that transitions from a high voltage signal to a low voltage signal (i.e., pulling the output voltage of the level conversion circuit 540 from a high level V ddH towards the low level 0), thereby enabling the entire level conversion circuit system to convert from 0V to a high power supply voltage signal (for example V ddH = 5V).

[0040] The inverting output buffer circuit 550 inverts and buffers the output of the level conversion circuit 540 to pull the low level 0 towards the high level / target level V ddH (for example, 5V) (for example Figure 4 in V oH rising edge).

[0041] During the falling edge of the input signal V iL (as shown in Figure 4 ), the high-speed level conversion circuit 500 can be used to achieve high-speed level conversion with low latency and a wide voltage conversion range (i.e., it can achieve voltage conversion from 1.8V to 5V). The specific implementation details are described below.

[0042] The in-phase and anti-phase signal output circuit 510 is used to output a first output signal in phase with the input signal and a second output signal anti-phase to the input signal during the falling edge of the input signal.

[0043] The level boosting circuit 520 is used to enter a charging state and boost the second output signal in response to the first output signal and the second output signal V BS .

[0044] The substrate voltage regulation circuit 530 is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal, so that the second NMOS transistor (for example, NMOS transistor 542) in the level conversion circuit is quickly turned on, and a negative pulse differential waveform is generated to quickly turn off the first NMOS transistor (for example, NMOS transistor 541) in the level conversion circuit.

[0045] The level conversion circuit 540 is used to pull the output voltage to the target level (i.e., V ddH , for example 5V) in response to the second NMOS transistor (for example, NMOS transistor 542) being quickly turned on and the first NMOS transistor (for example, NMOS transistor 541) being quickly turned off.

[0046] The inverting output buffer circuit 550 is used to invert the output voltage to convert the target level (i.e., V ddH , for example 5V) to a low level of 0.

[0047] Specifically, taking Figure 3 and Figure 4 as an example, the working process of the high-speed level conversion circuit is described.

[0048] When the input signal V iL falls from V ddL (for example, 1.8V) to the power supply ground (0V) during the falling edge of Figure 4 , the inverting and non-inverting signal output circuit 510 outputs a first output signal in phase with V iL and a second output signal inverted with V V iLC . iL V iNLC .

[0049] When the input signal V iL converts from V ddL to the power supply ground 0V ( V iLC is at a low level and V iNLC is at a high level), the level boost circuit 520 enters a charging state; and the second output signal V iNLC is lifted, and the magnitude of the lifted voltage is V BS (as shown in Figure 4 ViNLC_BS ), where V BS is less than the threshold voltages of NMOS transistors 541 and 542, so that the overdrive voltage of the input NMOS transistor can be increased, enhancing the pull-down ability of the NMOS transistor.

[0050] The substrate voltage regulation circuit 530 generates a positive pulse differential waveform when the NMOS transistor 542 is turned on (for example Figure 4 in V sub2 ), reducing the threshold voltage of the NMOS transistor 542, and then increasing the overdrive voltage of the NMOS transistor 542, enabling the NMOS transistor 542 to turn on faster; and when the NMOS transistor 541 is turned off, it generates a negative pulse differential waveform (for example Figure 4 in V sub1 ), increasing the threshold voltage of the NMOS transistor 541, causing the NMOS transistor 541 to turn off faster.

[0051] In response to the NMOS transistor 542 turning on quickly and the NMOS transistor 541 turning off quickly, the level conversion circuit 540, as the core circuit of the entire level conversion circuit system, the level conversion circuit 540 outputs the conversion of the low voltage signal to the high voltage signal at Q1 (i.e., pulling the output voltage of the level conversion circuit 540 from the low level 0 to the high level V ddH ), so that the entire level conversion circuit system realizes the conversion from the high power supply voltage signal (for example V ddH = 5V) to 0V.

[0052] The inverting output buffer circuit 550 inverts and buffers the output of the level conversion circuit 540 to pull the high level / target level V ddH (for example, 5V) to the low level 0 (for example Figure 4 in V oH at the falling edge).

[0053] In one embodiment, the same / different phase signal output circuit 510 can be a clock edge adjustment circuit.

[0054] Correspondingly, the clock edge adjustment circuit is further configured to align the center point of the rising edge of the first output signal with the center point of the falling edge of the second output signal, and align the center point of the falling edge of the first output signal with the center point of the rising edge of the second output signal.

[0055] In this embodiment, in addition to outputting two signals that are in-phase and anti-phase with the input signal, the clock edge adjustment circuit also aligns the centers of the rising edges and falling edges of the two signals, thereby avoiding charge leakage of the capacitors 523 and 524 in the subsequent level boosting circuit.

[0056] Next, the specific structure of the level boosting circuit 520 will be described.

[0057] The level boosting circuit 520 includes: a first circuit that, during the rising edge of the input signal, enters a charging state in response to the first output signal and the second output signal, or, during the falling edge of the input signal, raises the second output signal in response to the first output signal and the second output signal V BS ; and a second circuit that, during the rising edge of the input signal, raises the first output signal in response to the first output signal and the second output signal V BS , or, during the falling edge of the input signal, enters a charging state in response to the first output signal and the second output signal.

[0058] As Figure 3 shown, the first circuit includes: a third NMOS transistor (e.g., NMOS transistor 526), the gate of the third NMOS transistor (e.g., NMOS transistor 526) is connected to the first output signal (e.g., V iLC ), the source of the third NMOS transistor (e.g., NMOS transistor 526) is connected to the external bias voltage (e.g., V BS ); a first capacitor (e.g., capacitor 524), the first end is connected to the drain of the third NMOS transistor (e.g., NMOS transistor 526), and the second end is connected to the second output signal (e.g., V iNLC ).

[0059] As Figure 3 shown, the second circuit includes: a fourth NMOS transistor (e.g., NMOS transistor 521), the gate of the fourth NMOS transistor (e.g., NMOS transistor 521) is connected to the second output signal (e.g., V iNLC ), the source of the fourth NMOS transistor (e.g., NMOS transistor 521) is connected to the external bias voltage (e.g., V BS ); a second capacitor (e.g., capacitor 523), the first end is connected to the drain of the fourth NMOS transistor (e.g., NMOS transistor 521), and the second end is connected to the first output signal (e.g.,V iLC are connected.

[0060] In one embodiment, as Figure 3 shown, the first circuit further includes: a fifth NMOS transistor (e.g., NMOS transistor 525), the source of the fifth NMOS transistor (e.g., NMOS transistor 525) is connected to the drain of the third NMOS transistor (e.g., NMOS transistor 526), and the drain of the fifth NMOS transistor (e.g., NMOS transistor 525) is connected to the first end of the first capacitor (e.g., capacitor 524).

[0061] As Figure 3 shown, the second circuit further includes: a sixth NMOS transistor (e.g., NMOS transistor 522), the source of the sixth NMOS transistor (e.g., NMOS transistor 522) is connected to the drain of the fourth NMOS transistor (e.g., NMOS transistor 521), and the drain of the sixth NMOS transistor (e.g., NMOS transistor 522) is connected to the first end of the second capacitor (e.g., capacitor 523).

[0062] In this embodiment, the fifth NMOS transistor and the sixth NMOS transistor are used to isolate the V BS impact that the signal may bring. Moreover, compared with a resistor, the fifth NMOS transistor and the sixth NMOS transistor have a stronger isolation effect.

[0063] In another embodiment, the first circuit further includes: a first resistor (not shown), the first end of the first resistor is connected to the drain of the third NMOS transistor, and the second end of the first resistor is connected to the first end of the first capacitor.

[0064] The second circuit further includes: a second resistor (not shown), the first end of the second resistor is connected to the drain of the fourth NMOS transistor, and the second end of the second resistor is connected to the first end of the second capacitor.

[0065] In this embodiment, the first resistor and the second resistor are used to isolate the V BS impact that the signal may bring.

[0066] Next, the connection method of two capacitors (e.g., capacitors 523, 524) in the level boost circuit 520 will be described.

[0067] As Figure 3As shown, the first end of the second capacitor (e.g., capacitor 523) is connected to the gate of the first NMOS transistor (e.g., NMOS transistor 541) in the level conversion circuit 540. The first end of the first capacitor (e.g., capacitor 524) is connected to the gate of the second NMOS transistor (e.g., NMOS transistor 542) in the level conversion circuit 540.

[0068] The specific structure of the substrate voltage regulation circuit 530 will be described below.

[0069] As Figure 3 shown, the substrate voltage regulation circuit 530 includes: a first micro-branch (which includes a capacitor 531 and a resistor 532 connected in series), the input end of the first micro-branch is connected to the first output signal (e.g., V iLC ), and the output end of the first micro-branch (e.g., V sub1 ) is connected to the substrate of the first NMOS transistor (e.g., NMOS transistor 541) in the level conversion circuit 540; and a second micro-branch (which includes a capacitor 533 and a resistor 534 connected in series), the input end of the second micro-branch is connected to the second output signal (e.g., V iNLC ), and the output end of the second micro-branch (e.g., V sub2 ) is connected to the substrate of the second NMOS transistor (e.g., NMOS transistor 542) in the level conversion circuit 540.

[0070] Specifically, taking Figure 3 and Figure 4 as an example, the working process of the high-speed level conversion circuit will be described.

[0071] When the input signal V iL rises from the power ground (0V) to V ddL (e.g., 1.8V) (i.e., during the rising edge of Figure 4 ), the in-phase input signal buffer stage composed of NMOS transistors 515, 517 and PMOS transistors 516, 518 outputs a signal in phase with V iL (i.e., the first output signal V iLC ), and the anti-phase input signal buffer stage composed of NMOS transistors 511, 513 and PMOS transistors 512, 514 outputs a signal anti-phase with V iL (i.e., the second output signal V iNLC ). Among them ViLC The rising edge and V iNLC the center points of the falling edges are aligned, V iLC the falling edge and V iNLC the center points of the rising edges are aligned, avoiding charge leakage of the capacitors 523 and 524 in the level boosting circuit 520 of the subsequent stage.

[0072] When the input signal V iL transitions from 0 to V ddL converts ( V iLC to a low level and V iNLC to a high level), the level boosting circuit composed of the capacitor 524, NMOS transistors 525 and 526 starts to charge the capacitor 524; and at this time, the level boosting circuit composed of the capacitor 523, NMOS transistors 521 and 522 raises the input signal V iL / the first output signal V iLC by a magnitude of V BS (as shown in Figure 4 ), that is, V iLC_BS can be raised to V iLC + V ddL + V BS ), where V BS is less than the threshold voltages of the NMOS transistors 541 and 542, thereby increasing the overdrive voltage of the input NMOS transistor and enhancing the pull-down ability of the NMOS transistor to avoid incorrect turn-on of the NMOS transistors 541 and 542.

[0073] The differentiating circuit composed of the capacitor 531 and the resistor 532 generates a positive pulse differential waveform when the NMOS transistor 541 is turned on (such as Figure 4 in V sub1 ), reducing the threshold voltage of the NMOS transistor 541 and further increasing the overdrive voltage of the NMOS transistor 541 (i.e., briefly increasing the substrate voltage of the NMOS transistor 541), enabling the NMOS transistor 541 to turn on faster; while the differentiating circuit composed of the capacitor 533 and the resistor 534 generates a negative pulse differential waveform when the NMOS transistor 542 is turned off (such as Figure 4 in V sub2), increasing the threshold voltage of the NMOS transistor 542, briefly reducing the substrate voltage of the NMOS transistor 542, causing the NMOS transistor 542 to turn off faster, further preventing the NMOS transistor 542 from turning on, and at the same time reducing subthreshold leakage.

[0074] In response to the NMOS transistor 541 turning on quickly and the NMOS transistor 542 turning off quickly, the level conversion circuit 540, as the core circuit of the entire level conversion circuit system, outputs a signal at Q1 that is converted from a high voltage signal to a low voltage signal (i.e., pulling the output voltage of the level conversion circuit 540 from a high level V ddH to the low level 0), and thus the conversion of the entire level conversion circuit system from 0 to a high power supply voltage signal (e.g., V ddH = 5V) can be achieved. That is to say, when the NMOS transistor 541 turns on and the NMOS transistor 542 turns off, the PMOS transistor 544 turns on and the PMOS transistor 543 turns off, the voltage at Q1 drops to the power supply ground, and the voltage at Q2 rises to V ddH .

[0075] The inverting output buffer circuit 550 inverts and buffers the output of the level conversion circuit 540 to pull the low level 0 to the high level / target level V ddH (e.g., 5V) (e.g., Figure 4 in V oH the rising edge). That is to say, a high voltage is output after passing through the inverting output buffer circuit 550 V ddH . Among them, the inverting output buffer circuit 550 includes a PMOS transistor 552 and an NMOS transistor 551, as Figure 4 shown.

[0076] When the input signal V iL changes from V ddL (e.g., 1.8V) to the power supply ground (0V) during (i.e., Figure 4 during the falling edge of V iL ), the in-phase input signal buffer stage composed of NMOS transistors 515, 517 and PMOS transistors 516, 518 outputs a signal in phase with V iLC (i.e., the first output signal V iL ), and the inverting input signal buffer stage composed of NMOS transistors 511, 513 and PMOS transistors 512, 514 outputs a signal inverted with ViNLC ). Among them V iLC align the center points of the rising edge and V iNLC the falling edge, V iLC align the center points of the falling edge and V iNLC the rising edge, to avoid charge leakage of the capacitors 523 and 524 in the level boost circuit 520 of the subsequent stage.

[0077] When the input signal V iL changes from V ddL to 0 ( V iLC is at a low level and V iNLC is at a high level), the level boost circuit composed of the capacitor 523, NMOS transistors 521, and 522 starts to charge the capacitor 523; and at this time, the level boost circuit composed of the capacitor 524, NMOS transistors 525, and 526 raises the second output signal V iNLC by an amount, and the magnitude of the raised voltage is V BS (as shown in Figure 4 ), that is, V iNLC_BS can be raised to V iLC + V ddL + V BS ), where V BS is less than the threshold voltages of the NMOS transistors 541 and 542, so as to increase the overdrive voltage of the input NMOS transistor, enhance the pulling-down ability of the NMOS transistor, and avoid the incorrect turn-on of the NMOS transistors 541 and 542.

[0078] The differentiating circuit composed of the capacitor 533 and the resistor 534 generates a positive pulse differential waveform when the NMOS transistor 542 is turned on (for example, Figure 4 in V sub2 ), reducing the threshold voltage of the NMOS transistor 542, and then increasing the overdrive voltage of the NMOS transistor 542 (that is, briefly increasing the substrate voltage of the NMOS transistor 542), enabling the NMOS transistor 542 to turn on faster; while the differentiating circuit composed of the capacitor 531 and the resistor 532 generates a negative pulse differential waveform when the NMOS transistor 541 is turned off (for example, Figure 4 in V sub1), increasing the threshold voltage of NMOS transistor 541, briefly reducing the substrate voltage of NMOS transistor 541, causing NMOS transistor 541 to turn off faster, further preventing NMOS transistor 541 from turning on, and at the same time reducing subthreshold leakage.

[0079] In response to NMOS transistor 542 turning on quickly and NMOS transistor 541 turning off quickly, the level conversion circuit 540, as the core circuit of the entire level conversion circuit system, outputs the conversion of the low-voltage signal to the high-voltage signal at Q1 (i.e., pulling the output voltage of the level conversion circuit 540 from the low level 0 to the high level V ddH ), so that the entire level conversion circuit system realizes the conversion from the high power supply voltage signal (e.g., V ddH = 5V) to 0V. That is to say, when NMOS transistor 542 turns on and NMOS transistor 541 turns off, PMOS transistor 543 turns on and PMOS transistor 544 turns off, and the voltage at Q1 rises to V ddH , and the voltage at Q2 drops to the power supply ground (0V).

[0080] The inverting output buffer circuit 550 inverts and buffers the output of the level conversion circuit 540 to pull the high level / target level V ddH (e.g., 5V) to the low level 0 (e.g., Figure 4 in V oH the falling edge of). That is to say, the inverting output buffer circuit 550 outputs a low level of 0V.

[0081] With the help of the auxiliary boost circuit and the substrate voltage regulation circuit, the present invention speeds up the turn-on speed of NMOS transistors 541 and 542, increases the overdrive voltage at the same time, solves the problem of the weak pull-down network strength in Design One, and increases the threshold voltages of NMOS transistors 541 and 542 in the off state with the help of the substrate voltage modulation circuit, reducing the leakage power consumption. Under the same level conversion circuit size and load requirements, the high-level conversion delay of this design is about Figure 1a a quarter of Design One shown in Figure 2a and half of Design Two shown in

[0082] Among them, the specific structures of the level conversion circuit 540 and the inverting output buffer circuit 550 based on the cross-coupled structure can be referred to the prior art, and their specific structures are not the main improvement points of the present invention, so they will not be elaborated here.

[0083] The high-speed level conversion circuit may include a clock edge adjustment circuit, a level boost circuit, a substrate voltage adjustment circuit, a level conversion circuit with cross-coupled transistors as loads, and an output buffer circuit. Among them, the clock edge adjustment circuit, the level boost circuit, and the substrate voltage adjustment circuit operate in a low-voltage domain, and the level conversion circuit and the output buffer circuit operate in a high-voltage domain. The entire voltage conversion circuit has only one low-voltage domain input signal V iL , and the input signal first passes through the clock edge adjustment circuit to generate a pair of complementary input signals V iLC and V iNLC . When the input signal V iL converts from low level to high level, V iLC the signal converts from low level to high level, V iNLC and the signal converts from high level to low level. At this time, V iLC the signal is respectively connected to the capacitor bottom plate of the positive terminal level boost circuit, the control switch of the negative terminal level boost capacitor, and the positive terminal substrate voltage adjustment circuit as an input signal. The level boost circuit will boost the voltage of V iLC the signal. At the same time, the body potential of the positive terminal input NMOS transistor of the level conversion circuit is connected to the output terminal of the substrate voltage adjustment circuit, and the body potential will first increase and then decrease. Therefore, during the conversion of V iLC from low level to high level, the input transistor at the positive terminal of the level conversion circuit will conduct rapidly. Similarly, V iNLC the signal is respectively connected to the capacitor bottom plate of the negative terminal level boost circuit, the control switch of the positive terminal level boost capacitor, and the negative terminal substrate voltage adjustment circuit as an input signal. V iNLC The signal will pre-charge the negative terminal level boost circuit. At the same time, the body potential of the negative terminal input NMOS transistor of the level conversion circuit is connected to the output terminal of the substrate voltage adjustment circuit, and the body potential will first decrease and then increase. Therefore, during the conversion of V iNLC from low level to high level, the input transistor at the negative terminal of the level conversion circuit will turn off rapidly. After that, through the positive feedback process of the level conversion circuit, the conversion of the input signal from the low-voltage domain to the high-voltage domain is finally completed.

[0084] In summary, the present invention creatively uses an auxiliary level boosting circuit and a substrate voltage regulating circuit to increase the overdrive voltage of the pull-down network of the level conversion circuit. Without sacrificing the strength of the pull-up network, the strength of the pull-down network is increased, realizing high-speed level conversion. Compared with the existing design, when the circuit size and load size are comparable, it has the characteristics of high speed and wide level conversion range.

[0085] An embodiment of the present invention provides a chip, and the chip includes the high-speed level conversion circuit described above.

[0086] The preferred embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0087] In addition, it should be noted Ming that, among the various specific technical features described in the above specific embodiments, they can be combined in any appropriate manner without contradiction. To avoid unnecessary repetition, the present invention will not separately describe various possible combination methods.

[0088] In addition, any combination can be made between various different embodiments of the present invention as long as it does not violate the idea of the present invention, and it should also be regarded as the content disclosed by the present invention.

Claims

1. A high-speed level conversion circuit, characterized in that: The high-speed level conversion circuit includes: an inverse signal output circuit, a level boost circuit, a substrate voltage adjustment circuit, a level conversion circuit based on a cross-coupling structure, and an inverse output buffer circuit. The in-phase and inverted signal output circuit is used to output a first output signal in phase with the input signal and a second output signal in phase with the input signal during a rising edge of the input signal; The level boosting circuit is used to enter a charging state and raise the first output signal in response to the first output signal and the second output signal. V BS , wherein the V BS An external bias voltage for controlling the level boosting circuit; The substrate voltage regulating circuit is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal to quickly turn on the first NMOS transistor in the level conversion circuit, and to generate a negative pulse differential waveform to quickly turn off the second NMOS transistor in the level conversion circuit, wherein the V BS is smaller than the threshold voltage of the first NMOS tube and the second NMOS tube; The level conversion circuit is used for pulling the output voltage to a low level 0 in response to the first NMOS tube being quickly turned on and the second NMOS tube being quickly turned off; and The inverting output buffer circuit is used to invert the output voltage to convert the low level 0 into a target level; Wherein, the level boosting circuit comprises: a first circuit configured to enter a charging state in response to the first output signal and the second output signal during a rising edge of an input signal, or to raise the second output signal by VBS in response to the first output signal and the second output signal during a falling edge of an input signal; and The second circuit is used to raise the first output signal by VBS in response to the first output signal and the second output signal during the rising edge of the input signal, or to enter a charging state in response to the first output signal and the second output signal during the falling edge of the input signal.

2. The high-speed level conversion circuit according to claim 1, characterized in that: The in-phase and inverted signal output circuit is used to output a first output signal in phase with the input signal and a second output signal in phase with the input signal during the falling edge of the input signal; The level boosting circuit is used for entering a charging state and raising the second output signal to VBS in response to the first output signal and the second output signal; The substrate voltage regulating circuit is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal to quickly turn on the second NMOS transistor in the level conversion circuit, and to generate a negative pulse differential waveform to quickly turn off the first NMOS transistor in the level conversion circuit; The level conversion circuit is used for pulling the output voltage to the target level in response to the second NMOS tube being quickly turned on and the first NMOS tube being quickly turned off; as well as The inverting output buffer circuit is used to invert the output voltage to convert the target level into a low level 0.

3. The high-speed level conversion circuit according to claim 1 or 2, characterized in that: The in-phase and inverted signal output circuit is a clock edge adjustment circuit. The clock edge adjustment circuit is further used to align the center point of the rising edge of the first output signal with the falling edge of the second output signal, and to align the center point of the falling edge of the first output signal with the rising edge of the second output signal.

4. The high-speed level conversion circuit according to claim 1, characterized in that: The first circuit includes: a third NMOS transistor, a gate of the third NMOS transistor is connected to the first output signal, and a source of the third NMOS transistor is connected to the external bias voltage; a first capacitor, a first end of the first capacitor is connected to the drain of the third NMOS transistor, and a second end of the first capacitor is connected to the second output signal, The second circuit includes: a fourth NMOS tube, a gate of the fourth NMOS tube is connected to the second output signal, and a source of the fourth NMOS tube is connected to the external bias voltage; a second capacitor, a first end of which is connected to the drain of the fourth NMOS tube, and a second end of which is connected to the first output signal.

5. The high-speed level conversion circuit according to claim 4, characterized in that: The first circuit further includes: a fifth NMOS transistor, the source of the fifth NMOS transistor is connected to the drain of the third NMOS transistor, the drain of the fifth NMOS transistor is connected to the first end of the first capacitor, The second circuit further includes: a sixth NMOS transistor, a source of the sixth NMOS transistor is connected to a drain of the fourth NMOS transistor, and a drain of the sixth NMOS transistor is connected to a first end of the second capacitor.

6. The high-speed level conversion circuit according to claim 4, characterized in that: The first circuit further includes: a first resistor, a first end of the first resistor is connected to the drain of the third NMOS transistor, a second end of the first resistor is connected to the first end of the first capacitor, The second circuit further includes: a second resistor, a first end of the second resistor is connected to the drain of the fourth NMOS transistor, and a second end of the second resistor is connected to the first end of the second capacitor.

7. The high-speed level conversion circuit according to claim 4, characterized in that: A first end of the second capacitor is connected to a gate of a first NMOS transistor in the level conversion circuit; The first end of the first capacitor is connected to the gate of the second NMOS transistor in the level conversion circuit.

8. The high-speed level conversion circuit according to claim 7, characterized in that: The substrate voltage regulating circuit comprises: a first micro-branch, wherein an input end of the first micro-branch is connected to the first output signal, and an output end of the first micro-branch is connected to a substrate of a first NMOS tube in the level conversion circuit; and A second micro-branch, wherein an input end of the second micro-branch is connected to the second output signal, and an output end of the second micro-branch is connected to a substrate of a second NMOS tube in the level conversion circuit.

9. A chip, characterized in that: The chip comprises the high-speed level conversion circuit according to any one of claims 1-8.

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