Logic circuit and driving method thereof, digital chip and electronic equipment

Abstract

The embodiment of the invention provides a logic circuit and a driving method thereof, a digital chip and electronic equipment, relates to the technical field of transistors, and is used for reducing the power consumption of the logic circuit. The logic circuit comprises a first P-type transistor and a first N-type transistor, the control end of the first P-type transistor and the control end of the first N-type transistor are both connected with the input signal end, the first end of the first P-type transistor is connected with the power signal end, the second end of the first P-type transistor and the first end of the first N-type transistor are both connected with the output signal end, and the first end of the first N-type transistor is connected with the output signal end. The second end of the first N-type transistor is connected with the grounding end; the first P-type transistor and the first N-type transistor are super steep transistors; the voltage of an input signal transmitted by the input signal end and the voltage of an output signal transmitted by the output signal end are both smaller than the voltage of a power signal transmitted by the power signal end. The logic circuit can stably operate under the condition of non-full swing and is low in power consumption.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of transistor technology, and in particular to a logic circuit and a driving method thereof, a digital chip, and an electronic device. Background Art

[0002] The smallest unit in a logic circuit is a logic gate circuit, such as an AND gate, an OR gate, and a NOT gate. The logic gate circuit includes a complementary metal-oxide-semiconductor field effect transistor (CMOSFET). In the related art, there is a problem of high dynamic power consumption of CMOSFET. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a logic circuit and a driving method thereof, a digital chip and an electronic device.

[0004] In order to achieve the above purpose, the present application provides the following solutions:

[0005] On the one hand, a logic circuit is provided, comprising: a first P-type transistor and a first N-type transistor, wherein a control terminal of the first P-type transistor and a control terminal of the first N-type transistor are both connected to an input signal terminal, a first terminal of the first P-type transistor is connected to a power signal terminal, a second terminal of the first P-type transistor and a first terminal of the first N-type transistor are both connected to an output signal terminal, and a second terminal of the first N-type transistor is connected to a ground terminal; the first P-type transistor and the first N-type transistor are both super-steep transistors; and a voltage of an input signal transmitted by the input signal terminal and a voltage of an output signal transmitted by the output signal terminal are both less than a voltage of a power signal transmitted by the power signal terminal.

[0006] In the logic circuit provided by the embodiment of the present application, the first P-type transistor and the first N-type transistor are both super-steep transistors. In this way, the first P-type transistor and the first N-type transistor can realize switching characteristics under the control of a relatively small gate voltage (such as 0.5V-1V). On this basis, the voltage of the input signal transmitted by the input signal terminal and the voltage of the output signal transmitted by the output signal terminal can be controlled to be less than the voltage of the power signal transmitted by the power signal terminal. In this way, in combination with the characteristics of the super-steep transistor (i.e., the characteristics of the switch are realized under the control of a relatively small gate voltage), the logic circuit provided by the embodiment of the present application can operate in the case of an insufficient swing, thereby reducing the dynamic power consumption of the logic circuit.

[0007] In some embodiments, the input signal and the output signal are in anti-phase and both swing within a target voltage range; the lower limit of the target voltage range is greater than 0V, and the upper limit is less than the voltage of the power signal. This arrangement allows the input signal and the output signal to swing symmetrically within the target voltage range (i.e., in the case of a non-full swing), thereby forming a stable output voltage, and because the lower limit of the target voltage range is greater than 0V, and the upper limit is less than the voltage of the power signal, the first P-type transistor and the first N-type transistor both have a certain turn-on voltage, which is conducive to achieving a smaller gate voltage control for the first P-type transistor and the first N-type transistor.

[0008] In some embodiments, the lower limit of the target voltage range is equal to the difference between the voltage of the power signal and the upper limit of the target voltage range. In this way, the first P-type transistor and the first N-type transistor have the same turn-on voltage, which makes it easy to match the first P-type transistor and the first N-type transistor.

[0009] In some embodiments, the difference between the upper limit and the lower limit of the target voltage range is greater than 0.3 V, and the difference between the voltage of the power signal and the upper limit of the target voltage range is less than 1.8 V. This design enables the logic circuit to have a greater power consumption benefit when targeting a 28nm transistor node and Vdd=1.05V.

[0010] In some embodiments, the difference between the upper limit and the lower limit of the target voltage range is greater than 0.3 V, and the difference between the voltage of the power signal and the upper limit of the target voltage range is less than 1.05 V. This design enables the logic circuit to have a greater power consumption benefit when targeting 14nm transistor nodes and Vdd=0.8V.

[0011] In some embodiments, the difference between the upper limit and the lower limit of the target voltage range is greater than 0.3 V, and the difference between the voltage of the power signal and the upper limit of the target voltage range is less than 0.8 V. This design enables the logic circuit to have a greater power consumption benefit when targeting a 2nm transistor node and Vdd=0.7V.

[0012] In some embodiments, the logic circuit also includes a second P-type transistor and a second N-type transistor; the second N-type transistor is a super-steep transistor; the second P-type transistor is a non-super-steep transistor; the second P-type transistor is connected in series between the first end of the first P-type transistor and the power signal end; the second N-type transistor and the first N-type transistor are connected in parallel between the output signal end and the ground end; the control end of the second P-type transistor and the control end of the second N-type transistor are both connected to the first signal control end. In this embodiment, a first P-type transistor, a first N-type transistor, a second P-type transistor, and a second N-type transistor may form a NOR gate circuit, and since a non-super-steep transistor (ordinary pMOS) is connected in series near the power signal terminal and the others are super-steep transistors, the series route between the output signal terminal and the power signal terminal passes through and only passes through one super-steep transistor, that is, the voltage difference Vdmin=Vdd-V1 (here, Vdd is the voltage of the power signal, V1 is the upper limit value of the target voltage range, and the ordinary pMOS does not have a turn-on voltage difference) is only borne once by the super-steep transistor (P-type), so that the output signal terminal can be stabilized at V1 (such as the upper limit value of the target voltage range) when outputting a high voltage.

[0013] In some embodiments, the logic circuit also includes a third P-type transistor and a third N-type transistor; the third P-type transistor is a super-steep transistor; the third N-type transistor is a non-super-steep transistor; the third N-type transistor is connected in series between the second end of the first N-type transistor and the ground end; the third P-type transistor and the first P-type transistor are connected in parallel between the output signal end and the power supply signal end; the control end of the third N-type transistor and the control end of the third P-type transistor are both connected to the second signal control end.

[0014] In this embodiment, a first P-type transistor, a first N-type transistor, a second P-type transistor, and a second N-type transistor form a NOR gate circuit. In addition, since a non-super-steep transistor (ordinary nMOS) is connected in series near the ground terminal, and the others are all super-steep transistors, the series route between the output signal terminal and the ground terminal passes through and only passes through one super-steep transistor, that is, it only bears the voltage difference Vdmin=V0 (here, V0 is the lower limit value of the target voltage range, and the ordinary nMOS does not have a turn-on voltage difference) turned on by the super-steep transistor (N-type) once, so that the output signal terminal can be stabilized at V0 (such as the lower limit value of the target voltage range) when outputting a high voltage.

[0015] In some embodiments, the number of the super-steep transistors on each line between the power signal terminal and the output signal terminal, and the number of the super-steep transistors on each line between the ground terminal and the output signal terminal, are equal. For example, they can be one, two, or more. In this embodiment, the number of super-steep transistors passing through each line between the power signal terminal and the output signal terminal, and each line between the ground terminal and the output signal terminal is the same, so that they have the same voltage loss, so it is easier to achieve signal matching, so that, for example, the output signal terminal can be stabilized at V1 (such as the upper limit of the target voltage range) when outputting a high voltage, and the output signal terminal can be stabilized at V0 (such as the lower limit of the target voltage range) when outputting a high voltage.

[0016] In some embodiments, the ultra-steep transistor is configured to have a current greater than 10 when the gate voltage is less than 0.5 V and the source-drain voltage is less than 1 V and greater than the gate voltage. 4 Here, for example, the ultra-steep transistor can achieve this performance by applying pressure to the bottom gate (changing the bias voltage) and adjusting the gate work function. Furthermore, when applied to logic circuits, since the gate voltage can be smaller, it has higher sensitivity, which is conducive to further reducing power consumption.

[0017] In some embodiments, the IdVd curve of the ultra-steep transistor has a turn-on voltage greater than 0 V. Such a design allows the gate voltage of the ultra-steep transistor to be smaller, which is beneficial for further reducing power consumption when working under non-full swing conditions.

[0018] In some embodiments, the logic circuit includes any one of an inverter circuit, a cascade buffer circuit, a transmission gate circuit, a latch circuit, a trigger circuit, and a static random access memory circuit.

[0019] On the other hand, a driving method of a logic circuit is provided, which is applied to any of the above-mentioned logic circuits, and the driving method includes: controlling the voltage of the input signal transmitted by the input signal terminal and the voltage of the output signal transmitted by the output signal terminal to be smaller than the voltage of the power signal transmitted by the power signal terminal. In this way, the logic circuit provided in the embodiment of the present application can operate without full swing, thereby effectively reducing the dynamic power consumption of the logic circuit.

[0020] In another aspect, a digital chip is provided, comprising the logic circuit as described in any of the above embodiments. In this embodiment, since the digital chip comprises the logic circuit as described in any of the above embodiments, all the corresponding beneficial effects can be achieved, which will not be described in detail here.

[0021] On the other hand, an electronic device is provided, comprising a circuit board and a digital chip as described above, wherein the digital chip is mounted on the circuit board. In this embodiment, since the electronic device comprises a digital chip as described in any of the above embodiments, and the digital chip comprises a logic circuit as described in any of the above embodiments, all the corresponding beneficial effects can be achieved, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a graph showing the output current and gate-source voltage of the transistor under different conditions;

[0023] Figure 2 is a curve diagram of output current and gate-source voltage when a barrier lowering effect is introduced at the drain end of the transistor;

[0024] Figure 3 is a graph of the output current and source-drain voltage of the transistor;

[0025] Figure 4 Schematic diagram of super steep IdVg curve under different Vds conditions;

[0026] Figure 5 A structural diagram of a target ultra-steep transistor provided in an embodiment of the present application;

[0027] Figure 6 For a Figure 5 The structural diagram of the logic circuit composed of the target ultra-steep transistor;

[0028] Figure 7 A circuit diagram of a logic circuit provided in an embodiment of the present application;

[0029] Figure 8 for Figure 7 The vt relationship diagram of the logic circuit shown in the figure is when the swing is not full;

[0030] Fig. 9 for Figure 7 The Vin-Vout relationship diagram of the logic circuit shown in the figure under full swing and not full swing conditions;

[0031] Figure 10-11 for Figure 7 A schematic diagram of current matching between a first P-type transistor and a first N-type transistor in the logic circuit shown;

[0032] Fig.12 This is a schematic diagram of power consumption benefits when benchmarking 2nm transistor node and Vdd = 0.7V;

[0033] Fig.13 This is a schematic diagram of power consumption benefit when benchmarking 14nm transistor node and Vdd = 0.8V;

[0034] Fig.14 This is a schematic diagram of power consumption benefit when benchmarking 28nm transistor node and Vdd=1.05V;

[0035] Fig.15 Schematic diagram of frequency loss when Vdd = 0.7V for 2nm transistor node;

[0036] Fig.16 A schematic diagram showing the change of the output signal of the logic circuit provided in the embodiment of the present application over time in the full swing condition (Vdmin=0);

[0037] Fig.17 A schematic diagram showing the change of the output signal of the logic circuit provided in the embodiment of the present application over time in the case of insufficient swing (Vdmin=0.2);

[0038] Fig.18 The power-delay curves are shown in the two cases of full swing (Vdmin=0) and not full swing (Vdmin=0.2);

[0039] Fig.19 A structural diagram of another logic circuit provided in an embodiment of the present application;

[0040] Fig. 20 A structural diagram of another logic circuit provided in an embodiment of the present application;

[0041] Figure 21-22 Structural diagram of two logic circuits provided in the embodiments of the present application;

[0042] Fig.23 A structural block diagram of a digital chip provided in an embodiment of the present application;

[0043] Fig.24 A structural block diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0045] In the following, the terms "first", "second", etc. are used only for convenience of description and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0046] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "electrical connection" may refer to a direct electrical connection or an indirect electrical connection via an intermediate medium.

[0047] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0048] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0049] In the embodiments of the present application, directional indications such as up, down, left, right, front, and back, etc., used to explain the structure and movement of different components in the present application are relative. These indications are appropriate when the components are in the positions shown in the figures. However, if the description of the component position changes, then these directional indications will also change accordingly.

[0050] The following is a brief introduction to some concepts that may be involved in the embodiments of the present application.

[0051] Subthrehold Swing (SS): Subthrehold swing is a performance indicator that measures the rate of conversion between the on and off states of a transistor. It represents the change in gate voltage required for a tenfold change in source-drain current, also known as the S factor. The smaller the S, the faster the turn-on and turn-off rates.

[0052] Ultra-steep transistor: refers to a transistor with SS less than 60mV / decade at room temperature. Compared with ordinary transistors (transistors with SS greater than or equal to 60mV / decade), ultra-steep transistors can be realized by changing gate materials, channel materials, etc.

[0053] As Moore's Law approaches its limit, the development focus of transistor technology has shifted from increasing speed and reducing area to reducing power consumption. The dynamic power consumption of traditional CMOSFET is proportional to the square of the driving voltage (i.e., gate-source voltage). The main idea of ​​low-power transistors currently being focused on by the academic and industrial circles is to reduce the driving voltage and thus the dynamic power consumption by increasing the current turn-on speed in the subthreshold region (i.e., reducing SS). Related research is still being closely explored.

[0054] An important factor that makes it difficult to reduce the driving voltage is that a small gate voltage cannot control the rapid change of large transistor current / resistance. Figure 1-Figure 3 An electrical property graph of NMOS is shown. Figure 1 Graphs of the output current and gate-source voltage of the transistor under different circumstances show that, relative to the reference curve ref: the small Vth curve (i.e., the Vth of the transistor corresponding to the adjustment curve is smaller than the Vth of the transistor corresponding to the reference curve) shifts leftward, and the driving voltage Vdd of the transistor can be reduced when the driving current of the transistor remains almost unchanged; the small SS curve (i.e., the SS of the transistor corresponding to the adjustment curve is smaller than the SS of the transistor corresponding to the reference curve) becomes steeper in the subthreshold region, and the driving voltage Vdd of the transistor can also be reduced when the driving current of the transistor remains almost unchanged. Figure 2 This is a curve diagram of the output current and the gate-source voltage when the Drain Induced Barrier Lowering (DIBL) effect is introduced at the drain end of the transistor. It can be seen that, relative to the reference curve ref: the small Vds curve caused by the DIBL effect (that is, the Vds of the transistor corresponding to the adjustment curve is smaller than the Vds of the transistor corresponding to the reference curve) is slightly shifted to the right. At this time, when the driving voltage Vdd of the transistor remains unchanged, the driving current does not change much. Figure 3 The output current and source-drain voltage curve of the transistor are shown in Figure 2. Figure 1 and Figure 2 It can be seen that the decrease in gate voltage Vgs will cause a decrease in driving current, affecting performance; while the source-drain voltage Vds has a smaller effect on the current and tends to be more stable.

[0055] Figure 4 Schematic diagram of ultra-steep IdVg curve under different Vds conditions. The inventors of the present application further discovered that, under a relatively small source-drain voltage (e.g., less than 1V and greater than the gate voltage, corresponding to the solid curve in the figure), a very small gate voltage (e.g., less than 0.5V) can realize the switching of transistor current—a current or resistance change of more than 4 orders of magnitude, that is, a relatively large current switching ratio (e.g., greater than 10) can be achieved. 4 ). Hereinafter, the transistor having this characteristic is referred to as a target ultra-steep transistor. The target ultra-steep transistor is a type of ultra-steep transistor.

[0056] Figure 5A structural diagram of a target ultra-steep transistor provided in an embodiment of the present application. For example, taking the implementation on silicon-on-insulator (SOI) as an example, a metal or semi-metal can be used as the drain terminal (ie, D is the drain metal), and the Schottky barrier of the metal and semiconductor Si is used to guide the maximum electric field and the resulting ionization to the metal body-Si interface to form a target ultra-steep transistor.

[0057] Figure 6 For a Figure 5 The structure diagram of the logic circuit composed of the target ultra-steep transistor in FIG. The left side is a schematic diagram of the N-type transistor structure, and the right side is a schematic diagram of the P-type transistor structure. For example, G is the gate metal, D is the drain metal, and S is the source heavily doped Si (N + or P + , the doping ratio is greater than 1e20cm -3 ), the oxide below is the SOI self-contained oxide layer (box), for example, it can be SiO2, and the dielectric below G is a dielectric material. The channel is reverse doped about 1e18cm compared to the S end. -3 , such as 1e17cm -3 To 1e19cm -3 For example, for an N-type transistor, D may be a medium-low work function metal, maintaining the conduction band Schottky barrier between 0.2 eV and 0.6 eV; for a P-type transistor, D may be a medium-high work function metal, maintaining the valence band Schottky barrier between 0.2 eV and 0.6 eV.

[0058] Since the target ultra-steep transistor can be completed by a very small gate voltage Vg (such as less than 0.5V) and a small source-drain voltage Vds (such as less than 1V and greater than the gate voltage), the device is greater than 10 4 The current switching ratio is good, therefore, when it is applied to logic circuits (such as inverters, NAND gate circuits, NOR gate circuits, inverter circuits, cascade buffer circuits, transmission gate circuits, latch circuits, trigger circuits, and static random access memory circuits, etc.), it is beneficial to reduce the dynamic power consumption of logic circuits.

[0059] It should be noted that the realization of the above-mentioned ultra-steep transistor is not limited to Figure 5 and Figure 6 The Si system, planar structure, and single-gate process shown may also adopt a fin structure, a ring-gate structure, a double-gate structure, and the like.

[0060] Figure 7 FIG. 1 is a circuit diagram of a logic circuit 100 provided in an embodiment of the present application. Figure 7As shown, the logic circuit 100 provided in the embodiment of the present application includes: a first P-type transistor 1 and a first N-type transistor 2, the control terminal 1a of the first P-type transistor 1 and the control terminal 2a of the first N-type transistor 2 are both connected to the input signal terminal Q1, the first terminal 1b of the first P-type transistor 1 is connected to the power signal terminal Q2, the second terminal 1c of the first P-type transistor 1 and the first terminal 2b of the first N-type transistor 2 are both connected to the output signal terminal Q3, and the second terminal 2c of the first N-type transistor 2 is connected to the ground terminal Q4.

[0061] The first P-type transistor 1 and the first N-type transistor 2 are both super-steep transistors. In this way, the first P-type transistor 1 and the first N-type transistor 2 can realize switching characteristics under the control of a relatively small gate voltage (such as 0.5V-1V), which is beneficial to reduce the power consumption of the logic circuit. In some examples, the super-steep transistor here can be the target super-steep transistor mentioned above (that is, the device can be completed by a very small gate voltage Vg (such as less than 0.5V or even as small as 0.1V), a relatively small source-drain voltage Vds (such as less than 1V and greater than the gate voltage) greater than 10 4 The current switching ratio is 200), which has better control sensitivity and is conducive to reducing the power consumption of the logic circuit to a greater extent. On this basis, the voltage Vin of the input signal transmitted by the input signal terminal Q1 and the voltage Vout of the output signal transmitted by the output signal terminal Q3 can be controlled to be smaller than the voltage Vdd of the power signal transmitted by the power signal terminal Q2. In this way, the logic circuit provided in the embodiment of the present application can operate without full swing, thereby further reducing the dynamic power consumption of the logic circuit.

[0062] The logic circuit 100 provided in the embodiment of the present application is further introduced below.

[0063] exist Figure 7 In the logic circuit 100 shown, the voltage Vdd of the power signal can provide the voltage drop of the source and drain of the first P-type transistor 1 and the first N-type transistor 2, and can charge and discharge the load capacitor (connected to Vout, not shown); and the voltage Vin of the input signal is connected to the control terminal 1a of the first P-type transistor 1 and the control terminal 2a of the first N-type transistor 2, and the output voltage is changed by controlling the change of current or resistance. Based on the extremely small gate voltage of the above-mentioned super-steep transistor (further, it can be a target super-steep transistor) to realize the switching characteristics of the first P-type transistor 1 and the first N-type transistor 2, in this embodiment, the voltage Vin of the input signal transmitted by the input signal terminal Q1 and the voltage Vout of the output signal transmitted by the output signal terminal Q3 can be stably operated under the condition that both the voltage Vdd of the power signal transmitted by the power signal terminal Q2 are less than the voltage Vdd of the power signal transmitted by the power signal terminal Q2 (i.e., the full swing condition), so that the power consumption of the logic circuit 100 during operation is greatly reduced.

[0064] In some examples, the relationship between control voltage and time is as follows Figure 8 As shown, Figure 8 for Figure 7 The v (voltage) -t (time) relationship diagram of the logic circuit shown in the case of insufficient swing, the voltage Vin of the input signal and the voltage Vout of the output signal are between V0 (i.e., the lower limit of the target voltage range) and V1 (i.e., the upper limit of the target voltage range), and the difference is the signal swing Vswing. Fig. 9 for Figure 7 The Vin-Vout relationship diagram of the logic circuit in the full swing and partial swing conditions shown in the figure (wherein, curve L1 corresponds to the full swing condition, and curve L2 corresponds to the partial swing condition). It can be seen that in the partial swing condition, the distance between Vswing and the supply voltage is Vdmin (i.e., V0 or Vdd-V1, where V0 = Vdd-V1), which is the turn-on voltage of the transistor seen on the output characteristic curve. Curve L2 in the figure is the voltage transfer characteristics (VTC) curve, and Vout only swings within the range of Vswing. Curve L3 is the curve for exchanging Vin-Vout. The intersection of curves L2 and L3 is the stable point (i.e., the hexagonal star area). It can be seen that since the intersection of the input and output stable points is at V0 and V1, the signal can run stably below the supply voltage Vdd.

[0065] Figure 10-11 for Figure 7 The current matching diagram of the first P-type transistor 1 and the first N-type transistor 2 in the logic circuit shown in FIG. Fig.10 The output characteristic curve IdVd expressed in linear coordinates, Fig.11 is the transfer characteristic curve IdVg expressed in logarithmic coordinates. In some examples, the output characteristic curve IdVd and the transfer characteristic curve IdVg corresponding to the first P-type transistor 1 and the first N-type transistor 2 can be made as follows by applying a bottom gate voltage, adjusting a gate work function, changing a threshold voltage, etc. Figure 10-11 As shown. Fig.10 It can be seen that in the output characteristic curve IdVd, for N-type transistors, from left to right, they can be roughly divided into low current region, growth region and saturation region (for P-type transistors, from left to right, they are saturation region, growth region and low current region). When the voltage of the input signal is V1 and the voltage of the output signal is V0, the output characteristic curves of the first P-type transistor 1 and the first N-type transistor 2 have a stable intersection ( Fig.10 The hexagonal star area on the left); when the voltage of the input signal is V0 and the voltage of the output signal is V1, the output characteristic curves of the first P-type transistor 1 and the first N-type transistor 2 have another stable intersection ( Fig.10 The hexagonal area on the right). Fig.11 It can be seen that in the transfer characteristic curve IdVg, for N-type transistors, from left to right, they can be roughly divided into the turn-off region, the super steep region and the saturation region (for P-type transistors, from left to right, they are the saturation region, the super steep region and the turn-off region). When the voltage of the input signal is V1 and the voltage of the output signal is V0, the transfer characteristic curves of the first P-type transistor 1 and the first N-type transistor 2 have a stable intersection ( Fig.11 The hexagonal star area on the left); when the voltage of the input signal is V0 and the voltage of the output signal is V1, the transfer characteristic curves of the first P-type transistor 1 and the first N-type transistor 2 have another stable intersection ( Fig.11 The hexagonal star area on the right side). As described above, the input-output matching of the first P-type transistor 1 and the first N-type transistor 2 is achieved, and the current is very small, satisfying the low static power consumption characteristic of CMOS.

[0066] From the above analysis, it can be seen that in the embodiment of the present application, for transistors that only need a very small Vgs change to complete a large current (resistance) change, when Vdd is difficult to drop, a small Vgs change (i.e., Vswing) can be used to complete signal differentiation and reduce dynamic power consumption. From the previous signal voltage diagram, it can be seen that the voltage of the load circuit only swings within the range of Vswing (i.e., V1-V0), and the corresponding charge change is C L ·Vswing. Although the energy stored in the capacitor is L V1 2 and C L V0 2 However, considering the energy loss in the circuit, the energy consumption in a signal conversion cycle is always equal to the voltage multiplied by the charge transfer, that is, C L ·Vdd·Vswing.

[0067] In the case where a circuit switch can be realized with a smaller gate voltage, if there is no turn-on voltage on the IdVd curve, that is, when Vdmin = 0V, the circuit operates at full swing, and the dynamic power consumption returns to the traditional formula, which is proportional to Vdd 2 .

[0068] In the operation of the circuit of the embodiment of the present application, the voltage Vdd of the power signal transmitted by the power signal terminal Q2 is kept higher than the voltage Vin of the input signal transmitted by the input signal terminal Q1, and higher than the voltage Vout of the output signal transmitted by the output signal terminal Q3, so as to operate in a non-full swing mode. Thus, dynamic power consumption can be effectively reduced.

[0069] Fig.12It is a schematic diagram of power consumption benefit when benchmarking 2nm transistor nodes and Vdd=0.7V, wherein the horizontal axis is the voltage swing Vswing of the input signal, and the vertical axis is the distance between Vswing and the voltage of the power signal (ie, the supply voltage) is Vdmin. Fig.13 This is a schematic diagram of power consumption benefits when benchmarking 14nm transistor node and Vdd=0.8V. Fig.14 This is a power consumption benefit diagram for 28nm transistor nodes and Vdd=1.05V. The horizontal axis is the voltage swing Vswing of the input signal, and the vertical axis is the voltage Vdd of the power supply signal, (Vdd-Vswing) / 2=Vdmin. Since the power consumption of the embodiment of the present application is proportional to Vdd×Vswing, on the one hand, Vswing can be reduced while ensuring signal stability, and on the other hand, the power supply voltage Vdd can be reduced, thereby achieving the purpose of reducing power consumption. Compared with the traditional solution that is proportional to the square of the driving voltage, it can be seen that Fig.12 In the case where Vswing is greater than 0.3V and Vdmin is less than 0.8V, there is a large profit margin (as shown in the dotted box in the figure, more than 50% of power consumption can be saved); Fig.13 In the example, when Vswing is greater than 0.3V and Vdd is less than 2.4V (i.e., Vdmin is less than 1.05V), there is a large profit margin (as shown in the dotted box in the figure); Fig.14 In the example, when Vswing is greater than 0.3V and Vdd is less than 4V (ie, Vdmin is less than 1.8V), there is a large profit margin (as shown in the dotted box in the figure).

[0070] Fig.15 This is a diagram of the frequency loss when benchmarking 2nm transistor nodes and Vdd=0.7V. The horizontal axis is the voltage swing Vswing of the input signal, the vertical axis is the ratio of the on-state current Ion (relative to the full swing situation), and the curve represents the frequency ratio corresponding to the ratio of the on-state current Ion. Among them, while reducing power consumption, in order to keep the frequency without loss or very small loss (such as more than 100%), the on-state current Ion can be designed to reach more than 50% of the corresponding 2nm transistor (that is, the on-state current Ion ratio is greater than 0.5). When benchmarking more "backward" nodes, such as 28nm and 14nm, the corresponding Vdd is 1.05V and 0.8V respectively. Keeping the on-state current Ion more than 50% of the corresponding node transistor can also maintain the frequency while increasing power consumption.

[0071] Fig.16 A schematic diagram showing the change of the output signal of the logic circuit provided in the embodiment of the present application over time in the full swing condition (Vdmin=0), Fig.17The following is a schematic diagram of the output signal of the logic circuit provided in the embodiment of the present application changing with time under the condition of insufficient swing (Vdmin=0.2). It can be seen that under the condition of insufficient swing, the output signal can swing stably between 0.2V-0.6V, so the logic circuit 100 provided in the embodiment of the present application can be used stably.

[0072] Fig.18 The power-delay curves are shown in Table 1 for the full swing (Vdmin = 0) and the under-swing (Vdmin = 0.2). Fig.18 A table of parameters for each point on each curve in .

[0073] Table 1

[0074]

[0075] Depend on Fig.18 It can be seen from Table 1 that when the logic circuit 100 of the embodiment of the present application operates under the condition of full swing, the power corresponding to the horizontal axis is smaller, and the delay corresponding to the vertical axis is also smaller in most cases, so it has advantages in power consumption and delay.

[0076] Fig.19 This is a structural diagram of another logic circuit 100 provided in an embodiment of the present application. In some embodiments, as Fig.19 As shown, the logic circuit 100 also includes a second P-type transistor 3 and a second N-type transistor 4. The second P-type transistor 3 is connected in series between the first terminal 1b of the first P-type transistor 1 and the power signal terminal Q2; the second N-type transistor 4 is connected in parallel with the first N-type transistor 2 between the output signal terminal Q3 and the ground terminal Q4; the control terminal 3a of the second P-type transistor 3 and the control terminal 4a of the second N-type transistor 4 are both connected to the first signal control terminal Q5. Among them, the second P-type transistor 3 is a non-supersteep transistor, and the second N-type transistor 4 is a supersteep transistor.

[0077] In this embodiment, a first P-type transistor 1, a first N-type transistor 2, a second P-type transistor 3, and a second N-type transistor 4 may form a NOR gate circuit, and since a non-super-steep transistor (ordinary pMOS) is connected in series near the power signal terminal Q2, and the others are all super-steep transistors, the series route between the output signal terminal Q3 and the power signal terminal Q2 passes through and only passes through one super-steep transistor, that is, it only bears the voltage difference Vdmin=Vdd-V1 (here, Vdd is the voltage of the power signal, V1 is the upper limit value of the target voltage range, and the ordinary pMOS does not have a turn-on voltage difference) turned on by the super-steep transistor (P-type) once, so that the output signal terminal Q3 can be stabilized at V1 (such as the upper limit value of the target voltage range) when outputting a high voltage.

[0078] Table 2 Fig.19There are four working conditions corresponding to the embodiment of the present invention.

[0079] Table 2

[0080]

[0081] It can be seen from Table 2 that when Vin=V1, Vin1=V0, the second P-type transistor 3 is in the off state. However, since the second P-type transistor 3 is a non-super-steep transistor, the off effect is not very good compared to the super-steep transistor, so there will be a small leakage from VA to VDD at this time, so there will be a small increase in leakage in the 1 / 4 working interval (that is, when Vin=V1, Vin1=V0), and other benefits are inherited from the previous Figure 7 The circuit shown.

[0082] Fig. 20 A structural diagram of another logic circuit provided in an embodiment of the present application. In some embodiments, as Fig. 20 As shown, the logic circuit also includes a third P-type transistor 5 and a third N-type transistor 6. The third P-type transistor 5 is a super-steep transistor, and the third N-type transistor 6 is a non-super-steep transistor. The third N-type transistor 6 is connected in series between the second terminal 2c of the first N-type transistor 1 and the ground terminal Q4; the third P-type transistor 5 is connected in parallel with the first P-type transistor 1 between the output signal terminal Q3 and the power signal terminal Q2; the control terminal 6a of the third N-type transistor 6 and the control terminal 5a of the third P-type transistor 5 are both connected to the second signal control terminal Q6.

[0083] In this embodiment, a NOR gate circuit is formed by a first P-type transistor 1, a first N-type transistor 2, a second P-type transistor 3, and a second N-type transistor 4. In addition, since a non-super-steep transistor (ordinary nMOS) is connected in series near the ground terminal Q4, and the others are all super-steep transistors, the series route between the output signal terminal Q3 and the ground terminal Q4 passes through and only passes through one super-steep transistor, that is, it only bears the voltage difference Vdmin=V0 (here, V0 is the lower limit value of the target voltage range, and the ordinary nMOS does not have a turn-on voltage difference) turned on by the super-steep transistor (N-type) once, so that the output signal terminal Q3 can be stabilized at V0 (such as the lower limit value of the target voltage range) when outputting a high voltage.

[0084] Figure 21-22 The following are structural diagrams of two logic circuits provided in the embodiments of the present application. Fig.21 As a latch circuit, it can be regarded as two Figure 7 The circuits shown are connected in series; Fig. 22 This is an SR trigger circuit using a NAND gate. It can be seen that R is the reset terminal, S is the trigger terminal, Q and There are two output terminals.

[0085] The above are only some embodiments of the logic circuit provided by the present application. It can be understood that the present application may include, for example, but is not limited to other more complex logic gates using inverter circuits (inverter), NAND gate circuits (Nand), or NOT gate circuits (Nor), such as cascade buffer circuits (cascade buffer), transmission gate circuits (transmission gate), latch circuits (latch), trigger circuits (RS flip flop), 6T0C static random access memory circuits (6T0C SRAM, where "T" represents transistors and "C" represents capacitors), etc., which can be replaced using the above method.

[0086] In summary, the circuit design scheme based on the new ultra-steep transistor can effectively improve the profit space of dynamic power consumption. For example, it can have at least the following beneficial effects: 1. Rapid turn-on reduces short-circuit current (I short ) and delay; 2. Steep current, large gain, large relative noise margin or signal eye diagram area; 3. Dynamic power consumption decreases linearly with load capacitance and gate voltage; 4. Gate charge C L △Vgs drop leads to decreased delay; 5. Low gate capacitance requirement and reduced process difficulty.

[0087] Based on the above logic circuit embodiment, the present application embodiment further provides a digital chip 200, Fig.23 This is a structural block diagram of a digital chip 200 provided in an embodiment of the present application. The digital chip 200 may include one or more logic circuits 100 described in the previous embodiment. The digital chip 200 may inherit the power consumption benefits described above.

[0088] The embodiment of the present application further provides an electronic device 300, Fig.24 The electronic device 300 is a block diagram of the structure of the electronic device 300 provided in the embodiment of the present application. The electronic device 300 can be a mobile terminal such as a mobile phone, a tablet computer, a handheld computer, a personal digital assistant (PDA), a smart home device such as a smart TV, a smart camera, a wearable device such as a smart bracelet, a smart watch, and smart glasses, or other desktop, laptop, notebook computer, ultra-mobile personal computer (UMPC), netbook, smart screen and other devices. The electronic device 300 includes a circuit board 301 and the above-mentioned digital chip 200. The digital chip 200 is arranged on the circuit board 301, and the digital chip 200 can be interconnected with other components (such as a display screen, etc.) through the lines on the circuit board 301, and the digital chip 200 can realize at least one function such as calculation, storage and control.

[0089] The electronic device 300 provided in the embodiment of the present application includes the digital chip 200 having the logic circuit 100 described in the previous embodiment, and therefore has all the corresponding beneficial effects described above, which will not be described in detail here.

[0090] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A logic circuit, characterized in that: include: a first P-type transistor and a first N-type transistor, wherein a control terminal of the first P-type transistor and a control terminal of the first N-type transistor are both connected to an input signal terminal, a first terminal of the first P-type transistor is connected to a power signal terminal, a second terminal of the first P-type transistor and a first terminal of the first N-type transistor are both connected to an output signal terminal, and a second terminal of the first N-type transistor is connected to a ground terminal; The first P-type transistor and the first N-type transistor are both super-steep transistors; the voltage of the input signal transmitted by the input signal terminal and the voltage of the output signal transmitted by the output signal terminal are both smaller than the voltage of the power signal transmitted by the power signal terminal.

2. The logic circuit according to claim 1, characterized in that: The input signal and the output signal are in anti-phase and both swing within a target voltage range; a lower limit value of the target voltage range is greater than 0V, and an upper limit value is less than the voltage of the power supply signal.

3. The logic circuit according to claim 2, characterized in that: The lower limit value of the target voltage range is equal to the difference between the voltage of the power signal and the upper limit value of the target voltage range.

4. The logic circuit according to claim 2 or 3, characterized in that: The difference between the upper limit value and the lower limit value of the target voltage range is greater than 0.3V, and the difference between the voltage of the power signal and the upper limit value of the target voltage range is less than 1.8V.

5. The logic circuit according to claim 4, characterized in that: The difference between the voltage of the power signal and the upper limit of the target voltage range is less than 1.05V.

6. The logic circuit according to claim 4, characterized in that: The difference between the voltage of the power signal and the upper limit value of the target voltage range is less than 0.8V.

7. The logic circuit according to claim 1, characterized in that: It also includes a second P-type transistor and a second N-type transistor; the second N-type transistor is a super-steep transistor; the second P-type transistor is a non-super-steep transistor; The second P-type transistor is connected in series between the first end of the first P-type transistor and the power signal end; The second N-type transistor and the first N-type transistor are connected in parallel between the output signal terminal and the ground terminal; The control end of the second P-type transistor and the control end of the second N-type transistor are both connected to the first signal control end.

8. The logic circuit according to claim 1, characterized in that: It also includes a third P-type transistor and a third N-type transistor; the third P-type transistor is a super-steep transistor; the third N-type transistor is a non-super-steep transistor; The third N-type transistor is connected in series between the second end of the first N-type transistor and the ground end; The third P-type transistor is connected in parallel with the first P-type transistor between the output signal terminal and the power signal terminal; The control end of the third N-type transistor and the control end of the third P-type transistor are both connected to the second signal control end.

9. The logic circuit according to any one of claims 1 to 8, characterized in that: The number of the super-steep transistors on each line between the power signal terminal and the output signal terminal, and the number of the super-steep transistors on each line between the ground terminal and the output signal terminal are equal.

10. The logic circuit according to any one of claims 1 to 9, characterized in that: The ultra-steep transistor is configured to have a voltage greater than 10 when the gate voltage is less than 0.5 V and the source-drain voltage is less than 1 V and greater than the gate voltage. 4 The current switching ratio.

11. The logic circuit according to any one of claims 1 to 10, characterized in that: The IdVd curve of the ultra-steep transistor has a turn-on voltage greater than 0V.

12. The logic circuit according to any one of claims 1 to 11, characterized in that: The logic circuit includes any one of an inverter circuit, a cascade buffer circuit, a transmission gate circuit, a latch circuit, a trigger circuit, and a static random access memory circuit.

13. A method for driving a logic circuit, characterized in that: Applied to the logic circuit according to any one of claims 1 to 12, the driving method comprises: The voltage of the input signal transmitted by the input signal terminal and the voltage of the output signal transmitted by the output signal terminal are controlled to be smaller than the voltage of the power signal transmitted by the power signal terminal.

14. The driving method according to claim 13, characterized in that: The ultra-steep transistor is configured to have a voltage greater than 10 when the gate voltage is less than 0.5 V and the source-drain voltage is less than 1 V and greater than the gate voltage. 4 The current switching ratio.

15. A digital chip, characterized in that: Comprising the logic circuit as claimed in any one of claims 1-12.

16. An electronic device, characterized in that: The invention comprises a circuit board and the digital chip as claimed in claim 15, wherein the digital chip is mounted on the circuit board.

Images