Panel frame rate switching method and switching system
By using FPGA and phase-locked loop in the switching system to calculate and configure a new pixel clock, the problem of inaccurate delay and synchronization during frame rate switching in the prior art is solved, and stable frame rate switching is achieved and the possibility of picture flicker is reduced.
Patent Information
- Application Number
- CN202510078591.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-17
- Publication Date
- 2025-04-29
AI Technical Summary
When switching between panel frame rate in high frame rates and dynamic scenarios in the prior art, it may lead to inaccurate delay and synchronization, resulting in flashing or instability of the picture.
The application of FPGA in the switching system, using DDR memory and phase-locked loops, a new pixel clock is calculated and configured to ensure that the clock frequency at the target frame rate is consistent with the rest of the system.
The timing consistency during frame rate switching is achieved, and the screen flickering problem is avoided due to clock jump or out-of-synchronization, which significantly reduces the possibility of screen flickering when the panel switches frame rate.
Smart Images
Figure CN119906848A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of image and video processing technology, and in particular to a panel frame rate switching method and switching system. Background Art
[0002] In modern display technology, especially for high-resolution and high-frame-rate display panels, the panel's frame rate switching technology has a crucial impact on display effects and user experience. In order to improve display quality and response speed, the panel often needs to automatically switch the frame rate according to the application scenario. Frame rate switching can be performed in various scenarios. For example, when displaying different content such as video playback and game screen rendering, frame rate switching is frequently performed to adapt to different processing requirements.
[0003] In the prior art, the frame rate switching of the display panel usually relies on the controller to adjust the clock frequency to adapt to different display requirements. When switching the frame rate, the controller needs to synchronize the display content by adjusting the timing and refresh rate of the video signal. However, in high frame rates and dynamic scenes, the adjustment of the clock frequency and timing usually causes a certain delay, which may make the frame rate switching process unable to be completed in time. This delay and inaccurate synchronization will cause the display panel to flicker or be unstable when switching the frame rate. Summary of the invention
[0004] The embodiments of the present application provide a panel frame rate switching method and switching system, which can reduce the possibility of screen flickering when the panel switches the frame rate.
[0005] A first aspect of an embodiment of the present application provides a method for panel frame rate switching, the method being applied to a switching system, the switching system comprising an FPGA, a DDR memory, and two independent first phase-locked loops and a second phase-locked loop, the method comprising:
[0006] The FPGA intercepts frame data from the LVDS video stream and stores the frame data in the DDR memory according to a pre-configured resolution;
[0007] The FPGA reads the frame data from the DDR memory according to the first pixel clock in the first phase-locked loop and outputs the frame data to the target panel;
[0008] When receiving a first frame rate switching instruction, the FPGA determines a first target frame rate according to the first frame rate switching, and calculates a second pixel clock corresponding to the first target frame rate based on a current frame rate, the first target frame rate and the first pixel clock;
[0009] The FPGA configures the second pixel clock into a second phase-locked loop;
[0010] The FPGA reads the frame data from the DDR memory according to the second pixel clock in the second phase-locked loop and outputs the frame data to the target panel.
[0011] Optionally, the FPGA reads the frame data from the DDR memory and outputs the frame data to the target panel according to the second pixel clock in the second phase-locked loop, comprising:
[0012] The FPGA disconnects the first pixel clock and the RGB pixel clock in the first phase-locked loop;
[0013] The FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock;
[0014] The FPGA reads the frame data from the DDR memory according to the RGB pixel clock and outputs the frame data to the target panel.
[0015] Optionally, the FPGA disconnecting the first pixel clock and the RGB pixel clock in the first phase-locked loop includes:
[0016] The FPGA determines a rising edge and a falling edge of a clock corresponding to a current frame according to the first pixel clock;
[0017] When the rising edge of the clock ends, the FPGA disconnects the first pixel clock and the RGB pixel clock in the first phase-locked loop;
[0018] The FPGA connects the second pixel clock in the second phase-locked loop with the RGB pixel clock, comprising:
[0019] Before the falling edge of the clock ends, the FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock.
[0020] Optionally, after the FPGA reads the frame data from the DDR memory according to the second pixel clock in the second phase-locked loop and outputs the frame data to the target panel, the method further includes:
[0021] The FPGA acquires the actual frame rate of the target panel;
[0022] The FPGA determines whether a frame rate difference between the actual frame rate and the first target frame rate is within an error threshold range;
[0023] If so, the FPGA determines that the frame rate switching is successful.
[0024] Optionally, after the FPGA reads the frame data from the DDR memory according to the second pixel clock in the second phase-locked loop and outputs the frame data to the target panel, the method further includes:
[0025] When receiving the second frame rate switching instruction, the FPGA determines the second target frame rate according to the second frame rate switching, and calculates a third pixel clock corresponding to the second target frame rate based on the first target frame rate, the second target frame rate and the second pixel clock;
[0026] The FPGA configures the third pixel clock into a first phase-locked loop;
[0027] The FPGA reads the frame data from the DDR memory according to the third pixel clock in the first phase-locked loop and outputs the frame data to the target panel.
[0028] Optionally, it is characterized in that, before the FPGA intercepts frame data from the LVDS video stream, the method further includes:
[0029] The FPGA determines the frame data by detecting the rising edge of the Vsync signal of the LVDS video stream.
[0030] Optionally, the FPGA intercepting frame data from the LVDS video stream includes:
[0031] The FPGA intercepts frame data from the LVDS video stream at intervals of one frame.
[0032] A second aspect of an embodiment of the present application provides a switching system, the switching system comprising an FPGA, a DDR memory, two independent first phase-locked loops and a second phase-locked loop, the FPGA comprising:
[0033] An interception unit, used for intercepting frame data from the LVDS video stream, and storing the frame data in the DDR memory according to a pre-configured resolution;
[0034] A first output unit, configured to read the frame data from the DDR memory and output the frame data to a target panel according to a first pixel clock in the first phase-locked loop;
[0035] a calculation unit, configured to, when receiving a first frame rate switching instruction, determine a first target frame rate according to the first frame rate switching, and calculate a second pixel clock corresponding to the first target frame rate based on a current frame rate, the first target frame rate and the first pixel clock;
[0036] A configuration unit, configured to configure the second pixel clock into a second phase-locked loop;
[0037] The second output unit is used to read the frame data from the DDR memory and output the frame data to the target panel according to the second pixel clock in the second phase-locked loop.
[0038] Optionally, the second output unit includes:
[0039] A disconnection module, used to disconnect the first pixel clock and the RGB pixel clock in the first phase-locked loop;
[0040] A connection module, used for connecting the second pixel clock in the second phase-locked loop to the RGB pixel clock;
[0041] An output module is used to read the frame data from the DDR memory according to the RGB pixel clock and output the frame data to the target panel.
[0042] Optionally, the disconnection module is specifically used for:
[0043] The FPGA determines a rising edge and a falling edge of a clock corresponding to a current frame according to the first pixel clock;
[0044] When the rising edge of the clock ends, the FPGA disconnects the first pixel clock and the RGB pixel clock in the first phase-locked loop;
[0045] The connection module is specifically used for:
[0046] Before the falling edge of the clock ends, the FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock.
[0047] Optionally, the FPGA further includes:
[0048] An acquisition unit, used for the FPGA to acquire an actual frame rate of the target panel;
[0049] A judging unit, configured for the FPGA to judge whether a frame rate difference between the actual frame rate and the first target frame rate is within an error threshold range;
[0050] The first determining unit is configured to determine that the frame rate switching is successful when the judging unit determines that the frame rate difference is within the error threshold range.
[0051] Optionally, the FPGA further includes a switching unit, and the switching unit is used to:
[0052] When a second frame rate switching instruction is received, determining a second target frame rate according to the second frame rate switching, and calculating a third pixel clock corresponding to the second target frame rate based on the first target frame rate, the second target frame rate and the second pixel clock;
[0053] configuring the third pixel clock into the first phase-locked loop;
[0054] According to the third pixel clock in the first phase-locked loop, the frame data is read from the DDR memory and output to the target panel.
[0055] Optionally, the FPGA further includes:
[0056] The second determining unit is used to determine the frame data by detecting the rising edge of the Vsync signal of the LVDS video stream.
[0057] Optionally, the interception unit is specifically used for:
[0058] The FPGA intercepts frame data from the LVDS video stream at intervals of one frame.
[0059] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:
[0060] In an embodiment of the present application, the FPGA calculates a new pixel clock based on the current frame rate and the target frame rate, which ensures that the pixel clock frequency at the target frame rate is consistent with the clock frequency of other parts of the system, avoiding unstable image display due to clock frequency mismatch. Subsequently, the FPGA configures the calculated second pixel clock into the second phase-locked loop to generate a stable clock signal for subsequent data reading. Finally, the FPGA stably reads the video frame data based on the new clock signal and outputs it to the target panel. Through this precise clock adjustment mechanism, the panel can ensure timing consistency when switching frame rates, avoid screen flickering problems caused by clock jumps or asynchronism, and significantly reduce the possibility of screen flickering when the panel switches frame rates. BRIEF DESCRIPTION OF THE DRAWINGS
[0061] Figure 1 A schematic diagram of the structure of an embodiment of a switching system in an embodiment of the present application;
[0062] Figure 2 A schematic diagram of a flow chart of an embodiment of a method for switching a panel frame rate in an embodiment of the present application;
[0063] Figure 3 This is a flow chart of an embodiment of reading frame data from a DDR memory according to a second pixel clock in an embodiment of the present application;
[0064] Figure 4 A schematic diagram of a flow chart of an embodiment of disconnecting the first pixel clock from the RGB pixel clock in an embodiment of the present application;
[0065] Figure 5A flowchart of an embodiment of determining whether the frame rate is switched successfully in the embodiment of the present application;
[0066] Figure 6 A schematic diagram of a flow chart of an embodiment of switching the second target frame rate in an embodiment of the present application;
[0067] Figure 7 It is a structural diagram of another embodiment of the switching system in the embodiment of the present application. DETAILED DESCRIPTION
[0068] The embodiments of the present application provide a panel frame rate switching method and a switching system for reducing the possibility of screen flickering when the panel switches frame rates.
[0069] The embodiments of the present application will be described below in conjunction with the accompanying drawings.
[0070] See also Figure 1 , the switching system in the embodiment of the present application includes:
[0071] FPGA 101, DDR memory 102, two independent first phase-locked loops 102 and second phase-locked loops 103;
[0072] The FPGA 101 is connected to the DDR memory 102 , two independent first phase-locked loops 102 and second phase-locked loops 103 , respectively.
[0073] See also Figure 2 The panel frame rate switching method in the embodiment of the present application is applied to Figure 1 The switching system shown, an embodiment of a panel frame rate switching method includes:
[0074] 201. FPGA intercepts frame data from the LVDS video stream and stores the frame data in the DDR memory according to a pre-configured resolution;
[0075] The connection between FPGA, DDR memory and two phase-locked loops ensures efficient data transmission and synchronization. FPGA extracts frame data from the received LVDS video stream and stores the data according to the set resolution in the DDR memory. The purpose of storage is to provide a buffer area for subsequent data reading, processing and display, ensuring that data will not be lost and can be read efficiently at the right time. The phase-locked loop is used to generate a synchronous clock to ensure that the video data reading and transmission are accurately connected with the timing of the display device.
[0076] 202. The FPGA reads frame data from the DDR memory according to the first pixel clock in the first phase-locked loop and outputs the frame data to the target panel;
[0077] FPGA controls data reading and output through the first pixel clock signal in the first phase-locked loop, ensuring that data can be transmitted to the display panel at precise time intervals. Through the first pixel clock, FPGA can stably extract the stored frame data from the DDR memory and output the data to the target panel in the correct order. Due to the synchronization of the clock signal, the output data can be accurately matched with the refresh rate and display resolution of the display device, ensuring a stable and smooth display effect.
[0078] 203. When receiving the first frame rate switching instruction, the FPGA determines the first target frame rate according to the first frame rate switching, and calculates the second pixel clock corresponding to the first target frame rate based on the current frame rate, the first target frame rate and the first pixel clock;
[0079] After receiving the frame rate switching instruction, the FPGA needs to recalculate the clock frequency to support the new display requirements. First, the FPGA determines the new target frame rate (first target frame rate), which is usually input by the system or user. On this basis, the FPGA calculates the new second pixel clock frequency based on the current frame rate, target frame rate and first pixel clock. This new pixel clock will match the target frame rate to ensure that data reading and display can be synchronized to the new frame rate.
[0080] 204. The FPGA configures the second pixel clock into the second phase-locked loop;
[0081] After calculating the new second pixel clock, the FPGA will pass the clock signal to the second phase-locked loop for clock configuration and synchronization. The second phase-locked loop will generate a new synchronization clock based on the newly input clock signal so that the system can work stably at the new frame rate. This configuration process ensures that the clock frequency is completely consistent with the target frame rate, thereby ensuring the correctness and stability of subsequent data transmission.
[0082] 205. The FPGA reads frame data from the DDR memory according to the second pixel clock in the second phase-locked loop and outputs the frame data to the target panel.
[0083] After receiving the second pixel clock signal provided by the second phase-locked loop, the FPGA will re-read the frame data from the DDR memory according to the new clock frequency, and transmit the data to the target panel at the new frame rate. This process ensures that even after the frame rate is switched, the video stream can maintain stable output and can be displayed smoothly at the new frame rate, avoiding freezes or unsmooth images.
[0084] In this embodiment, the FPGA calculates a new pixel clock based on the current frame rate and the target frame rate, which ensures that the pixel clock frequency at the target frame rate is consistent with the clock frequency of other parts of the system, avoiding unstable image display due to clock frequency mismatch. Subsequently, the FPGA configures the calculated second pixel clock into the second phase-locked loop to generate a stable clock signal for subsequent data reading. Finally, the FPGA stably reads the video frame data based on the new clock signal and outputs it to the target panel. Through this precise clock adjustment mechanism, the panel can ensure timing consistency when switching frame rates, avoiding screen flickering problems caused by clock jumps or asynchronism, and significantly reducing the possibility of screen flickering when the panel switches frame rates.
[0085] See also Figure 3 In some embodiments of the present application, in step 205 in the above embodiment, the FPGA reads frame data from the DDR memory and outputs it to the target panel according to the second pixel clock in the second phase-locked loop, which may include the following steps:
[0086] 301. FPGA disconnects the first pixel clock and the RGB pixel clock in the first phase-locked loop;
[0087] The FPGA will first disconnect the connection between the first pixel clock and the RGB pixel clock in the first phase-locked loop. The RGB pixel clock is the time reference for controlling the display of each pixel on the display panel. The first pixel clock and the RGB pixel clock are originally synchronized, but when switching the frame rate, the system clock needs to be switched from the first pixel clock to the second pixel clock. Therefore, the purpose of disconnection is to isolate the old clock signal to prevent it from continuing to interfere with the new clock signal. This ensures that the first pixel clock no longer affects the subsequent video output, avoids the conflict between the two clock signals, and provides preparation for the subsequent connection of the second pixel clock.
[0088] 302. FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock;
[0089] After disconnecting the first pixel clock, the FPGA reconnects the second pixel clock in the second phase-locked loop to the RGB pixel clock. The key to this step is to ensure that the timing of the second pixel clock can accurately drive the RGB pixel clock so that the video output can run stably at the new frame rate. The second pixel clock has been calculated based on the new target frame rate, and this clock signal will become the new reference signal to control the update cycle of the display panel. By connecting the second pixel clock to the RGB pixel clock, the system can achieve clock synchronization after the frame rate switch, ensuring that the new pixel clock does not have timing errors during the display process, and ensuring the continuity and stability of the image display.
[0090] 303. FPGA reads frame data from DDR memory according to RGB pixel clock and outputs it to the target panel.
[0091] After completing the clock connection, the FPGA starts to read frame data from the DDR memory according to the new RGB pixel clock. The RGB pixel clock serves as a new clock signal to ensure that the data reading and display cycle matches the new frame rate. The FPGA outputs the read frame data to the target panel in the correct timing to update the image display. At this point, the system works at the new frame rate, and the image can be displayed smoothly on the target device, thereby ensuring the stable output of the system after the frame rate switch. The data reading and display timing have been synchronized according to the new pixel clock, avoiding display anomalies caused by clock mismatch, such as flickering, freezes, etc., and ensuring the stable display of the picture.
[0092] In this embodiment, accurate clock switching ensures that when the frame rate is changed, the video data can be smoothly transmitted to the display device, and the consistency and high quality of the image output are guaranteed.
[0093] See also Figure 4 In some embodiments of the present application, in step 301 in the above embodiment, the FPGA disconnects the first pixel clock in the first phase-locked loop from the RGB pixel clock, which may include the following steps:
[0094] 401. FPGA determines a rising edge and a falling edge of a clock corresponding to a current frame according to a first pixel clock;
[0095] Before disconnecting, the FPGA first determines the timing of the current frame through the first pixel clock. The pixel clock usually has a rising edge and a falling edge, which are used to define the boundaries of data transmission. In this step, the FPGA identifies the rising and falling edges of the clock corresponding to the data of the current frame by analyzing the first pixel clock signal. The rising and falling edges are usually used to synchronize the reading and display of video data, so accurately grasping these moments is crucial for subsequent clock switching.
[0096] 402. When the rising edge of the clock ends, the FPGA disconnects the first pixel clock and the RGB pixel clock in the first phase-locked loop;
[0097] Next, at the end of the rising edge of the first pixel clock, the FPGA immediately disconnects the first pixel clock in the first phase-locked loop from the RGB pixel clock. The timing of the disconnection is usually after the rising edge of the clock ends, because at this moment, the reading and display of the data have been completed, and the clock switching can be performed safely to avoid interference during data transmission. By disconnecting at this critical moment, it can be ensured that the video signal is not affected by clock changes, avoiding data confusion or display abnormalities caused by clock synchronization. By disconnecting the clock connection at the end of the rising edge, the FPGA can accurately control the timing of the clock switching, avoid data transmission errors caused by clock conflicts or asynchrony, and ensure a smooth transition of the clock switching process.
[0098] At the same time, in step 302 of the above embodiment, the FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock, which may include the following steps:
[0099] 403. Before the falling edge of the clock ends, the FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock.
[0100] After the connection between the first pixel clock and the RGB pixel clock is disconnected, the FPGA needs to reconnect the second pixel clock in the second phase-locked loop to the RGB pixel clock. In order to ensure smooth system clock switching, the FPGA will connect the second pixel clock to the RGB pixel clock before the falling edge of the second pixel clock ends. The falling edge is usually in the second half of the clock cycle. Choosing to connect at this time helps reduce interference with data transmission, because the data reading and display cycle has been completed at this time, and connecting the second pixel clock will not affect the ongoing data transmission. In this way, the FPGA ensures the smooth switching of the clock signal and avoids the impact of clock frequency changes on image display. At the same time, it ensures that the second pixel clock can be smoothly connected to the RGB pixel clock, avoiding data confusion or image display abnormalities during the switching process, and providing stable clock signal support for subsequent video output.
[0101] In this embodiment, accurate control of clock switching is ensured, avoiding image freeze, flicker or data loss caused by unstable or asynchronous clock. By connecting and disconnecting at the appropriate clock edge, FPGA can accurately control the video timing and ensure the stability of image output.
[0102] See also Figure 5 In some embodiments of the present application, the panel frame rate switching method may further include the following steps:
[0103] 501, FPGA obtains the actual frame rate of the target panel;
[0104] The FPGA first obtains the actual frame rate of the target panel. The actual frame rate refers to the refresh rate of the current panel display image, that is, the number of frames displayed per second. Usually, the target panel will have a built-in mechanism to report its refresh rate, and the FPGA can obtain this data by reading the panel status information. The actual frame rate of the target panel is obtained in order to compare it with the target frame rate to determine whether further adjustments are needed. By obtaining the actual frame rate, the FPGA can understand the display status of the panel in real time and provide accurate data support for subsequent frame rate judgment and adjustment.
[0105] 502. The FPGA determines whether the frame rate difference between the actual frame rate and the first target frame rate is within the error threshold range; if so, execute step 503;
[0106] At this time, the FPGA compares the actual frame rate obtained with the first target frame rate. The first target frame rate is the target frame rate during the switching process, that is, the refresh frequency that the system hopes to achieve. The FPGA calculates the difference between the two and determines whether the difference is within the error threshold range set in advance. The error threshold is to allow a certain error fluctuation to avoid unnecessary adjustments or interference caused by overly strict frame rate matching requirements. If the difference is within the error threshold range, it means that the frame rate switching is close to expectations and meets the requirements, and subsequent operations can continue; if it exceeds the range, further adjustment of the clock or other compensation measures may be required. By judging the difference between the actual frame rate and the target frame rate, the FPGA can ensure the accuracy of the frame rate switching, while avoiding display problems caused by excessive errors, such as stuttering, screen tearing, etc. Allowing a certain error range can improve the fault tolerance of the system and reduce unnecessary adjustments.
[0107] 503. FPGA determines that the frame rate switching is successful.
[0108] If the frame rate difference in step 502 meets the error threshold requirement, the FPGA will determine that the frame rate switch is successful. This means that the actual frame rate of the target panel has been synchronized with the expected first target frame rate and there are no problems with the switching process. At this point, the system can assume that the frame rate switch has been successfully completed and subsequent image output will be displayed at the new frame rate. The FPGA will update the internal status flag and can be ready for further operations, such as processing other frame rate switches, input data, or optimization.
[0109] In this embodiment, by gradually obtaining the actual frame rate, determining the error with the target frame rate, and finally confirming whether the frame rate switching is successful, the FPGA can ensure the high accuracy and reliability of the entire frame rate switching process. This process can smoothly transition between different frame rates, ensure the image quality and stable display effect, and avoid problems such as image flickering and freezing.
[0110] See also Figure 6 In some embodiments of the present application, the panel frame rate switching method may further include the following steps:
[0111] 601. When receiving a second frame rate switching instruction, the FPGA determines a second target frame rate according to the second frame rate switching, and calculates a third pixel clock corresponding to the second target frame rate based on the first target frame rate, the second target frame rate, and the second pixel clock;
[0112] When the FPGA receives the second frame rate switching instruction, it first needs to determine the new target frame rate, namely the second target frame rate. The second target frame rate is a frame rate set based on the current display requirements or system requirements, and is usually used to adjust the refresh frequency of the display panel. In order to ensure the synchronization of the second target frame rate and the display panel, the FPGA will calculate a new clock frequency, namely the third pixel clock, through the current first target frame rate, the second target frame rate and the current second pixel clock. The third pixel clock is a new clock signal used to drive subsequent display operations.
[0113] The FPGA will perform calculations based on the following relationship:
[0114] First target frame rate: The target frame rate that the current system is already running at.
[0115] Second target frame rate: The new target frame rate.
[0116] Second pixel clock: video clock for the second target frame rate.
[0117] With these known data, the FPGA can calculate the third pixel clock to ensure that the panel can display the image correctly after the new frame rate is switched.
[0118] 602. FPGA configures the third pixel clock into the first phase-locked loop;
[0119] After calculating the third pixel clock, the FPGA configures this new clock signal into the first phase-locked loop. Configuring the third pixel clock into the first phase-locked loop means guiding this clock signal into the display system to ensure that the clock can stably drive the display process. At this time, the clock signal in the first phase-locked loop will be adjusted, and the new third pixel clock will become the new reference clock to drive all subsequent video data reading and output operations.
[0120] 603. The FPGA reads frame data from the DDR memory according to the third pixel clock in the first phase-locked loop and outputs the frame data to the target panel.
[0121] After the third pixel clock is successfully configured to the first phase-locked loop, the FPGA will then read the frame data from the DDR memory according to the new clock signal. The RGB pixel clock (driven by the third pixel clock) ensures that the data reading and display timing are synchronized and that the image can be output to the target panel at the expected frame rate. Once the data is read from the DDR memory and transmitted to the target panel, the image will be displayed on the panel.
[0122] In this embodiment, the FPGA can achieve accurate frame rate switching and ensure smooth clock transition during the switching process to ensure the stability of image display. The new third pixel clock is calculated and configured so that the system can quickly adapt to the new frame rate. At the same time, the high quality and smoothness of the video output are maintained through phase-locked loop and clock synchronization.
[0123] See also Figure 7 In the embodiment of the present application, an embodiment of the switching system includes:
[0124] FPGA 701, DDR memory 702, two independent first phase-locked loops 702 and second phase-locked loops 703, FPGA 701 includes:
[0125] The interception unit 7011 is used to intercept frame data from the LVDS video stream and store the frame data in the DDR memory according to a pre-configured resolution;
[0126] The first output unit 7012 is used to read the frame data from the DDR memory and output it to the target panel according to the first pixel clock in the first phase-locked loop;
[0127] The calculation unit 7013 is used for, when receiving the first frame rate switching instruction, determining the first target frame rate according to the first frame rate switching, and calculating the second pixel clock corresponding to the first target frame rate based on the current frame rate, the first target frame rate and the first pixel clock;
[0128] A configuration unit 7014, configured to configure the second pixel clock into the second phase-locked loop;
[0129] The second output unit 7015 is used to read frame data from the DDR memory and output it to the target panel according to the second pixel clock in the second phase-locked loop.
[0130] In this embodiment, FPGA701 calculates a new pixel clock based on the current frame rate and the target frame rate, which ensures that the pixel clock frequency at the target frame rate is consistent with the clock frequency of other parts of the system, avoiding unstable image display due to clock frequency mismatch. Subsequently, FPGA701 configures the calculated second pixel clock into the second phase-locked loop 702 to generate a stable clock signal for subsequent data reading. Finally, FPGA701 stably reads the video frame data based on the new clock signal and outputs it to the target panel. Through this precise clock adjustment mechanism, the panel can ensure timing consistency when switching frame rates, avoid screen flickering problems caused by clock jumps or asynchronism, and significantly reduce the possibility of screen flickering when the panel switches frame rates.
[0131] Optionally, the second output unit 7015 includes:
[0132] A disconnection module, used to disconnect the first pixel clock and the RGB pixel clock in the first phase-locked loop;
[0133] A connection module, used for connecting the second pixel clock in the second phase-locked loop to the RGB pixel clock;
[0134] The output module is used to read the frame data from the DDR memory according to the RGB pixel clock and output it to the target panel.
[0135] Optionally, the disconnect module is specifically used for:
[0136] The FPGA determines the rising edge and falling edge of the clock corresponding to the current frame according to the first pixel clock;
[0137] At the end of the rising edge of the clock, the FPGA disconnects the first pixel clock in the first phase-locked loop from the RGB pixel clock;
[0138] The connection module is specifically used for:
[0139] Before the falling edge of the clock ends, the FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock.
[0140] Optionally, the FPGA also includes:
[0141] An acquisition unit is used by FPGA to acquire the actual frame rate of the target panel;
[0142] A judgment unit, used for the FPGA to judge whether a frame rate difference between an actual frame rate and a first target frame rate is within an error threshold range;
[0143] The first determining unit is configured to determine that the frame rate switching is successful when the judging unit determines that the frame rate difference is within the error threshold range.
[0144] Optionally, the FPGA further includes a switching unit, and the switching unit is used to:
[0145] When a second frame rate switching instruction is received, determining a second target frame rate according to the second frame rate switching, and calculating a third pixel clock corresponding to the second target frame rate based on the first target frame rate, the second target frame rate and the second pixel clock;
[0146] configuring the third pixel clock into the first phase-locked loop;
[0147] According to the third pixel clock in the first phase-locked loop, frame data is read from the DDR memory and output to the target panel.
[0148] Optionally, the FPGA also includes:
[0149] The second determining unit is used to determine the frame data by detecting the rising edge of the Vsync signal of the LVDS video stream.
[0150] Optionally, the interception unit 7011 is specifically used for:
[0151] FPGA intercepts frame data from the LVDS video stream every other frame.
[0152] In this implementation, the functions of each unit and module are the same as those described above. Figures 2 to 6 The steps in the illustrated embodiment correspond to each other and are not described again. The embodiment of the present application provides a panel frame rate switching method and switching system for reducing the possibility of screen flickering when the panel switches the frame rate.
[0153] The embodiments of the present application will be described below in conjunction with the accompanying drawings.
[0154] See also Figure 1 , the switching system in the embodiment of the present application includes:
[0155] FPGA 101, DDR memory 102, two independent first phase-locked loops 102 and second phase-locked loops 103;
[0156] The FPGA 101 is connected to the DDR memory 102 , two independent first phase-locked loops 102 and second phase-locked loops 103 , respectively.
[0157] See also Figure 2 The panel frame rate switching method in the embodiment of the present application is applied to Figure 1 The switching system shown, an embodiment of a panel frame rate switching method includes:
[0158] 201. FPGA intercepts frame data from the LVDS video stream and stores the frame data in the DDR memory according to a pre-configured resolution;
[0159] The connection between FPGA, DDR memory and two phase-locked loops ensures efficient data transmission and synchronization. FPGA extracts frame data from the received LVDS video stream and stores the data according to the set resolution in the DDR memory. The purpose of storage is to provide a buffer area for subsequent data reading, processing and display, ensuring that data will not be lost and can be read efficiently at the right time. The phase-locked loop is used to generate a synchronous clock to ensure that the video data reading and transmission are accurately connected with the timing of the display device.
[0160] 202. The FPGA reads frame data from the DDR memory according to the first pixel clock in the first phase-locked loop and outputs the frame data to the target panel;
[0161] FPGA controls data reading and output through the first pixel clock signal in the first phase-locked loop, ensuring that data can be transmitted to the display panel at precise time intervals. Through the first pixel clock, FPGA can stably extract the stored frame data from the DDR memory and output the data to the target panel in the correct order. Due to the synchronization of the clock signal, the output data can be accurately matched with the refresh rate and display resolution of the display device, ensuring a stable and smooth display effect.
[0162] 203. When receiving the first frame rate switching instruction, the FPGA determines the first target frame rate according to the first frame rate switching, and calculates the second pixel clock corresponding to the first target frame rate based on the current frame rate, the first target frame rate and the first pixel clock;
[0163] After receiving the frame rate switching instruction, the FPGA needs to recalculate the clock frequency to support the new display requirements. First, the FPGA determines the new target frame rate (first target frame rate), which is usually input by the system or user. On this basis, the FPGA calculates the new second pixel clock frequency based on the current frame rate, target frame rate and first pixel clock. This new pixel clock will match the target frame rate to ensure that data reading and display can be synchronized to the new frame rate.
[0164] 204. The FPGA configures the second pixel clock into the second phase-locked loop;
[0165] After calculating the new second pixel clock, the FPGA will pass the clock signal to the second phase-locked loop for clock configuration and synchronization. The second phase-locked loop will generate a new synchronization clock based on the newly input clock signal so that the system can work stably at the new frame rate. This configuration process ensures that the clock frequency is completely consistent with the target frame rate, thereby ensuring the correctness and stability of subsequent data transmission.
[0166] 205. The FPGA reads frame data from the DDR memory according to the second pixel clock in the second phase-locked loop and outputs the frame data to the target panel.
[0167] After receiving the second pixel clock signal provided by the second phase-locked loop, the FPGA will re-read the frame data from the DDR memory according to the new clock frequency, and transmit the data to the target panel at the new frame rate. This process ensures that even after the frame rate is switched, the video stream can maintain stable output and can be displayed smoothly at the new frame rate, avoiding freezes or unsmooth images.
[0168] In this embodiment, the FPGA calculates a new pixel clock based on the current frame rate and the target frame rate, which ensures that the pixel clock frequency at the target frame rate is consistent with the clock frequency of other parts of the system, avoiding unstable image display due to clock frequency mismatch. Subsequently, the FPGA configures the calculated second pixel clock into the second phase-locked loop to generate a stable clock signal for subsequent data reading. Finally, the FPGA stably reads the video frame data based on the new clock signal and outputs it to the target panel. Through this precise clock adjustment mechanism, the panel can ensure timing consistency when switching frame rates, avoiding screen flickering problems caused by clock jumps or asynchronism, and significantly reducing the possibility of screen flickering when the panel switches frame rates.
[0169] See also Figure 3 In some embodiments of the present application, in step 205 in the above embodiment, the FPGA reads frame data from the DDR memory and outputs it to the target panel according to the second pixel clock in the second phase-locked loop, which may include the following steps:
[0170] 301. FPGA disconnects the first pixel clock and the RGB pixel clock in the first phase-locked loop;
[0171] The FPGA will first disconnect the connection between the first pixel clock and the RGB pixel clock in the first phase-locked loop. The RGB pixel clock is the time reference for controlling the display of each pixel on the display panel. The first pixel clock and the RGB pixel clock are originally synchronized, but when switching the frame rate, the system clock needs to be switched from the first pixel clock to the second pixel clock. Therefore, the purpose of disconnection is to isolate the old clock signal to prevent it from continuing to interfere with the new clock signal. This ensures that the first pixel clock no longer affects the subsequent video output, avoids the conflict between the two clock signals, and provides preparation for the subsequent connection of the second pixel clock.
[0172] 302. FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock;
[0173] After disconnecting the first pixel clock, the FPGA reconnects the second pixel clock in the second phase-locked loop to the RGB pixel clock. The key to this step is to ensure that the timing of the second pixel clock can accurately drive the RGB pixel clock so that the video output can run stably at the new frame rate. The second pixel clock has been calculated based on the new target frame rate, and this clock signal will become the new reference signal to control the update cycle of the display panel. By connecting the second pixel clock to the RGB pixel clock, the system can achieve clock synchronization after the frame rate switch, ensuring that the new pixel clock does not have timing errors during the display process, and ensuring the continuity and stability of the image display.
[0174] 303. FPGA reads frame data from DDR memory according to RGB pixel clock and outputs it to the target panel.
[0175] After completing the clock connection, the FPGA starts to read frame data from the DDR memory according to the new RGB pixel clock. The RGB pixel clock serves as a new clock signal to ensure that the data reading and display cycle matches the new frame rate. The FPGA outputs the read frame data to the target panel in the correct timing to update the image display. At this point, the system works at the new frame rate, and the image can be displayed smoothly on the target device, thereby ensuring the stable output of the system after the frame rate switch. The data reading and display timing have been synchronized according to the new pixel clock, avoiding display anomalies caused by clock mismatch, such as flickering, freezes, etc., and ensuring the stable display of the picture.
[0176] In this embodiment, accurate clock switching ensures that when the frame rate is changed, the video data can be smoothly transmitted to the display device, and the consistency and high quality of the image output are guaranteed.
[0177] See also Figure 4 In some embodiments of the present application, in step 301 in the above embodiment, the FPGA disconnects the first pixel clock in the first phase-locked loop from the RGB pixel clock, which may include the following steps:
[0178] 401. FPGA determines a rising edge and a falling edge of a clock corresponding to a current frame according to a first pixel clock;
[0179] Before disconnecting, the FPGA first determines the timing of the current frame through the first pixel clock. The pixel clock usually has a rising edge and a falling edge, which are used to define the boundaries of data transmission. In this step, the FPGA identifies the rising and falling edges of the clock corresponding to the data of the current frame by analyzing the first pixel clock signal. The rising and falling edges are usually used to synchronize the reading and display of video data, so accurately grasping these moments is crucial for subsequent clock switching.
[0180] 402. When the rising edge of the clock ends, the FPGA disconnects the first pixel clock and the RGB pixel clock in the first phase-locked loop;
[0181] Next, at the end of the rising edge of the first pixel clock, the FPGA immediately disconnects the first pixel clock in the first phase-locked loop from the RGB pixel clock. The timing of the disconnection is usually after the rising edge of the clock ends, because at this moment, the reading and display of the data have been completed, and the clock switching can be performed safely to avoid interference during data transmission. By disconnecting at this critical moment, it can be ensured that the video signal is not affected by clock changes, avoiding data confusion or display abnormalities caused by clock synchronization. By disconnecting the clock connection at the end of the rising edge, the FPGA can accurately control the timing of the clock switching, avoid data transmission errors caused by clock conflicts or asynchrony, and ensure a smooth transition of the clock switching process.
[0182] At the same time, in step 302 of the above embodiment, the FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock, which may include the following steps:
[0183] 403. Before the falling edge of the clock ends, the FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock.
[0184] After the connection between the first pixel clock and the RGB pixel clock is disconnected, the FPGA needs to reconnect the second pixel clock in the second phase-locked loop to the RGB pixel clock. In order to ensure smooth system clock switching, the FPGA will connect the second pixel clock to the RGB pixel clock before the falling edge of the second pixel clock ends. The falling edge is usually in the second half of the clock cycle. Choosing to connect at this time helps reduce interference with data transmission, because the data reading and display cycle has been completed at this time, and connecting the second pixel clock will not affect the ongoing data transmission. In this way, the FPGA ensures the smooth switching of the clock signal and avoids the impact of clock frequency changes on image display. At the same time, it ensures that the second pixel clock can be smoothly connected to the RGB pixel clock, avoiding data confusion or image display abnormalities during the switching process, and providing stable clock signal support for subsequent video output.
[0185] In this embodiment, accurate control of clock switching is ensured, avoiding image freeze, flicker or data loss caused by unstable or asynchronous clock. By connecting and disconnecting at the appropriate clock edge, FPGA can accurately control the video timing and ensure the stability of image output.
[0186] See also Figure 5 In some embodiments of the present application, the panel frame rate switching method may further include the following steps:
[0187] 501, FPGA obtains the actual frame rate of the target panel;
[0188] The FPGA first obtains the actual frame rate of the target panel. The actual frame rate refers to the refresh rate of the current panel display image, that is, the number of frames displayed per second. Usually, the target panel will have a built-in mechanism to report its refresh rate, and the FPGA can obtain this data by reading the panel status information. The actual frame rate of the target panel is obtained in order to compare it with the target frame rate to determine whether further adjustments are needed. By obtaining the actual frame rate, the FPGA can understand the display status of the panel in real time and provide accurate data support for subsequent frame rate judgment and adjustment.
[0189] 502. The FPGA determines whether the frame rate difference between the actual frame rate and the first target frame rate is within the error threshold range; if so, execute step 503;
[0190] At this time, the FPGA compares the actual frame rate obtained with the first target frame rate. The first target frame rate is the target frame rate during the switching process, that is, the refresh frequency that the system hopes to achieve. The FPGA calculates the difference between the two and determines whether the difference is within the error threshold range set in advance. The error threshold is to allow a certain error fluctuation to avoid unnecessary adjustments or interference caused by overly strict frame rate matching requirements. If the difference is within the error threshold range, it means that the frame rate switching is close to expectations and meets the requirements, and subsequent operations can continue; if it exceeds the range, further adjustment of the clock or other compensation measures may be required. By judging the difference between the actual frame rate and the target frame rate, the FPGA can ensure the accuracy of the frame rate switching, while avoiding display problems caused by excessive errors, such as stuttering, screen tearing, etc. Allowing a certain error range can improve the fault tolerance of the system and reduce unnecessary adjustments.
[0191] 503. FPGA determines that the frame rate switching is successful.
[0192] If the frame rate difference in step 502 meets the error threshold requirement, the FPGA will determine that the frame rate switch is successful. This means that the actual frame rate of the target panel has been synchronized with the expected first target frame rate and there are no problems with the switching process. At this point, the system can assume that the frame rate switch has been successfully completed and subsequent image output will be displayed at the new frame rate. The FPGA will update the internal status flag and can be ready for further operations, such as processing other frame rate switches, input data, or optimization.
[0193] In this embodiment, by gradually obtaining the actual frame rate, determining the error with the target frame rate, and finally confirming whether the frame rate switching is successful, the FPGA can ensure the high accuracy and reliability of the entire frame rate switching process. This process can smoothly transition between different frame rates, ensure the image quality and stable display effect, and avoid problems such as image flickering and freezing.
[0194] See also Figure 6 In some embodiments of the present application, the panel frame rate switching method may further include the following steps:
[0195] 601. When receiving a second frame rate switching instruction, the FPGA determines a second target frame rate according to the second frame rate switching, and calculates a third pixel clock corresponding to the second target frame rate based on the first target frame rate, the second target frame rate, and the second pixel clock;
[0196] When the FPGA receives the second frame rate switching instruction, it first needs to determine the new target frame rate, namely the second target frame rate. The second target frame rate is a frame rate set based on the current display requirements or system requirements, and is usually used to adjust the refresh frequency of the display panel. In order to ensure the synchronization of the second target frame rate and the display panel, the FPGA will calculate a new clock frequency, namely the third pixel clock, through the current first target frame rate, the second target frame rate and the current second pixel clock. The third pixel clock is a new clock signal used to drive subsequent display operations.
[0197] The FPGA will perform calculations based on the following relationship:
[0198] First target frame rate: The target frame rate that the current system is already running at.
[0199] Second target frame rate: The new target frame rate.
[0200] Second pixel clock: video clock for the second target frame rate.
[0201] With these known data, the FPGA can calculate the third pixel clock to ensure that the panel can display the image correctly after the new frame rate is switched.
[0202] 602. FPGA configures the third pixel clock into the first phase-locked loop;
[0203] After calculating the third pixel clock, the FPGA configures this new clock signal into the first phase-locked loop. Configuring the third pixel clock into the first phase-locked loop means guiding this clock signal into the display system to ensure that the clock can stably drive the display process. At this time, the clock signal in the first phase-locked loop will be adjusted, and the new third pixel clock will become the new reference clock to drive all subsequent video data reading and output operations.
[0204] 603. The FPGA reads frame data from the DDR memory according to the third pixel clock in the first phase-locked loop and outputs the frame data to the target panel.
[0205] After the third pixel clock is successfully configured to the first phase-locked loop, the FPGA will then read the frame data from the DDR memory according to the new clock signal. The RGB pixel clock (driven by the third pixel clock) ensures that the data reading and display timing are synchronized and that the image can be output to the target panel at the expected frame rate. Once the data is read from the DDR memory and transmitted to the target panel, the image will be displayed on the panel.
[0206] In this embodiment, the FPGA can achieve accurate frame rate switching and ensure smooth clock transition during the switching process to ensure the stability of image display. The new third pixel clock is calculated and configured so that the system can quickly adapt to the new frame rate. At the same time, the high quality and smoothness of the video output are maintained through phase-locked loop and clock synchronization.
[0207] See also Figure 7 In the embodiment of the present application, an embodiment of the switching system includes:
[0208] FPGA 701, DDR memory 702, two independent first phase-locked loops 702 and second phase-locked loops 703, FPGA 701 includes:
[0209] The interception unit 7011 is used to intercept frame data from the LVDS video stream and store the frame data in the DDR memory according to a pre-configured resolution;
[0210] The first output unit 7012 is used to read the frame data from the DDR memory and output it to the target panel according to the first pixel clock in the first phase-locked loop;
[0211] The calculation unit 7013 is used for, when receiving the first frame rate switching instruction, determining the first target frame rate according to the first frame rate switching, and calculating the second pixel clock corresponding to the first target frame rate based on the current frame rate, the first target frame rate and the first pixel clock;
[0212] A configuration unit 7014, configured to configure the second pixel clock into the second phase-locked loop;
[0213] The second output unit 7015 is used to read frame data from the DDR memory and output it to the target panel according to the second pixel clock in the second phase-locked loop.
[0214] In this embodiment, FPGA701 calculates a new pixel clock based on the current frame rate and the target frame rate, which ensures that the pixel clock frequency at the target frame rate is consistent with the clock frequency of other parts of the system, avoiding unstable image display due to clock frequency mismatch. Subsequently, FPGA701 configures the calculated second pixel clock into the second phase-locked loop 702 to generate a stable clock signal for subsequent data reading. Finally, FPGA701 stably reads the video frame data based on the new clock signal and outputs it to the target panel. Through this precise clock adjustment mechanism, the panel can ensure timing consistency when switching frame rates, avoid screen flickering problems caused by clock jumps or asynchronism, and significantly reduce the possibility of screen flickering when the panel switches frame rates.
[0215] Optionally, the second output unit 7015 includes:
[0216] A disconnection module, used to disconnect the first pixel clock and the RGB pixel clock in the first phase-locked loop;
[0217] A connection module, used for connecting the second pixel clock in the second phase-locked loop to the RGB pixel clock;
[0218] The output module is used to read the frame data from the DDR memory according to the RGB pixel clock and output it to the target panel.
[0219] Optionally, the disconnect module is specifically used for:
[0220] The FPGA determines the rising edge and falling edge of the clock corresponding to the current frame according to the first pixel clock;
[0221] At the end of the rising edge of the clock, the FPGA disconnects the first pixel clock in the first phase-locked loop from the RGB pixel clock;
[0222] The connection module is specifically used for:
[0223] Before the falling edge of the clock ends, the FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock.
[0224] Optionally, the FPGA also includes:
[0225] An acquisition unit is used by FPGA to acquire the actual frame rate of the target panel;
[0226] A judgment unit, used for the FPGA to judge whether a frame rate difference between an actual frame rate and a first target frame rate is within an error threshold range;
[0227] The first determining unit is configured to determine that the frame rate switching is successful when the judging unit determines that the frame rate difference is within the error threshold range.
[0228] Optionally, the FPGA further includes a switching unit, and the switching unit is used to:
[0229] When a second frame rate switching instruction is received, determining a second target frame rate according to the second frame rate switching, and calculating a third pixel clock corresponding to the second target frame rate based on the first target frame rate, the second target frame rate and the second pixel clock;
[0230] configuring the third pixel clock into the first phase-locked loop;
[0231] According to the third pixel clock in the first phase-locked loop, frame data is read from the DDR memory and output to the target panel.
[0232] Optionally, the FPGA also includes:
[0233] The second determining unit is used to determine the frame data by detecting the rising edge of the Vsync signal of the LVDS video stream.
[0234] Optionally, the interception unit 7011 is specifically used for:
[0235] FPGA intercepts frame data from the LVDS video stream every other frame.
[0236] In this implementation, the functions of each unit and module are the same as those described above. Figures 2 to 6 The steps in the illustrated embodiments correspond to each other and will not be described again here.
[0237] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.
[0238] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.
[0239] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0240] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0241] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), disk or optical disk and other media that can store program code.
Claims
1. A method for switching a panel frame rate, characterized in that: The method is applied to a switching system, the switching system comprising an FPGA, a DDR memory, two independent first phase-locked loops and a second phase-locked loop, and the method comprises: The FPGA intercepts frame data from the LVDS video stream and stores the frame data in the DDR memory according to a pre-configured resolution; The FPGA reads the frame data from the DDR memory according to the first pixel clock in the first phase-locked loop and outputs the frame data to the target panel; When receiving a first frame rate switching instruction, the FPGA determines a first target frame rate according to the first frame rate switching, and calculates a second pixel clock corresponding to the first target frame rate based on a current frame rate, the first target frame rate and the first pixel clock; The FPGA configures the second pixel clock into a second phase-locked loop; The FPGA reads the frame data from the DDR memory according to the second pixel clock in the second phase-locked loop and outputs the frame data to the target panel.
2. The method according to claim 1, characterized in that The FPGA reads the frame data from the DDR memory and outputs the frame data to the target panel according to the second pixel clock in the second phase-locked loop, comprising: The FPGA disconnects the first pixel clock and the RGB pixel clock in the first phase-locked loop; The FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock; The FPGA reads the frame data from the DDR memory according to the RGB pixel clock and outputs the frame data to the target panel.
3. The method according to claim 2, characterized in that The FPGA disconnecting the first pixel clock and the RGB pixel clock in the first phase-locked loop includes: The FPGA determines a rising edge and a falling edge of a clock corresponding to a current frame according to the first pixel clock; When the rising edge of the clock ends, the FPGA disconnects the first pixel clock and the RGB pixel clock in the first phase-locked loop; The FPGA connects the second pixel clock in the second phase-locked loop with the RGB pixel clock, comprising: Before the falling edge of the clock ends, the FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock.
4. The method according to claim 1, characterized in that: After the FPGA reads the frame data from the DDR memory according to the second pixel clock in the second phase-locked loop and outputs the frame data to the target panel, the method further includes: The FPGA acquires the actual frame rate of the target panel; The FPGA determines whether a frame rate difference between the actual frame rate and the first target frame rate is within an error threshold range; If so, the FPGA determines that the frame rate switching is successful.
5. The method according to claim 1, characterized in that After the FPGA reads the frame data from the DDR memory according to the second pixel clock in the second phase-locked loop and outputs the frame data to the target panel, the method further includes: When receiving the second frame rate switching instruction, the FPGA determines the second target frame rate according to the second frame rate switching, and calculates a third pixel clock corresponding to the second target frame rate based on the first target frame rate, the second target frame rate and the second pixel clock; The FPGA configures the third pixel clock into a first phase-locked loop; The FPGA reads the frame data from the DDR memory according to the third pixel clock in the first phase-locked loop and outputs the frame data to the target panel.
6. The method according to any one of claims 1 to 5, characterized in that Before the FPGA intercepts frame data from the LVDS video stream, the method further includes: The FPGA determines the frame data by detecting the rising edge of the Vsync signal of the LVDS video stream.
7. The method according to any one of claims 1 to 5, characterized in that The FPGA intercepts frame data from the LVDS video stream including: The FPGA intercepts frame data from the LVDS video stream at intervals of one frame.
8. A switching system, characterized in that: The switching system includes an FPGA, a DDR memory, two independent first phase-locked loops and a second phase-locked loop, and the FPGA includes: An interception unit, used for intercepting frame data from the LVDS video stream, and storing the frame data in the DDR memory according to a pre-configured resolution; A first output unit, configured to read the frame data from the DDR memory and output the frame data to a target panel according to a first pixel clock in the first phase-locked loop; a calculation unit, configured to, when receiving a first frame rate switching instruction, determine a first target frame rate according to the first frame rate switching, and calculate a second pixel clock corresponding to the first target frame rate based on a current frame rate, the first target frame rate and the first pixel clock; A configuration unit, configured to configure the second pixel clock into a second phase-locked loop; The second output unit is used to read the frame data from the DDR memory and output the frame data to the target panel according to the second pixel clock in the second phase-locked loop.
9. The switching system according to claim 8, characterized in that: The second output unit comprises: A disconnection module, used to disconnect the first pixel clock and the RGB pixel clock in the first phase-locked loop; A connection module, used for connecting the second pixel clock in the second phase-locked loop to the RGB pixel clock; An output module is used to read the frame data from the DDR memory according to the RGB pixel clock and output the frame data to the target panel.
10. The switching system according to claim 9, characterized in that: The disconnection module is specifically used for: The FPGA determines a rising edge and a falling edge of a clock corresponding to a current frame according to the first pixel clock; When the rising edge of the clock ends, the FPGA disconnects the first pixel clock and the RGB pixel clock in the first phase-locked loop; The connection module is specifically used for: Before the falling edge of the clock ends, the FPGA connects the second pixel clock in the second phase-locked loop to the RGB pixel clock.