Circuit board assembly and display device

Abstract

The invention discloses a circuit board assembly and a display device, the circuit board assembly comprises a circuit board, a time schedule controller and a first memory, the circuit board comprises a first serial peripheral interface bus, and the first serial peripheral interface bus comprises a plurality of first sub-lines; the time schedule controller is arranged on the circuit board; the first memory is arranged on the circuit board; wherein the plurality of first sub-lines are electrically connected with the time schedule controller and the first memory, and the length of the first sub-lines is less than or equal to 9000 mil. According to the application, the length of the serial peripheral interface bus for electrically connecting the time sequence control chip and the storage chip can be reduced, so that a communication signal transmission path between the time sequence control chip and the storage chip is shortened, and the stability of signal transmission between the time sequence control chip and the storage chip is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a circuit board assembly and a display device. Background Art

[0002] In a printed circuit board assembly (PCBA), there are two main control components, multiple memory chips (Flash), level shift ICs, and a burning interface. Among them, the main control components can be a field programmable gate array chip (FPGA) and a timing control chip (Tcon). In the printed circuit board assembly of the related art, the timing control chip and the memory chip are located on both sides of the programmable gate array chip in the length direction of the printed circuit board (PCB).

[0003] During the process of programming printed circuit board components, programming failure may occur. The reason for this phenomenon is that the wiring length of the serial peripheral interface bus (SPI) that electrically connects the timing control chip and the memory chip is long, causing the communication signal between the timing control chip and the memory chip to be interfered by many other signals (such as the GOA signal output by the level conversion chip), resulting in unstable signal transmission between the timing control chip and the memory chip.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the invention

[0005] The purpose of the present application is to provide a circuit board and a display device, which can reduce the length of the serial peripheral interface bus that electrically connects the timing control chip and the memory chip, thereby shortening the communication signal transmission path between the timing control chip and the memory chip, so as to improve the stability of the signal transmission between the timing control chip and the memory chip.

[0006] To solve the above problems, the technical solution of this application is as follows:

[0007] In a first aspect, the present application proposes a circuit board assembly, comprising:

[0008] A circuit board, comprising a first serial peripheral interface bus, wherein the first serial peripheral interface bus comprises a plurality of first sub-lines;

[0009] A timing controller is disposed on the circuit board; and

[0010] A first memory, disposed on the circuit board;

[0011] Wherein, a plurality of the first sub-lines electrically connect the timing controller and the first memory, and a length of the first sub-line is less than or equal to 9000 mils.

[0012] In one embodiment of the present application, the circuit board assembly further comprises a programmable gate array chip, and the programmable gate array chip is disposed on the circuit board;

[0013] In a plan view of the circuit board assembly, the timing controller is located between the first memory and the programmable gate array chip, and a distance between the timing controller and the first memory is smaller than a distance between the timing controller and the programmable gate array chip.

[0014] In one embodiment of the present application, in a plan view of the circuit board assembly, the first memory and the programmable gate array chip are respectively located on both sides of the timing controller in the long side direction of the circuit board;

[0015] The length of the first sub-line is less than or equal to 3000 mils.

[0016] In one embodiment of the present application, the plurality of first sub-lines include:

[0017] A first data input signal line electrically connecting the timing controller and the first memory;

[0018] A first data output signal line electrically connecting the timing controller and the first memory;

[0019] A first clock signal line electrically connecting the timing controller and the first memory; and

[0020] A first chip selection signal line electrically connecting the timing controller and the first memory;

[0021] The absolute value of the length difference between any two of the first data input signal line, the first data output signal line, the first clock signal line, and the first chip select signal line is less than 20 mils.

[0022] In one embodiment of the present application, the plurality of first sub-lines further include:

[0023] A first write protection input signal line electrically connecting the timing controller and the first memory;

[0024] A first state maintaining input signal line electrically connecting the timing controller and the first memory;

[0025] Among them, the absolute value of the length difference between any two of the first data input signal line, the first data output signal line, the first clock signal line, the first chip select signal line, the first write protection input signal line, and the first state maintenance input signal line is less than 10 mils.

[0026] In one embodiment of the present application, the circuit board assembly further includes a level converter, which is disposed on the circuit board and electrically connected to the timing controller;

[0027] In a plan view of the circuit board assembly, the first memory is located between the level converter and the timing controller;

[0028] The circuit board comprises a first wiring layer, a reference ground layer and a second wiring layer stacked along the thickness direction of the circuit board;

[0029] The first routing layer includes the first serial peripheral interface bus;

[0030] The reference ground layer is insulated from the first routing layer and the second routing layer respectively, and the reference ground layer is connected to a reference ground potential;

[0031] The second wiring layer includes a row drive signal bus, the row drive signal bus is electrically connected to the level converter, and the row drive signal bus is configured to output a row drive signal to the display panel.

[0032] In an embodiment of the present application, the row drive signal bus includes a plurality of second sub-lines, and the second sub-lines are configured to output row drive signals to the display panel;

[0033] The orthographic projection of at least one of the first sub-lines on the reference stratum intersects with the orthographic projection of at least one of the second sub-lines on the reference stratum; and / or,

[0034] The orthographic projections of the plurality of second sub-lines on the reference formation are arranged at intervals, a gap is formed between the orthographic projections of two adjacent second sub-lines on the reference formation, and at least one of the gaps does not completely overlap with the orthographic projection of the first sub-line on the reference formation.

[0035] In one embodiment of the present application, the circuit board assembly further includes a second memory, and the second memory is disposed on the circuit board;

[0036] In a plan view of the circuit board assembly, the second memory is located between the level converter and the timing controller, and the second memory and the first memory are arranged at intervals along a short side direction of the circuit board;

[0037] The first wiring layer further includes a second serial peripheral interface bus, the second serial peripheral interface bus is electrically connected to the timing controller and the second memory, and the second serial peripheral interface bus is spaced apart from the first serial peripheral interface bus on a side of the reference ground layer away from the second wiring layer;

[0038] The second serial peripheral interface bus includes a plurality of third sub-lines, and the third sub-lines are electrically connected to the timing controller and the second memory;

[0039] The row drive signal bus includes a plurality of second sub-lines, and the second sub-lines are configured to output row drive signals to the display panel;

[0040] The orthographic projection of at least one of the third sub-lines on the reference stratum intersects with the orthographic projection of at least one of the second sub-lines on the reference stratum; and / or,

[0041] The orthographic projections of the plurality of second sub-lines on the reference formation are arranged at intervals, a gap is formed between the orthographic projections of two adjacent second sub-lines on the reference formation, and at least one of the gaps does not completely overlap with the orthographic projection of the third sub-line on the reference formation.

[0042] In one embodiment of the present application, the circuit board includes a first area, the first area includes a proximal area and a distal area located at least on one side of the proximal area, and the timing controller and the first memory are located in the proximal area;

[0043] A plurality of the first sub-lines are arranged at intervals in the first region, at least one of the first sub-lines is located in the proximal region, and at least one of the first sub-lines is located in the distal region;

[0044] The first sub-line located in the proximal region includes a plurality of first bending portions;

[0045] In the plan view of the circuit board assembly, the pattern of the first bending portion is one of an arc structure, a folded line structure or a square structure.

[0046] In one embodiment of the present application, the circuit board assembly further includes a burning interface, the burning interface is provided on the circuit board, and the burning interface is electrically connected to the first memory;

[0047] The circuit board includes a third serial peripheral interface bus, the third serial peripheral interface bus includes a plurality of fourth sub-lines, the fourth sub-lines are electrically connected to the burning interface and the timing controller, and the length of the fourth sub-lines is less than 9000 mils.

[0048] In the second aspect, the present application proposes a display device, including a circuit board assembly, the circuit board assembly including a circuit board, a timing controller and a first memory, the circuit board including a first serial peripheral interface bus, the first serial peripheral interface bus including a plurality of first sub-lines; the timing controller is arranged on the circuit board; the first memory is arranged on the circuit board; wherein, the plurality of first sub-lines electrically connect the timing controller and the first memory, and the length of the first sub-line is less than or equal to 9000 mils.

[0049] In the present application, the first serial peripheral interface bus electrically connecting the timing controller and the first memory includes multiple first sub-lines. By controlling the length of each first sub-line within 9000 mils, the length of the serial peripheral interface bus electrically connecting the timing control chip and the memory chip can be reduced, thereby shortening the communication signal transmission path between the timing control chip and the memory chip, so as to improve the stability of signal transmission between the timing control chip and the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 is a schematic diagram of a circuit board assembly in the related art;

[0051] Figure 2 is a schematic diagram of an embodiment of a circuit board assembly of the present application;

[0052] Figure 3 is a schematic diagram of an embodiment of a circuit board assembly of the present application;

[0053] Figure 4 is a schematic diagram of an embodiment of a circuit board of the present application;

[0054] Figure 5 is a schematic diagram of an embodiment of orthographic projections of a plurality of first sub-lines on a reference stratum and orthographic projections of a plurality of second sub-lines on a reference stratum in the present application;

[0055] Figure 6 It is a schematic diagram of an embodiment of the orthographic projections of a plurality of first sub-lines on a reference stratum and the orthographic projections of a plurality of second sub-lines on a reference stratum in the present application;

[0056] Figure 7 It is a schematic diagram of an embodiment of the orthographic projections of a plurality of third sub-lines on the reference stratum and the orthographic projections of a plurality of second sub-lines on the reference stratum in the present application;

[0057] Figure 8 It is a schematic diagram of an embodiment of the orthographic projections of a plurality of first sub-lines on a reference stratum and the orthographic projections of a plurality of second sub-lines on a reference stratum in the present application. DETAILED DESCRIPTION

[0058] The meanings of the terms used in this specification and claims correspond to the meanings commonly understood by those of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are only for the purpose of facilitating the description and understanding of this application, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0059] See also Figure 1 In the relevant circuit board assembly 100a, the timing control chip 20a and the memory chip 31a are located on both sides of the programmable gate array chip 40a in the length direction of the printed circuit board 10a. The serial peripheral interface bus SPI needs to cross the programmable gate array chip 40a to electrically connect the timing control chip 20a and the memory chip 31a, resulting in a longer length of the serial peripheral interface bus SPI, so that the communication signal between the timing control chip 20a and the memory chip 31a is interfered by many other signals (such as the GOA signal output by the level conversion chip), resulting in unstable signal transmission between the timing control chip 20a and the memory chip 31a.

[0060] The present application proposes a display device, which may be a tablet computer, an electronic reader, an electronic display screen, a laptop computer, a mobile phone, an augmented reality (AR) or virtual reality (VR) device, a media player, a wearable device, a digital camera, a car navigation system, etc. The display device includes a display panel and a printed circuit board assembly 100 (PCBA).

[0061] Optionally, the display panel may be a micro light emitting diode (Micro Light Emitting Diode, MicroLED) display panel, the display panel may be a sub-millimeter light emitting diode (Mini Light Emitting Diode, MiniLED) display panel, or the display panel may be an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel.

[0062] The circuit board assembly 100 is bound to the non-display area of ​​the display panel.

[0063] See also Figure 2 The present application proposes a circuit board assembly 100, including a circuit board 10 (Printed Circuit Board, PCB), a timing controller 20 (Timing Controller, Tcon) and a first memory 31 (Flash).

[0064] The circuit board 10 includes a first serial peripheral interface (SPI) bus. The first serial peripheral interface bus SPI0 includes a plurality of first sub-lines 15. The timing controller 20 is disposed on the circuit board 10. The first memory 31 is disposed on the circuit board 10. The plurality of first sub-lines 15 electrically connect the timing controller 20 and the first memory 31, and the length of the first sub-lines 15 is less than or equal to 9000 mils.

[0065] In this embodiment, the first serial peripheral interface bus SPI0 electrically connecting the timing controller 20 and the first memory 31 includes multiple first sub-lines 15. By controlling the length of each first sub-line 15 within 9000 mils, the length of the serial peripheral interface bus electrically connecting the timing control chip and the memory chip can be reduced, thereby shortening the communication signal transmission path between the timing control chip and the memory chip, thereby improving the stability of signal transmission between the timing control chip and the memory chip.

[0066] It should be understood that mil is a unit of length, also known as milli-inch, where one inch is equal to 1000 mils.

[0067] Optionally, the length of the first sub-line 15 is 100 mils, 200 mils, 300 mils, 400 mils, 500 mils, 600 mils, 700 mils, 800 mils, 900 mils, 1000 mils, 1100 mils, 1200 mils, 1300 mils, 1400 mils, 1500 mils, 1600 mils, 1700 mils, 1800 mils, 1900 mils, 2000 mils, 2100 mils, 2200 mils. , 2300 mils, 2400 mils, 2500 mils, 2600 mils, 2700 mils, 2800 mils, 2900 mils, 3000 mils, 3100 mils, 3200 mils, 3300 mils, 3400 mils, 3500 mils, 3600 mils, 3700 mils, 3800 mils, 3900 mils, 4000 mils, 4100 mils, 4200 mils, 4300 mils, 4400 mils, 4500 mils , 4600 mils, 4700 mils, 4800 mils, 4900 mils, 5000 mils, 5100 mils, 5200 mils, 5300 mils, 5400 mils, 5500 mils, 5600 mils, 5700 mils, 5800 mils, 5900 mils, 6000 mils, 6100 mils, 6200 mils, 6300 mils, 6400 mils, 6500 mils, 6600 mils, 6700 mils, 6800 mils , 6900 mils, 7000 mils, 7100 mils, 7200 mils, 7300 mils, 7400 mils, 7500 mils, 7600 mils, 7700 mils, 7800 mils, 7900 mils, 8000 mils, 8100 mils, 8200 mils, 8300 mils, 8400 mils, 8500 mils, 8600 mils, 8700 mils, 8800 mils, 8900 mils, and 9000 mils.

[0068] Optionally, the circuit board assembly 100 further includes a field programmable gate array (FPGA) chip 40 . The field programmable gate array chip 40 is disposed on the circuit board 10 .

[0069] In a plan view of the circuit board assembly 100 , the timing controller 20 is located between the first memory 31 and the programmable gate array chip 40 . The distance between the timing controller 20 and the first memory 31 is smaller than the distance between the timing controller 20 and the programmable gate array chip 40 .

[0070] In this embodiment, by setting the timing controller 20 between the first memory 31 and the programmable gate array chip 40, the first serial peripheral interface bus SPI0 does not need to cross the programmable gate array chip 40 to electrically connect the timing control chip and the memory chip, thereby shortening the length of the first sub-line 15 of the first serial peripheral interface bus SPI0 and reducing the interference of the communication signal between the timing control chip and the memory chip. Compared with the related circuit board assembly 100a, in the circuit board assembly 100 of the present application, the signal transmission between the timing control chip and the memory chip is more stable.

[0071] Optionally, in the plan view of the circuit board assembly 100, the first memory 31 and the programmable gate array chip 40 are respectively located on both sides of the timing controller 20 in the long side direction X of the circuit board 10. The length of the first sub-line 15 is less than or equal to 3000 mils.

[0072] In this embodiment, by setting the timing controller 20 between the first memory 31 and the programmable gate array chip 40, the layout of the circuit board assembly 100 of the present application is adjusted compared to the layout of the related circuit board assembly 100a, thereby further reducing the length of the first sub-line 15 of the first serial peripheral interface bus SPI0.

[0073] Optionally, the length of the first sub-line 15 is a value selected from the group consisting of 100 mils, 200 mils, 300 mils, 400 mils, 500 mils, 600 mils, 700 mils, 800 mils, 900 mils, 1000 mils, 1100 mils, 1200 mils, 1300 mils, 1400 mils, 1500 mils, 1600 mils, 1700 mils, 1800 mils, 1900 mils, 2000 mils, 2100 mils, 2200 mils, 2300 mils, 2400 mils, 2500 mils, 2600 mils, 2700 mils, 2800 mils, 2900 mils, and 3000 mils.

[0074] Optionally, the plurality of first sub-lines 15 include a first data input signal line i1, a first data output signal line o1, a first clock signal line ck1, and a first chip select signal line cs1. The first data input signal line i1 is electrically connected to the timing controller 20 and the first memory 31. The first data output signal line o1 is electrically connected to the timing controller 20 and the first memory 31. The first clock signal line ck1 is electrically connected to the timing controller 20 and the first memory 31. The first chip select signal line cs1 is electrically connected to the timing controller 20 and the first memory 31.

[0075] In the present embodiment, the first data input signal line i1 and the first data output signal line o1 are used to send and receive data between the timing controller 20 and the first memory 31. The first clock signal line ck1 is controlled by the timing controller 20 and is used to synchronize data transmission. The first chip select signal line cs1 is used to activate the first memory 31. In the present application, the circuit board assembly 100 includes a plurality of memories, including at least a first memory 31 and a second memory 32. Therefore, in the present embodiment, the first chip select signal line cs1 is used to activate the first memory 31, and the first chip select signal line cs1 is controlled by the master device to select the slave device currently communicating.

[0076] Optionally, an absolute value of a length difference between any two of the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, and the first chip select signal line cs1 is less than 20 mils.

[0077] In this embodiment, in order to improve the signal quality of the first serial peripheral interface bus SPI0, it is necessary to make the multiple first sub-lines 15 equal in length. By controlling the absolute value of the length difference between any two of the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, and the first chip select signal line cs1 to be less than 20 mils, the delay of the multiple first sub-lines 15 can be controlled, so that the transmission speeds of the multiple first sub-lines 15 are similar, thereby improving the signal quality of the first serial peripheral interface bus SPI0.

[0078] Optionally, the absolute value of the length difference between any two of the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, and the first chip select signal line cs1 is 0.1 mil, 0.2 mil, 0.3 mil, 0.4 mil, 0.5 mil, 0.6 mil, 0.7 mil, 0.8 mil, 0.9 mil, 1.0 mil, 1.1 mil, 1.2 mil, 1.3 mil, 1.4 mil, 1.5 mil, 1.6 mil, 1.7 mil, 1.8 mil, 1.9 mil, 2.0 mil, 2.1 mil, 2.2 mil, 2.3 mil, 2.4 mil, 2.5 mil, 2.6 mil, 2.7 mil, 2.8 mil, 2.9 mil, 3.0 mil, 3.1 mil, 3.2 mil, 3.3 mil, 3.4 mil, 3.5 mil, 3.6 mil, 3.7 mil, 3.8 mil, 3.9 mil, 4.0 mil, 4.1 mil, 4.2 mil, 4.3 mil, 4.4 mil, 4.5 mil, 4.6 mil, 4.7 mil, 4.8 mil, 4.9 mil, 5.0 mil, 5.1 mil, 5.9 mil, 1 mil, 3.2 mil, 3.3 mil, 3.4 mil, 3.5 mil, 3.6 mil, 3.7 mil, 3.8 mil, 3.9 mil, 4.0 mil, 4.1 mil, 4.2 mil, 4.3 mil, 4.4 mil, 4.5 mil, 4.6 mil, 4.7 mil, 4.8 mil, 4.9 mil, 5.0 mil, 5.1 mil, 5.2 mil, 5.3 mil, 5.4 mil, 5.5 mil, 5.6 mil, 5.7 mil, 5.8 mil, 5.9 mil, 5.0 mil, 5.1 mil, 5.2 mil, 5.3 mil, 5.4 mil, 5.6 mil, 5.7 mil, 5.8 .2 mil, 5.3 mil, 5.4 mil, 5.5 mil, 5.6 mil, 5.7 mil, 5.8 mil, 5.9 mil, 6.0 mil, 6.1 mil, 6.2 mil, 6.3 mil, 6.4 mil, 6.5 mil, 6.6 mil, 6.7 mil, 6.8 mil, 6.9 mil, 7.0 mil, 7.1 mil, 7.2 mil, 7.3 mil, 7.4 mil, 7.5 mil, 7.6 mil, 7.7 mil, 7.8 mil, 7.9 mil, 8.0 mil, 8.1 mil, 8.2 mil, 8.3 mil, 8.4 mil, 8.5 mil, 8.6 mil, 8.7 mil, 8.8 mil, 8.9 mil, 9.0 mil, 9.1 mil, 9.2 mil, 9.3 mil , 9.4 mil, 9.5 mil, 9.6 mil, 9.7 mil, 9.8 mil, 9.9 mil, 10.0 mil, 10.1 mil, 10.2 mil, 10.3 mil, 10.4 mil, 10.5 mil, 10.6 mil, 10.7 mil, 10.8 mil, 10.9 mil, 11.0 mil, 11.1 mil, 11.2 mil, 11.3 mil, 11.4 mil, 11.5 mil, 11.6 mil, 11.7 mil, 11.8 mil, 11.9 mil, 12.0 mil, 12.1 mil, 12.2 mil, 12.3 mil, 12.4 mil, 12.5 mil, 12.6 mil, 12.7 mil, 12.8 mil, 12.9 mil, 13. 0 mil, 13.1 mil, 13.2 mil, 13.3 mil, 13.4 mil, 13.5 mil, 13.6 mil, 13.7 mil, 13.8 mil, 13.9 mil, 14.0 mil, 14.1 mil, 14.2 mil, 14.3 mil, 14.4 mil, 14.5 mil, 14.6 mil, 14.7 mil, 14.8 mils, 14.9 mils, 15.0 mils, 15.1 mils, 15.2 mils, 15.3 mils, 15.4 mils, 15.5 mils, 15.6 mils, 15.7 mils, 15.8 mils, 15.9 mils, 16.0 mils, 16.1 mils, 16.2 mils, 16.3 mils, 16.4 mils, 16.5 mils, 16.6 mils, 16.7 mils, 16.8 mils, 16.9 mils, 17.0 mils, 17.1 mils, 17.2 mils, 17.3 mils, 17.4 mils, One of 17.5 mils, 17.6 mils, 17.7 mils, 17.8 mils, 17.9 mils, 18.0 mils, 18.1 mils, 18.2 mils, 18.3 mils, 18.4 mils, 18.5 mils, 18.6 mils, 18.7 mils, 18.8 mils, 18.9 mils, 19.0 mils, 19.1 mils, 19.2 mils, 19.3 mils, 19.4 mils, 19.5 mils, 19.6 mils, 19.7 mils, 19.8 mils, 19.9 mils, 20 mils.

[0079] Optionally, the plurality of first sub-lines 15 further include a first write protection input signal line wp1 and a first state holding input signal line hold1. The first write protection input signal line wp1 is electrically connected to the timing controller 20 and the first memory 31. The first state holding input signal line hold1 is electrically connected to the timing controller 20 and the first memory 31.

[0080] In the present embodiment, the first write protection signal line is used to prevent an unexpected write operation to the first memory 31 connected to the first write protection signal line. The first state maintenance input signal line hold1 is used to suspend or maintain the operation of the first memory 31 so that the timing controller 20 can process other tasks. For example, when the signal output by the first state maintenance input signal line hold1 is one of a logic low level and a logic high level, the first memory 31 will suspend the operation and maintain its current state. When the signal output by the first state maintenance input signal line hold1 is the other of a logic low level and a logic high level, the read and write operations of the first memory 31 can continue.

[0081] In the present application, the first serial peripheral interface bus SPI0 may include only four first sub-lines 15, and the four first sub-lines 15 are respectively the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, and the first chip select signal line cs1. The first serial peripheral interface bus SPI0 may also include only six first sub-lines 15, and the six first sub-lines 15 are respectively the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, the first chip select signal line cs1, the first write protection input signal line wp1, and the first state maintenance input signal line hold1.

[0082] Optionally, the absolute value of the length difference between any two of the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, the first chip select signal line cs1, the first write protection input signal line wp1, and the first state maintenance input signal line hold1 is less than 10 mils.

[0083] In this embodiment, in order to further improve the signal quality of the first serial peripheral interface bus SPI0, by controlling the absolute value of the length difference between any two of the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, the first chip select signal line cs1, the first write protection input signal line wp1, and the first state maintenance input signal line hold1 to be less than 10 mils, the delay of the multiple first sub-lines 15 can be further controlled, so that the transmission speeds of the multiple first sub-lines 15 tend to be the same, thereby further improving the signal quality of the first serial peripheral interface bus SPI0.

[0084] Optionally, the absolute value of the length difference between any two of the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, the first chip select signal line cs1, the first write protection input signal line wp1, and the first state maintenance input signal line hold1 is 0.1 mil, 0.2 mil, 0.3 mil, 0.4 mil, 0.5 mil, 0.6 mil, 0.7 mil, 0.8 mil, 0.9 mil, 1.0 mil, 1.1 mil, 1.2 mil, 1.3 mil. , 1.4 mil, 1.5 mil, 1.6 mil, 1.7 mil, 1.8 mil, 1.9 mil, 2.0 mil, 2.1 mil, 2.2 mil, 2.3 mil, 2.4 mil, 2.5 mil, 2.6 mil, 2.7 mil, 2.8 mil, 2.9 mil, 3.0 mil, 3.1 mil, 3.2 mil, 3.3 mil, 3.4 mil, 3.5 mil, 3.6 mil, 3.7 mil, 3.8 mil, 3.9 mil, 4.0 mil, 4.1 mil, 4.2 mil, 4. 3 mil, 4.4 mil, 4.5 mil, 4.6 mil, 4.7 mil, 4.8 mil, 4.9 mil, 5.0 mil, 5.1 mil, 5.2 mil, 5.3 mil, 5.4 mil, 5.5 mil, 5.6 mil, 5.7 mil, 5.8 mil, 5.9 mil, 6.0 mil, 6.1 mil, 6.2 mil, 6.3 mil, 6.4 mil, 6.5 mil, 6.6 mil, 6.7 mil, 6.8 mil, 6.9 mil, 7.0 mil, 7.1 mil, 7.2 mil mil, 7.3 mil, 7.4 mil, 7.5 mil, 7.6 mil, 7.7 mil, 7.8 mil, 7.9 mil, 8.0 mil, 8.1 mil, 8.2 mil, 8.3 mil, 8.4 mil, 8.5 mil, 8.6 mil, 8.7 mil, 8.8 mil, 8.9 mil, 9.0 mil, 9.1 mil, 9.2 mil, 9.3 mil, 9.4 mil, 9.5 mil, 9.6 mil, 9.7 mil, 9.8 mil, 9.9 mil, and 10.0 mil.

[0085] Optionally, the absolute value of the difference in length between the first data input signal line i1 and the first clock signal line ck1 is less than 10 mils. The absolute value of the difference in length between the first data output signal line o1 and the first clock signal line ck1 is less than 10 mils. The absolute value of the difference in length between the first chip select signal line cs1 and the first clock signal line ck1 is less than 10 mils. The absolute value of the difference in length between the first write protection input signal line wp1 and the first clock signal line ck1 is less than 10 mils. The absolute value of the difference in length between the first state maintenance input signal line hold1 and the first clock signal line ck1 is less than 10 mils.

[0086] In this embodiment, the first clock signal line ck1 is taken as the target line, and the remaining first sub-lines 15 are treated as equal in length compared to the first clock signal line ck1, so that the delay of multiple first sub-lines 15 can be further controlled, so that the transmission speeds of multiple first sub-lines 15 tend to be the same, thereby further improving the signal quality of the first serial peripheral interface bus SPI0.

[0087] Optional, see Figure 3 , the circuit board 10 includes a first area A1. The first area A1 includes a proximal area A2 and a distal area A3 located at least on one side of the proximal area A2. The timing controller 20 and the first memory 31 are located in the proximal area A2. A plurality of first sub-lines 15 are arranged at intervals in the first area A1. At least one first sub-line 15 is located in the proximal area A2, and at least one first sub-line 15 is located in the distal area A3. The first sub-line 15 located in the proximal area A2 includes a plurality of first bending portions W.

[0088] In the plan view of the circuit board assembly 100 , the pattern of the first bending portion W is one of an arc structure, a folded line structure or a square structure.

[0089] In this embodiment, the shortest distance between the two endpoints of the first sub-line 15 arranged in the proximal area A2 is smaller than the shortest distance between the two endpoints of the first sub-line 15 arranged in the distal area A3. If the first routing line is arranged along the shortest distance between the two endpoints of the first sub-line 15 in the proximal area A2, the difference between the length of the first sub-line 15 in the proximal area A2 and the length of the first sub-line 15 in the distal area A3 will be greater than 10 mils, which cannot meet the signal quality requirements. In order to achieve equal length processing of different first sub-lines 15, the present application sets a first bending portion W in the first sub-line 15 in the proximal area A2, so that a part of the first sub-line 15 in the proximal area A2 forms a serpentine route, thereby increasing the total length of the first sub-line 15 in the proximal area A2, and making the difference between the length of the first sub-line 15 in the proximal area A2 and the length of the first sub-line 15 in the distal area A3 less than or equal to 10 mils. The delay of the multiple first sub-lines 15 can be further controlled, so that the transmission speeds of the multiple first sub-lines 15 tend to be the same, thereby further improving the signal quality of the first serial peripheral interface bus SPI0.

[0090] Optional, see Figure 2 The circuit board assembly 100 further includes a programming interface 60. The programming interface 60 is disposed on the circuit board 10. The programming interface 60 is electrically connected to the first memory 31. The circuit board 10 includes a third serial peripheral interface bus SPI2. The third serial peripheral interface bus SPI2 includes a plurality of fourth sub-lines. The fourth sub-line is electrically connected to the programming interface 60 and the timing controller 20. The length of the fourth sub-line is less than 9000 mils.

[0091] Optionally, the timing controller 20 is located between the programming interface 60 and the programmable gate array chip 40. In the plan view of the circuit board assembly 100, the programming interface 60 is located on one side of the first memory 31 in the short side direction Y of the circuit board 10.

[0092] In this embodiment, by setting the timing controller 20 between the burning interface 60 and the programmable gate array chip 40, the layout of the circuit board assembly 100 of the present application is adjusted compared to the layout of the related circuit board assembly 100a, thereby reducing the length of the third sub-line 17 of the third serial peripheral interface bus SPI2.

[0093] Preferably, the length of the third sub-line 17 is less than or equal to 3000 mils.

[0094] Optionally, the length of the third sub-line 17 is a value selected from the group consisting of 100 mils, 200 mils, 300 mils, 400 mils, 500 mils, 600 mils, 700 mils, 800 mils, 900 mils, 1000 mils, 1100 mils, 1200 mils, 1300 mils, 1400 mils, 1500 mils, 1600 mils, 1700 mils, 1800 mils, 1900 mils, 2000 mils, 2100 mils, 2200 mils, 2300 mils, 2400 mils, 2500 mils, 2600 mils, 2700 mils, 2800 mils, 2900 mils, and 3000 mils.

[0095] Optionally, the circuit board assembly 100 further includes a level shifter 50 (Level Shift IC). The level shifter 50 is disposed on the circuit board 10 and is electrically connected to the timing controller 20.

[0096] In a plan view of the circuit board assembly 100 , the first memory 31 is located between the level converter 50 and the timing controller 20 .

[0097] In this embodiment, the level converter 50 is used to output a gate driver on array (GOA) signal to the display panel.

[0098] Optional, see Figure 4 The circuit board 10 includes a first wiring layer 11 , a reference ground layer 12 , and a second wiring layer 13 stacked along the thickness direction of the circuit board 10 .

[0099] The first wiring layer 11 includes a first serial peripheral interface bus SPI0. The reference ground layer 12 is insulated from the first wiring layer 11 and the second wiring layer 13 respectively. The reference ground layer 12 is connected to the reference ground potential. The second wiring layer 13 includes a row drive signal bus 14. The row drive signal bus 14 is electrically connected to the level converter 50. The row drive signal bus 14 is configured to output a row drive signal to the display panel.

[0100] In the present embodiment, when the level converter 50 outputs the row drive signal to the reality panel through the row drive signal bus 14, it will interfere with the signal transmitted in the first serial peripheral interface bus SPI0. Therefore, in the present embodiment, the first serial peripheral interface bus SPI0 and the row drive signal bus 14 are arranged in layers, and a reference ground layer 12 is arranged between the two layers of wiring. The reference ground layer 12 includes a prepreg. The prepreg, as a dielectric material, plays a role of filling and bonding, ensures electrical isolation and mechanical stability between the layers, and can provide a return path and a potential reference point for the signal and power supply. By arranging the reference ground layer 12 between the first wiring layer 11 and the second wiring layer 13, electrical isolation between the first wiring layer 11 and the second wiring layer 13 can be achieved, the signal interference between the first serial peripheral interface bus SPI0 and the row drive signal bus 14 is reduced, and the signal quality of the first serial peripheral interface bus SPI0 and the row drive signal bus 14 is improved.

[0101] Optionally, the row driving signal bus 14 includes a plurality of second sub-lines 16. The second sub-lines 16 are configured to output row driving signals to the display panel.

[0102] In this embodiment, the plurality of second sub-lines 16 include at least one row driving clock signal line, at least one pull-down signal line, and at least one scan start signal line.

[0103] Optional, see Figure 5 The orthographic projections of the plurality of second sub-lines 16 on the reference stratum 12 are arranged at intervals, a gap K is formed between the orthographic projections of two adjacent second sub-lines 16 on the reference stratum 12 , and at least one gap K does not completely overlap with the orthographic projection of the first sub-line 15 on the reference stratum 12 .

[0104] In this embodiment, by setting the orthographic projection of the first sub-line 15 on the reference stratum 12 and the orthographic projection of the second sub-line 16 on the reference stratum 12 to non-interlaced routing, the signal interference between the first serial peripheral interface bus SPI0 and the row drive signal bus 14 is reduced, and the signal quality of the first serial peripheral interface bus SPI0 and the row drive signal bus 14 is improved.

[0105] It should be understood that non-staggered routing means that the orthographic projection of the first sub-line 15 on the reference stratum 12 and the orthographic projection of the second sub-line 16 on the reference stratum 12 are not arranged alternately, but the partial gap K does not overlap with the orthographic projection of the first sub-line 15 on the reference stratum 12.

[0106] Optional, see Figure 6 , the orthographic projection of at least one first sub-line 15 on the reference stratum 12 intersects with the orthographic projection of at least one second sub-line 16 on the reference stratum 12 .

[0107] In this embodiment, the orthographic projection of the first sub-line 15 on the reference stratum 12 and the orthographic projection of the second sub-line 16 on the reference stratum 12 are cross-arranged, thereby reducing signal interference between the first serial peripheral interface bus SPI0 and the row drive signal bus 14 and improving the signal quality of the first serial peripheral interface bus SPI0 and the row drive signal bus 14.

[0108] Optionally, the circuit board assembly 100 further includes a second memory 32 . The second memory 32 is disposed on the circuit board 10 .

[0109] In a plan view of the circuit board assembly 100, the second memory 32 is located between the level converter 50 and the timing controller 20. The second memory 32 and the first memory 31 are arranged in a spaced relationship along the short side direction Y of the circuit board 10.

[0110] The first wiring layer 11 also includes a second serial peripheral interface bus SPI1. The second serial peripheral interface bus SPI1 is electrically connected to the timing controller 20 and the second memory 32. The second serial peripheral interface bus SPI1 is spaced apart from the first serial peripheral interface bus SPI0 on a side of the reference ground layer 12 away from the second wiring layer 13.

[0111] The second serial peripheral interface bus SPI1 includes a plurality of third sub-lines 17 . The third sub-lines 17 are electrically connected to the timing controller 20 and the second memory 32 .

[0112] In this embodiment, the circuit board assembly 100 includes a first memory 31 and a second memory 32. The timing controller 20 is electrically connected to the second memory 32 and the timing controller 20 via a second serial peripheral interface bus SPI1.

[0113] The second serial peripheral interface bus SPI1 may also be interfered by other signals when transmitting data. Therefore, the second serial peripheral interface bus SPI1 may apply the corresponding improvements of the first serial peripheral interface bus SPI0 in this application to improve the signal quality of the second serial peripheral interface bus SPI1. In order to avoid redundancy, it will not be elaborated here.

[0114] Optional, see Figure 7, the orthographic projections of the plurality of second sub-lines 16 on the reference stratum 12 are arranged at intervals, a gap K is formed between the orthographic projections of two adjacent second sub-lines 16 on the reference stratum 12, and at least one of the gaps K does not completely overlap with the orthographic projection of the third sub-line 17 on the reference stratum 12.

[0115] In this embodiment, by setting the orthographic projection of the third sub-line 17 on the reference stratum 12 and the orthographic projection of the second sub-line 16 on the reference stratum 12 to non-interlaced routing, the signal interference between the second serial peripheral interface bus SPI1 and the row drive signal bus 14 is reduced, and the signal quality of the second serial peripheral interface bus SPI1 and the row drive signal bus 14 is improved.

[0116] Optionally, the orthographic projection of at least one third sub-line 17 on the reference stratum 12 intersects with the orthographic projection of at least one second sub-line 16 on the reference stratum 12 .

[0117] In this embodiment, the orthographic projection of the third sub-line 17 on the reference stratum 12 is cross-arranged with the orthographic projection of the second sub-line 16 on the reference stratum 12, thereby reducing signal interference between the second serial peripheral interface bus SPI1 and the row drive signal bus 14 and improving the signal quality of the second serial peripheral interface bus SPI1 and the row drive signal bus 14.

[0118] The above is a detailed description of the specific implementation of the present application. The above implementation disclosed in the present application is only the preferred implementation of the present application. For ordinary technicians in this field, many modifications and improvements can be made without departing from the concept of the present application. These modifications and improvements all fall within the scope of protection defined by the claims of the present application.

Claims

1. A circuit board assembly, characterized in that: include: A circuit board, comprising a first serial peripheral interface bus, wherein the first serial peripheral interface bus comprises a plurality of first sub-lines; A timing controller, arranged on the circuit board; as well as A first memory, disposed on the circuit board; Wherein, a plurality of the first sub-lines electrically connect the timing controller and the first memory, and a length of the first sub-line is less than or equal to 9000 mils.

2. The circuit board assembly according to claim 1, wherein: The circuit board assembly further comprises a programmable gate array chip, and the programmable gate array chip is arranged on the circuit board; In a plan view of the circuit board assembly, the timing controller is located between the first memory and the programmable gate array chip, and a distance between the timing controller and the first memory is smaller than a distance between the timing controller and the programmable gate array chip.

3. The circuit board assembly according to claim 2, wherein: In a plan view of the circuit board assembly, the first memory and the programmable gate array chip are respectively located on both sides of the timing controller in the long side direction of the circuit board; The length of the first sub-line is less than or equal to 3000 mils.

4. The circuit board assembly according to claim 1, wherein: The plurality of first sub-lines include: A first data input signal line electrically connecting the timing controller and the first memory; A first data output signal line electrically connecting the timing controller and the first memory; A first clock signal line electrically connecting the timing controller and the first memory; and A first chip selection signal line electrically connecting the timing controller and the first memory; The absolute value of the length difference between any two of the first data input signal line, the first data output signal line, the first clock signal line, and the first chip select signal line is less than 20 mils.

5. The circuit board assembly according to claim 4, wherein: The plurality of first sub-lines further include: A first write protection input signal line electrically connecting the timing controller and the first memory; A first state maintaining input signal line electrically connecting the timing controller and the first memory; Among them, the absolute value of the length difference between any two of the first data input signal line, the first data output signal line, the first clock signal line, the first chip select signal line, the first write protection input signal line, and the first state maintenance input signal line is less than 10 mils.

6. The circuit board assembly according to claim 1, wherein: The circuit board assembly further includes a level converter, which is disposed on the circuit board and electrically connected to the timing controller; In a plan view of the circuit board assembly, the first memory is located between the level converter and the timing controller; The circuit board comprises a first wiring layer, a reference ground layer and a second wiring layer stacked along the thickness direction of the circuit board; The first routing layer includes the first serial peripheral interface bus; The reference ground layer is insulated from the first routing layer and the second routing layer respectively, and the reference ground layer is connected to a reference ground potential; The second wiring layer includes a row drive signal bus, the row drive signal bus is electrically connected to the level converter, and the row drive signal bus is configured to output a row drive signal to the display panel.

7. The circuit board assembly according to claim 6, wherein: The row drive signal bus includes a plurality of second sub-lines, and the second sub-lines are configured to output row drive signals to the display panel; The orthographic projection of at least one of the first sub-lines on the reference stratum intersects with the orthographic projection of at least one of the second sub-lines on the reference stratum; and / or, The orthographic projections of the plurality of second sub-lines on the reference formation are arranged at intervals, a gap is formed between the orthographic projections of two adjacent second sub-lines on the reference formation, and at least one of the gaps does not completely overlap with the orthographic projection of the first sub-line on the reference formation.

8. The circuit board assembly according to claim 6, wherein: The circuit board assembly further includes a second memory, which is disposed on the circuit board; In a plan view of the circuit board assembly, the second memory is located between the level converter and the timing controller, and the second memory and the first memory are arranged at intervals along a short side direction of the circuit board; The first wiring layer further includes a second serial peripheral interface bus, the second serial peripheral interface bus is electrically connected to the timing controller and the second memory, and the second serial peripheral interface bus is spaced apart from the first serial peripheral interface bus on a side of the reference ground layer away from the second wiring layer; The second serial peripheral interface bus includes a plurality of third sub-lines, and the third sub-lines are electrically connected to the timing controller and the second memory; The row drive signal bus includes a plurality of second sub-lines, and the second sub-lines are configured to output row drive signals to the display panel; The orthographic projection of at least one of the third sub-lines on the reference stratum intersects with the orthographic projection of at least one of the second sub-lines on the reference stratum; and / or, The orthographic projections of the plurality of second sub-lines on the reference formation are arranged at intervals, a gap is formed between the orthographic projections of two adjacent second sub-lines on the reference formation, and at least one of the gaps does not completely overlap with the orthographic projection of the third sub-line on the reference formation.

9. The circuit board assembly according to any one of claims 1 to 8, characterized in that: The circuit board includes a first area, the first area includes a proximal area and a distal area located at least on one side of the proximal area, and the timing controller and the first memory are located in the proximal area; A plurality of the first sub-lines are arranged at intervals in the first region, at least one of the first sub-lines is located in the proximal region, and at least one of the first sub-lines is located in the distal region; The first sub-line located in the proximal region includes a plurality of first bending portions; In the plan view of the circuit board assembly, the pattern of the first bending portion is one of an arc structure, a folded line structure or a square structure.

10. The circuit board assembly according to any one of claims 1 to 8, characterized in that: The circuit board assembly further includes a burning interface, which is arranged on the circuit board and is electrically connected to the first memory; The circuit board includes a third serial peripheral interface bus, the third serial peripheral interface bus includes a plurality of fourth sub-lines, the fourth sub-lines are electrically connected to the burning interface and the timing controller, and the length of the fourth sub-lines is less than 9000 mils.

11. A display device, characterized in that: The invention comprises a circuit board assembly as claimed in any one of claims 1 to 10.

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