Circuit board assembly and display device

Abstract

The application discloses a circuit board assembly and a display device. The circuit board assembly comprises a circuit board, a timing controller and a first memory. The circuit board comprises a first serial peripheral interface bus, and the first serial peripheral interface bus comprises a plurality of first sub-lines. The timing controller is arranged on the circuit board. The first memory is arranged on the circuit board. The plurality of first sub-lines are electrically connected to the timing controller and the first memory. The length of the first sub-line is less than or equal to 9000 mil. The application can reduce the length of the serial peripheral interface bus electrically connecting the timing control chip and the memory chip, thereby shortening the communication signal transmission path between the timing control chip and the memory chip, and improving the stability of the signal transmission between the timing control chip and the memory chip.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a circuit board assembly and a display device. Background Technology

[0002] A printed circuit board assembly (PCBA) typically contains two main control components, multiple flash memory chips, a level shifter IC, and a programming interface. The main control components can be field-programmable gate arrays (FPGAs) or timer control registers (Tcon). In related technologies, the timing control chip and flash memory chips are located on either side of the FPGA along the length of the PCB.

[0003] During the programming process of printed circuit board components, programming failures may occur. The reason for this phenomenon is that the trace length of the Serial Peripheral Interface (SPI) bus that electrically connects the timing control chip and the memory chip is relatively long. This causes the communication signals between the timing control chip and the memory chip to be interfered with by many other signals (such as the GOA signal output by the level conversion chip), resulting in unstable signal transmission between the timing control chip and the memory chip.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this application is to provide a circuit board and a display device that can reduce the length of the serial peripheral interface bus that electrically connects the timing control chip and the memory chip, thereby shortening the communication signal transmission path between the timing control chip and the memory chip and improving the stability of signal transmission between the timing control chip and the memory chip.

[0006] To solve the above problems, the technical solution of this application is as follows:

[0007] In a first aspect, this application proposes a circuit board assembly, comprising:

[0008] The circuit board includes a first serial peripheral interface bus, which includes multiple first sub-lines.

[0009] A timing controller is mounted on the circuit board; and

[0010] A first memory is disposed on the circuit board;

[0011] Among them, multiple first sub-lines are electrically connected to the timing controller and the first memory, and the length of the first sub-lines is less than or equal to 9000 mils.

[0012] In one embodiment of this application, the circuit board assembly further includes a programmable gate array (PGA) chip disposed on the circuit board;

[0013] In a plan view of the circuit board assembly, the timing controller is located between the first memory and the programmable gate array chip, and the distance between the timing controller and the first memory is less than the distance between the timing controller and the programmable gate array chip.

[0014] In one embodiment of this application, in a plan view of the circuit board assembly, the first memory and the programmable gate array chip are respectively located on both sides of the timing controller along the long side of the circuit board;

[0015] The length of the first sub-line is less than or equal to 3000 mils.

[0016] In one embodiment of this application, the plurality of first sub-lines include:

[0017] The first data input signal line is electrically connected to the timing controller and the first memory;

[0018] The first data output signal line is electrically connected to the timing controller and the first memory;

[0019] A first clock signal line is electrically connected to the timing controller and the first memory; and

[0020] The first select signal line is electrically connected to the timing controller and the first memory;

[0021] Wherein, the absolute value of the length difference between any two of the first data input signal line, the first data output signal line, the first clock signal line, and the first chip select signal line is less than 20 mils.

[0022] In one embodiment of this application, the plurality of first sub-lines further include:

[0023] The first write-protect input signal line is electrically connected to the timing controller and the first memory;

[0024] The first state maintains the input signal line, which is electrically connected to the timing controller and the first memory;

[0025] Wherein, the absolute value of the length difference between any two of the first data input signal line, the first data output signal line, the first clock signal line, the first chip select signal line, the first write protect input signal line, and the first state maintenance input signal line is less than 10 mils.

[0026] In one embodiment of this application, the circuit board assembly further includes a level converter, which is disposed on the circuit board and electrically connected to the timing controller;

[0027] In a plan view of the circuit board assembly, the first memory is located between the level shifter and the timing controller;

[0028] The circuit board includes a first trace layer, a reference ground layer, and a second trace layer stacked along the thickness direction of the circuit board;

[0029] The first routing layer includes the first serial peripheral interface bus;

[0030] The reference ground layer is insulated from the first trace layer and the second trace layer, respectively, and the reference ground layer is connected to the reference ground potential;

[0031] The second routing layer includes a horizontal drive signal bus, which is electrically connected to the level converter and is configured to output a horizontal drive signal to the display panel.

[0032] In one embodiment of this application, the row drive signal bus includes a plurality of second sub-lines, the second sub-lines being configured to output row drive signals to the display panel;

[0033] At least one of the first sub-lines' orthogonal projections onto the reference stratum intersects with at least one of the second sub-lines' orthogonal projections onto the reference stratum; and / or,

[0034] Multiple second sub-lines are spaced apart by their orthogonal projections onto the reference stratum, and gaps are formed between the orthogonal projections of two adjacent second sub-lines onto the reference stratum. At least one of the gaps does not completely overlap with the orthogonal projection of the first sub-line onto the reference stratum.

[0035] In one embodiment of this application, the circuit board assembly further includes a second memory disposed on the circuit board;

[0036] In a plan view of the circuit board assembly, the second memory is located between the level shifter and the timing controller, and the second memory and the first memory are spaced apart along the short side of the circuit board.

[0037] The first routing layer also includes a second serial peripheral interface bus, which is electrically connected to the timing controller and the second memory. The second serial peripheral interface bus is disposed on the side of the reference ground layer away from the second routing layer, spaced apart from the first serial peripheral interface bus.

[0038] The second serial peripheral interface bus includes multiple third sub-lines, which are electrically connected to the timing controller and the second memory.

[0039] The row drive signal bus includes multiple second sub-lines, which are configured to output row drive signals to the display panel.

[0040] At least one of the third sub-lines, when projected onto the reference stratum, intersects with the orthogonal projection of at least one of the second sub-lines onto the reference stratum; and / or,

[0041] Multiple second sub-lines are spaced apart by their orthogonal projections onto the reference stratum, and gaps are formed between the orthogonal projections of two adjacent second sub-lines onto the reference stratum. At least one of the gaps does not completely overlap with the orthogonal projection of the third sub-line onto the reference stratum.

[0042] In one embodiment of this application, the circuit board includes a first region, the first region including a proximal region and a distal region located on at least one side of the proximal region, the timing controller and the first memory being located in the proximal region;

[0043] Multiple first sub-lines are spaced apart in the first region, with at least one first sub-line located in the proximal region and at least one first sub-line located in the distal region.

[0044] The first sub-line located in the proximal region includes a plurality of first bends;

[0045] In a plan view of the circuit board assembly, the pattern of the first bend is one of an arc-shaped structure, a zigzag structure, or a square structure.

[0046] In one embodiment of this application, the circuit board assembly further includes a programming interface, which is disposed on the circuit board and electrically connected to the first memory.

[0047] The circuit board includes a third serial peripheral interface bus, which includes multiple fourth sub-lines. The fourth sub-lines are electrically connected to the programming interface and the timing controller. The length of the fourth sub-lines is less than 9000 mils.

[0048] Secondly, this application proposes a display device including a circuit board assembly, the circuit board assembly including a circuit board, a timing controller and a first memory, the circuit board including a first serial peripheral interface bus, the first serial peripheral interface bus including a plurality of first sub-lines; the timing controller is disposed on the circuit board; the first memory is disposed on the circuit board; wherein, the plurality of first sub-lines are electrically connected to the timing controller and the first memory, and the length of the first sub-lines is less than or equal to 9000 mils.

[0049] In this application, the first serial peripheral interface bus that electrically connects the timing controller and the first memory includes multiple first sub-lines. By controlling the length of each first sub-line to within 9000 mils, the length of the serial peripheral interface bus that electrically connects the timing controller chip and the memory chip can be reduced, thereby shortening the communication signal transmission path between the timing controller chip and the memory chip and improving the stability of signal transmission between the timing controller chip and the memory chip. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of a circuit board assembly in related technologies;

[0051] Figure 2 This is a schematic diagram of one embodiment of the circuit board assembly of this application;

[0052] Figure 3 This is a schematic diagram of one embodiment of the circuit board assembly of this application;

[0053] Figure 4 This is a schematic diagram of one embodiment of the circuit board of this application;

[0054] Figure 5 This is a schematic diagram of an embodiment of the orthographic projection of multiple first sub-lines onto a reference stratum and the orthographic projection of multiple second sub-lines onto a reference stratum in this application;

[0055] Figure 6 This is a schematic diagram of an embodiment of the orthographic projection of multiple first sub-lines onto a reference stratum and the orthographic projection of multiple second sub-lines onto a reference stratum in this application;

[0056] Figure 7 This is a schematic diagram of an embodiment of the orthographic projection of multiple third sub-lines onto a reference stratum and the orthographic projection of multiple second sub-lines onto a reference stratum in this application;

[0057] Figure 8 This is a schematic diagram of an embodiment of the orthographic projection of multiple first sub-lines onto a reference stratum and the orthographic projection of multiple second sub-lines onto a reference stratum in this application. Detailed Implementation

[0058] The terms used in this specification and claims have the meanings that are commonly understood by one of ordinary skill in the art to which this application pertains. The terms used in this specification and claims are for the purpose of facilitating the description and understanding of this application only, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0059] Please see Figure 1 In the relevant circuit board assembly 100a, the timing control chip 20a and the memory chip 31a are located on opposite sides of the programmable gate array chip 40a along the length of the printed circuit board 10a. The Serial Peripheral Interface (SPI) bus needs to cross the programmable gate array chip 40a to electrically connect the timing control chip 20a and the memory chip 31a, resulting in a relatively long SPI bus length. This causes the communication signal between the timing control chip 20a and the memory chip 31a to be subject to interference from other signals (such as the GOA signal output by the level conversion chip), resulting in unstable signal transmission between the timing control chip 20a and the memory chip 31a.

[0060] This application discloses a display device, which can be a tablet computer, e-reader, electronic display screen, laptop computer, mobile phone, augmented reality (AR) / virtual reality (VR) device, media player, wearable device, digital camera, car navigation system, etc. The display device includes a display panel and a printed circuit board assembly (PCBA).

[0061] Optionally, the display panel can be a micro light-emitting diode (MicroLED) display panel, a mini light-emitting diode (MiniLED) display panel, or an organic light-emitting diode (OLED) display panel.

[0062] The circuit board assembly 100 is attached to the non-display area of ​​the display panel.

[0063] Please see Figure 2 This application proposes a circuit board assembly 100, including a printed circuit board 10 (PCB), a timing controller 20 (Tcon), and a first memory 31 (Flash).

[0064] Circuit board 10 includes a first Serial Peripheral Interface (SPI) bus. The first SPI bus SPI0 includes multiple first sub-lines 15. Timing controller 20 is disposed on circuit board 10. First memory 31 is disposed on circuit board 10. The multiple first sub-lines 15 are electrically connected to timing controller 20 and first memory 31, and the length of the first sub-lines 15 is less than or equal to 9000 mils.

[0065] In this embodiment, the first serial peripheral interface bus SPI0, which electrically connects the timing controller 20 and the first memory 31, includes multiple first sub-lines 15. By controlling the length of each first sub-line 15 to within 9000 mils, the length of the serial peripheral interface bus electrically connecting the timing controller chip and the memory chip can be reduced, thereby shortening the communication signal transmission path between the timing controller chip and the memory chip and improving the stability of signal transmission between the timing controller chip and the memory chip.

[0066] It's important to understand that the mil is a unit of length, also known as a milliinch. One inch equals 1000 mils.

[0067] Optionally, the length of the first sub-line 15 can be 100 mils, 200 mils, 300 mils, 400 mils, 500 mils, 600 mils, 700 mils, 800 mils, 900 mils, 1000 mils, 1100 mils, 1200 mils, 1300 mils, 1400 mils, 1500 mils, 1600 mils, 1700 mils, 1800 mils, 1900 mils, 2000 mils, 2100 mils, or 2200 mils. 2300 mil, 2400 mil, 2500 mil, 2600 mil, 2700 mil, 2800 mil, 2900 mil, 3000 mil, 3100 mil, 3200 mil, 3300 mil, 3400 mil, 3500 mil, 3600 mil, 3700 mil, 3800 mil, 3900 mil, 4000 mil, 4100 mil, 4200 mil, 4300 mil, 4400 mil, 4500 mil 4600 mil, 4700 mil, 4800 mil, 4900 mil, 5000 mil, 5100 mil, 5200 mil, 5300 mil, 5400 mil, 5500 mil, 5600 mil, 5700 mil, 5800 mil, 5900 mil, 6000 mil, 6100 mil, 6200 mil, 6300 mil, 6400 mil, 6500 mil, 6600 mil, 6700 mil, 6800 mil One of the following values: 6900 mil, 7000 mil, 7100 mil, 7200 mil, 7300 mil, 7400 mil, 7500 mil, 7600 mil, 7700 mil, 7800 mil, 7900 mil, 8000 mil, 8100 mil, 8200 mil, 8300 mil, 8400 mil, 8500 mil, 8600 mil, 8700 mil, 8800 mil, 8900 mil, or 9000 mil.

[0068] Optionally, the circuit board assembly 100 may also include a field-programmable gate array (FPGA) chip 40. The FPGA chip 40 is disposed on the circuit board 10.

[0069] In a plan view of the circuit board assembly 100, the timing controller 20 is located between the first memory 31 and the programmable gate array chip 40. The distance between the timing controller 20 and the first memory 31 is less than the distance between the timing controller 20 and the programmable gate array chip 40.

[0070] In this embodiment, by placing the timing controller 20 between the first memory 31 and the programmable gate array chip 40, the first serial peripheral interface bus SPI0 does not need to cross the programmable gate array chip 40 to electrically connect the timing control chip and the memory chip. This shortens the length of the first sub-line 15 of the first serial peripheral interface bus SPI0 and reduces interference to the communication signal between the timing control chip and the memory chip. Compared with the related circuit board assembly 100a, the signal transmission between the timing control chip and the memory chip in the circuit board assembly 100 of this application is more stable.

[0071] Optionally, in a plan view of the circuit board assembly 100, the first memory 31 and the programmable gate array chip 40 are located on either side of the timing controller 20 in the long side direction X of the circuit board 10. The length of the first sub-line 15 is less than or equal to 3000 mils.

[0072] In this embodiment, by placing the timing controller 20 between the first memory 31 and the programmable gate array chip 40, the layout of the circuit board assembly 100 of this application is adjusted compared with the layout of the related circuit board assembly 100a, thereby further reducing the length of the first sub-line 15 of the first serial peripheral interface bus SPI0.

[0073] Optionally, the length of the first sub-line 15 can be one of the following values: 100 mil, 200 mil, 300 mil, 400 mil, 500 mil, 600 mil, 700 mil, 800 mil, 900 mil, 1000 mil, 1100 mil, 1200 mil, 1300 mil, 1400 mil, 1500 mil, 1600 mil, 1700 mil, 1800 mil, 1900 mil, 2000 mil, 2100 mil, 2200 mil, 2300 mil, 2400 mil, 2500 mil, 2600 mil, 2700 mil, 2800 mil, 2900 mil, or 3000 mil.

[0074] Optionally, the multiple first sub-lines 15 include a first data input signal line i1, a first data output signal line o1, a first clock signal line ck1, and a first chip select signal line CS1. The first data input signal line i1 is electrically connected to the timing controller 20 and the first memory 31. The first data output signal line o1 is electrically connected to the timing controller 20 and the first memory 31. The first clock signal line ck1 is electrically connected to the timing controller 20 and the first memory 31. The first chip select signal line CS1 is electrically connected to the timing controller 20 and the first memory 31.

[0075] In this embodiment, the first data input signal line i1 and the first data output signal line o1 are used to send and receive data between the timing controller 20 and the first memory 31. The first clock signal line ck1 is controlled by the timing controller 20 and is used to synchronize data transmission. The first chip select signal line CS1 is used to activate the first memory 31. In this application, the circuit board assembly 100 includes multiple memories, including at least the first memory 31 and the second memory 32. Therefore, in this embodiment, the first chip select signal line CS1 is used to activate the first memory 31, and the first chip select signal line CS1 is controlled by the master device to select the slave device currently communicating.

[0076] Optionally, the absolute value of the length difference between any two of the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, and the first chip select signal line cs1 is less than 20 mils.

[0077] In this embodiment, to improve the signal quality of the first serial peripheral interface bus SPI0, multiple first sub-lines 15 need to be made of equal length. By controlling the absolute value of the length difference between any two of the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, and the first chip select signal line CS1 to be less than 20 mils, the delay of multiple first sub-lines 15 can be controlled, making the transmission speed of multiple first sub-lines 15 similar, thereby improving the signal quality of the first serial peripheral interface bus SPI0.

[0078] Optionally, the absolute value of the length difference between any two of the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, and the first chip select signal line cs1 can be 0.1 mil, 0.2 mil, 0.3 mil, 0.4 mil, 0.5 mil, 0.6 mil, 0.7 mil, 0.8 mil, 0.9 mil, 1.0 mil, 1.1 mil, 1.2 mil, 1.3 mil, 1.4 mil, 1.5 mil, 1.6 mil, 1.7 mil, 1.8 mil, 1.9 mil, 2.0 mil, 2.1 mil, 2.2 mil, 2.3 mil, 2.4 mil, 2.5 mil, 2.6 mil, 2.7 mil, 2.8 mil, 2.9 mil, 3.0 mil, 3. 1 mil, 3.2 mil, 3.3 mil, 3.4 mil, 3.5 mil, 3.6 mil, 3.7 mil, 3.8 mil, 3.9 mil, 4.0 mil, 4.1 mil, 4.2 mil, 4.3 mil, 4.4 mil, 4.5 mil, 4.6 mil, 4.7 mil, 4.8 mil, 4.9 mil, 5.0 mil, 5.1 mil, 5 0.2 mil, 5.3 mil, 5.4 mil, 5.5 mil, 5.6 mil, 5.7 mil, 5.8 mil, 5.9 mil, 6.0 mil, 6.1 mil, 6.2 mil, 6.3 mil, 6.4 mil, 6.5 mil, 6.6 mil, 6.7 mil, 6.8 mil, 6.9 mil, 7.0 mil, 7.1 mil, 7.2 mil 7.3 mil, 7.4 mil, 7.5 mil, 7.6 mil, 7.7 mil, 7.8 mil, 7.9 mil, 8.0 mil, 8.1 mil, 8.2 mil, 8.3 mil, 8.4 mil, 8.5 mil, 8.6 mil, 8.7 mil, 8.8 mil, 8.9 mil, 9.0 mil, 9.1 mil, 9.2 mil, 9.3 mil 9.4 mil, 9.5 mil, 9.6 mil, 9.7 mil, 9.8 mil, 9.9 mil, 10.0 mil, 10.1 mil, 10.2 mil, 10.3 mil, 10.4 mil, 10.5 mil, 10.6 mil, 10.7 mil, 10.8 mil, 10.9 mil, 11.0 mil, 11.1 mil, 11.2 mil Mills, 11.3 Mills, 11.4 Mills, 11.5 Mills, 11.6 Mills, 11.7 Mills, 11.8 Mills, 11.9 Mills, 12.0 Mills, 12.1 Mills, 12.2 Mills, 12.3 Mills, 12.4 Mills, 12.5 Mills, 12.6 Mills, 12.7 Mills, 12.8 Mills, 12.9 Mills, 13. 0 mils, 13.1 mils, 13.2 mils, 13.3 mils, 13.4 mils, 13.5 mils, 13.6 mils, 13.7 mils, 13.8 mils, 13.9 mils, 14.0 mils, 14.1 mils, 14.2 mils, 14.3 mils, 14.4 mils, 14.5 mils, 14.6 mils, 14.7 mils, 14.8 mil, 14.9 mil, 15.0 mil, 15.1 mil, 15.2 mil, 15.3 mil, 15.4 mil, 15.5 mil, 15.6 mil, 15.7 mil, 15.8 mil, 15.9 mil, 16.0 mil, 16.1 mil, 16.2 mil, 16.3 mil, 16.4 mil, 16.5 mil, 16.6 mil, 16.7 mil, 16.8 mil, 16.9 mil, 17.0 mil, 17.1 mil, 17.2 mil, 17.3 mil, 17.4 mil, A value from 17.5 mil, 17.6 mil, 17.7 mil, 17.8 mil, 17.9 mil, 18.0 mil, 18.1 mil, 18.2 mil, 18.3 mil, 18.4 mil, 18.5 mil, 18.6 mil, 18.7 mil, 18.8 mil, 18.9 mil, 19.0 mil, 19.1 mil, 19.2 mil, 19.3 mil, 19.4 mil, 19.5 mil, 19.6 mil, 19.7 mil, 19.8 mil, 19.9 mil, to 20 mil.

[0079] Optionally, the multiple first sub-lines 15 may further include a first write-protect input signal line wp1 and a first state-hold input signal line hold1. The first write-protect input signal line wp1 is electrically connected to the timing controller 20 and the first memory 31. The first state-hold input signal line hold1 is electrically connected to the timing controller 20 and the first memory 31.

[0080] In this embodiment, the first write-protect signal line is used to prevent unintended write operations to the first memory 31 connected to the first write-protect signal line. The first state hold input signal line hold1 is used to pause or maintain the operation of the first memory 31 so that the timing controller 20 can handle other tasks. For example, when the signal output by the first state hold input signal line hold1 is either a logic low level or a logic high level, the first memory 31 will pause its operation and maintain its current state. When the signal output by the first state hold input signal line hold1 is either a logic low level or a logic high level, read and write operations of the first memory 31 can continue.

[0081] In this application, the first serial peripheral interface bus SPI0 may include only four first sub-lines 15, which are respectively the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, and the first chip select signal line CS1. The first serial peripheral interface bus SPI0 may also include only six first sub-lines 15, which are respectively the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, the first chip select signal line CS1, the first write-protect input signal line wp1, and the first state maintenance input signal line hold1.

[0082] Optionally, the absolute value of the length difference between any two of the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, the first chip select signal line cs1, the first write protect input signal line wp1, and the first state hold input signal line hold1 is less than 10 mils.

[0083] In this embodiment, in order to further improve the signal quality of the first serial peripheral interface bus SPI0, by controlling the absolute value of the length difference between any two of the first data input signal line i1, the first data output signal line o1, the first clock signal line ck1, the first chip select signal line cs1, the first write protect input signal line wp1, and the first state hold input signal line hold1 to a range of less than 10 mils, the delay of multiple first sub-lines 15 can be further controlled, making the transmission speed of multiple first sub-lines 15 tend to be the same, thereby further improving the signal quality of the first serial peripheral interface bus SPI0.

[0084] Optionally, the absolute value of the length difference between any two of the following signals can be 0.1 mil, 0.2 mil, 0.3 mil, 0.4 mil, 0.5 mil, 0.6 mil, 0.7 mil, 0.8 mil, 0.9 mil, 1.0 mil, 1.1 mil, 1.2 mil, or 1.3 mil. 1.4 mil, 1.5 mil, 1.6 mil, 1.7 mil, 1.8 mil, 1.9 mil, 2.0 mil, 2.1 mil, 2.2 mil, 2.3 mil, 2.4 mil, 2.5 mil, 2.6 mil, 2.7 mil, 2.8 mil, 2.9 mil, 3.0 mil, 3.1 mil, 3.2 mil, 3.3 mil, 3.4 mil, 3.5 mil, 3.6 mil, 3.7 mil, 3.8 mil, 3.9 mil, 4.0 mil, 4.1 mil, 4.2 mil, 4. 3 mil, 4.4 mil, 4.5 mil, 4.6 mil, 4.7 mil, 4.8 mil, 4.9 mil, 5.0 mil, 5.1 mil, 5.2 mil, 5.3 mil, 5.4 mil, 5.5 mil, 5.6 mil, 5.7 mil, 5.8 mil, 5.9 mil, 6.0 mil, 6.1 mil, 6.2 mil, 6.3 mil, 6.4 mil, 6.5 mil, 6.6 mil, 6.7 mil, 6.8 mil, 6.9 mil, 7.0 mil, 7.1 mil, 7.2 mil The value is one of the following: 7.3 mil, 7.4 mil, 7.5 mil, 7.6 mil, 7.7 mil, 7.8 mil, 7.9 mil, 8.0 mil, 8.1 mil, 8.2 mil, 8.3 mil, 8.4 mil, 8.5 mil, 8.6 mil, 8.7 mil, 8.8 mil, 8.9 mil, 9.0 mil, 9.1 mil, 9.2 mil, 9.3 mil, 9.4 mil, 9.5 mil, 9.6 mil, 9.7 mil, 9.8 mil, 9.9 mil, or 10.0 mil.

[0085] Optionally, the absolute value of the length difference between the first data input signal line i1 and the first clock signal line ck1 is less than 10 mils. The absolute value of the length difference between the first data output signal line o1 and the first clock signal line ck1 is less than 10 mils. The absolute value of the length difference between the first chip select signal line CS1 and the first clock signal line ck1 is less than 10 mils. The absolute value of the length difference between the first write-protect input signal line wp1 and the first clock signal line ck1 is less than 10 mils. The absolute value of the length difference between the first state hold input signal line hold1 and the first clock signal line ck1 is less than 10 mils.

[0086] In this embodiment, taking the first clock signal line ck1 as the target line, the remaining first sub-lines 15 are made to be of equal length relative to the first clock signal line ck1. This can further control the delay of multiple first sub-lines 15, making the transmission speed of multiple first sub-lines 15 tend to be the same, thereby further improving the signal quality of the first serial peripheral interface bus SPI0.

[0087] Optional, please refer to Figure 3 The circuit board 10 includes a first region A1. The first region A1 includes a proximal region A2 and a distal region A3 located on at least one side of the proximal region A2. The timing controller 20 and the first memory 31 are located in the proximal region A2. A plurality of first sub-lines 15 are spaced apart in the first region A1. At least one first sub-line 15 is located in the proximal region A2, and at least one first sub-line 15 is located in the distal region A3. The first sub-line 15 located in the proximal region A2 includes a plurality of first bends W.

[0088] In a plan view of the circuit board assembly 100, the pattern of the first bend W is one of an arc-shaped structure, a zigzag structure, or a square structure.

[0089] In this embodiment, the shortest distance between the two endpoints of the first sub-line 15 located in the near-end region A2 is less than the shortest distance between the two endpoints of the first sub-line 15 located in the far-end region A3. If the first trace is set along the shortest distance between the two endpoints of the first sub-line 15 in the near-end region A2, the difference between the length of the first sub-line 15 in the near-end region A2 and the length of the first sub-line 15 in the far-end region A3 will be greater than 10 mils, which will not meet the signal quality requirements. To achieve equal length processing for different first sub-lines 15, this application provides a first bend W in the first sub-line 15 of the near-end region A2, causing a portion of the first sub-line 15 in the near-end region A2 to form a serpentine trace, thereby increasing the total length of the first sub-line 15 in the near-end region A2. This makes the difference between the length of the first sub-line 15 in the near-end region A2 and the length of the first sub-line 15 in the far-end region A3 less than or equal to 10 mils. This further controls the delay of multiple first sub-lines 15, making the transmission speed of multiple first sub-lines 15 tend to be the same, thereby further improving the signal quality of the first serial peripheral interface bus SPI0.

[0090] Optional, please refer to Figure 2 The circuit board assembly 100 also includes a programming interface 60. The programming interface 60 is located on the circuit board 10. The programming interface 60 is electrically connected to the first memory 31. The circuit board 10 includes a third serial peripheral interface bus SPI2. The third serial peripheral interface bus SPI2 includes multiple fourth sub-lines. The fourth sub-lines are electrically connected to the programming interface 60 and the timing controller 20. The length of the fourth sub-lines is less than 9000 mils.

[0091] Optionally, the timing controller 20 is located between the programming interface 60 and the programmable gate array chip 40. In a plan view of the circuit board assembly 100, the programming interface 60 is located on the side of the first memory 31 in the short side direction Y of the circuit board 10.

[0092] In this embodiment, by placing the timing controller 20 between the programming interface 60 and the programmable gate array chip 40, the layout of the circuit board assembly 100 of this application is adjusted compared to the layout of the related circuit board assembly 100a, thereby reducing the length of the third sub-line 17 of the third serial peripheral interface bus SPI2.

[0093] Preferably, the length of the third sub-line 17 is less than or equal to 3000 mils.

[0094] Optionally, the length of the third sub-line 17 can be one of the following values: 100 mil, 200 mil, 300 mil, 400 mil, 500 mil, 600 mil, 700 mil, 800 mil, 900 mil, 1000 mil, 1100 mil, 1200 mil, 1300 mil, 1400 mil, 1500 mil, 1600 mil, 1700 mil, 1800 mil, 1900 mil, 2000 mil, 2100 mil, 2200 mil, 2300 mil, 2400 mil, 2500 mil, 2600 mil, 2700 mil, 2800 mil, 2900 mil, or 3000 mil.

[0095] Optionally, the circuit board assembly 100 also includes a level shifter 50 (Level Shift IC). The level shifter 50 is disposed on the circuit board 10 and electrically connected to the timing controller 20.

[0096] In a plan view of the circuit board assembly 100, the first memory 31 is located between the level shifter 50 and the timing controller 20.

[0097] In this embodiment, the level converter 50 is used to output a gate driver on array (GOA) signal to the display panel.

[0098] Optional, please refer to Figure 4 The circuit board 10 includes a first trace layer 11, a reference ground layer 12, and a second trace layer 13 stacked along the thickness direction of the circuit board 10.

[0099] The first routing layer 11 includes a first serial peripheral interface bus (SPI0). A reference ground layer 12 is insulated from both the first routing layer 11 and the second routing layer 13. The reference ground layer 12 is connected to a reference ground potential. The second routing layer 13 includes a horizontal drive signal bus 14. The horizontal drive signal bus 14 is electrically connected to a level shifter 50. The horizontal drive signal bus 14 is configured to output horizontal drive signals to the display panel.

[0100] In this embodiment, when the level converter 50 outputs a horizontal drive signal to the display panel via the horizontal drive signal bus 14, it interferes with the signal transmitted within the first serial peripheral interface bus SPI0. Therefore, this embodiment layers the first serial peripheral interface bus SPI0 and the horizontal drive signal bus 14, and sets a reference ground layer 12 between the two layers. The reference ground layer 12 includes a prepreg. As a dielectric material, the prepreg serves to fill and bond, ensuring electrical isolation and mechanical stability between the layers, and providing return paths and potential reference points for signals and power. By setting the reference ground layer 12 between the first trace layer 11 and the second trace layer 13, electrical isolation between the first trace layer 11 and the second trace layer 13 can be achieved, reducing signal interference between the first serial peripheral interface bus SPI0 and the horizontal drive signal bus 14, and improving the signal quality of the first serial peripheral interface bus SPI0 and the horizontal drive signal bus 14.

[0101] Optionally, the horizontal drive signal bus 14 includes multiple second sub-lines 16. The second sub-lines 16 are configured to output horizontal drive signals to the display panel.

[0102] In this embodiment, the multiple second sub-lines 16 include at least one row drive clock signal line, at least one pull-down signal line, and at least one scan start signal line.

[0103] Optional, please refer to Figure 5 Multiple second sub-lines 16 are spaced apart on the reference stratum 12 by orthogonal projections. A gap K is formed between the orthogonal projections of two adjacent second sub-lines 16 on the reference stratum 12. At least one gap K does not completely overlap with the orthogonal projection of the first sub-line 15 on the reference stratum 12.

[0104] In this embodiment, by setting the orthographic projection of the first sub-line 15 on the reference ground layer 12 and the orthographic projection of the second sub-line 16 on the reference ground layer 12 as non-intersecting traces, the signal interference between the first serial peripheral interface bus SPI0 and the row drive signal bus 14 is reduced, thereby improving the signal quality of the first serial peripheral interface bus SPI0 and the row drive signal bus 14.

[0105] It is important to understand that "non-interlaced routing" means that the orthographic projection of the first sub-line 15 on the reference stratum 12 and the orthographic projection of the second sub-line 16 on the reference stratum 12 are not alternately arranged, but rather that the gap K between them does not overlap with the orthographic projection of the first sub-line 15 on the reference stratum 12.

[0106] Optional, please refer to Figure 6 At least one first sub-line 15 is projected onto the reference stratum 12 and intersects with at least one second sub-line 16.

[0107] In this embodiment, by interleaving the orthographic projection of the first sub-line 15 on the reference ground layer 12 with the orthographic projection of the second sub-line 16 on the reference ground layer 12, signal interference between the first serial peripheral interface bus SPI0 and the row drive signal bus 14 is reduced, thereby improving the signal quality of the first serial peripheral interface bus SPI0 and the row drive signal bus 14.

[0108] Optionally, the circuit board assembly 100 may also include a second memory 32. The second memory 32 is disposed on the circuit board 10.

[0109] In a plan view of the circuit board assembly 100, the second memory 32 is located between the level shifter 50 and the timing controller 20. The second memory 32 and the first memory 31 are spaced apart along the short side Y direction of the circuit board 10.

[0110] The first routing layer 11 also includes a second serial peripheral interface bus SPI1. The second serial peripheral interface bus SPI1 is electrically connected to the timing controller 20 and the second memory 32. The second serial peripheral interface bus SPI1 and the first serial peripheral interface bus SPI0 are spaced apart on the side of the reference ground layer 12 away from the second routing layer 13.

[0111] The second serial peripheral interface bus SPI1 includes multiple third sub-lines 17, which are electrically connected to the timing controller 20 and the second memory 32.

[0112] In this embodiment, the circuit board assembly 100 includes a first memory 31 and a second memory 32. The timing controller 20 is electrically connected to the second memory 32 and the timing controller 20 through a second serial peripheral interface bus SPI1.

[0113] When the second serial peripheral interface bus SPI1 transmits data, it will also be subject to interference from other signals. Therefore, the second serial peripheral interface bus SPI1 can apply the corresponding improvements of the first serial peripheral interface bus SPI0 in this application to improve the signal quality of the second serial peripheral interface bus SPI1. To avoid redundancy, this will not be elaborated here.

[0114] Optional, please refer to Figure 7Multiple second sub-lines 16 are spaced apart by their orthogonal projections on the reference stratum 12, and a gap K is formed between the orthogonal projections of two adjacent second sub-lines 16 on the reference stratum 12. At least one of the gaps K does not completely overlap with the orthogonal projection of the third sub-line 17 on the reference stratum 12.

[0115] In this embodiment, by setting the orthographic projection of the third sub-line 17 on the reference ground layer 12 and the orthographic projection of the second sub-line 16 on the reference ground layer 12 as non-intersecting traces, the signal interference between the second serial peripheral interface bus SPI1 and the row drive signal bus 14 is reduced, thereby improving the signal quality of the second serial peripheral interface bus SPI1 and the row drive signal bus 14.

[0116] Optionally, the orthographic projection of at least one third sub-line 17 onto the reference stratum 12 intersects the orthographic projection of at least one second sub-line 16 onto the reference stratum 12.

[0117] In this embodiment, by intersecting the orthographic projection of the third sub-line 17 on the reference ground layer 12 with the orthographic projection of the second sub-line 16 on the reference ground layer 12, signal interference between the second serial peripheral interface bus SPI1 and the row drive signal bus 14 is reduced, thereby improving the signal quality of the second serial peripheral interface bus SPI1 and the row drive signal bus 14.

[0118] The specific embodiments of this application have been described in detail above. The embodiments disclosed above are merely preferred embodiments of this application. Those skilled in the art can make many modifications and improvements without departing from the concept of this application. All such modifications and improvements fall within the scope of protection defined by the claims of this application.

Claims

1. A circuit board assembly, characterized in that, include: The circuit board includes a first trace layer, a reference ground layer, and a second trace layer stacked along the thickness direction of the circuit board. The first trace layer includes a first serial peripheral interface bus, which includes multiple first sub-lines. The reference ground layer is insulated from the first trace layer and the second trace layer, respectively, and is connected to a reference ground potential. The second trace layer includes a horizontal drive signal bus, which is configured to output a horizontal drive signal to a display panel. A timing controller is mounted on the circuit board; as well as A first memory is disposed on the circuit board; A level converter is mounted on the circuit board and electrically connected to the timing controller; the row drive signal bus is electrically connected to the level converter. Among them, multiple first sub-lines are electrically connected to the timing controller and the first memory, and the length of the first sub-lines is less than or equal to 9000 mils; In a plan view of the circuit board assembly, the first memory is located between the level shifter and the timing controller.

2. The circuit board assembly as claimed in claim 1, characterized in that, The circuit board assembly also includes a programmable gate array (PGA) chip, which is disposed on the circuit board; In a plan view of the circuit board assembly, the timing controller is located between the first memory and the programmable gate array chip, and the distance between the timing controller and the first memory is less than the distance between the timing controller and the programmable gate array chip.

3. The circuit board assembly as described in claim 2, characterized in that, In a plan view of the circuit board assembly, the first memory and the programmable gate array chip are respectively located on both sides of the timing controller along the long side of the circuit board; The length of the first sub-line is less than or equal to 3000 mils.

4. The circuit board assembly as claimed in claim 1, characterized in that, Multiple first sub-lines include: The first data input signal line is electrically connected to the timing controller and the first memory; The first data output signal line is electrically connected to the timing controller and the first memory; A first clock signal line is electrically connected to the timing controller and the first memory; and The first select signal line is electrically connected to the timing controller and the first memory; Wherein, the absolute value of the length difference between any two of the first data input signal line, the first data output signal line, the first clock signal line, and the first chip select signal line is less than 20 mils.

5. The circuit board assembly as claimed in claim 4, characterized in that, The multiple first sub-lines also include: The first write-protect input signal line is electrically connected to the timing controller and the first memory; The first state maintains the input signal line, which is electrically connected to the timing controller and the first memory; Wherein, the absolute value of the length difference between any two of the first data input signal line, the first data output signal line, the first clock signal line, the first chip select signal line, the first write protect input signal line, and the first state maintenance input signal line is less than 10 mils.

6. The circuit board assembly as claimed in claim 1, characterized in that, The row drive signal bus includes multiple second sub-lines, which are configured to output row drive signals to the display panel. At least one of the first sub-lines' orthogonal projections onto the reference stratum intersects with at least one of the second sub-lines' orthogonal projections onto the reference stratum; And / or, Multiple second sub-lines are spaced apart by their orthogonal projections onto the reference stratum, and gaps are formed between the orthogonal projections of two adjacent second sub-lines onto the reference stratum. At least one of the gaps does not completely overlap with the orthogonal projection of the first sub-line onto the reference stratum.

7. The circuit board assembly as claimed in claim 1, characterized in that, The circuit board assembly further includes a second memory, which is disposed on the circuit board; In a plan view of the circuit board assembly, the second memory is located between the level shifter and the timing controller, and the second memory and the first memory are spaced apart along the short side of the circuit board. The first routing layer also includes a second serial peripheral interface bus, which is electrically connected to the timing controller and the second memory. The second serial peripheral interface bus is disposed on the side of the reference ground layer away from the second routing layer, spaced apart from the first serial peripheral interface bus. The second serial peripheral interface bus includes multiple third sub-lines, which are electrically connected to the timing controller and the second memory. The row drive signal bus includes multiple second sub-lines, which are configured to output row drive signals to the display panel. At least one of the third sub-lines, when projected onto the reference stratum, intersects with at least one of the second sub-lines, when projected onto the reference stratum. And / or, Multiple second sub-lines are spaced apart by their orthogonal projections onto the reference stratum, and gaps are formed between the orthogonal projections of two adjacent second sub-lines onto the reference stratum. At least one of the gaps does not completely overlap with the orthogonal projection of the third sub-line onto the reference stratum.

8. The circuit board assembly as described in any one of claims 1-7, characterized in that, The circuit board includes a first region, the first region including a proximal region and a distal region located on at least one side of the proximal region, the timing controller and the first memory being located in the proximal region; Multiple first sub-lines are spaced apart in the first region, with at least one first sub-line located in the proximal region and at least one first sub-line located in the distal region. The first sub-line located in the proximal region includes a plurality of first bends; In a plan view of the circuit board assembly, the pattern of the first bend is one of an arc-shaped structure, a zigzag structure, or a square structure.

9. The circuit board assembly as described in any one of claims 1-7, characterized in that, The circuit board assembly further includes a programming interface, which is disposed on the circuit board and electrically connected to the first memory. The circuit board includes a third serial peripheral interface bus, which includes multiple fourth sub-lines. The fourth sub-lines are electrically connected to the programming interface and the timing controller. The length of the fourth sub-lines is less than 9000 mils.

10. A display device, characterized in that, Includes the circuit board assembly as described in any one of claims 1-9.

Images