Three-dimensional memory, preparation method thereof, memory system and electronic equipment

Abstract

The embodiment of the invention provides a three-dimensional memory, a preparation method thereof, a memory system and electronic equipment, relates to the technical field of semiconductor chips, and aims to increase the capacity of the three-dimensional memory. According to the three-dimensional memory provided by the embodiment of the invention, the middle layer is provided with the first side and the second side in the thickness direction, the first device layer is located on the first side of the middle layer, the first memory array layer is located on the side, away from the middle layer, of the first device layer, and the second device layer is located on the second side of the middle layer. The second storage array layer is located on the side, away from the middle layer, of the second device layer, so that a five-layer structure of the first storage array layer, the first device layer, the middle layer, the second device layer and the second storage array layer which are stacked is formed in the thickness direction of the middle layer; the three-dimensional memory is provided with the first memory array layer and the second memory array layer which are used for storage in unit area, so that the capacity of the three-dimensional memory is increased.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor chip technology, and in particular to a three-dimensional memory and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] There are multiple chips packaged inside the memory, each chip is used to store data. The total amount of data that all chips can store is the maximum capacity of the memory. During use, the memory is affected by its size, and the maximum number of chips that can be packaged in its packaging area is limited, which in turn limits the maximum capacity of the memory. Summary of the invention

[0003] Embodiments of the present invention provide a three-dimensional memory and a preparation method thereof, a storage system, and an electronic device, aiming to increase the capacity of the three-dimensional memory.

[0004] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0005] On the one hand, an embodiment of the present invention provides a three-dimensional memory, including an intermediate layer, a first device layer, a second device layer, a first storage array layer, and a second storage array layer, having a first side and a second side opposite to each other in the thickness direction of the intermediate layer, the first device layer including a plurality of first transistors, the first device layer being located on the first side of the intermediate layer, the second device layer including a plurality of second transistors, the second device layer being located on the second side of the intermediate layer, the first storage array layer being located on a side of the first device layer facing away from the intermediate layer, and the second storage array layer being located on a side of the second device layer facing away from the intermediate layer.

[0006] In the three-dimensional memory provided by the embodiment of the present invention, the middle layer has a first side and a second side in the thickness direction, the first device layer is located on the first side of the middle layer, the first storage array layer is located on the side of the first device layer away from the middle layer, the second device layer is located on the second side of the middle layer, and the second storage array layer is located on the side of the second device layer away from the middle layer, thereby forming a five-layer structure of the first storage array layer, the first device layer, the middle layer, the second device layer, and the second storage array layer stacked in the thickness direction of the middle layer, with the first storage array layer and the second storage array layer for storage per unit area, thereby increasing the capacity of the three-dimensional memory.

[0007] In some embodiments, the first memory array layer is connected to at least one of the plurality of first transistors, and the second memory array layer is connected to at least one of the plurality of second transistors.

[0008] Through the above-mentioned setting, after the first transistor is connected to the first storage array layer, multiple first storage structures in the first storage array layer can be logically controlled so that the first storage array layer can realize the storage or reading function. Similarly, after the second transistor is connected to the second storage array layer, multiple second storage structures in the second storage array layer can be logically controlled so that the second storage array layer can realize the storage or reading function.

[0009] In some embodiments, the three-dimensional memory also includes a packaging substrate, on which a connecting circuit is provided. The packaging substrate is located on the side of the first storage array layer away from the middle layer, and at least one first transistor, the first storage array layer, at least one second transistor, and the second storage array layer are all connected to the connecting circuit.

[0010] Through the above arrangement, at least one first transistor is connected to the connecting circuit, realizing the connection between the first device layer and the connecting circuit, and at least one second transistor is connected to the connecting circuit, realizing the connection between the second device layer and the connecting circuit. The first storage array layer and the second storage array layer are both connected to the connecting circuit, and the connecting circuit realizes the connection between the first device layer, the second device layer, the first storage array layer and the second storage array layer stacked along the thickness direction of the intermediate layer, thereby increasing the capacity of the three-dimensional memory.

[0011] In some embodiments, the first storage array layer includes a first pad and a second pad that are spaced apart, and both the first pad and the second pad are located on a side of the first storage array layer away from the middle layer, the first pad connects at least one first transistor and a connecting circuit, and the second pad connects the first storage array layer and the connecting circuit.

[0012] Through the above arrangement, the first pad and the second pad are both connected to the connection circuit, the first pad is connected to at least one first transistor, and the second pad is connected to the first storage array layer, so that the first device layer and the first storage array layer are both connected to the connection circuit.

[0013] In some embodiments, the first memory array layer includes a first conductive pillar, one end of the first conductive pillar is connected to the first pad, and the other end of the first conductive pillar is connected to the first transistor.

[0014] Through the above arrangement, the first conductive column leads the at least one first transistor to the first pad, so that the at least one first transistor can be connected to the connection circuit of the package substrate through the first pad.

[0015] In some embodiments, a first contact and a second contact are disposed on a surface of the packaging substrate close to the middle layer, both of which are connected to the connection circuit, the first contact is connected to the first pad, and the second contact is connected to the second pad.

[0016] Through the above arrangement, the connection circuit of the packaging substrate is connected to the first pad through the first contact and to the second pad through the second contact, which can not only realize the connection between the packaging substrate and the first storage array layer and the first device layer, but also make the connection circuit located inside the packaging substrate to avoid leakage of the connection circuit, thereby affecting the storage efficiency of the three-dimensional memory.

[0017] In some embodiments, the first contact is welded to the first pad, and the second contact is welded to the second pad.

[0018] Through the above-mentioned setting, welding between the first contact and the first pad can realize electrical interconnection between the first contact and the first pad, and welding between the second contact and the second pad can realize electrical interconnection between the second contact and the second pad. At the same time, the solder formed by welding can also play a stress buffering role between the first storage array layer and the packaging substrate.

[0019] In some embodiments, the second storage array layer includes a third pad and a fourth pad that are spaced apart, and the third pad and the fourth pad are both located on a side of the second storage array layer away from the middle layer, the third pad connects at least one second transistor and a connecting circuit, and the fourth pad connects the second storage array layer and the connecting circuit.

[0020] Through the above arrangement, the third pad and the fourth pad are both connected to the connecting circuit, the third pad is connected to at least one second transistor, and the fourth pad is connected to the second storage array layer, so that the second device layer and the second storage array layer are both connected to the connecting circuit.

[0021] In some embodiments, the second memory array layer includes a second conductive pillar, one end of the second conductive pillar is connected to the third pad, and the other end of the second conductive pillar is connected to the second transistor.

[0022] Through the above arrangement, the second conductive column leads the at least one second transistor to the third pad, so that the at least one second transistor can be connected to the connection circuit of the packaging substrate through the third pad.

[0023] In some embodiments, a third contact and a fourth contact are provided on the surface of the packaging substrate close to the middle layer, and the third contact and the fourth contact are both connected to the connection circuit; the three-dimensional memory also includes a first wire and a second wire, one end of the first wire is connected to the third pad, the other end of the first wire is connected to the third contact, one end of the second wire is connected to the fourth pad, and the other end of the second wire is connected to the fourth contact.

[0024] Through the above arrangement, electrical interconnection between the third pad and the third contact can be achieved through the first wire, and electrical interconnection between the fourth pad and the fourth contact can be achieved through the second wire.

[0025] On the other hand, an embodiment of the present invention further provides a method for preparing a three-dimensional memory, comprising:

[0026] A first device layer and a second device layer are formed on the first initial intermediate layer to obtain an intermediate layer; the first device layer includes a plurality of first transistors, the first device layer is located on a first side of the intermediate layer, the second device layer includes a plurality of second transistors, the second device layer is located on a second side of the intermediate layer, the first side and the second side are two opposite sides of the intermediate layer in a thickness direction;

[0027] A first storage array layer and a second storage array layer are formed, wherein the first storage array layer is located on a side of the first device layer away from the middle layer, and the first storage array layer is connected to at least one of the plurality of first transistors, and the second storage array layer is located on a side of the second device layer away from the middle layer, and the second storage array layer is connected to at least one of the plurality of first transistors.

[0028] A method for preparing a three-dimensional memory provided by an embodiment of the present invention forms a five-layer structure of a first storage array layer, a first device layer, an intermediate layer, a second device layer, and a first storage array layer stacked in the thickness direction of the intermediate layer. The first storage array layer and the second storage array layer for storage are provided per unit area, thereby increasing the capacity of the three-dimensional memory.

[0029] In some embodiments, forming a first device layer and a second device layer on a first initial intermediate layer, and obtaining an intermediate layer comprises:

[0030] forming a second device layer on one side of the first initial intermediate layer to obtain a second initial intermediate layer;

[0031] forming a first protective layer on the second device layer;

[0032] The second initial intermediate layer is turned over, and a first device layer is formed on a side of the second initial intermediate layer facing away from the second device layer, thereby obtaining an intermediate layer.

[0033] Through the above arrangement, a four-layer structure of a first device layer, an intermediate layer, a second device layer, and a first protective layer is formed in a stacked arrangement in the thickness direction of the intermediate layer, a first device layer and a second device layer are formed on both sides in the thickness direction of the intermediate layer, and a first device layer and a second device layer that can be connected to a memory cell string are provided per unit area, the number of transistors used to be connected to a memory cell string is increased, that is, the total number of first transistors and second transistors, the number of memory cell strings that can be connected to the three-dimensional memory is increased, and thus the capacity of the three-dimensional memory is increased. In addition, the first protective layer is located on the side of the second device layer away from the second initial intermediate layer to avoid the second device layer from being worn during the process of forming the first device layer on the second initial intermediate layer.

[0034] In some embodiments, forming a first memory array layer and a second memory array layer includes:

[0035] attaching the first storage array layer to the first device layer;

[0036] forming a second protective layer on the first storage array layer;

[0037] Turn over the middle layer and remove the first protective layer;

[0038] attaching the second storage array layer to the second device layer;

[0039] Remove the second protective layer.

[0040] Through the above arrangement, the second protection layer is located on the side of the first memory array layer away from the first device layer, so as to avoid the first memory array layer being worn during the process of forming the second memory array layer on the second device layer.

[0041] In some embodiments, the preparation method further comprises:

[0042] Forming a packaging substrate, wherein a connection circuit is provided on the packaging substrate, and a first contact and a second contact are provided on a surface of the packaging substrate close to the middle layer, and both the first contact and the second contact are connected to the connection circuit;

[0043] After the first memory array layer is formed, the first memory array layer further comprises a first pad and a second pad which are spaced apart from each other, the first pad and the second pad are both located on a side of the first memory array layer away from the middle layer, and the first pad is connected to at least one first transistor;

[0044] After the first storage array layer is attached to the first device layer, the method further includes: connecting the first contact and the first pad by welding; and connecting the second contact and the second pad by welding.

[0045] Through the above-mentioned setting, welding between the first contact and the first pad can realize electrical interconnection between the first contact and the first pad, and welding between the second contact and the second pad can realize electrical interconnection between the second contact and the second pad. At the same time, the solder formed by welding can also play a stress buffering role between the first storage array layer and the packaging substrate.

[0046] In some embodiments, the preparation method further comprises:

[0047] After the packaging substrate is formed, a third contact and a fourth contact are arranged on the surface of the packaging substrate close to the middle layer, and the third contact and the fourth contact are both connected to the connection circuit;

[0048] After the second memory array layer is formed, the second memory array layer further includes a third pad and a fourth pad which are spaced apart from each other, the third pad and the fourth pad are both located on a side of the second memory array layer away from the middle layer, and the third pad is connected to at least one second transistor;

[0049] After attaching the second storage array layer to the second device layer, the method further includes: forming a first wire and a second wire, connecting the third contact and the third pad through the first wire, and connecting the fourth contact and the fourth pad through the second wire.

[0050] Through the above arrangement, electrical interconnection between the third pad and the third contact can be achieved through the first wire, and electrical interconnection between the fourth pad and the fourth contact can be achieved through the second wire.

[0051] On the other hand, an embodiment of the present invention further provides a storage system, including a three-dimensional memory and a controller, wherein the three-dimensional memory is the three-dimensional memory as described above; the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0052] On the other hand, an embodiment of the present invention further provides an electronic device, including a host and the above storage system, wherein the host and the storage system are coupled.

[0053] It can be understood that the beneficial effects achieved by the method for preparing the three-dimensional memory, the storage system and the electronic device provided by the above embodiments of the present invention can refer to the beneficial effects of the three-dimensional memory described above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the present invention, the following briefly introduces the drawings required to be used in some embodiments of the present invention. Obviously, the drawings described below are only drawings of some embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present invention, the actual process of the method, the actual timing of the signal, etc.

[0055] Figure 1 A schematic diagram of a three-dimensional structure of a three-dimensional memory in some embodiments of the present invention;

[0056] Figure 2 A cross-sectional view of a three-dimensional memory in some embodiments of the present invention;

[0057] Figure 3 for Figure 1 A cross-sectional view of a memory cell string in the three-dimensional memory along the section line AA' shown;

[0058] Figure 4is an equivalent circuit diagram of a memory cell string in some embodiments of the present invention;

[0059] Figure 5 A schematic diagram of the structure of a three-dimensional memory in some embodiments of the present invention;

[0060] Figure 6 is a flow chart of a method for preparing a three-dimensional memory in some embodiments of the present invention;

[0061] Figure 7 Schematic diagram of the structure of the first initial intermediate layer in some embodiments of the present invention;

[0062] Figure 8 It is a schematic diagram of the structure after the second device layer is formed in some embodiments of the present invention;

[0063] Fig. 9 It is a schematic diagram of the structure after the first protective layer is formed in some embodiments of the present invention;

[0064] Fig.10 It is a schematic diagram of the structure after the first device layer is formed in some embodiments of the present invention;

[0065] Fig.11 A schematic diagram of a structure after a first storage array layer is formed in some embodiments of the present invention;

[0066] Fig.12 It is a schematic diagram of the structure after removing the first protective layer in some embodiments of the present invention;

[0067] Fig.13 It is a schematic diagram of the structure after removing the second protective layer in some embodiments of the present invention;

[0068] Fig.14 It is a schematic diagram of the structure after the packaging substrate and the first storage array layer are connected in some embodiments of the present invention;

[0069] Fig.15 A schematic diagram of the structure after the packaging substrate and the second storage array layer are connected in some embodiments of the present invention;

[0070] Fig.16 is a block diagram of a storage system according to some embodiments;

[0071] Fig.17 is a block diagram of a storage system according to some other embodiments.

[0072] Description of the drawings: 301, three-dimensional memory; 302, intermediate layer; 303, first device layer; 304, second device layer; 305, first transistor; 306, second transistor; 307, first storage array layer; 308, first connection part; 309, second connection part; 310, second storage array layer; 311, third connection part; 312, fourth connection part; 313, packaging substrate; 314, connecting circuit; 315, first pad; 316, first conductive column; 317, second pad; 318, first contact; 319, second contact; 320, third pad; 321, second conductive column; 322, fourth pad; 323, third contact; 324, fourth contact; 325, first wire; 326, second wire; 327, first initial intermediate layer; 328, second initial intermediate layer; 329, first protective layer; 330, second protective layer. DETAILED DESCRIPTION

[0073] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments provided by the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0074] In the description of the present invention, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0075] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present invention. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0076] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, unless otherwise specified, "plurality" means two or more.

[0077] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments invented here are not necessarily limited to the contents of this document.

[0078] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0079] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0080] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0081] In the context of the present invention, the meaning of "on", "above", and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" not only means "above" or "over" something, but also includes the meaning of "above" or "over" something without intervening features or layers in between (i.e., directly on something).

[0082] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0083] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0084] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0085] Please refer to Figure 1 and Figure 2 , the three-dimensional memory 10 extends in the XY plane, the first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (for example, the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The third direction Z is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the XY plane.

[0086] As used in the present invention, whether a component (e.g., layer, structure, or device) is "on," "over," or "under" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a substrate or source layer of the semiconductor device in a third direction Z when the substrate or source layer is located in the lowest plane of the semiconductor device in the third direction Z. The same concept is applied to describe spatial relationships throughout the present invention.

[0087] In order to more clearly illustrate the structure of the device, Figure 2In FIG. 1 , a view of the array area CA is shown. The view of the array area CA is based on the left coordinate system, that is, the view of the array area CA shows the cross-sectional structure along the Y direction.

[0088] Reference Figure 1 and Figure 2 Some embodiments of the present invention provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200. The three-dimensional memory 10 may also include a peripheral device 100 coupled to the semiconductor structure 200. The semiconductor structure 200 includes a source layer SL, and the peripheral device 100 may be disposed on a side of the semiconductor structure 200 away from the source layer SL.

[0089] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0090] The semiconductor structure 200 may include a memory cell transistor string (referred to herein as a “channel structure”) 40 arranged in an array. The source layer SL may be connected to the plurality of memory cell strings 40 (eg, Figure 3 The source terminal is coupled as shown).

[0091] In some embodiments, please refer to Figure 3 and Figure 4 , the memory cell string 40 may include a plurality of transistors T, a transistor T (eg Figure 4 The transistors T1 to T6 in the figure can be set as a memory cell, and these transistors T are connected together to form a memory cell string. A transistor T (for example, each transistor T) can be formed by a semiconductor channel 241 and a gate line G surrounding the semiconductor channel 241. The gate line G is configured to control the conduction state of the transistor.

[0092] Understandably, Figure 1 to Figure 4 The number of transistors is only illustrative, and the storage cell string of the three-dimensional memory provided by the embodiment of the present invention may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0093] In some embodiments, along the third direction Z, the gate line located at the bottom among the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source selection gate SGS, and the source selection gate SGS is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 40. The gate line located at the top among the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) is constructed as a drain selection gate SGD, and the drain selection gate SGD is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 40. The gate line located in the middle among the multiple gate lines G can be constructed as a plurality of word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. Data writing, reading, and erasing of corresponding memory cells (for example, transistors T) in the memory cell string 40 can be completed through the word lines WL.

[0094] Continue to refer to Figure 1 and Figure 2 In some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 40. The array interconnect layer 290 may include a drain terminal (i.e., a bit line BL) of the memory cell string 40, and the drain terminal may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 40.

[0095] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292, the contacts may include, for example, a bit line contact BL-CNT coupled to the bit line BL, and a drain select gate contact SGD-CNT coupled to the drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, for example, a bit line BL, and a word line connection line WL-CL coupled to the word line WL. The material of the first interconnect conductor layer 291 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other suitable materials.

[0096] The peripheral device 100 may include peripheral circuits. The peripheral circuits are configured to control and sense the array device. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs) or storage circuits (e.g., static random access memories (SRAMs)).

[0097] In some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuit may include the transistor 120.

[0098] The material of the substrate 110 may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0099] The peripheral interconnection layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnection layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled through contacts. The material of the second interconnect conductor layer 132 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0100] The peripheral interconnect layer 130 may be coupled to the array interconnect layer 290, so that the semiconductor structure 200 and the peripheral device 100 may be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuit in the peripheral device 100 may be coupled to the memory cell string in the semiconductor structure 200 to achieve transmission of electrical signals between the peripheral circuit and the memory cell string. In some possible implementations, a bonding interface 50 may be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, and the peripheral interconnect layer 130 and the array interconnect layer 290 may be bonded and coupled to each other through the bonding interface 50.

[0101] Please refer to Figure 5 The three-dimensional memory 301 provided by the embodiment of the present invention includes an intermediate layer 302, a first device layer 303 and a second device layer 304. The intermediate layer 302 is along Figure 2 The plane where XY is located is set, and the intermediate layer 302 is in the thickness direction (i.e., along Figure 2 The intermediate layer 302 has a first side and a second side that are relatively arranged in the XY direction (in the middle Z direction), the first device layer 303 and the second device layer 304 are both arranged along the XY plane, and the first device layer 303 is located on the first side of the intermediate layer 302, and the second device layer 304 is located on the second side of the intermediate layer 302, wherein the intermediate layer 302 may include semiconductor materials, such as silicon, germanium and other materials, the first device layer 303 may include a plurality of first transistors 305, the second device layer 304 may include a plurality of second transistors 306, and the first transistor 305 and the second transistor 306 may both include complementary metal oxide semiconductors (Complementary Metal Oxide Semiconductor, CMOS).

[0102] Continue to refer to Figure 5 The three-dimensional memory 301 may further include a first memory array layer 307. The first memory array layer 307 is arranged along Figure 2 The first storage array layer 307 is arranged in the plane where XY is located, and is located on the side of the first device layer 303 away from the middle layer 302. The first storage array layer 307 may include a plurality of first storage structures (not shown). Figure 2 In the Z direction, the first storage structure may include: Figure 3In the memory cell string 40 shown in the figure, one end of each first memory structure close to the first device layer 303 is connected to a first transistor 305 in the first device layer 303, thereby connecting the first memory array layer 307 to at least one of the plurality of first transistors 305, wherein the first memory array layer 307 and the first device layer 303 can be formed separately, that is, the formation of the first memory array layer 307 is not based on the existence of the first device layer 303 as a prerequisite, and at the same time, the formation of the first device layer 303 is not based on the existence of the first memory array layer 307 as a prerequisite, and the first memory array layer 307 is not based on the existence of the first device layer 303 as a prerequisite. 7 and the first device layer 303 can be separately formed on different substrates, wherein a first connection portion 308 is formed at one end of the first storage structure close to the first device layer 303, and a second connection portion 309 is formed at one end of the first transistor 305 close to the first storage array layer 307. The connection method between the first storage structure and the first transistor 305 may include a wafer bonding connection, that is, the connection between the first storage structure and the first transistor 305 is achieved through the bonding between the first connection portion 308 and the second connection portion 309, thereby achieving the connection between the first storage array layer 307 and the first device layer 303.

[0103] Continue to refer to Figure 5 The three-dimensional memory 301 may further include a second memory array layer 310, the second memory array layer 310 also being arranged along Figure 2 The second storage array layer 310 is arranged in the plane where XY is located, and is located on the side of the second device layer 304 away from the middle layer 302. The second storage array layer 310 may include a plurality of second storage structures (not shown). Figure 2 The second storage structure may also include: Figure 3In the memory cell string 40 shown in the figure, one end of each second memory structure close to the second device layer 304 is connected to a corresponding second transistor 306 in the second device layer 304, so that the second memory array layer 310 is connected to at least one of the plurality of second transistors 306, wherein the second memory array layer 310 and the second device layer 304 can also be formed separately, that is, the formation of the second memory array layer 310 is not based on the existence of the second device layer 304 as a prerequisite, and at the same time, the formation of the second device layer 304 is not based on the existence of the second memory array layer 310 as a prerequisite, and the second memory array layer 310 is not based on the existence of the second device layer 304 as a prerequisite. 0 and the second device layer 304 can be separately formed on different substrates, wherein a third connection portion 311 is formed at one end of the second storage structure close to the second device layer 304, and a fourth connection portion 312 is formed at one end of the second transistor 306 close to the second storage array layer 310. The connection method between the second storage structure and the second transistor 306 may include a wafer bonding connection, that is, the connection between the second storage structure and the second transistor 306 is achieved through the bonding between the third connection portion 311 and the fourth connection portion 312, thereby achieving the connection between the second storage array layer 310 and the second device layer 304.

[0104] Through the above settings, after the first transistor 305 is connected to the first storage array layer 307, it can logically control the multiple first storage structures in the first storage array layer 307, so that the first storage array layer 307 can achieve the storage or reading function. Similarly, after the second transistor 306 is connected to the second storage array layer 310, it can logically control the multiple second storage structures in the second storage array layer 310, so that the second storage array layer 310 can achieve the storage or reading function.

[0105] Continue to refer to Figure 5 At the same time, in the above implementation, the first storage array layer 307 and the first device layer 303 are connected by wafer bonding. The first storage array layer 307 and the first device layer 303 can be formed on different substrates and then bonded to avoid forming the first device layer 303 on the first storage array layer 307 or forming the first storage array layer 307 on the first device layer 303. In this way, the impact on the first storage array layer 307 when the first device layer 303 is formed on the first storage array layer 307 can be reduced or the impact on the first device layer 303 when the first storage array layer 307 is formed on the first device layer 303 can be reduced, thereby improving the yield of the three-dimensional memory 301. It can be understood that the second storage array layer 310 and the second device layer 304 are also connected by wafer bonding, which can obtain the same beneficial effect, which will not be repeated here.

[0106] Continue to refer to Figure 5In the three-dimensional memory 301 provided by the embodiment of the present invention, the middle layer 302 has a first side and a second side in the thickness direction, the first device layer 303 is located on the first side of the middle layer 302, the first storage array layer 307 is located on the side of the first device layer 303 away from the middle layer 302, the second device layer 304 is located on the second side of the middle layer 302, and the second storage array layer 310 is located on the side of the second device layer 304 away from the middle layer 302, thereby forming a five-layer structure of the first storage array layer 307, the first device layer 303, the middle layer 302, the second device layer 304, and the second storage array layer 310 stacked in the thickness direction of the middle layer 302, and having the first storage array layer 307 and the second storage array layer 310 for storage per unit area, thereby increasing the capacity of the three-dimensional memory 301.

[0107] Continue to refer to Figure 5 In the embodiment of the present invention, the three-dimensional memory 301 also includes a packaging substrate 313, which is located on the side of the first storage array layer 307 away from the middle layer 302. A connecting circuit 314 is provided on the packaging substrate 313. The first device layer 303 and the first storage array layer 307 are both connected to the connecting circuit 314, and the second device layer 304 and the second storage array layer 310 are also connected to the connecting circuit 314.

[0108] Continue to refer to Figure 5 In the implementation mode of connecting the first device layer 303 with the connection circuit 314, the first storage array layer 307 may include a first pad 315 and an internal first conductive column 316, wherein the first pad 315 is located on the side of the first storage array layer 307 away from the middle layer 302, the first pad 315 is used to connect with the connection circuit 314 on the packaging substrate 313, and the first conductive column 316 is connected along the first device layer 303 and the connection circuit 314 is connected to ... Figure 2 The first conductive pillar 316 is arranged in the middle Z direction, one end of the first conductive pillar 316 is connected to the first pad 315, and the other end of the first conductive pillar 316 is located on a side of the first storage array layer 307 close to the first device layer 303. In the implementation method in which the three-dimensional memory 301 includes a first connecting portion 308 and a second connecting portion 309, one end of the first conductive pillar 316 close to the first device layer 303 is connected to at least one first connecting portion 308, the first connecting portion 308 is bonded to the second connecting portion 309, and the second connecting portion 309 is connected to the first transistor 305.

[0109] Through the above configuration, the first conductive pillar 316 leads the at least one first transistor 305 to the first pad 315 , so that the at least one first transistor 305 can be connected to the connection circuit 314 of the package substrate 313 through the first pad 315 .

[0110] Continue to refer to Figure 5In an implementation in which the first storage array layer 307 is connected to the connection circuit 314, the first storage array layer 307 may further include a second pad 317, the second pad 317 is located on a side of the first storage array layer 307 away from the intermediate layer 302, the second pad 317 is spaced apart from the first pad 315, and the second pad 317 is used to connect to the connection circuit 314 on the packaging substrate 313. In an implementation in which the first storage array layer 307 includes a first storage structure, the second pad 317 is connected to the first storage structure on a side away from the packaging substrate 313.

[0111] Through the above configuration, the first storage structure is connected to the second pad 317, so that the first storage structure can be connected to the connection circuit 314 of the package substrate 313 through the second pad 317. In combination with the above implementation, the first pad 315 and the second pad 317 are both connected to the connection circuit 314, the first pad 315 is connected to at least one first transistor 305, and the second pad 317 is connected to the first storage array layer 307, so that the first device layer 303 and the first storage array layer 307 can be connected to the connection circuit 314.

[0112] Continue to refer to Figure 5 A first contact 318 and a second contact 319 are provided on the packaging substrate 313. The first contact 318 and the second contact 319 are located on the surface of the packaging substrate 313 close to the intermediate layer 302. The first contact 318 and the second contact 319 are both connected to the connecting circuit 314, wherein the first contact 318 is connected to the first pad 315, and the second contact 319 is connected to the second pad 317.

[0113] Through the above arrangement, the connection circuit 314 of the packaging substrate 313 is connected to the first pad 315 through the first contact 318, and is connected to the second pad 317 through the second contact 319. This can not only realize the connection between the packaging substrate 313 and the first storage array layer 307 and the first device layer 303, but also make the connection circuit 314 located inside the packaging substrate 313 to avoid leakage of the connection circuit 314, thereby affecting the storage efficiency of the three-dimensional memory 301.

[0114] Continue to refer to Figure 5In the above implementation, the first contact 318 is connected to the first pad 315 by welding, and the second contact 319 is connected to the second pad 317 by welding. Exemplarily, the first contact 318 and the first pad 315 can be welded by a bumping process, and the bumping process can form a bump on the first contact 318. The bump can be a protrusion with metal conductive properties, such as copper, copper-tin alloy, etc. The bump is used to connect with the first pad 315, wherein the bump formed between the first contact 318 and the first pad 315 after welding can be spherical, columnar, or block-shaped. Similarly, the second contact 319 and the second pad 317 can also be welded by a bumping process, which will not be described in detail here.

[0115] Through the above-mentioned setting, welding between the first contact 318 and the first pad 315 can realize electrical interconnection between the first contact 318 and the first pad 315, and welding between the second contact 319 and the second pad 317 can realize electrical interconnection between the second contact 319 and the second pad 317. At the same time, the solder formed by welding can also play a stress buffering role between the first storage array layer 307 and the packaging substrate 313.

[0116] Continue to refer to Figure 5 In an implementation manner in which the second device layer 304 is connected to the connection circuit 314, the second storage array layer 310 may include a third pad 320 and an internal second conductive pillar 321, wherein the third pad 320 is located on a side of the second storage array layer 310 away from the middle layer 302, the third pad 320 is used to connect to the connection circuit 314 on the packaging substrate 313, the second conductive pillar 321 is arranged along the Z direction, one end of the second conductive pillar 321 is connected to the third pad 320, and the other end of the third conductive pillar is located on a side of the second storage array layer 310 close to the second device layer 304, in an implementation manner in which the three-dimensional memory 301 includes a third connection portion 311 and a fourth connection portion 312, one end of the second conductive pillar 321 close to the second device layer 304 is connected to at least one third connection portion 311, the third connection portion 311 is bonded to the fourth connection portion 312, and the fourth connection portion 312 is connected to the second transistor 306.

[0117] Through the above configuration, the second conductive pillar 321 leads the at least one second transistor 306 to the third pad 320 , so that the at least one second transistor 306 can be connected to the connection circuit 314 of the package substrate 313 through the third pad 320 .

[0118] Continue to refer to Figure 5In an implementation in which the second storage array layer 310 is connected to the connection circuit 314, the second storage array layer 310 may further include a fourth pad 322, the fourth pad 322 is located on a side of the second storage array layer 310 away from the middle layer 302, the fourth pad 322 is spaced apart from the third pad 320, and the fourth pad 322 is used to connect to the connection circuit 314 on the packaging substrate 313. In an implementation in which the second storage array layer 310 includes a second storage structure, the fourth pad 322 is connected to the first storage structure on a side close to the middle layer 302.

[0119] Through the above configuration, the second storage structure is connected to the fourth pad 322, so that the second storage structure can be connected to the connection circuit 314 of the package substrate 313 through the fourth pad 322. In combination with the above implementation, the third pad 320 and the fourth pad 322 are both connected to the connection circuit 314, the third pad 320 is connected to at least one second transistor 306, and the fourth pad 322 is connected to the second storage array layer 310, so that the second device layer 304 and the second storage array layer 310 can be connected to the connection circuit 314.

[0120] Continue to refer to Figure 5 A third contact 323 and a fourth contact 324 are provided on the packaging substrate 313. The third contact 323 and the fourth contact 324 are located on the surface of the packaging substrate 313 close to the intermediate layer 302. The third contact 323 and the fourth contact 324 are both connected to the connecting circuit 314, wherein the third contact 323 is connected to the third pad 320, and the fourth contact 324 is connected to the fourth pad 322.

[0121] Through the above arrangement, the connection circuit 314 of the packaging substrate 313 is connected to the third pad 320 through the third contact 323, and is connected to the fourth pad 322 through the fourth contact 324. This can not only realize the connection between the packaging substrate 313 and the second storage array layer 310 and the second device layer 304, but also make the connection circuit 314 located inside the packaging substrate 313 to avoid leakage of the connection circuit 314, thereby affecting the storage efficiency of the three-dimensional memory 301.

[0122] Continue to refer to Figure 5 In the implementation mode in which the first contact 318 and the second contact 319 are arranged on the package substrate 313, the first contact 318 and the second contact 319 are located within the projection of the first storage array layer 307 on the package substrate 313, and the third contact 323 and the fourth contact 324 are located outside the projection of the first storage array layer 307 on the package substrate 313. This facilitates the connection between the third contact 323 and the third pad 320, and between the fourth contact 324 and the fourth pad 322.

[0123] In the above implementation, the third contact 323 and the third pad 320 may be connected by wire bonding, and the fourth contact 324 and the fourth pad 322 may also be connected by wire bonding. Exemplarily, the three-dimensional memory 301 may also include a first wire 325 and a second wire 326, one end of the first wire 325 is connected to the third pad 320, the other end of the first wire 325 is connected to the third contact 323, one end of the second wire 326 is connected to the fourth pad 322, and the other end of the second wire 326 is connected to the fourth contact 324.

[0124] Through the above configuration, electrical interconnection between the third pad 320 and the third contact 323 can be achieved through the first wire 325 , and electrical interconnection between the fourth pad 322 and the fourth contact 324 can be achieved through the second wire 326 .

[0125] Continue to refer to Figure 5 In combination with the above embodiments, at least one first transistor 305 is connected to the connection circuit 314, realizing the connection between the first device layer 303 and the connection circuit 314, and at least one second transistor 306 is connected to the connection circuit 314, realizing the connection between the second device layer 304 and the connection circuit 314. The first storage array layer 307 and the second storage array layer 310 are both connected to the connection circuit 314, and the connection circuit 314 realizes the connection between the first device layer 303, the second device layer 304, the first storage array layer 307 and the second storage array layer 310 stacked along the thickness direction of the intermediate layer 302, thereby increasing the capacity of the three-dimensional memory 301.

[0126] The present invention also provides a method for preparing a three-dimensional memory 301, which can be used to prepare the three-dimensional memory in the above embodiment. Figure 6 The preparation method may include steps S100-S200:

[0127] S100: forming a first device layer and a second device layer on a first initial intermediate layer to obtain an intermediate layer; the first device layer includes a plurality of first transistors, the first device layer is located on a first side of the intermediate layer, the second device layer includes a plurality of second transistors, the second device layer is located on a second side of the intermediate layer, the first side and the second side are two opposite sides of the intermediate layer in a thickness direction.

[0128] Please refer to Figures 7 to 10 In step S100, forming a first device layer 303 and a second device layer 304 on the first initial intermediate layer 327, and obtaining the intermediate layer 302 may include:

[0129] Please refer to Figure 7 and Figure 8, a second device layer 304 is formed on one side of the first initial intermediate layer 327, and a second initial intermediate layer 328 is obtained. Exemplarily, the first initial intermediate layer 327 is used as a substrate, a plurality of second transistors 306 are formed on one side of the first initial intermediate layer 327, the plurality of second transistors 306 constitute the second device layer 304, and the remaining first initial intermediate layer 327 forms the second initial intermediate layer 328. The first initial intermediate layer 327 may include semiconductor materials, such as silicon, germanium and the like. It can be understood that the second initial intermediate layer 328 is formed by the remaining first initial intermediate layer 327, that is, the material of the second initial intermediate layer 328 is the same as the material of the first initial intermediate layer 327.

[0130] Please refer to Fig. 9 , a first protective layer 329 is formed on the second device layer 304. Exemplarily, the material of the first protective layer 329 can completely cover the surface of the second device layer 304 away from the second initial intermediate layer 328 to prevent the second transistor 306 in the second device layer 304 from being worn. The material of the first protective layer 329 is different from the material of the first initial intermediate layer 327, and there is a certain etching selectivity, such as 50:1, 100:1, etc. Since the second transistor 306 of the second device layer 304 is formed with the first initial intermediate layer 327 as the substrate, in the implementation method with a high etching selectivity between the first protective layer 329 and the first initial intermediate layer 327, it can be ensured that when the first protective layer 329 is removed, the second device layer 304 will not be affected.

[0131] Continue to refer to Fig. 9 , flip the second initial intermediate layer 328; in this embodiment, the relative positions of the second initial intermediate layer 328, the second device layer 304 and the first protective layer 329 remain unchanged. It can be considered that after flipping the second initial intermediate layer 328, the first protective layer 329 is located at the bottom, and the second device layer 304 and the second initial intermediate layer 328 are stacked upward in sequence. At this time, the first protective layer 329 can prevent the second device layer 304 from being worn.

[0132] Please refer to Fig.10 , after flipping the second initial intermediate layer 328, a first device layer 303 is formed on the side of the second initial intermediate layer 328 away from the second device layer 304, and an intermediate layer 302 is obtained. Exemplarily, with the second initial intermediate layer 328 as a substrate, a plurality of first transistors 305 are formed on the side of the second initial intermediate layer 328 away from the second device layer 304, the plurality of first transistors 305 constitute the first device layer 303, and the remaining second initial intermediate layer 328 forms the intermediate layer 302. It can be understood that the intermediate layer 302 is formed by the remaining second initial intermediate layer 328, that is, the material of the intermediate layer 302 is the same as the material of the second initial intermediate layer 328.

[0133] Through the above arrangement, a four-layer structure of the first device layer 303, the middle layer 302, the second device layer 304, and the first protective layer 329 is formed in a stacked arrangement in the thickness direction of the middle layer 302, the first device layer 303 and the second device layer 304 are formed on both sides in the thickness direction of the middle layer 302, and the first device layer 303 and the second device layer 304 that can be connected to the memory cell string are provided per unit area, the number of transistors used to be connected to the memory cell string is increased, that is, the total number of the first transistors 305 and the second transistors 306, the number of memory cell strings that can be connected to the three-dimensional memory 301 is increased, and the capacity of the three-dimensional memory 301 is increased. In addition, the first protective layer 329 is located on the side of the second device layer 304 away from the second initial middle layer 328, so as to avoid the second device layer 304 from being worn during the process of forming the first device layer 303 on the second initial middle layer 328.

[0134] S200: A first storage array layer 307 and a second storage array layer 310 are formed, wherein the first storage array layer 307 is located on a side of the first device layer 303 away from the middle layer 302, and the first storage array layer 307 is connected to at least one of the plurality of first transistors 305, and the second storage array layer 310 is located on a side of the second device layer 304 away from the middle layer 302, and the second storage array layer 310 is connected to at least one of the plurality of first transistors 305.

[0135] Please refer to Figures 11 to 13 In step S200, forming the first storage array layer 307 and the second storage array layer 310 includes:

[0136] Please refer to Fig.11 , attaching the first storage array layer 307 to the first device layer 303. Combined with the previous description, it can be considered that the second initial intermediate layer 328 is the substrate on which the first device layer 303 is formed, and the first storage array layer 307 is formed on another substrate (not shown in the figure), and then the first storage array layer 307 is attached to the first device layer 303.

[0137] In the process of forming the first storage array layer 307, the first storage array layer 307 includes a plurality of first storage structures and a plurality of first connection parts 308, the first connection parts 308 are located on the side of the first storage array layer 307 close to the first device layer 303, and one end of the first storage structure close to the first device layer 303 is connected to the first connection part 308; and in the process of forming the first device layer 303 in step 100, after forming the first transistor 305, a second connection part 309 can be formed on the side of the first transistor 305 away from the middle layer 302, and the first transistor 305 is connected to the second connection part 309. Then, the connection between the first storage array layer 307 and the first device layer 303 can be realized through the bonding between the first connection part 308 and the second connection part 309, thereby realizing the connection between the first storage array layer 307 and the first device layer 303.

[0138] Please refer to Fig.11 and Fig.12 , a second protection layer 330 is formed on the first storage array layer 307; illustratively, the material of the second protection layer 330 can completely cover the surface of the first storage array layer 307 away from the first device layer 303, so as to prevent the first storage structure in the first storage array layer 307 from being worn. The material of the second protection layer 330 is different from that of the first storage array layer 307, and there is a certain etching selectivity, such as 50:1, 100:1, etc. In the implementation method in which there is a high etching selectivity between the second protection layer 330 and the first storage array layer 307, it can be ensured that when the second protection layer 330 is removed, the first storage array layer 307 will not be affected.

[0139] Continue to refer to Fig.11 and Fig.12 , flip the middle layer 302; in this embodiment, the relative positions of the second protection layer 330, the first storage array layer 307, the first device layer 303, the middle layer 302, the second device layer 304 and the first protection layer 329 remain unchanged. It can be considered that after flipping the middle layer 302, the second protection layer 330 is located at the bottom, and the first storage array layer 307, the first device layer 303, the middle layer 302, the second device layer 304 and the first protection layer 329 are stacked upward in sequence. At this time, the second protection layer 330 can prevent the first storage array layer 307 from being worn.

[0140] The first protection layer 329 is removed to expose the second device layer 304 , so as to facilitate the subsequent connection between the second device layer 304 and the second storage array layer 310 .

[0141] Please refer to Fig.13, attaching the second storage array layer 310 to the second device layer 304; combined with the previous description, it can be considered that the first initial intermediate layer 327 is the substrate on which the second device layer 304 is formed, and the second storage array layer 310 is formed on another substrate (not shown in the figure), and then the second storage array layer 310 is attached to the second device layer 304.

[0142] In the process of forming the second storage array layer 310, the second storage array layer 310 includes a plurality of second storage structures and a plurality of third connection parts 311, the third connection part 311 is located on the side of the second storage array layer 310 close to the second device layer 304, and one end of the second storage structure close to the second device layer 304 is connected to the third connection part 311; and in the process of forming the second device layer 304 in step 100, after forming the second transistor 306, a fourth connection part 312 can also be formed on the side of the second transistor 306 away from the middle layer 302, and the second transistor 306 is connected to the fourth connection part 312. Then, the connection between the second storage array layer 310 and the second device layer 304 can be realized by bonding between the third connection part 311 and the fourth connection part 312, thereby realizing the connection between the second storage array layer 310 and the second device layer 304.

[0143] Combined with reference Fig.12 and Fig.13 , remove the second protection layer 330 to expose the first storage array layer 307 , so as to facilitate the subsequent connection between the first storage array layer 307 and the packaging substrate 313 .

[0144] Through the above configuration, the second protection layer 330 is located on the side of the first storage array layer 307 away from the first device layer 303 to prevent the first storage array layer 307 from being worn during the process of forming the second storage array layer 310 on the second device layer 304 .

[0145] A method for preparing a three-dimensional memory 301 provided in an embodiment of the present invention forms a five-layer structure of a first storage array layer 307, a first device layer 303, an intermediate layer 302, a second device layer 304, and a first storage array layer 307 stacked in the thickness direction of the intermediate layer 302. The first storage array layer 307 and the second storage array layer 310 for storage are provided per unit area, thereby increasing the capacity of the three-dimensional memory 301.

[0146] The method for preparing a three-dimensional memory 301 provided in an embodiment of the present invention may further include:

[0147] Please refer to Fig.14, forming a packaging substrate 313, on which a connecting circuit 314 is provided, and on a surface of the packaging substrate 313 close to the middle layer 302, a first contact 318 and a second contact 319 are provided, and both the first contact 318 and the second contact 319 are connected to the connecting circuit 314;

[0148] After the first memory array layer 307 is formed, the first memory array layer 307 further includes a first pad 315 and a second pad 317 that are spaced apart from each other. The first pad 315 and the second pad 317 are both located on a side of the first memory array layer 307 away from the middle layer 302 . The first pad 315 is connected to at least one first transistor 305 .

[0149] After the first storage array layer 307 is attached to the first device layer 303, the following steps further include: connecting the first contact 318 and the first pad 315 by welding; and connecting the second contact 319 and the second pad 317 by welding.

[0150] In the above implementation, the first contact 318 and the first pad 315 may be welded by using a bumping process. Similarly, the second contact 319 and the second pad 317 may be welded by using a bumping process.

[0151] Through the above-mentioned setting, welding between the first contact 318 and the first pad 315 can realize electrical interconnection between the first contact 318 and the first pad 315, and welding between the second contact 319 and the second pad 317 can realize electrical interconnection between the second contact 319 and the second pad 317. At the same time, the solder formed by welding can also play a stress buffering role between the first storage array layer 307 and the packaging substrate 313.

[0152] Please refer to Fig.15 After the package substrate 313 is formed, a third contact 323 and a fourth contact 324 are provided on the surface of the package substrate 313 close to the middle layer 302, and the third contact 323 and the fourth contact 324 are both connected to the connection circuit 314;

[0153] After the second memory array layer 310 is formed, the second memory array layer 310 further includes a third pad 320 and a fourth pad 322 that are spaced apart from each other. The third pad 320 and the fourth pad 322 are both located on a side of the second memory array layer 310 away from the middle layer 302. The third pad 320 is connected to at least one second transistor 306.

[0154] After attaching the second storage array layer 310 to the second device layer 304 , the steps further include: forming a first conductive wire 325 and a second conductive wire 326 , connecting the third contact 323 and the third pad 320 via the first conductive wire 325 , and connecting the fourth contact 324 and the fourth pad 322 via the second conductive wire 326 .

[0155] In the above implementation, the third contact 323 and the third pad 320 may be connected by wire bonding, and the fourth contact 324 and the fourth pad 322 may also be connected by wire bonding.

[0156] Through the above configuration, electrical interconnection between the third pad 320 and the third contact 323 can be achieved through the first wire 325 , and electrical interconnection between the fourth pad 322 and the fourth contact 324 can be achieved through the second wire 326 .

[0157] Please refer to Fig.16 and Fig.17 Some embodiments of the present invention further provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 301, wherein the three-dimensional memory 301 may include the three-dimensional memory 301 described above, and the controller 20 is coupled to the three-dimensional memory 301 to control the three-dimensional memory 301 to store data.

[0158] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0159] In some embodiments, reference Fig.16 , the storage system 1000 includes a controller 20 and a three-dimensional memory 301, and the storage system 1000 can be integrated into a memory card.

[0160] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0161] In other embodiments, referring to Fig.17 The storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 301, and the storage system 1000 is integrated into a solid state drive (SSD).

[0162] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0163] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0164] In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 301 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 301, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 301, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 20 may also be configured to process error correction codes regarding data read from or written to the three-dimensional memory 301.

[0165] Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 301; for example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0166] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0167] Some embodiments of the present invention further provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0168] The electronic device may include a host and the storage system 1000 described above, wherein the host and the storage system 1000 may be coupled and may further include at least one of a central processing unit (CPU) and a cache.

[0169] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A three-dimensional memory, characterized in that: include: an intermediate layer having a first side and a second side opposite to each other in a thickness direction of the intermediate layer; A first device layer, the first device layer comprising a plurality of first transistors, the first device layer being located on a first side of the middle layer; a second device layer, the second device layer comprising a plurality of second transistors, the second device layer being located on a second side of the middle layer; a first storage array layer, the first storage array layer being located on a side of the first device layer away from the middle layer; A second storage array layer, wherein the second storage array layer is located on a side of the second device layer away from the middle layer.

2. The three-dimensional memory according to claim 1, characterized in that: The first memory array layer is connected to at least one of the first transistors, and the second memory array layer is connected to at least one of the second transistors.

3. The three-dimensional memory according to claim 2, characterized in that: The three-dimensional memory also includes a packaging substrate, on which a connecting circuit is provided. The packaging substrate is located on a side of the first storage array layer away from the middle layer, and at least one of the first transistors, the first storage array layer, at least one of the second transistors, and the second storage array layer are all connected to the connecting circuit.

4. The three-dimensional memory according to claim 3, characterized in that: The first storage array layer includes a first pad and a second pad that are spaced apart from each other. The first pad and the second pad are both located on a side of the first storage array layer away from the middle layer. The first pad connects at least one of the first transistors to the connection circuit, and the second pad connects the first storage array layer to the connection circuit.

5. The three-dimensional memory according to claim 4, characterized in that: The first memory array layer includes a first conductive pillar, one end of the first conductive pillar is connected to the first pad, and the other end of the first conductive pillar is connected to the first transistor.

6. The three-dimensional memory according to claim 4, characterized in that: A first contact and a second contact are provided on the surface of the packaging substrate close to the middle layer, the first contact and the second contact are both connected to the connection circuit, the first contact is connected to the first pad, and the second contact is connected to the second pad.

7. The three-dimensional memory according to claim 6, characterized in that: The first contact is welded to the first pad, and the second contact is welded to the second pad.

8. The three-dimensional memory according to any one of claims 3 to 7, characterized in that: The second storage array layer includes a third pad and a fourth pad that are spaced apart from each other. The third pad and the fourth pad are both located on a side of the second storage array layer away from the middle layer. The third pad connects at least one of the second transistors with the connection circuit, and the fourth pad connects the second storage array layer with the connection circuit.

9. The three-dimensional memory according to claim 8, characterized in that: The second storage array layer includes a second conductive pillar, one end of the second conductive pillar is connected to the third pad, and the other end of the second conductive pillar is connected to the second transistor.

10. The three-dimensional memory according to claim 8, characterized in that: A third contact and a fourth contact are arranged on the surface of the packaging substrate close to the middle layer, and the third contact and the fourth contact are both connected to the connection circuit; the three-dimensional memory also includes a first wire and a second wire, one end of the first wire is connected to the third pad, the other end of the first wire is connected to the third contact, one end of the second wire is connected to the fourth pad, and the other end of the second wire is connected to the fourth contact.

11. A method for preparing a three-dimensional memory, characterized in that: include: forming a first device layer and a second device layer on the first initial intermediate layer to obtain an intermediate layer; The first device layer includes a plurality of first transistors, and the first device layer is located on a first side of the middle layer; the second device layer includes a plurality of second transistors, and the second device layer is located on a second side of the middle layer, and the first side and the second side are two opposite sides of the middle layer in a thickness direction; A first storage array layer and a second storage array layer are formed, wherein the first storage array layer is located on a side of the first device layer away from the middle layer, the first storage array layer is connected to at least one of the first transistors, and the second storage array layer is located on a side of the second device layer away from the middle layer, the second storage array layer is connected to at least one of the first transistors.

12. The preparation method according to claim 11, characterized in that: The forming of the first device layer and the second device layer on the first initial intermediate layer comprises: forming a second device layer on one side of the first initial intermediate layer to obtain a second initial intermediate layer; forming a first protective layer on the second device layer; The second initial intermediate layer is turned over, and a first device layer is formed on a side of the second initial intermediate layer facing away from the second device layer, to obtain an intermediate layer.

13. The preparation method according to claim 12, characterized in that: Forming a first storage array layer and a second storage array layer includes: attaching the first storage array layer to the first device layer; forming a second protective layer on the first storage array layer; Turning over the intermediate layer and removing the first protective layer; attaching the second storage array layer to the second device layer; The second protective layer is removed.

14. The preparation method according to claim 13, characterized in that: The preparation method further comprises: forming a packaging substrate, wherein a connection circuit is provided on the packaging substrate, and a first contact and a second contact are provided on a surface of the packaging substrate close to the middle layer, wherein the first contact and the second contact are both connected to the connection circuit; After the first memory array layer is formed, the first memory array layer further comprises a first pad and a second pad which are spaced apart from each other, the first pad and the second pad are both located on a side of the first memory array layer away from the middle layer, and the first pad is connected to at least one of the first transistors; After the first storage array layer is attached to the first device layer, the method further includes: connecting the first contact and the first pad by welding; and connecting the second contact and the second pad by welding.

15. The preparation method according to claim 14, characterized in that: The preparation method further comprises: After the packaging substrate is formed, a third contact and a fourth contact are arranged on a surface of the packaging substrate close to the middle layer, and both the third contact and the fourth contact are connected to the connection circuit; After the second memory array layer is formed, the second memory array layer further comprises a third pad and a fourth pad which are spaced apart from each other, the third pad and the fourth pad are both located on a side of the second memory array layer away from the middle layer, and the third pad is connected to at least one of the second transistors; After attaching the second storage array layer to the second device layer, the method further includes: forming a first wire and a second wire, connecting the third contact and the third pad through the first wire, and connecting the fourth contact and the fourth pad through the second wire.

16. A storage system, characterized in that: include: The three-dimensional memory as claimed in any one of claims 1 to 10; The controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

17. An electronic device, characterized in that: The device comprises a host and the storage system as claimed in claim 16, wherein the host and the storage system are coupled.

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