Depletion type GaN HEMT vertical structure chip and preparation method thereof

Abstract

The invention discloses a depletion mode GaN HEMT vertical structure chip and a preparation method thereof, and relates to the technical field of depletion mode HEMT chip preparation, and the method comprises the steps: sequentially growing a GaN drift region, an AlN insertion layer, an AlXGa (1-X) N barrier layer and a SiN dielectric cap layer on a substrate, then forming an isolation region through ion implantation, photoetching and etching a source window, manufacturing a source electrode, a grid electrode and a drain electrode, and finally forming a depletion mode HEMT vertical structure chip. And performing rapid thermal annealing treatment to form ohmic contact, and finally growing a passivation layer and photoetching an electrode leading-out region. According to the method, by accurately controlling growth parameters and process steps, high quality and high performance of the chip are ensured, the current transmission capacity, breakdown voltage, carrier mobility and stability of the chip are improved, and powerful support is provided for application of GaN HEMT devices.

Description

Technical Field

[0001] The invention belongs to the technical field of preparation of depletion-type GaN HEMT devices, and in particular relates to a depletion-type GaN HEMT vertical structure chip and a preparation method thereof. Background Art

[0002] With the rapid development of information technology, especially the rise of emerging fields such as 5G communications, the Internet of Things, and new energy vehicles, higher requirements are placed on high-efficiency, high-power, and high-frequency semiconductor chips. Gallium nitride (GaN) materials have become an ideal choice for the preparation of high-performance power electronic devices due to their excellent physical and chemical properties. As a representative of wide-bandgap semiconductor devices, GaN-based high electron mobility transistors (HEMTs) have shown great application potential in microwave communications, power conversion, and other fields due to their high electron mobility, high saturated electron velocity, high breakdown electric field, and good thermal stability.

[0003] At present, as an important type of GaN HEMT device, depletion-mode GaN HEMT has received extensive attention and research. Depletion-mode GaN HEMT is in the on state when the gate-source voltage is zero. This characteristic gives it unique advantages in certain specific applications. In terms of preparation methods, researchers usually use epitaxial growth technology to sequentially grow GaN and related layer materials on the substrate, and form electrode structures through process steps such as lithography and etching. In addition, in order to improve the performance and reliability of the device, packaging technology has also become one of the research hotspots, aiming to give full play to the excellent performance of GaNHEMT devices by optimizing the packaging structure and materials.

[0004] Although significant progress has been made in the preparation and application of depletion-mode GaN HEMT vertical structure chips, there are still some problems that need to be solved. First, the control of material defects and interface states during epitaxial growth is one of the difficulties, and these defects and interface states will affect the electrical properties and stability of the chip. Secondly, the accuracy and uniformity of process steps such as lithography and etching have an important impact on chip performance, but the current process level still needs to be improved. In addition, packaging technology and material selection are also one of the key factors restricting the performance of GaN HEMT chips, which need further optimization and innovation. Therefore, in-depth research and improvement on the preparation method and packaging technology of depletion-mode GaN HEMT vertical structure chips are of great significance to promote their widespread application. Summary of the invention

[0005] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a depletion-mode GaN HEMT vertical structure chip and a preparation method thereof, so as to solve the technical problems of complex GaN heteroepitaxial growth process, difficult material quality control and high preparation cost.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] Compared with the prior art, the present invention has the following beneficial effects:

[0008] The invention discloses a method for preparing a depletion-type GaN HEMT vertical structure chip. By performing chip epitaxial growth on a GaN homogeneous substrate, the defects of the epitaxial layer introduced by the material lattice mismatch and thermal mismatch in the heterogeneous epitaxial growth process are avoided, so as to solve the technical problems of complex growth process and difficult material quality control in the GaN heterogeneous epitaxial growth process. In addition, the introduction of the GaN homogeneous substrate does not require the complex process brought by the heterogeneous substrate when preparing the electrode at the bottom, thereby reducing the chip preparation cost and improving the working reliability of the chip. The metal organic compound chemical vapor deposition (MOCVD) technology is adopted, and under strictly controlled temperature, gas flow and doping conditions, the GaN drift region, AlN insertion layer, AlXGa(1-X)N barrier layer and SiN dielectric cap layer are grown in sequence. This precisely controlled epitaxial growth process ensures the high quality of each layer and provides a solid foundation for the high performance of the chip. By optimizing key parameters such as growth temperature, pressure, gas flow, etc., the precise control of the thickness, composition and crystal quality of each layer is achieved. This helps to reduce interface scattering and defects, improve carrier mobility and current density, and thus optimize the electrical performance of the chip. Using ion implantation technology, an isolation area is formed on the top of the chip to achieve effective electrical isolation of the active area. This helps to reduce mutual interference between different areas and improve the integration and reliability of the chip. Passivation layers are grown on the top and bottom of the chip, consisting of materials such as SiN, SiO2, and Al2O3. The passivation layer not only protects the chip surface from the influence of the external environment, but also improves the stability and reliability of the chip. Ohmic contacts are formed in the source and drain regions through steps such as photolithography, inductively coupled plasma etching (ICP), and deposition and annealing of electrode metals. This helps to reduce the contact resistance between the electrode and the semiconductor material and improve the current transmission capacity of the chip. Electrode metals are grown using electron beam evaporation or magnetron sputtering technology, and gate electrodes are formed through a lift-off process. This preparation method ensures the accuracy and stability of the gate electrode, which helps to improve the switching speed and current control capability of the chip. During the entire preparation process, the growth conditions of each layer and the preparation parameters of the electrode can be adjusted according to specific needs. This provides a flexible preparation process for the development of GaN HEMT chips with different performance requirements. The method of the present invention is not only applicable to the preparation of depletion-type GaN HEMT vertical structure chips, but can also be extended to the preparation of other types of GaN HEMT chips by adjusting the growth conditions and electrode design. This helps to promote the application and development of GaN HEMT technology in a wider range of fields. Due to the use of high-quality epitaxial growth, efficient electrical isolation and protection, and optimized electrode design and preparation, the depletion-type GaN HEMT vertical structure chip prepared by the present invention has excellent performance, such as high current transmission capability, high breakdown voltage, high switching speed, etc. The chip has broad application prospects in the fields of power electronics, microwave communications, and radio frequency power amplification.Especially in application scenarios such as high voltage, high frequency, and high power density, the chips prepared by the present invention are expected to play an important role in promoting scientific and technological progress and industrial development in related fields.

[0009] Furthermore, the material used for the barrier layer is at least one of AlN, AlGaN, InAlN and InAlGaN, with a thickness of 1 to 35 nm. Different materials have different band structures, electron affinities and polarization effects, and the most suitable material can be selected according to specific application requirements to optimize the performance of the chip. The thickness of the barrier layer is controlled in the range of 1 to 35 nm, so that the performance of the chip can be regulated in a wider range. By precisely controlling the thickness of the barrier layer, key parameters such as the current transfer characteristics, breakdown voltage and switching speed of the chip can be optimized to meet different application requirements.

[0010] Furthermore, the dielectric cap layer is an in-situ dielectric cap layer grown by metal organic chemical vapor deposition (MOCVD), and the material is at least one of AlN and SiN, with a thickness of 0 to 100 nm. The dielectric cap layer adopts MOCVD in-situ growth technology, which can be directly formed during the epitaxial growth process, avoiding contamination and damage during subsequent processing. This in-situ growth method helps to improve the overall quality and stability of the chip. The dielectric cap layer material selects a variety of materials such as AlN and SiN, which also provides greater flexibility for chip design. Different materials have different dielectric constants, chemical stability and thermal stability. The most suitable material can be selected according to the specific application environment, thereby enhancing the reliability and durability of the chip. The thickness of the dielectric cap layer is controlled in the range of 0 to 100 nm, providing a wider control space for chip design. By adjusting the thickness of the dielectric cap layer, the surface electrical properties, protection effect and heat dissipation performance of the chip can be optimized to meet different application requirements.

[0011] The invention discloses a depletion-mode GaN HEMT vertical structure chip, comprising a GaN substrate, a GaN drift region, an AlN insertion layer, a barrier layer, a dielectric cap layer and a passivation layer arranged in sequence from bottom to top. A high-quality GaN substrate is used as a growth basis to ensure the uniformity and stability of the epitaxial layer, providing a solid foundation for the high performance of the chip. The optimized growth of the GaN drift region improves the current transmission capacity and breakdown voltage of the chip by precisely controlling the growth parameters, so that the chip can withstand higher operating voltages and current densities. The introduction of the AlN insertion layer optimizes the interface characteristics of the chip, reduces interface scattering and defects, thereby improving the carrier mobility and current density of the chip, and further improving the performance of the chip. The precisely controlled growth of the barrier layer enables the chip to more effectively control the current size and reliability, and improves the switching speed and current control capability of the chip. The protective effect of the dielectric cap layer (such as the SiN dielectric cap layer) not only improves the stability of the chip surface, but also further improves the electrical characteristics of the chip surface by optimizing the growth parameters and introducing an appropriate amount of doping. The chip isolation area formed by ion implantation realizes effective electrical isolation of the active area, reduces mutual interference between different areas, and improves the integration and reliability of the chip. The setting of the passivation layer provides additional protection for the chip, prevents the negative impact of the external environment on the chip performance, and prolongs the service life of the chip. The entire preparation process adopts advanced processes such as metal organic chemical vapor deposition to ensure the high-quality growth of each layer, and at the same time provides flexible process adjustment space to meet the needs of different application scenarios. By accurately controlling key parameters such as temperature, gas flow and doping conditions, precise regulation of chip performance is achieved, and the controllability and repeatability of the preparation process are improved. Due to its high performance, high stability and good electrical properties, the depletion-type GaN HEMT vertical structure chip has broad application prospects in power electronics, microwave communications, radio frequency power amplification and other fields. The chip structure design and preparation process of the present invention provide strong support for the development of more efficient and reliable GaN HEMT devices, and are expected to promote scientific and technological progress and industrial development in related fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the structure of the vertical structure epitaxy of GaN HEMT disclosed in the present invention;

[0013] Figure 2 It is a schematic diagram of the structure of the vertical structure AlGaN / GaN power chip disclosed in the present invention;

[0014] Figure 3 The present invention is a flow chart of a method for preparing a depletion-mode GaN HEMT vertical structure chip disclosed in the present invention. DETAILED DESCRIPTION

[0015] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0016] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0017] The present invention is further described in detail below in conjunction with the accompanying drawings:

[0018] Table 1 Preparation method and conditions of GaN HEMT vertical structure epitaxy disclosed in the present invention

[0019]

[0020]

[0021] The present invention discloses a method for preparing a GaN HEMT vertical structure epitaxy, comprising the following steps:

[0022] GaN substrate preparation: Select 300-1000μm n-type doped GaN substrate as the growth basis. Selecting a GaN substrate of appropriate thickness can ensure the uniformity and stability of the epitaxial layer. Thicker substrates usually have better thermal stability and mechanical strength, which is conducive to the subsequent epitaxial growth process.

[0023] GaN substrate treatment: pre-treat the GaN substrate at a temperature of 1000-1150°C (preferably 1100°C), and at the same time, introduce nitrogen (N2) at a rate of 0-100L / min (preferably 0L / min), hydrogen (H2) at a rate of 50-200L / min (preferably 120L / min), and ammonia (NH3) at a rate of 1-100L / min (preferably 50L / min) to prepare for subsequent epitaxial growth. High-temperature pretreatment helps to remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the flow rate of the gas, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0024] GaN drift region growth: In the temperature range of 1000-1150℃ (preferably 1100℃) and the growth pressure of 200torr, by precisely controlling the flow rates of trimethylgallium (TMGA), N2, H2, NH3 and first monosilane (SiH4), a GaN drift region with a thickness of 0.5-50μm (preferably 7μm) is grown. This layer is crucial to chip performance. Among them, the introduction rate of TMGA is 200-1000sccm / min (preferably 600sccm / min), the introduction rate of N2 is 0-100L / min (preferably 10L / min), the introduction rate of H2 is 50-200L / min (preferably 90L / min), the introduction rate of NH3 is 1-100L / min (preferably 45L / min), the concentration of the first SIH4 is 200ppm, the introduction rate is 0-500sccm / min (preferably 10sccm / min), the growth temperature is 1000-1150℃ (preferably 1100℃), and the growth speed is 800-1200rpm (preferably 1200rpm). The drift region is a key part of the HEMT chip, and its thickness and growth conditions have an important influence on the chip performance. By precisely controlling the growth parameters, a high-quality drift region can be obtained, thereby improving the current transmission capability and breakdown voltage of the chip.

[0025] Ion implantation: The carrier blocking layer region is defined by photolithography on the epitaxial drift region grown in the previous step, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions destroy the lattice of the implanted region, achieving high resistance in the implanted region, thereby limiting the current direction. The implantation depth of the N ions is 0.1 to 20 μm (preferably 3 μm).

[0026] Channel layer growth: secondary epitaxy is performed on the epitaxial wafer after ion implantation, wherein the growth temperature is 1000-1150°C (preferably 1080°C), the rotation speed is 800-1200rpm (preferably 1200rpm), the growth pressure is 200torr, and TMGa, N2, H2, and NH3 are introduced simultaneously to grow undoped GaN, and its thickness is controlled at 150-400nm (preferably 300nm). The TMGa introduction rate is 200-1000sccm / min (preferably 500scmm / min), the N2 introduction rate is 0-100L / min (preferably 64L / min), the H2 introduction rate is 0-200L / min (preferably 120L / min), and the NH3 introduction rate is 0-100L / min (preferably 50L / min). The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. The flatness of the interface can be improved and the scattering of the two-dimensional electron gas can be reduced by adjusting the temperature and growth rate.

[0027] Growth of AlN insertion layer: Subsequently, at a temperature of 800-1100°C (preferably 1000°C) and a growth pressure of 75torr, trimethylaluminum (TMAL), H2, and NH3 are introduced simultaneously to grow an extremely thin AlN insertion layer with a thickness controlled at 0-2nm (preferably 0.8nm) to optimize chip performance. Among them, the introduction rate of TMAL is 0-500sccm / min (preferably 200sccm / min), the introduction rate of H2 is 50-200L / min (preferably 190L / min), and the introduction rate of NH3 is 1-100L / min (preferably 5L / min). The introduction of the insertion layer can optimize the interface characteristics of the chip, reduce interface scattering and defects, and thus improve the carrier mobility and current density of the chip. By precisely controlling the thickness and growth conditions of the insertion layer, the chip performance can be further optimized.

[0028] Al X Ga (1-X) N barrier layer growth: Next, at a temperature range of 800-1100°C (preferably 1020°C), 800-1200rpm (preferably 1000rpm), and a growth pressure of 100torr, by adjusting the flow rates of TMGA, TMAL, N2, H2, and NH3 gases, an Al layer with a thickness of 15-35nm (preferably 22nm) is grown. X Ga (1-X)N barrier layer, in which the Al component X ranges from 15% to 50% (preferably 20-25%), plays a key role in controlling the current size and reliability. Among them, the introduction rate of TMGA is 0-500sccm / min (preferably 80sccm / min), the introduction rate of TMAL is 50-500sccm / min (preferably 300sccm / min), the introduction rate of N2 is 0-100L / min (preferably 64L / min), the introduction rate of H2 is 50-200L / min (preferably 120L / min), and the introduction rate of NH3 is 1-100L / min (preferably 50L / min). The barrier layer is a key part of the HEMT chip, and its thickness and growth conditions have an important influence on the current transmission characteristics of the chip. By accurately controlling the growth parameters of the barrier layer, a high-quality barrier layer can be obtained, thereby improving the switching speed and current control capability of the chip.

[0029] Growth of SiN dielectric cap layer: Finally, at a temperature of 700-1100°C (preferably 1000°C) and a growth pressure of 200 torr, by adjusting the flow of N2, H2, and NH3 gases and introducing a second SiH4 gas, a SiN dielectric cap layer with a thickness of 0.1-100nm (preferably 2nm) is grown to protect and optimize the chip surface. Among them, the N2 introduction rate is 0-100L / min (preferably 64L / min), the H2 introduction rate is 50-200L / min (preferably 120L / min), the NH3 introduction rate is 1-100L / min (preferably 50L / min), the concentration of the second SIH4 is 2%, and the introduction rate is 0-500sccm / min (preferably 40sccm / min), and the above gases are introduced simultaneously. The introduction of the SiN dielectric cap layer can protect the chip surface from the influence of the external environment and improve the stability and reliability of the chip. At the same time, the electrical properties of the chip surface can be further optimized by precisely controlling the growth parameters of the dielectric cap layer and introducing an appropriate amount of second SIH4.

[0030] Finally, the vertical structure epitaxy of GaN HEMT is obtained.

[0031] During the entire preparation process, the growth of each layer must be carried out under strictly controlled temperature, gas flow and doping conditions to ensure high-quality epitaxial growth of the vertical structure of GaN HEMT.

[0032] The present invention discloses a method for preparing a depletion-mode GaN HEMT vertical structure chip, comprising the following steps:

[0033] 1. The GaN drift region, AlN insertion layer, AlN and other layers are grown in sequence on the substrate by metal organic chemical vapor deposition. X Ga (1-X)N barrier layer and SiN dielectric cap layer.

[0034] 2. Form a chip isolation area on the top by ion implantation to achieve electrical isolation of the active area, and the implanted element is at least one of F, Ar, B, and N.

[0035] 3. A window area of ​​the source electrode is photoetched on the top, and the SiN dielectric cap layer in the window area is removed by inductively coupled plasma etching (ICP).

[0036] 4. Photolithography the source electrode contact area on the top, and grow the electrode metal by electron beam evaporation or magnetron sputtering. The metal is composed of at least one of Ti, Al, Ni, TiN, and AlSi. The source electrode is formed by a stripping process, and the source electrode metal is subjected to rapid thermal annealing (Rapid Termal Anneal) in a nitrogen atmosphere to form an ohmic contact in the source area.

[0037] 5. Photolithography the electrode contact area of ​​the gate on the top, grow the electrode metal Ti / Al / Ti by electron beam evaporation or magnetron sputtering, and form the gate electrode by lift-off process.

[0038] 6. Grow a passivation layer on the top by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition), and the passivation layer is composed of at least one of SiN, SiO2 and Al2O3 chips.

[0039] 7. Form the main structure of the chip and prepare to make electrodes.

[0040] 8. Photolithography the drain electrode contact area at the bottom, and grow electrode metal by electron beam evaporation or magnetron sputtering. The metal is composed of at least one of Ti, Al, Ni, TiN, and AlSi. The drain electrode is formed by a lift-off process, and the drain electrode metal is rapidly thermally annealed in a nitrogen atmosphere to form an ohmic contact in the drain area.

[0041] 9. A passivation layer is grown at the bottom by plasma enhanced chemical vapor deposition, the passivation layer is composed of at least one of SiN, SiO2, and Al2O3, and a drain electrode lead-out region is photolithographically formed.

[0042] 10. Photolithography is performed on the top to form the gate electrode and source electrode lead-out regions.

[0043] See also Figure 1The schematic diagram of the structure of the vertical structure epitaxy of GaN HEMT disclosed in the present invention; it can be seen from the figure that when preparing the vertical structure epitaxy of GaN HEMT disclosed in the present invention, first, high-quality GaN is selected as the substrate material, which provides mechanical support and thermal conductivity for the entire epitaxial structure, and avoids the epitaxial layer defects introduced in the heterogeneous epitaxy process. The GaN drift region and the GaN channel layer are epitaxially grown on the GaN substrate in sequence. This region is the key part for the chip to withstand the off-state voltage and has a direct impact on the on-resistance of the chip. Subsequently, an AlN (aluminum nitride) insertion layer is deposited on the GaN channel layer. This AlN insertion layer is used to adjust the height and distribution of the electron barrier and further optimize the chip performance. Next, a barrier layer is epitaxially grown on the AlN insertion layer. This layer and the GaN channel layer form a heterojunction to induce the generation of a high-concentration and high-mobility two-dimensional electron gas, which is the key to forming an efficient electron transport channel. Finally, a dielectric cap layer is in-situ deposited on the barrier layer. This dielectric cap layer not only plays a protective role to prevent subsequent processes from damaging the underlying structure, but also serves as an etch stop layer to ensure the accuracy of subsequent processes.

[0044] See also Figure 2 The schematic diagram of the vertical structure AlGaN / GaN power chip disclosed in the present invention; it can be seen from the figure that the AlGaN / GaN heterojunction provides a two-dimensional electron gas that participates in the operation of the chip, as a source of carriers for the chip to participate in conduction. The chip gate is located between the source and the current is controlled by applying a voltage. When the gate voltage is lower than the turn-on voltage (also called the threshold voltage) of the chip, the two-dimensional electron gas in the channel layer region below the gate is depleted, and the chip is in the off state. The chip withstand voltage depends on the thickness of the channel layer, the drift region and the substrate. When the gate voltage is higher than the threshold voltage, the two-dimensional electron gas in the channel layer region below the gate is restored, and under the action of the electric field, it flows to the drain through the channel layer, the drift region and the substrate in the vertical direction. The dielectric layer in the gate region can effectively reduce the gate leakage and reduce the chip working loss. The drift region and the substrate are doped with n-type to reduce the body resistance, thereby realizing the low on-resistance of the chip. The carrier blocking layers on both sides of the drift region are used to regulate the current direction to ensure that the current does not flow to other areas of the chip. The entire structure shows a complete path for current injection from the source, efficient conduction through the GaN epitaxial layer and substrate, and finally outflow through the drain. This vertical structure design optimizes the current path, weakens the effect of the passivation layer / barrier layer interface state on carrier transport, and improves the efficiency and reliability of the chip.

[0045] See also Figure 3This is a flow chart of the preparation method of the depletion-mode GaN HEMT vertical structure chip disclosed in the present invention; as can be seen from the figure, the epitaxial wafer first undergoes a strict cleaning step to remove surface contaminants and impurities. Subsequently, through precise positioning and hole-opening processes, key structures such as the source and drain are formed on the material. The electronic isolation step ensures the electrical isolation between the electrodes to prevent current leakage. Next, the source, drain and gate are prepared, and the precise formation of these electrodes is crucial to the performance of the chip. Finally, after the passivation layer is deposited and the holes are opened, the depletion-mode GaN HEMT vertical structure chip is completed. The entire preparation process strictly follows the process flow, ensuring the high performance and stability of the finished product, and providing reliable high-performance electronic chips for the modern electronics industry.

[0046] Example 1

[0047] A method for preparing a depletion-mode GaN HEMT vertical structure chip comprises the following steps:

[0048] 1. Cleaning: Soak in a 90°C 511 strong oxidizing solution tank in a cleaning machine for 10 minutes, then transfer to a 60°C IPA solution tank and soak for 10 minutes to remove the residual solution on the surface. Finally, transfer to a pure water tank at room temperature for 10 minutes.

[0049] 2. After the film source is taken out from the pure water tank, it is transferred to the spin dryer. The spin dryer needs to be purged with N2 at all times and the temperature is controlled at 60°C. First, rinse the film with pure water with a water resistance of more than 8. The speed of the spin dryer changes from 500rpm for 5min, 2000rpm for 10min, 1000rpm for 5min, and finally to 0rpm.

[0050] 3. Positioning preparation: Use photolithography and evaporation processes to prepare marks to achieve the purpose of positioning. First, use a negative photoresist of about 1μm and evenly apply it on the surface. Use a photolithography machine to expose the pattern, use 100℃ baking, and use a positive photoresist developer to remove excess photoresist. Use an ion source to bombard the surface of the source for 2 minutes before metal evaporation. CrTiNi is used for evaporation metal. After evaporation, use a stripper to strip. The stripper is first soaked in the degumming tank for 10 minutes, and finally rinsed with pure water at high pressure. The rinsing process is added with 2 minutes of rotation at 1000rpm.

[0051] 4. Source hole: Use photolithography and etching process to make the hole. Photolithography uses 3μm positive photoresist, and after exposure and development, a layer of pattern is made as a mask before etching. Etching uses ICP etcher to etch the medium first with F-base, and then etch GaN with Cl-base.

[0052] 5. Electronic isolation: Use photolithography and ion implantation for electronic isolation. Photolithography uses a 3μm positive photoresist, which is exposed and developed to make a layer of pattern as a mask before ion implantation. Ion implantation uses boron ions to dope in places where there is no photolithography mask to achieve the purpose of electronic isolation.

[0053] 6. Source preparation: Use photolithography and evaporation to make the source of the device. Use a negative photoresist of about 2μm for liftoff. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlTi, and use a rapid thermal annealing furnace to anneal to make an alloy.

[0054] 7. Gate preparation: Use photolithography and evaporation to make the gate of the device. Use a negative photoresist of about 2μm for lift off. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlNi.

[0055] 8. Field plate preparation: First, use plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition) to passivate a layer of SiO2 film, and then etch the conductive channels of the source and gate after photolithography. Use a negative photoresist of about 2μm for lift off. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlNi to complete the production of the field plate.

[0056] 9. Deep etching: Use photolithography and etching to do deep etching. Use a photoresist of about 8μm as a mask. After exposure and development, make a deep hole at a specific location. Then use an etching machine with Cl - The substrate is deeply etched to a depth of about 3-5 μm.

[0057] 10. Drain preparation: Use photolithography, etching and evaporation to make the drain of the device. Use a positive photoresist of about 2μm as a mask, and use an etcher to etch out the drain channel at a specific location. Use a negative photoresist of about 2μm for photolithography to do peeling. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlTi on the drain channel, and use RTA annealing to make an alloy.

[0058] 11. Bonding metal preparation: Use photolithography and evaporation to make the required bonding metal. Use negative photoresist of about 8μm for peeling in photolithography. Develop the pattern through exposure. Use metal evaporator to evaporate TiAlNi. Use bonding machine, align with infrared laser before bonding, align the bonding metal and deep etched hole, and use vacuum to make AB two pieces bonded.

[0059] The method for preparing the vertical structure epitaxy of GaN HEMT comprises the following steps:

[0060] Substrate preparation: A 300μm GaN substrate was selected as the growth basis.

[0061] Substrate treatment: The GaN substrate was pretreated at a temperature of 1000°C. At the same time, H2 was introduced at a rate of 50 L / min and NH3 at a rate of 1 L / min to prepare for subsequent epitaxial growth.

[0062] Drift region growth: In the temperature range of 1000℃ and the growth pressure of 200torr, by precisely controlling the flow of TMGA, N2, H2, NH3 and the first SIH4, a drift region with a thickness of 0.5μm is grown. This layer is crucial to the performance of the device. Among them, the flow rate of TMGA is 200sccm / min, the flow rate of H2 is 50L / min, the flow rate of NH3 is 1L / min, and the concentration of the first SIH4 is 200ppm, and the flow rate is 0.1sccm / min.

[0063] Insertion layer growth: Subsequently, at a temperature of 800°C and a growth pressure of 75torr, the flow rates of TMAL, N2, H2, and NH3 were adjusted, especially reducing the flow rate of N2 to almost zero, to grow an extremely thin insertion layer with a thickness of 0.1nm to optimize device performance. The H2 feed rate was 50L / min and the NH3 feed rate was 1L / min.

[0064] Barrier layer growth: Then, at a temperature range of 800°C and a growth pressure of 100 torr, by adjusting the flow rates of TMGA, TMAL, N2, H2, and NH3 gases, a barrier layer with a thickness of 15 nm is grown, which plays a key role in controlling current transmission. Among them, the flow rate of TMAL is 50 sccm / min, the flow rate of H2 is 50 L / min, and the flow rate of NH3 is 1 L / min.

[0065] Growth of SiN dielectric cap layer: Finally, at a temperature of 700°C and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing a second SIH4 gas, a 0.1nm thick SiN dielectric cap layer was grown to protect and optimize the device surface. The H2 feed rate was 50L / min, the NH3 feed rate was 1L / min, the second SIH4 concentration was 2%, and the feed rate was 0.1sccm / min.

[0066] Finally, the vertical structure epitaxy of GaN HEMT is obtained.

[0067] Example 2

[0068] A method for preparing a depletion-mode GaN HEMT vertical structure chip comprises the following steps:

[0069] 1. Cleaning: Soak in a 90°C 511 strong oxidizing solution tank in a cleaning machine for 10 minutes, then transfer to a 60°C IPA solution tank and soak for 10 minutes to remove the residual solution on the surface. Finally, transfer to a pure water tank at room temperature for 10 minutes.

[0070] 2. After the film source is taken out from the pure water tank, it is transferred to the spin dryer. The spin dryer needs to be purged with N2 at all times and the temperature is controlled at 60°C. First, rinse the film with pure water with a water resistance of more than 8. The speed of the spin dryer changes from 500rpm for 5min, 2000rpm for 10min, 1000rpm for 5min, and finally to 0rpm.

[0071] 3. Positioning preparation: Use photolithography and evaporation processes to prepare marks to achieve the purpose of positioning. First, use a negative photoresist of about 1μm and evenly apply it on the surface. Use a photolithography machine to expose the pattern, use 100℃ baking, and use a positive photoresist developer to remove excess photoresist. Use an ion source to bombard the surface of the source for 2 minutes before metal evaporation. CrTiNi is used for evaporation metal. After evaporation, use a stripper to strip. The stripper is first soaked in the degumming tank for 10 minutes, and finally rinsed with pure water at high pressure. The rinsing process is added with 2 minutes of rotation at 1000rpm.

[0072] 4. Source hole: Use photolithography and etching process to make the hole. Photolithography uses 3μm positive photoresist, and after exposure and development, a layer of pattern is made as a mask before etching. Etching uses ICP etcher to etch the medium first with F-base, and then etch GaN with Cl-base.

[0073] 5. Electronic isolation: Use photolithography and ion implantation for electronic isolation. Photolithography uses a 3μm positive photoresist, which is exposed and developed to make a layer of pattern as a mask before ion implantation. Ion implantation uses boron ions to dope in places where there is no photolithography mask to achieve the purpose of electronic isolation.

[0074] 6. Source preparation: Use photolithography and evaporation to make the source of the device. Use a negative photoresist of about 2μm for liftoff. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlTi, and use a rapid thermal annealing furnace to anneal to make an alloy.

[0075] 7. Gate preparation: Use photolithography and evaporation to make the gate of the device. Use a negative photoresist of about 2μm for lift off. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlNi.

[0076] 8. Field plate preparation: First, use plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition) to passivate a layer of SiO2 film, and then etch the conductive channels of the source and gate after photolithography. Use a negative photoresist of about 2μm for lift off. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlNi to complete the production of the field plate.

[0077] 9. Deep etching: Use photolithography and etching to do deep etching. Use a photoresist of about 8μm as a mask. After exposure and development, make a deep hole at a specific location. Then use an etching machine with Cl - The substrate is deeply etched to a depth of about 3-5 μm.

[0078] 10. Drain preparation: Use photolithography, etching and evaporation to make the drain of the device. Use a positive photoresist of about 2μm as a mask, and use an etcher to etch out the drain channel at a specific location. Use a negative photoresist of about 2μm for photolithography to do peeling. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlTi on the drain channel, and use RTA annealing to make an alloy.

[0079] 11. Bonding metal preparation: Use photolithography and evaporation to make the required bonding metal. Use negative photoresist of about 8μm for peeling in photolithography. Develop the pattern through exposure. Use metal evaporator to evaporate TiAlNi. Use bonding machine, align with infrared laser before bonding, align the bonding metal and deep etched hole, and use vacuum to make AB two pieces bonded.

[0080] The method for preparing the vertical structure epitaxy of GaN HEMT comprises the following steps:

[0081] Substrate preparation: A 500μm GaN substrate was selected as the growth basis.

[0082] Substrate treatment: The GaN substrate is pretreated at a temperature of 1050°C. At the same time, N2, H2, and NH3 are introduced at a rate of 40L / min, 100L / min, and 50L / min, in preparation for subsequent epitaxial growth. High-temperature pretreatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the flow rate of the gas, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0083] Drift region growth: In the temperature range of 1050℃ and the growth pressure of 200torr, by precisely controlling the flow of TMGA, N2, H2, NH3 and the first SIH4, a drift region with a thickness of 7μm is grown. This layer is crucial to the performance of the device. Among them, the flow rate of TMGA is 400sccm / min, the flow rate of N2 is 10L / min, the flow rate of H2 is 90L / min, the flow rate of NH3 is 45L / min, and the concentration of the first SIH4 is 200ppm, and the flow rate is 5sccm / min.

[0084] Insertion layer growth: Subsequently, at a temperature of 900°C and a growth pressure of 75torr, the flow rates of TMAL, N2, H2, and NH3 were adjusted, especially reducing the flow rate of N2 to almost zero, to grow an extremely thin insertion layer with a thickness of 0.6nm to optimize device performance. Among them, the TMAL feed rate was 200sccm / min, the N2 feed rate was 10L / min, the H2 feed rate was 100L / min, and the NH3 feed rate was 5L / min.

[0085] Barrier layer growth: Then, at a temperature range of 1000°C and a growth pressure of 100 torr, a barrier layer with a thickness of 20 nm was grown by adjusting the flow rates of TMGA, TMAL, N2, H2, and NH3 gases. This layer plays a key role in controlling current transmission. Among them, the introduction rate of TMGA is 80 sccm / min, the introduction rate of TMAL is 300 sccm / min, the introduction rate of N2 is 50 L / min, the introduction rate of H2 is 100 L / min, and the introduction rate of NH3 is 50 L / min.

[0086] Growth of SiN dielectric cap layer: Finally, at a temperature of 800°C and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing a second SIH4 gas, a 2nm thick SiN dielectric cap layer was grown to protect and optimize the device surface. The N2 feed rate was 50L / min, the H2 feed rate was 100L / min, the NH3 feed rate was 50L / min, the second SIH4 concentration was 2%, and the feed rate was 40sccm / min.

[0087] Finally, the vertical structure epitaxy of GaN HEMT is obtained.

[0088] Example 3

[0089] A method for preparing a depletion-mode GaN HEMT vertical structure chip comprises the following steps:

[0090] 1. Cleaning: Soak in a 90°C 511 strong oxidizing solution tank in a cleaning machine for 10 minutes, then transfer to a 60°C IPA solution tank and soak for 10 minutes to remove the residual solution on the surface. Finally, transfer to a pure water tank at room temperature for 10 minutes.

[0091] 2. After the film source is taken out from the pure water tank, it is transferred to the spin dryer. The spin dryer needs to be purged with N2 at all times and the temperature is controlled at 60°C. First, rinse the film with pure water with a water resistance of more than 8. The speed of the spin dryer changes from 500rpm for 5min, 2000rpm for 10min, 1000rpm for 5min, and finally to 0rpm.

[0092] 3. Positioning preparation: Use photolithography and evaporation processes to prepare marks to achieve the purpose of positioning. First, use a negative photoresist of about 1μm and evenly apply it on the surface. Use a photolithography machine to expose the pattern, use 100℃ baking, and use a positive photoresist developer to remove excess photoresist. Use an ion source to bombard the surface of the source for 2 minutes before metal evaporation. CrTiNi is used for evaporation metal. After evaporation, use a stripper to strip. The stripper is first soaked in the degumming tank for 10 minutes, and finally rinsed with pure water at high pressure. The rinsing process is added with 2 minutes of rotation at 1000rpm.

[0093] 4. Source hole: Use photolithography and etching process to make the hole. Photolithography uses 3μm positive photoresist, and after exposure and development, a layer of pattern is made as a mask before etching. Etching uses ICP etcher to etch the medium first with F-base, and then etch GaN with Cl-base.

[0094] 5. Electronic isolation: Use photolithography and ion implantation for electronic isolation. Photolithography uses a 3μm positive photoresist, which is exposed and developed to make a layer of pattern as a mask before ion implantation. Ion implantation uses boron ions to dope in places where there is no photolithography mask to achieve the purpose of electronic isolation.

[0095] 6. Source preparation: Use photolithography and evaporation to make the source of the device. Use a negative photoresist of about 2μm for liftoff. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlTi, and use a rapid thermal annealing furnace to anneal to make an alloy.

[0096] 7. Gate preparation: Use photolithography and evaporation to make the gate of the device. Use a negative photoresist of about 2μm for lift off. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlNi.

[0097] 8. Field plate preparation: First, use plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition) to passivate a layer of SiO2 film, and then etch the conductive channels of the source and gate after photolithography. Use a negative photoresist of about 2μm for lift off. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlNi to complete the production of the field plate.

[0098] 9. Deep etching: Use photolithography and etching to do deep etching. Use a photoresist of about 8μm as a mask. After exposure and development, make a deep hole at a specific location. Then use an etching machine with Cl - The substrate is deeply etched to a depth of about 3-5 μm.

[0099] 10. Drain preparation: Use photolithography, etching and evaporation to make the drain of the device. Use a positive photoresist of about 2μm as a mask, and use an etcher to etch out the drain channel at a specific location. Use a negative photoresist of about 2μm for photolithography to do peeling. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlTi on the drain channel, and use RTA annealing to make an alloy.

[0100] 11. Bonding metal preparation: Use photolithography and evaporation to make the required bonding metal. Use negative photoresist of about 8μm for peeling in photolithography. Develop the pattern through exposure. Use metal evaporator to evaporate TiAlNi. Use bonding machine, align with infrared laser before bonding, align the bonding metal and deep etched hole, and use vacuum to make AB two pieces bonded.

[0101] The method for preparing the vertical structure epitaxy of GaN HEMT comprises the following steps:

[0102] Substrate preparation: A 800μm GaN substrate was selected as the growth basis.

[0103] Substrate treatment: The GaN substrate is pretreated at a temperature of 1100°C. At the same time, N2, H2, and NH3 are introduced at a rate of 80L / min, 120L / min, and 70L / min, respectively, to prepare for subsequent epitaxial growth. High-temperature pretreatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the flow rate of the gas, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0104] Drift region growth: Under a temperature range of 1100°C and a growth pressure of 200torr, a drift region with a thickness of 20μm is grown by precisely controlling the flow rates of TMGA, N2, H2, NH3 and the first SIH4. This layer is critical to device performance. Among them, the flow rate of TMGA is 600sccm / min, the flow rate of N2 is 50L / min, the flow rate of H2 is 150L / min, the flow rate of NH3 is 80L / min, and the concentration of the first SIH4 is 200ppm, and the flow rate is 100sccm / min.

[0105] Insertion layer growth: Subsequently, at a temperature of 1000°C and a growth pressure of 75torr, the flow rates of TMAL, N2, H2, and NH3 were adjusted, especially reducing the flow rate of N2 to almost zero, to grow an extremely thin insertion layer with a thickness of 0.8nm to optimize device performance. Among them, the TMAL feed rate was 400sccm / min, the N2 feed rate was 50L / min, the H2 feed rate was 190L / min, and the NH3 feed rate was 50L / min.

[0106] Barrier layer growth: Then, at a temperature range of 1020°C and a growth pressure of 100 torr, by adjusting the flow rates of TMGA, TMAL, N2, H2, and NH3 gases, a barrier layer with a thickness of 22nm was grown, which plays a key role in controlling current transmission. Among them, the introduction rate of TMGA is 200sccm / min, the introduction rate of TMAL is 400sccm / min, the introduction rate of N2 is 64L / min, the introduction rate of H2 is 120L / min, and the introduction rate of NH3 is 70L / min.

[0107] Growth of SiN dielectric cap layer: Finally, at a temperature of 1000°C and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing a second SIH4 gas, a 50nm thick SiN dielectric cap layer was grown to protect and optimize the device surface. The N2 feed rate was 64L / min, the H2 feed rate was 120L / min, the NH3 feed rate was 70L / min, the concentration of the second SIH4 was 2%, and the feed rate was 100sccm / min.

[0108] Finally, the vertical structure epitaxy of GaN HEMT is obtained.

[0109] Example 4

[0110] A method for preparing a depletion-mode GaN HEMT vertical structure chip comprises the following steps:

[0111] 1. Cleaning: Soak in a 90°C 511 strong oxidizing solution tank in a cleaning machine for 10 minutes, then transfer to a 60°C IPA solution tank and soak for 10 minutes to remove the residual solution on the surface. Finally, transfer to a pure water tank at room temperature for 10 minutes.

[0112] 2. After the film source is taken out from the pure water tank, it is transferred to the spin dryer. The spin dryer needs to be purged with N2 at all times and the temperature is controlled at 60°C. First, rinse the film with pure water with a water resistance of more than 8. The speed of the spin dryer changes from 500rpm for 5min, 2000rpm for 10min, 1000rpm for 5min, and finally to 0rpm.

[0113] 3. Positioning preparation: Use photolithography and evaporation processes to prepare marks to achieve the purpose of positioning. First, use a negative photoresist of about 1μm and evenly apply it on the surface. Use a photolithography machine to expose the pattern, use 100℃ baking, and use a positive photoresist developer to remove excess photoresist. Use an ion source to bombard the surface of the source for 2 minutes before metal evaporation. CrTiNi is used for evaporation metal. After evaporation, use a stripper to strip. The stripper is first soaked in the degumming tank for 10 minutes, and finally rinsed with pure water at high pressure. The rinsing process is added with 2 minutes of rotation at 1000rpm.

[0114] 4. Source hole: Use photolithography and etching process to make the hole. Photolithography uses 3μm positive photoresist, and after exposure and development, a layer of pattern is made as a mask before etching. Etching uses ICP etcher to etch the medium first with F-base, and then etch GaN with Cl-base.

[0115] 5. Electronic isolation: Use photolithography and ion implantation for electronic isolation. Photolithography uses a 3μm positive photoresist, which is exposed and developed to make a layer of pattern as a mask before ion implantation. Ion implantation uses boron ions to dope in places where there is no photolithography mask to achieve the purpose of electronic isolation.

[0116] 6. Source preparation: Use photolithography and evaporation to make the source of the device. Use a negative photoresist of about 2μm for liftoff. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlTi, and use a rapid thermal annealing furnace to anneal to make an alloy.

[0117] 7. Gate preparation: Use photolithography and evaporation to make the gate of the device. Use a negative photoresist of about 2μm for lift off. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlNi.

[0118] 8. Field plate preparation: First, use plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition) to passivate a layer of SiO2 film, and then etch the conductive channels of the source and gate after photolithography. Use a negative photoresist of about 2μm for lift off. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlNi to complete the production of the field plate.

[0119] 9. Deep etching: Use photolithography and etching to do deep etching. Use a photoresist of about 8μm as a mask. After exposure and development, make a deep hole at a specific location. Then use an etching machine with Cl - The substrate is deeply etched to a depth of about 3-5 μm.

[0120] 10. Drain preparation: Use photolithography, etching and evaporation to make the drain of the device. Use a positive photoresist of about 2μm as a mask, and use an etcher to etch out the drain channel at a specific location. Use a negative photoresist of about 2μm for photolithography to do peeling. Develop the pattern through exposure. Use a metal evaporator to evaporate TiAlTi on the drain channel, and use RTA annealing to make an alloy.

[0121] 11. Bonding metal preparation: Use photolithography and evaporation to make the required bonding metal. Use negative photoresist of about 8μm for peeling in photolithography. Develop the pattern through exposure. Use metal evaporator to evaporate TiAlNi. Use bonding machine, align with infrared laser before bonding, align the bonding metal and deep etched hole, and use vacuum to make AB two pieces bonded.

[0122] The method for preparing the vertical structure epitaxy of GaN HEMT comprises the following steps:

[0123] Substrate preparation: A 1000μm GaN substrate is selected as the growth basis.

[0124] Substrate treatment: The GaN substrate is pretreated at a temperature of 1150°C. At the same time, N2, H2, and NH3 are introduced at a rate of 100L / min, 200L / min, and 100L / min, respectively, to prepare for subsequent epitaxial growth. High-temperature pretreatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the flow rate of the gas, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0125] Drift region growth: Under a temperature range of 1150°C and a growth pressure of 200torr, a drift region with a thickness of 50μm is grown by precisely controlling the flow rates of TMGA, N2, H2, NH3 and the first SIH4. This layer is critical to device performance. Among them, the flow rate of TMGA is 1000sccm / min, the flow rate of N2 is 100L / min, the flow rate of H2 is 200L / min, the flow rate of NH3 is 100L / min, and the concentration of the first SIH4 is 200ppm, and the flow rate is 500sccm / min.

[0126] Insertion layer growth: Subsequently, at a temperature of 1100°C and a growth pressure of 75torr, the flow rates of TMAL, N2, H2, and NH3 were adjusted, especially reducing the flow rate of N2 to almost zero, to grow an extremely thin insertion layer with a thickness of 1nm to optimize device performance. Among them, the introduction rate of TMAL was 500sccm / min, the introduction rate of N2 was 100L / min, the introduction rate of H2 was 200L / min, and the introduction rate of NH3 was 100L / min.

[0127] Barrier layer growth: Then, at a temperature range of 1100°C and a growth pressure of 100 torr, by adjusting the flow rates of TMGA, TMAL, N2, H2, and NH3 gases, a barrier layer with a thickness of 35 nm was grown, which plays a key role in controlling current transmission. Among them, the introduction rate of TMGA is 500 sccm / min, the introduction rate of TMAL is 500 sccm / min, the introduction rate of N2 is 100 L / min, the introduction rate of H2 is 200 L / min, and the introduction rate of NH3 is 100 L / min.

[0128] Growth of SiN dielectric cap layer: Finally, at a temperature of 1100°C and a growth pressure of 200 torr, by adjusting the flow of N2, H2, and NH3 gases and introducing a second SIH4 gas, a 100nm thick SiN dielectric cap layer was grown to protect and optimize the device surface. The N2 feed rate was 100L / min, the H2 feed rate was 200L / min, the NH3 feed rate was 100L / min, the second SIH4 concentration was 2%, and the feed rate was 500sccm / min.

[0129] Finally, the vertical structure epitaxy of GaN HEMT is obtained.

[0130] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A method for preparing a depletion-mode GaN HEMT vertical structure chip, characterized in that: The following steps are involved: 1) After the GaN substrate is processed, the GaN drift region, AlN insertion layer, and Al X Ga (1-X) N barrier layer and dielectric cap layer; 2) Form a chip isolation area on the top by ion implantation to achieve electrical isolation of the active area; 3) Photolithography a source window area on the top and remove the dielectric cap layer in the window area; 4) Photolithography is performed on the top to form the electrode contact area of ​​the source electrode, electrode metal is grown to form a source electrode, and the source electrode is subjected to rapid thermal annealing to form an ohmic contact in the source area; 5) Photolithography the gate electrode contact area on the top, grow electrode metal, and form a gate electrode; 6) growing a passivation layer on top; 7) Photolithography is performed to form a drain electrode contact region at the bottom, electrode metal is grown to form a drain electrode, and rapid thermal annealing is performed on the drain electrode to form an ohmic contact in the drain region; 8) Grow a passivation layer at the bottom and photolithography the drain electrode lead-out area; 9) Photolithography is performed on the top to form the gate electrode and source electrode lead-out regions, thereby obtaining a depletion-mode GaN HEMT vertical structure chip.

2. The method for preparing a depletion-mode GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the Al X Ga (1-X) In the N barrier layer, the molar percentage of the Al component X is 15%-50%; In step 2), the ion implanted element includes at least one of F, Ar, B and N; the depth of the ion implantation is 0.1 to 20 μm; In step 3), the dielectric cap layer in the window area is removed by inductively coupled plasma etching.

3. The method for preparing a depletion-mode GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 4), a source electrode is formed by electron beam evaporation or magnetron sputtering growth; the source electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN and AlSi; In step 5), a gate electrode is formed by electron beam evaporation or magnetron sputtering growth; the gate electrode is a Ti / Al / Ti electrode metal; In step 6), the passivation layer is formed by growing at least one of SiN, SiO2 and Al2O3 using plasma enhanced chemical vapor deposition.

4. The method for preparing a depletion-mode GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 7), a drain electrode is grown by electron beam evaporation or magnetron sputtering; the drain electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN and AlSi; In step 8), the passivation layer is formed by growing at least one of SiN, SiO2 and Al2O3 using plasma enhanced chemical vapor deposition.

5. The method for preparing a depletion-mode GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the GaN substrate processing conditions include: pre-treating the GaN substrate at 1000-1150° C., and at the same time, introducing N2 at a rate of 0-100 L / min, H2 at a rate of 50-200 L / min, and NH3 at a rate of 1-100 L / min.

6. The method for preparing a depletion-mode GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the conditions for the growth of the GaN drift region include: at 1000-1150°C and a growth pressure of 200torr, by controlling the flow rates of trimethylgallium, N2, H2, NH3 and the first monosilane, a GaN drift region with a thickness of 0.5-50 μm is grown, the growth temperature is 1000-1150°C, and the growth speed is 800-1200rpm; wherein the introduction rate of TMGA is 200-1000sccm / min, the introduction rate of N2 is 0-100L / min, the introduction rate of H2 is 50-200L / min, the introduction rate of NH3 is 1-100L / min, the concentration of the first monosilane is 200ppm, and the introduction rate is 0-500sccm / min.

7. The method for preparing a depletion-mode GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), a carrier blocking layer region is defined on the grown GaN epitaxial drift region by photolithography, and ion implantation is performed on the carrier blocking layer region. After the ion implantation is completed, secondary epitaxy is performed; the growth temperature of the secondary epitaxy is 1000-1150°C, the rotation speed is 800-1200rpm, the growth pressure is 200torr, and TMGa, N2, H2 and NH3 are introduced at the same time to grow undoped GaN with a thickness controlled at 150-400nm, wherein the introduction rate of TMGa is 200-1000sccm / min, the introduction rate of N2 is 0-100L / min, the introduction rate of H2 is 0-200L / min, and the introduction rate of NH3 is 0-100L / min.

8. The method for preparing a depletion-mode GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the conditions for growing the AlN insertion layer include: at 800-1100° C. and a growth pressure of 75 torr, trimethylaluminum, H2 and NH3 are introduced simultaneously to grow an extremely thin AlN insertion layer with a thickness controlled at 0-2 nm; wherein the introduction rate of trimethylaluminum is 0-500 sccm / min, the introduction rate of H2 is 50-200 L / min, and the introduction rate of NH3 is 1-100 L / min; In step 1), Al X Ga (1-X) The conditions for the growth of the N barrier layer include: growing an Al layer with a thickness of 15-35 nm by adjusting the flow rates of trimethylgallium, trimethylaluminum, N2, H2, and NH3 at 800-1100°C, 800-1200rpm, and a growth pressure of 100 torr. X Ga (1-X) N barrier layer; wherein the molar percentage of the Al component X is 15%-50%, the introduction rate of trimethylgallium is 0-500sccm / min, the introduction rate of TMAL is 50-500sccm / min, the introduction rate of N2 is 0-100L / min, the introduction rate of H2 is 50-200L / min, and the introduction rate of NH3 is 1-100L / min.

9. The method for preparing a depletion-mode GaN HEMT vertical structure chip according to claim 1, characterized in that: The dielectric cap layer includes a SiN dielectric cap layer. In step 1), the conditions for growing the SiN dielectric cap layer include: growing a SiN dielectric cap layer with a thickness of 0.1-100 nm at 700-1100° C. and a growth pressure of 200 torr by adjusting the flow rates of N2, H2 and NH3 and introducing a second monosilane; wherein the N2 introduction rate is 0-100 L / min, the H2 introduction rate is 50-200 L / min, the NH3 introduction rate is 1-100 L / min, the concentration of the second monosilane is 2%, and the introduction rate is 0-500 sccm / min.

10. A depletion-mode GaN HEMT vertical structure chip manufactured by the manufacturing method according to any one of claims 1 to 9.

Images