Silicon carbide transistor structure and preparation method thereof
By forming a well region on a silicon carbide substrate and forming an inverted first doped region through ion implantation, the problem of limited size of the doped region in the prior art is solved, and a silicon carbide transistor structure with a smaller size and lower on-resistance is achieved.
Patent Information
- Application Number
- CN202510081837.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-17
- Publication Date
- 2025-04-29
AI Technical Summary
The existing silicon carbide transistor structure is affected by the hard mask when forming the first doped region, resulting in limited size of the doped region, thereby increasing the on-resistance.
A well region is formed on a silicon carbide substrate by ion implantation, and the first doped region and the second doped region are formed by ion implantation, and the first doped region is inverted by ion implantation of different concentrations, thereby forming a smaller sized first doped region and a second doped region.
By reducing the size and on-resistance of the first doped region, the on-resistance of the overall silicon carbide transistor is reduced, and the conductive performance of the device is improved.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor device technology, and in particular to a silicon carbide transistor structure and a method for preparing the same. Background Art
[0002] Silicon carbide (SiC) has a wide bandgap, high thermal conductivity, high breakdown voltage and high electron saturation drift rate, and has good prospects in the field of high power, high temperature, high frequency and radiation-resistant electronic power. Compared with silicon MOSFETs of the same power level, the on-resistance and switching loss of silicon carbide planar MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) are greatly reduced, suitable for higher operating frequencies, and greatly improved high temperature stability. Among them, channel mobility is a key parameter of silicon carbide MOSFET device performance. Improving channel mobility can effectively reduce the turn-on voltage and on-resistance, thereby reducing losses under high currents and improving the conductivity of the device. In other words, if you want to improve the channel mobility of silicon carbide MOSFET devices, you need to reduce their on-resistance when they are turned on.
[0003] On-resistance is one of the important parameters to measure the performance of SiC planar MOSFET. In order to achieve high switching efficiency of power devices, the power loss of the device itself should be reduced as much as possible. The smaller the on-resistance of the device, the higher the output power of the device and the lower the power loss of the device at the same rated current. Figure 1 A SiC planar MOSFET device in the prior art is shown. Taking the SiC planar MOSFET device as an example, the overall on-resistance R of the SiC device when it is turned on is introduced. dson .like Figure 1 As shown, the resistance of SiC MOSFET when it is turned on is:
[0004] R dson =R CS +R N+ +R ch +R A +R jfet +R drift +R buffer +R sub +R CD
[0005] Among them, R CS is the source contact resistance, R N+ is the resistance of the first doped region (N-type heavily doped region), R ch is the channel resistance, R A is the resistance of the accumulation layer, R jfetis the JFET (junction field effect transistor) region resistance, R drift is the drift region resistance, R buffer is the buffer layer resistance, R sub is the substrate resistance, R CD is the drain contact resistance.
[0006] In the existing silicon carbide transistor structure preparation process, when forming the first doping region, a mask layer needs to be used to cover the position where the second doping region is subsequently formed, so as to leave a hole in the first doping region. This preparation method limits the size of the first doping region and cannot be further reduced, and the larger size of the first doping region also leads to a larger overall on-resistance of the transistor.
[0007] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0008] In view of the problems in the prior art, the purpose of the present application is to provide a silicon carbide transistor structure and a method for preparing the same, which is not affected by the hard mask when preparing the first doping region and can be designed to be smaller in size, thereby helping to reduce the on-resistance of the transistor structure.
[0009] The present invention provides a method for preparing a silicon carbide transistor structure, comprising:
[0010] providing a silicon carbide substrate;
[0011] forming a well region in the silicon carbide substrate;
[0012] forming a first doped region in the well region;
[0013] Performing ion implantation on the first doping region and the well region to form a second doping region extending from the first doping region to the well region, wherein when forming the second doping region portion located in the well region, ion implantation with a first concentration is adopted, and when forming the second doping region portion located in the first doping region, ion implantation with a second concentration is adopted, and the second concentration is higher than the first concentration;
[0014] A gate structure is formed on the top surface of the silicon carbide substrate.
[0015] In some embodiments, the well region and the second doped region have a first conductivity type, the first doped region has a second conductivity type, and the first conductivity type and the second conductivity type are different.
[0016] In some embodiments, a top surface of the second doping region is flush with a top surface of the first doping region.
[0017] In some embodiments, when a first doped region is formed in the well region, the first doped region is a structure that is continuous in both a first direction and a second direction, the first direction is parallel to the top surface of the silicon carbide substrate, and the second direction is perpendicular to the top surface of the silicon carbide substrate.
[0018] In some embodiments, after ion implantation is performed on the first doping region and the well region to form a second doping region extending from the first doping region to the well region, the second doping region separates the first doping region into two independent parts in the first direction.
[0019] In some embodiments, ion implantation is performed on the first doped region and the well region to form a second doped region extending from the first doped region to the well region, comprising the following steps:
[0020] Using ion implantation of a first concentration, ion doping of a first conductivity type is performed in the well region to form a portion of the second doped region in the well region;
[0021] Ion implantation of a second concentration is used to perform ion doping of a first conductivity type in the first doping region, so that a portion of the first doping region is inverted and a portion of the second doping region in the first doping region is formed.
[0022] In some embodiments, a size of the first doped region in the first direction is smaller than a size of the well region in the first direction, and a size of the first doped region in the second direction is smaller than a size of the well region in the second direction.
[0023] In some embodiments, forming a well region in the silicon carbide substrate comprises the following steps:
[0024] forming a mask layer having a first opening on a top surface of the silicon carbide substrate;
[0025] Ion implantation is performed using the mask layer as a shield to form a well region in the silicon carbide substrate corresponding to the first opening.
[0026] In some embodiments, forming a first doped region in the well region comprises the following steps:
[0027] forming a blocking layer on the sidewall of the first opening of the mask layer;
[0028] Ion implantation is performed under self-alignment of the barrier layer to form a first doped region in the well region.
[0029] The present application also provides a silicon carbide transistor structure, which is obtained by the preparation method, and the structure includes:
[0030] A silicon carbide substrate, wherein a well region is formed in the silicon carbide substrate, and a first doped region is formed in the well region;
[0031] a second doped region extending from the first doped region into the well region;
[0032] A gate structure is formed on the top surface of the silicon carbide substrate.
[0033] The silicon carbide transistor structure and preparation method provided in this application have the following advantages:
[0034] By adopting the preparation method of the silicon carbide transistor structure of the present application, when preparing the first doping region, it is not affected by the hard mask and can be designed to be smaller in size. When forming the part of the second doping region in the first doping region, a higher concentration of ion implantation is used to first invert the first doping region, and then doping is performed to obtain the second doping region. The silicon carbide transistor structure obtained by this method can have a first doping region of smaller size and a smaller on-resistance of the first doping region, thereby reducing the on-resistance of the overall silicon carbide transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0036] Figure 1 It is a schematic diagram of the structure of a silicon carbide MOSFET;
[0037] Figures 2 to 4 It is a schematic diagram of the process of the existing method for preparing silicon carbide MOSFET;
[0038] Figure 5 is a flow chart of a method for preparing a silicon carbide transistor structure according to an embodiment of the present application;
[0039] Figures 6 to 9 is a schematic diagram of a process of preparing a silicon carbide transistor structure according to an embodiment of the present application; wherein, Figure 6 is a schematic diagram of forming a well region in a silicon carbide substrate; Figure 7 is a schematic diagram of forming a first doping region in a well region; Figure 8 is a schematic diagram of forming a second doping region in a first doping region and a well region; Fig. 9 A schematic diagram of forming a gate structure on the top surface of a silicon carbide substrate. DETAILED DESCRIPTION
[0040] The example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present application will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. "Or" and "or" in the specification may both represent "and" or "or". Spatial relationship terms such as "on..." and the like can be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented to be "under..." other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptions used herein are interpreted accordingly.
[0041] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Although "first" or "second" etc. are used in this specification to represent certain features, they are only used to represent the role, and are not used as a limitation on the number and importance of specific features.
[0042] Figures 2 to 4 FIG. 1 is a schematic diagram of the process of preparing an existing silicon carbide MOSFET. Figure 2 As shown, a first mask layer 200' is formed on the top surface of the substrate 100', and ion implantation is performed using the first mask layer 200' as a shield to form a well region 300'. Figure 3 As shown, a retaining wall 400' and a second mask layer 500' are formed on the top surface of the well region 300', and ion implantation is performed to form a first doped region 600'. When forming the first doped region 600', the second mask layer 500' needs to be used to block the position where the second doped region is subsequently formed, so as to leave a hole in the first doped region 600'. Figure 4 As shown, after removing the second mask layer, ion implantation is performed to form the second doping region 700'. This preparation method limits the size of the first doping region 600' and prevents further reduction, and the larger size of the first doping region 600' also leads to a larger overall on-resistance of the transistor.
[0043] In order to solve the technical problems in the prior art, an embodiment of the present application provides a method for preparing a silicon carbide transistor structure, which aims to prepare a first doping region without being affected by a hard mask and can be designed to be smaller in size, thereby facilitating reducing the on-resistance of the transistor structure.
[0044] like Figure 5 As shown, an embodiment of the present application provides a method for preparing a silicon carbide transistor structure, which is used to prepare a silicon carbide planar MOSFET transistor, and the preparation method includes the following steps:
[0045] S100: providing a silicon carbide substrate;
[0046] S200: forming a well region in the silicon carbide substrate;
[0047] In this embodiment, the well region is a well region of the first conductivity type;
[0048] S300: forming a first doped region in the well region;
[0049] In this embodiment, the first doping region and the well region have different conductivity types, the first doping region is a doping region of the second conductivity type, taking the first conductivity type as P type as an example, the well region is a P-type well region (PWL), and the first doping region is an N-type doping region, and for example, is an N-type heavily doped region, but the present application is not limited thereto;
[0050] S400: performing ion implantation on the first doping region and the well region to form a second doping region extending from the first doping region to the well region, wherein when forming the second doping region portion located in the well region, ion implantation with a first concentration is adopted, and when forming the second doping region portion located in the first doping region, ion implantation with a second concentration is adopted, and the second concentration is higher than the first concentration;
[0051] In this embodiment, the second doping region has the same conductivity type as the well region. Therefore, the second doping region has a different conductivity type from the first doping region. Taking the first conductivity type as P type as an example, the second doping region is a P type doping region, such as a P type heavily doped region (PPlus), and the doping concentration of the second doping region is greater than the doping concentration of the well region.
[0052] In this embodiment, the top surface of the second doping region is flush with the top surface of the first doping region;
[0053] S500: forming a gate structure on the top surface of the silicon carbide substrate.
[0054] By adopting the preparation method of the silicon carbide transistor structure of the present application, when preparing the first doping region, it is not affected by the hard mask and can be designed to be smaller in size. When forming the part of the second doping region in the first doping region, a higher concentration of ion implantation is used to first invert the first doping region, and then doping is performed to obtain the second doping region. The silicon carbide transistor structure obtained by this method can have a first doping region of smaller size and a smaller on-resistance of the first doping region, thereby reducing the on-resistance of the overall silicon carbide transistor.
[0055] In this embodiment, the size of the first doped region in the first direction is smaller than the size of the well region in the first direction, and the size of the first doped region in the second direction is smaller than the size of the well region in the second direction. In the step S300, when the first doped region is formed in the well region, the first doped region is a structure that is continuous in both the first direction and the second direction, the first direction is parallel to the top surface of the silicon carbide substrate, and the second direction is perpendicular to the top surface of the silicon carbide substrate. Therefore, when forming the first doped region, there is no need to use the existing second mask layer for shielding, and the first doped region that is continuous in the first direction is directly formed, the size of the first doped region is easier to control, and a first doped region of a smaller size can be prepared.
[0056] In this embodiment, in step S400: after ion implantation is performed on the first doping region and the well region to form a second doping region extending from the first doping region to the well region, the second doping region separates the first doping region into two independent parts in the first direction.
[0057] In this embodiment, the step S400 of performing ion implantation on the first doping region and the well region to form a second doping region extending from the first doping region to the well region includes the following steps:
[0058] Using ion implantation of a first concentration, ion doping of a first conductivity type is performed in the well region to form a portion of the second doped region in the well region; the first concentration may be the same as the existing implantation concentration when forming the second doped region, so that a second doped region of the first conductivity type is formed in the well region, and the specific value of the first concentration may vary according to specific transistor design requirements;
[0059] Ion implantation of the second concentration is used to perform ion doping of the first conductivity type in the first doping region, so that the first doping region is partially inverted, and a portion of the second doping region in the first doping region is formed. The second doping region finally formed includes a portion formed in the well region and a portion formed in the first doping region. The second concentration is higher than the first concentration. During ion implantation, the first doping region of the second conductivity type is first inverted, and then a portion of the second doping region is formed in the first doping region. The specific value of the second concentration can be obtained through simulation experiments. When the simulation experiment tests that the first doping region needs to be partially inverted and the second doping region needs to be formed, and the concentration of the portion of the second doping region in the first doping region is the same as that of the portion of the second doping region in the well region, the second concentration needs to be used, and the second concentration varies with the doping concentration of the first doping region and the doping concentration of the second doping region. When forming the second doping region, ion implantation and diffusion are performed through multiple steps to form a second doping region of the first conductivity type. When ion implantation is performed at a position corresponding to the well region, a lower first concentration is used, and when ion implantation is performed at a position corresponding to the first doping region, a higher second concentration is used. Since the first doping region is located at a shallow position above the well region, this method of forming the second doping region is called shallow concentrated implantation.
[0060] In this embodiment, in step S200, forming a well region in the silicon carbide substrate includes the following steps:
[0061] forming a mask layer having a first opening on a top surface of the silicon carbide substrate;
[0062] Ion implantation is performed with the mask layer as a shield to form a well region in the silicon carbide substrate corresponding to the first opening. The well region is of the first conductivity type and its position corresponds to the first opening of the mask layer.
[0063] In this embodiment, in step S300, forming a first doped region in the well region includes the following steps:
[0064] forming a blocking layer on the sidewall of the first opening of the mask layer;
[0065] Ion implantation is performed under the self-alignment of the barrier layer to form a first doped region in the well region. The first doped region is of the second conductivity type and its position corresponds to the position of the first opening not blocked by the barrier layer.
[0066] Combine the following Figures 6 to 9 The implementation process of the method for preparing the silicon carbide transistor structure in one embodiment is specifically introduced. Figures 6 to 9 The preparation process and the dimensional relationship of each layer are only examples and are not intended to limit the scope of protection of this application.
[0067] like Figure 6As shown, corresponding to step S100, a silicon carbide substrate 100 is provided. Corresponding to step S200, a mask layer having a first opening is formed on the top surface of the silicon carbide substrate 100, and ion implantation is performed using the mask layer as a shield to form a well region 300 of a first conductivity type. In this embodiment, the first conductivity type is P type. Therefore, the well region 300 is a P-type well region (PWL). Figure 6 As shown, the top surface of the silicon carbide substrate 100 is the upper surface of the silicon carbide substrate 100 .
[0068] like Figure 7 As shown, corresponding to step S300, a barrier layer 400 is formed on the sidewall of the first opening of the mask layer, and ion implantation (IMP) is performed to form a second conductivity type first doping region 500. In this embodiment, the second conductivity type is N type, and the first doping region 500 is an N type heavily doped region (NPS).
[0069] like Figure 8 As shown, corresponding to step S400, a second doping region 600 is formed by ion implantation at a position where the second doping region needs to be formed. The second doping region 600 includes a portion formed in the first doping region 500 and a portion formed in the well region 300. In the process of forming the second doping region 600 by ion implantation, it is implemented in a plurality of ion implantation and diffusion steps. In the step corresponding to the position of the well region 300, ion implantation of a first concentration is adopted, and in the step corresponding to the position of the upper first doping region 500, ion implantation of a second concentration is adopted, and finally a second doping region 600 with consistent upper and lower concentrations is formed. The second concentration is greater than the first concentration. Since the first doping region 500 is located at a relatively shallow position of the well region 300, the method of forming the second doping region 600 by ion implantation can also be called shallow-concentrated implantation. The first doping region 500 is partially inverted by shallow-concentrated implantation and finally forms the second doping region 600.
[0070] like Fig. 9 As shown, corresponding to step S500 , a gate structure 700 is formed on the top surface of the silicon carbide substrate 100 .
[0071] By adopting the method for preparing the silicon carbide transistor structure, no additional hard mask (the second mask layer in the prior art) is required when forming the first doping region 500, so that the size of the first doping region 500 can be made smaller, thereby reducing the on-resistance of the first doping region 500 ( Figure 1 R N+), thereby achieving the purpose of reducing the on-resistance of the overall transistor device. For example, for a transistor product with a 5.2μm pitch specification (the spacing between repeating units in the transistor is 5.2 microns), when the existing preparation method is used, the size of the second doping region is 1.0μm, and the size of the first doping region is 2.8μm. After using the preparation method of the present application, while keeping the size of the second doping region at 1.0μm unchanged, the size of the first doping region can be reduced to 2.4μm, reducing the on-resistance of the first doping region by 0.2μm (22%) on one side.
[0072] like Fig. 9 As shown, the embodiment of the present application also provides a silicon carbide transistor structure, which is obtained by using the preparation method, and the structure includes:
[0073] A silicon carbide substrate 100, wherein a well region 300 is formed in the silicon carbide substrate, wherein a first doping region 500 is formed in the well region; in this embodiment, the well region 300 is of a first conductivity type, such as a P type, and the first doping region 500 is of a second conductivity type, such as an N type heavily doped region;
[0074] The second doping region 600 extends from the first doping region 500 to the well region 300; in the first direction ( Fig. 9 In the left-right direction), the second doping region 600 separates the first doping region 500 into two independent parts, and the top surface of the second doping region 600 is flush with the top surface of the first doping region 500; in this embodiment, the second doping region 600 is of the first conductivity type, such as P type;
[0075] The gate structure 700 is formed on the top surface of the silicon carbide substrate 100. Fig. 9 As shown, the top surface of the silicon carbide substrate 100 is the upper surface of the silicon carbide substrate 100 .
[0076] In summary, the silicon carbide transistor structure and the preparation method thereof provided in the present application have the following advantages:
[0077] By adopting the preparation method of the silicon carbide transistor structure of the present application, when preparing the first doping region, it is not affected by the hard mask and can be designed to be smaller in size. When forming the part of the second doping region in the first doping region, a higher concentration of ion implantation is used to first invert the first doping region, and then doping is performed to obtain the second doping region. The silicon carbide transistor structure obtained by this method can have a first doping region of smaller size and a smaller on-resistance of the first doping region, thereby reducing the on-resistance of the overall silicon carbide transistor.
[0078] The above content is a further detailed description of the present application in combination with specific preferred implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.
Claims
1. A method for preparing a silicon carbide transistor structure, characterized in that: include: providing a silicon carbide substrate; forming a well region in the silicon carbide substrate; forming a first doped region in the well region; Performing ion implantation on the first doping region and the well region to form a second doping region extending from the first doping region to the well region, wherein when forming the second doping region portion located in the well region, ion implantation with a first concentration is adopted, and when forming the second doping region portion located in the first doping region, ion implantation with a second concentration is adopted, and the second concentration is higher than the first concentration; A gate structure is formed on the top surface of the silicon carbide substrate.
2. The method for preparing a silicon carbide transistor structure according to claim 1, characterized in that: The well region and the second doping region have a first conductivity type, the first doping region has a second conductivity type, and the first conductivity type and the second conductivity type are different.
3. The method for preparing a silicon carbide transistor structure according to claim 1, characterized in that: A top surface of the second doping region is flush with a top surface of the first doping region.
4. The method for preparing a silicon carbide transistor structure according to claim 1, characterized in that: When a first doped region is formed in the well region, the first doped region is a continuous structure in both a first direction and a second direction, the first direction is parallel to the top surface of the silicon carbide substrate, and the second direction is perpendicular to the top surface of the silicon carbide substrate.
5. The method for preparing a silicon carbide transistor structure according to claim 4, characterized in that: After ion implantation is performed on the first doping region and the well region to form a second doping region extending from the first doping region to the well region, the second doping region separates the first doping region into two independent parts in the first direction.
6. The method for preparing a silicon carbide transistor structure according to claim 2, characterized in that: Performing ion implantation on the first doping region and the well region to form a second doping region extending from the first doping region to the well region comprises the following steps: Using ion implantation of a first concentration, ion doping of a first conductivity type is performed in the well region to form a portion of the second doped region in the well region; Ion implantation of a second concentration is used to perform ion doping of a first conductivity type in the first doping region, so that a portion of the first doping region is inverted and a portion of the second doping region in the first doping region is formed.
7. The method for preparing a silicon carbide transistor structure according to claim 4, characterized in that: The size of the first doping region in the first direction is smaller than the size of the well region in the first direction, and the size of the first doping region in the second direction is smaller than the size of the well region in the second direction.
8. The method for preparing a silicon carbide transistor structure according to claim 1, characterized in that: Forming a well region in the silicon carbide substrate comprises the following steps: forming a mask layer having a first opening on a top surface of the silicon carbide substrate; Ion implantation is performed using the mask layer as a shield to form a well region in the silicon carbide substrate corresponding to the first opening.
9. The method for preparing a silicon carbide transistor structure according to claim 8, characterized in that: Forming a first doped region in the well region comprises the following steps: forming a blocking layer on the sidewall of the first opening of the mask layer; Ion implantation is performed under self-alignment of the barrier layer to form a first doped region in the well region.
10. A silicon carbide transistor structure, characterized in that: The structure is obtained by the preparation method according to any one of claims 1 to 9, comprising: A silicon carbide substrate, wherein a well region is formed in the silicon carbide substrate, and a first doped region is formed in the well region; a second doped region extending from the first doped region into the well region; A gate structure is formed on the top surface of the silicon carbide substrate.