High-thermal-conductivity AlGaN / InxAl1-xSb high-electron-mobility transistor and preparation method thereof

Abstract

The invention relates to a high-thermal-conductivity AlGaN / InxAl1-xSb high-electron-mobility transistor and a preparation method thereof. The transistor comprises a high-thermal-conductivity substrate layer, a buffer layer, an InxAl1-xSb channel layer, an AlGaN barrier layer, a cap layer, a source electrode, a drain electrode, a passivation layer and a grid electrode. Wherein the value range of x is 0.8 to 1; and the In < x > Al < 1-x > Sb channel layer and the AlGaN barrier layer form an AlGaN / In < x > Al < 1-x > Sb heterojunction. The AlGaN / InxAl1-xSb heterojunction has larger forbidden bandwidth difference, 2DEG with higher concentration can be generated in a channel, the heat dissipation performance of the device is improved through the high-heat-conductivity substrate layer, and the switching characteristic of the device and the performance and stability of the device in an application scene under high temperature and high power are improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and specifically relates to an AlGaN / In x Al 1-x Sb high electron mobility transistor and preparation method thereof. Background Art

[0002] Traditional high electron mobility transistors (HEMTs) are mainly made of AlGaN / GaN heterojunctions, and most of these HEMT devices are epitaxially grown on sapphire substrates.

[0003] However, the concentration of two-dimensional electron gas in the channel of traditional AlGaN / GaN high electron mobility transistors is not high, which affects the switching characteristics of the device and the stability of the device under high temperature and high power. At the same time, due to the high bias voltage working state of HEMT devices, excessive power dissipation will cause the temperature of the device to rise, and the traditional low thermal conductivity substrate and heat dissipation path have limited heat dissipation capacity, which hinders the heat from diffusing to the surrounding environment, thereby enhancing phonon scattering and reducing the carrier mobility in the potential well, which greatly limits the application scenarios of AlGaN / GaN HEMT. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides an AlGaN / In x Al 1-x Sb high electron mobility transistor and its preparation method. The technical problem to be solved by the present invention is achieved by the following technical solution:

[0005] The first aspect of the present invention provides an AlGaN / In x Al 1-x Sb high electron mobility transistor, comprising: a high thermal conductivity substrate layer, a buffer layer, an In x Al 1-x Sb channel layer, AlGaN barrier layer, cap layer, source, drain, passivation layer and gate;

[0006] The high thermal conductivity substrate layer, the buffer layer, the In x Al 1-x The Sb channel layer, the AlGaN barrier layer and the cap layer are arranged in sequence from bottom to top; wherein the value range of x is 0.8 to 1; the In x Al 1-x The Sb channel layer and the AlGaN barrier layer form an AlGaN / In x Al 1-x Sb heterojunction;

[0007] The source electrode and the drain electrode are arranged on the upper surface of the cap layer at intervals;

[0008] The passivation layer covers the surfaces of the cap layer, the source electrode and the drain electrode;

[0009] The gate is disposed between the source and the drain, and penetrates from the upper surface of the passivation layer to the upper surface of the cap layer.

[0010] In one achievable manner, the number of the source electrode and the number of the gate electrode are both two;

[0011] The drain electrode is arranged between the two source electrodes and is spaced apart from the two source electrodes;

[0012] The two gates are arranged at intervals between the drain and the two sources, and there are intervals between the gate and the source and the drain.

[0013] In one practicable manner, interconnecting metal is also included;

[0014] The interconnection metal is arranged on the upper surfaces of the source electrode and the drain electrode and penetrates the passivation layer.

[0015] In one achievable manner, the material of the high thermal conductivity substrate layer includes diamond or SiC.

[0016] In one achievable manner, the buffer layer is made of GaN and has a thickness of 0.5 to 5 μm.

[0017] In one achievable manner, x=1, the In x Al 1-x The material of the Sb channel layer is InSb.

[0018] In one achievable manner, the In x Al 1-x The thickness of the Sb channel layer is 1 to 5 nm.

[0019] In a feasible manner, the thickness of the AlGaN barrier layer is 10-30 nm, and the content of Al component in the AlGaN barrier layer is 10%-30%.

[0020] In one achievable manner, the cap layer is made of InSb and has a thickness of 2 to 3 nm;

[0021] The material of the passivation layer is SiN.

[0022] A second aspect of the present invention provides an AlGaN / In x Al 1-xA method for preparing a Sb high electron mobility transistor, which is used to prepare the high thermal conductivity AlGaN / In x Al 1-x Sb high electron mobility transistor, comprising the following steps:

[0023] S1: On the surface of the high thermal conductivity substrate layer, the buffer layer, In x Al 1-x Sb channel layer, AlGaN barrier layer and cap layer;

[0024] S2: preparing a source electrode and a drain electrode spaced apart on the surface of the cap layer;

[0025] S3: preparing a passivation layer on the surfaces of the cap layer, the source electrode and the drain electrode;

[0026] S4: etching the passivation layer to form a gate groove located between the source electrode and the drain electrode and extending from the upper surface of the passivation layer to the upper surface of the cap layer; and preparing a gate in the gate groove.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention provides a high thermal conductivity AlGaN / In x Al 1-x Sb high electron mobility transistor, through In x Al 1-x Sb channel layer and AlGaN barrier layer form AlGaN / In x Al 1-x Sb heterojunction to replace the traditional AlGaN / GaN heterojunction, AlGaN / In x Al 1-x The Sb heterojunction has a larger bandgap width difference, which can produce a higher concentration of 2DEG in the channel, and improve the heat dissipation performance of the device through the high thermal conductivity substrate layer, effectively alleviating the self-heating effect of the device under high bias voltage working state, thereby improving the switching characteristics of the device and the performance and stability in high temperature and high power application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 An AlGaN / In with high thermal conductivity provided by the embodiment of the present invention x Al 1-x Schematic diagram of the structure of Sb high electron mobility transistor;

[0030] Figure 2a to Figure 2i An AlGaN / In with high thermal conductivity provided by the embodiment of the present invention x Al 1-xSchematic diagram of the steps of the method for preparing a Sb high electron mobility transistor.

[0031] Reference numerals:

[0032] 1: High thermal conductivity substrate layer; 2: Buffer layer; 3: In x Al 1-x Sb channel layer; 4: AlGaN barrier layer; 5: cap layer; 6: source; 7: drain; 8: passivation layer; 9: gate; 10: interconnect metal. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0034] Embodiment 1

[0035] See also Figure 1 , Figure 1 An AlGaN / In with high thermal conductivity provided by the embodiment of the present invention x Al 1-x Schematic diagram of the structure of the Sb high electron mobility transistor.

[0036] This embodiment provides an AlGaN / In high thermal conductivity x Al 1-x Sb high electron mobility transistor, comprising: a high thermal conductivity substrate layer 1, a buffer layer 2, an In x Al 1-x Sb channel layer 3, AlGaN barrier layer 4, cap layer 5, source 6, drain 7, passivation layer 8 and gate 9. High thermal conductivity substrate layer 1, buffer layer 2, In x Al 1-x The Sb channel layer 3, the AlGaN barrier layer 4 and the cap layer 5 are arranged in sequence from bottom to top. x Al 1-x The content of In in Sb, x ranges from 0.8 to 1. x Al 1-x Sb channel layer 3 and AlGaN barrier layer 4 form AlGaN / In x Al 1-x The source electrode 6 and the drain electrode 7 are spaced apart on the upper surface of the cap layer 5. The passivation layer 8 covers the surfaces of the cap layer 5, the source electrode 6 and the drain electrode 7. The gate electrode 9 is arranged between the source electrode 6 and the drain electrode 7, and penetrates from the upper surface of the passivation layer 8 to the upper surface of the cap layer 5.

[0037] Specifically, in x Al 1-xAs a third-generation semiconductor material, Sb has high electron mobility and electron saturation drift velocity, and can form a variety of quantum well band structures with the wide-bandgap material AlGaN. The quantum well structure has a strong ability to restrict carriers. x Al 1-x Sb channel layer 3 and AlGaN barrier layer 4 form AlGaN / In x Al 1-x Sb heterojunction to replace the traditional AlGaN / GaN heterojunction, AlGaN / In x Al 1-x The Sb heterojunction has a larger bandgap width difference, which can produce a higher concentration of two-dimensional electron gas (2DEG) in the channel, and improve the heat dissipation performance of the device through the high thermal conductivity substrate layer 1, effectively alleviating the self-heating effect of the device under high bias voltage working state, thereby improving the switching characteristics of the device and the performance and stability in high temperature and high power application scenarios. In addition, by adjusting In x Al 1-x The ratio of Al component to In component in the Sb channel layer 3 can achieve different device performance requirements.

[0038] In this embodiment, there are two source electrodes 6 and two gate electrodes 9. The drain electrode 7 is arranged between the two source electrodes 6, and there is a gap between the two source electrodes 6. The two gate electrodes 9 are arranged at the gap between the drain electrode 7 and the two source electrodes 6, and there is a gap between the gate electrode 9 and the source electrode 6 and the drain electrode 7.

[0039] In one achievable manner, the high thermal conductivity AlGaN / In x Al 1-x The Sb high electron mobility transistor further includes an interconnection metal 10 . The interconnection metal 10 is disposed on the upper surface of the source 6 and the drain 7 and penetrates the passivation layer 8 .

[0040] In this embodiment, the material of the high thermal conductivity substrate layer 1 includes diamond or SiC. The material of the buffer layer 2 includes GaN, and the thickness is 0.5-5 μm. x Al 1-x The thickness of the Sb channel layer 3 is 1-5 nm. The thickness of the AlGaN barrier layer 4 is 10-30 nm, and the content of Al component in the AlGaN barrier layer 4 is 10%-30%. The material of the cap layer 5 is InSb, and the thickness is 2-3 nm. The material of the passivation layer 8 is SiN. The gate 9 is a T-type gate.

[0041] Specifically, the InSb material has a relatively small work function, and using InSb as the cap layer 5 can make it easier for the source electrode 6 and the drain electrode 7 to form an ohmic contact.

[0042] In one practicable manner, x=0.8, In x Al 1-x The material of the Sb channel layer 3 is In 0.8 Al 0.2 Sb.

[0043] In another possible implementation, x=0.9, In x Al 1-x The material of the Sb channel layer 3 is In 0.9 Al 0.1 Sb.

[0044] In another possible implementation, x=1, In x Al 1-x The material of the Sb channel layer 3 is InSb. InSb has the highest electron mobility and electron saturation drift velocity, and the AlGaN / InSb heterojunction can further increase the 2DEG concentration of the device, thereby further improving the switching characteristics of the device and the performance in high-power application scenarios.

[0045] A second aspect of the present embodiment provides an AlGaN / In x Al 1-x A method for preparing a Sb high electron mobility transistor is used to prepare the transistor provided in the first aspect of this embodiment, and the preparation method comprises the following steps:

[0046] S1: Buffer layer 2, In layer 3 and In layer 4 are grown on the surface of high thermal conductivity substrate layer 1 from bottom to top. x Al 1-x Sb channel layer 3 , AlGaN barrier layer 4 and cap layer 5 .

[0047] Specifically, step S1 includes:

[0048] S101: Figure 2a As shown, a diamond or SiC material is obtained as a high thermal conductivity substrate layer 1, and the high thermal conductivity substrate layer 1 is cleaned to remove organic and inorganic residues on the surface.

[0049] In one achievable manner, a diamond material is obtained as the high thermal conductivity substrate layer 1 , the high thermal conductivity substrate layer 1 is ultrasonically cleaned with acetone, the acetone is washed off with anhydrous ethanol and the substrate layer 1 is dried to remove organic and inorganic residues on the surface of the high thermal conductivity substrate layer 1 .

[0050] S102: Figure 2b As shown, on the upper surface of the high thermal conductivity substrate layer 1, GaN with a thickness of 0.5 to 5 μm is grown using a novel vapor phase epitaxial growth technology (MOCVD) as a buffer layer 2.

[0051] In a feasible manner, the high thermal conductivity substrate layer 1 is placed in a MOCVD reaction chamber, and the reaction chamber is evacuated to reduce the vacuum degree to 3×10 -2 Torr, the temperature in the reaction chamber is maintained at 950°C. Under the condition of maintaining the pressure at 20 Torr, Ga(CH3)3 with a flow rate of 25sccm is introduced, and then the temperature is raised to 1000°C, and NH3 with a flow rate of 1500sccm is introduced to grow GaN with a thickness of 2μm on the upper surface of the high thermal conductivity substrate layer 1 to obtain the buffer layer 2.

[0052] S103: Figure 2c As shown, on the upper surface of the buffer layer 2, 1 to 5 nm of unintentionally doped In is grown using molecular beam epitaxy (MBE). x Al 1-x Sb, as In x Al 1-x Sb channel layer 3. Wherein, x represents In x Al 1-x The molar content of In in Sb, x ranges from 0.8 to 1.

[0053] In one achievable method, the wafer obtained in step S102 is moved from the MOCVD chamber to the molecular beam epitaxy (MBE) chamber, the Sb / In beam ratio is maintained at 3, and the temperatures of the indium beam source and the antimony cracking beam source are increased respectively until the indium beam equivalent pressure reaches 5×10 -8 mbar, the equivalent pressure of antimony cracking beam reaches 15×10 -8 mbar, open the baffles of the indium beam source and the antimony beam source at the same time to start growing the InSb nucleation layer. After the nucleation layer growth is completed, keep the In and Sb beams unchanged, increase the growth temperature to 250℃, start the growth of the InSb channel layer, and stop heating after the InSb grows 5nm, and cool naturally to room temperature. x Al 1-x When the value of x in the Sb channel layer 3 is 1, it is an InSb channel layer. It should be understood that the InSb nucleation layer serves as a buffer layer 2 and an InSb channel layer. x Al 1-x Sb channel layer 3 to improve the transition between In x Al 1-x Material quality of Sb channel layer 3.

[0054] S104: Figure 2d As shown in x Al 1-x On the upper surface of the Sb channel layer 3, a 10 to 30 nm thick AlGaN is grown using a novel vapor phase epitaxial growth technique (MOCVD) to form an AlGaN barrier layer 4. x Al 1-xThe Sb channel layer 3 and the AlGaN barrier layer 4 form an AlGaN / In x Al 1-x Sb heterojunction.

[0055] In one feasible method, the wafer obtained in step S103 is transferred from the MBE chamber to the MOCVD chamber, the temperature of the reaction chamber is raised to 1000°C, a nitrogen source with a flow rate of 2000sccm, a gallium source with a flow rate of 50sccm, and an aluminum source with a flow rate of 20sccm are introduced, and an MOCVD growth process is used to grow an AlGaN barrier layer 4 with an Al component of 30% and a thickness of 20nm.

[0056] S105: Figure 2e As shown, on the upper surface of the AlGaN barrier layer 4, 2 to 3 nm of InSb is grown by MBE to form a cap layer 5.

[0057] In a feasible manner, the wafer obtained in step S103 is moved from the MOCVD chamber to the MBE chamber, and while maintaining the Sb / In beam ratio at 3, the temperatures of the indium beam source and the antimony cracking beam source are increased respectively until the indium beam equivalent pressure reaches 5×10 -8 mbar, the equivalent pressure of antimony cracking beam reaches 15×10 -8 mbar, open the baffles of the indium beam source and the antimony beam source at the same time to start growing the InSb nucleation layer. After the nucleation layer growth is completed, keep the In and Sb beams unchanged, increase the growth temperature to 250°C, start the growth of the InSb cap layer, and after the InSb grows 2.5nm, stop heating and cool naturally to room temperature. It should be understood that the InSb nucleation layer serves as a transition between the AlGaN barrier layer 4 and the cap layer 5 to improve the material quality of the cap layer 5.

[0058] The grown wafers were transferred to the MBE chamber, the Sb / In beam ratio was maintained at 3, and the temperatures of the indium beam source and the antimony cracking beam source were increased until the indium beam equivalent pressure reached 5×10 -8 mbar, the equivalent pressure of antimony cracking beam reaches 15×10 -8 mbar, the baffles of the indium beam source and the antimony beam source are opened at the same time to start the growth of the InSb nucleation layer. After the nucleation layer growth is completed, the In and Sb beams are kept unchanged, the growth temperature is increased to 250°C, and the growth of the InSb cap layer 5 is started. After the InSb grows 2.5nm, the heating is stopped and it is naturally cooled to room temperature.

[0059] S2: preparing a source electrode 6 and a drain electrode 7 spaced apart from each other on the surface of the cap layer 5 .

[0060] like Figure 2fAs shown, the epitaxial wafer obtained in step S1 is cleaned, and then photolithography alignment marks are made at both ends of the upper surface of the cap layer 5 to facilitate the subsequent overlay process. Ti / Al / Ni / Au stacked metal (20nm / 160nm / 55nm / 45nm) is deposited on the upper surface of the cap layer 5 by electron beam evaporation, and then rapidly thermally annealed at 850-900°C in an N2 environment to form an ohmic contact, thereby obtaining a source 6 and a drain 7 that are spaced apart. Furthermore, there are two sources 6, and the drain 7 is disposed between the two sources 6, and there is a gap between the two sources 6. After the source 6 and the drain 7 are prepared, ion implantation is performed at the left and right ends of the epitaxial wafer to prepare a device isolation region to isolate the active region and prevent the devices from affecting each other.

[0061] In one achievable method, the epitaxial wafer obtained in step S1 is ultrasonically cleaned with acetone, and then the acetone is washed off with anhydrous ethanol and blown dry to remove grease and oxides on the surface of the sample. Subsequently, photolithography alignment marks are made at both ends of the upper surface of the cap layer 5. The annealing temperature is 850° C. and the time is 50 seconds.

[0062] S3: preparing a passivation layer 8 on the surfaces of the cap layer 5 , the source electrode 6 and the drain electrode 7 .

[0063] like Figure 2g As shown, a plasma enhanced chemical vapor deposition (PECVD) device is used to perform surface passivation of Si3N4 on the surface of the cap layer 5, the source electrode 6 and the drain electrode 7. After the surface passivation is completed, an ellipsometer is used to monitor the thickness and refractive index of Si3N4 to ensure that the thickness and refractive index of Si3N4 are within the set range, and the leakage of Si3N4 is monitored to ensure that it meets the device requirements.

[0064] In one achievable manner, before preparing the passivation layer 8, the sample is subjected to a pre-passivation surface treatment, first cleaned with acetone and isopropanol organic solutions in sequence, then immersed in a 55°C ammonia solution (28% ammonia: H2O=1:6) for 5 minutes, then rinsed with deionized water and dried with N2. Subsequently, the device is subjected to Si3N4 surface passivation using PECVD equipment, the passivation layer thickness is 20nm, and the deposition conditions are temperature 250°C, pressure 600mTorr, and RF power 22W.

[0065] S4: etching the passivation layer 8 to form a gate groove located between the source electrode 6 and the drain electrode 7 and penetrating from the upper surface of the passivation layer 8 to the upper surface of the cap layer 5, and preparing a gate 9 in the gate groove.

[0066] like Figure 2hAs shown, a gate groove is formed between the source 6 and the drain 7 by photolithography. After the gate groove photolithography is completed, the film is hardened on a hot plate. Inductively coupled plasma etching (ICP) is used to remove the passivation layer 8 in the gate groove area, and then a gate metal is deposited. The gate metal should be neat and without adhesion to obtain a gate 9. In this embodiment, there are two gate groove photolithography areas, which are set at the intervals between the drain 7 and the two source electrodes 6, and there are intervals between the gate groove photolithography area and the source 6 and the drain 7. Figure 2i As shown, after the gate 9 is prepared, the passivation layer 8 on the upper surface of the source 6 and the drain 7 is etched to expose the source 6 and the drain 7, and the interconnection metal 10 is deposited or electroplated in the etched area to complete the preparation of the device.

[0067] In an achievable manner, the process conditions of ICP are upper electrode power 80 W, lower electrode power 10 W, CF4 flow rate 25 sccm, O2 flow rate 5 sccm, and an etching rate of 0.67 nm / s.

[0068] The high thermal conductivity AlGaN / In x Al 1-x Sb high electron mobility transistor, through In x Al 1- x Sb channel layer 3 and AlGaN barrier layer 4 form AlGaN / In x Al 1-x Sb heterojunction to replace the traditional AlGaN / GaN heterojunction, AlGaN / In x Al 1-x The Sb heterojunction has a larger difference in bandgap width, can produce a higher concentration of 2DEG in the channel, and improve the heat dissipation performance of the device through the high thermal conductivity substrate layer 1, effectively alleviate the self-heating effect of the device under high bias voltage working state, thereby improving the switching characteristics of the device and the performance and stability in high temperature and high power application scenarios. In addition, the material of the cap layer 5 is InSb, which has a smaller work function, which can make it easier for the source 6 and the drain 7 to form an ohmic contact.

[0069] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A high thermal conductivity AlGaN / In x Al 1-x Sb high electron mobility transistor, characterized in that include: High thermal conductivity substrate layer (1), buffer layer (2), In x Al 1-x Sb channel layer (3), AlGaN barrier layer (4), cap layer (5), source electrode (6), drain electrode (7), passivation layer (8) and gate electrode (9); The high thermal conductivity substrate layer (1), the buffer layer (2), the In x Al 1-x The Sb channel layer (3), the AlGaN barrier layer (4) and the cap layer (5) are arranged in sequence from bottom to top; wherein the value range of x is 0.8 to 1; the In x Al 1-x The Sb channel layer (3) and the AlGaN barrier layer (4) form an AlGaN / In x Al 1-x Sb heterojunction; The source electrode (6) and the drain electrode (7) are arranged at intervals on the upper surface of the cap layer (5); The passivation layer (8) covers the surfaces of the cap layer (5), the source electrode (6) and the drain electrode (7); The gate (9) is arranged between the source (6) and the drain (7), and penetrates from the upper surface of the passivation layer (8) to the upper surface of the cap layer (5).

2. The high thermal conductivity AlGaN / In according to claim 1 x Al 1-x Sb high electron mobility transistor, characterized in that The number of the source electrode (6) and the number of the gate electrode (9) are both two; The drain electrode (7) is arranged between the two source electrodes (6) and is spaced apart from the two source electrodes (6); The two gate electrodes (9) are arranged at the intervals between the drain electrode (7) and the two source electrodes (6), and there are intervals between the gate electrode (9) and the source electrode (6) and the drain electrode (7).

3. The high thermal conductivity AlGaN / In according to claim 1 x Al 1-x Sb high electron mobility transistor, characterized in that Also includes interconnect metal (10); The interconnection metal (10) is arranged on the upper surfaces of the source electrode (6) and the drain electrode (7), and penetrates the passivation layer (8).

4. The high thermal conductivity AlGaN / In according to claim 1 x Al 1-x Sb high electron mobility transistor, characterized in that The material of the high thermal conductivity substrate layer (1) includes diamond or SiC.

5. The high thermal conductivity AlGaN / In according to claim 1 x Al 1-x Sb high electron mobility transistor, characterized in that The material of the buffer layer (2) includes GaN and has a thickness of 0.5 to 5 μm.

6. The high thermal conductivity AlGaN / In according to claim 1 x Al 1-x Sb high electron mobility transistor, characterized in that x=1, the In x Al 1-x The material of the Sb channel layer (3) is InSb.

7. The high thermal conductivity AlGaN / In according to claim 1 x Al 1-x Sb high electron mobility transistor, characterized in that In x Al 1-x The thickness of the Sb channel layer (3) is 1 to 5 nm.

8. The AlGaN / In with high thermal conductivity according to claim 1 x Al 1-x Sb high electron mobility transistor, characterized in that The thickness of the AlGaN barrier layer (4) is 10-30 nm, and the content of the Al component in the AlGaN barrier layer (4) is 10%-30%.

9. The high thermal conductivity AlGaN / In according to claim 1 x Al 1-x Sb high electron mobility transistor, characterized in that The material of the cap layer (5) is InSb, and the thickness is 2-3 nm; The material of the passivation layer (8) is SiN.

10. A high thermal conductivity AlGaN / In x Al 1-x The method for preparing a Sb high electron mobility transistor is characterized in that: For preparing the AlGaN / In with high thermal conductivity as claimed in any one of claims 1 to 9 x Al 1-x Sb high electron mobility transistor, comprising the following steps: S1: On the surface of the high thermal conductivity substrate layer (1), a buffer layer (2), an In x Al 1-x Sb channel layer (3), AlGaN barrier layer (4) and cap layer (5); S2: preparing a source electrode (6) and a drain electrode (7) spaced apart on the surface of the cap layer (5); S3: preparing a passivation layer (8) on the surfaces of the cap layer (5), the source electrode (6) and the drain electrode (7); S4: etching the passivation layer (8) to form a gate groove located between the source electrode (6) and the drain electrode (7) and extending from the upper surface of the passivation layer (8) to the upper surface of the cap layer (5); and preparing a gate electrode (9) in the gate groove.

Images