A transistor with storage effect and semiconductor device thereof

Abstract

The application relates to a transistor with a storage effect and a semiconductor device thereof, the transistor with the storage effect is provided with the storage effect due to the addition of a material with the storage effect in an insulating layer or a semiconductor layer, the transistor itself has the storage effect, a channel electrode is arranged in a channel region, the channel electrode can form a junction capacitor with the channel, the transistor also has a planar transistor structure and a vertical transistor structure, so that the difference between two lines representing state 0 and state 1 can be expanded by regulating the charge of the channel electrode junction capacitor, the existing 2 states are changed into multiple states, the regulation is changed from two dimensions to three dimensions, and can be further expanded to multiple dimensions; the application provides a thought for reducing required circuit area and reducing equipment energy consumption, and greatly expands the application scene of the transistor.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of semiconductor, and particularly relates to a transistor with storage effect and a semiconductor device thereof. BACKGROUND

[0002] In recent years, with the gradual end of Moore's law, building new advanced electronic information devices has become one of the focuses in the post-Moore era. Among them, the electronic device based on two-dimensional van der Waals heterostructure is known as a breakthrough point in the post-Moore era. Meanwhile, the ferroelectric field effect transistor prepared by using the material with storage effect as the gate dielectric is one of the new information devices which is expected to break through the thermodynamic limit of traditional CMOS devices, and has wide application prospects in low-power chips and non-volatile long-term storage.

[0003] However, the current ferroelectric field effect transistor has only two states, and the contrast of the states is not high, which limits its further application in small size and high density. SUMMARY

[0004] The technical problem to be solved by the application is to provide a transistor with storage effect and a semiconductor device thereof. The transistor has a channel electrode arranged in the channel region, and the channel electrode can form a junction capacitor with the channel. The difference between the two lines representing state 0 and state 1 can be expanded by adding the charge of the junction capacitor of the channel electrode, from 2 states to multiple states, from two dimensions to three dimensions, and can be further expanded to multiple dimensions. The application provides a method for reducing the required circuit area and reducing the energy consumption of the device, which greatly expands the application scenarios of the transistor, or can consider adding logic gate function and artificial synapse bionic function. When implementing the logic function, one function of the channel electrode is to extract the voltage from the channel. The existing COMS process technology can completely realize or compatible with the new structure of the application. Similarly, the triode process can also propose a new structure of adding a channel electrode.

[0005] The application provides a transistor with storage effect, comprising:

[0006] a substrate;

[0007] a channel region, a source region and a drain region located on one side of the substrate, the substrate and the doped region serving as the source region and the drain region of the transistor respectively; the channel region has opposite first and second ends in the extension direction; the source region is in electrical contact with the first end to form a source electrode; and the drain region is in electrical contact with the second end to form a drain electrode;

[0008] a gate electrode located between the source region and the drain region, the gate electrode surrounding part of the channel region, and the channel region and the gate electrode having a gate insulating layer between the opposite regions;

[0009] One or several of the following materials are located between the gate and the gate insulating layer: ferroelectric material, magnetoelectric material, phase change material, quantum effect material, resistance change effect material, storage effect material, semiconductor material, superconductor material, conductor material, insulator material, dielectric material, two-dimensional material, one-dimensional material, three-dimensional material, perovskite material, oxide, sulfide, cyanide, hydride, silicide, or the gate and the material with storage effect are separated by a gate insulating layer, or the gate insulating layer itself is a material with storage effect;

[0010] A channel electrode is arranged on the gate insulating layer between the gate and the channel region, or on the material with storage effect, or a channel electrode is arranged in the channel region, and the channel electrode is separated from the source and the drain;

[0011] The at least one channel electrode is composed of a conductor, a semiconductor, or a combination of a conductor and a semiconductor. The purpose of the channel electrode is to form a junction capacitance with the connection part, or to extract the local voltage of the connection area, or to regulate the connection area.

[0012] Optionally, the channel electrode comprises one or more sub-channel electrodes, and the at least one sub-channel electrode is used to regulate the transistor.

[0013] Optionally, the channel electrode is processed by a doping process, or / and a deposition process, or / and an epitaxy process, or / and a self-assembly process, or / and a spin coating process, or / and a sputtering process, or / and a filling process, or / and a Roll-to-Roll process, or / and a hydrothermal method process, or / and an imprint process, or / and a rolling process, or / and a printing process, or / and an evaporation process.

[0014] Further, the regulating transistor comprises at least one sub-channel electrode for storing the charge of the junction capacitance.

[0015] Further, the at least one sub-channel electrode is connected with the channel region and the gate insulating layer for regulating the transistor.

[0016] Further, when there are a plurality of sub-channel electrodes, the plurality of sub-channel electrodes are located on the same side or different sides of the channel region.

[0017] Optionally, in the extension direction, the width of the channel region is uneven or uniform; in the direction from the end of the channel electrode connected with the channel region to the end of the channel electrode away from the channel region, the width of the channel electrode is uneven or uniform.

[0018] Optionally, the substrate is a semiconductor substrate or an insulating substrate.

[0019] Optionally, the channel electrode is selected from any one of Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti or any alloy thereof. For example, the channel electrode is composed of Pt.

[0020] One or more of ferroelectric material, magnetoelectric material, phase change material, quantum effect material, resistive switching effect material, storage effect material, semiconductor material, superconductor material, conductor material, insulator material, dielectric material, two-dimensional material, one-dimensional material, three-dimensional material, perovskite material, oxide, sulfide, cyanide, hydride, silicide is added as an insulating layer, insulating layer material, insulating layer additive material, semiconductor layer material, semiconductor channel material, or channel electrode material, to realize logic polymorphism and storage polymorphism.

[0021] Optionally, the ferroelectric material is H3S, NbN, LaH 10 , BaTiO3, PbZr x Ti 1-x O3, BiFeO3, CIPS (CuIn x P (3-x) S y 6), HZO (HfZrO x ), MoTe2, ZrTiO4, PbTiO3, Ba(Zr,Ti)O3, SrTiO3, BaWO4, BaFe 12 O 19 , YBCO (YBa2Cu3O 7-x , for example YBa2Cu3O7), BFMO (BiFe 1-x MnxO3, for example BiFe 0.9 Mn 0.1 O3), PCMO (Pr 1-x CaxMnO3, for example Pr 0.7 Ca 0.3 MnO3), LBCO (La 2-x BaxCuO4, for example La 1.9 Ba 0.1 CuO4), SmFeAsO 1-x Fx(for example SmFeAsO 0.85 F 0.15 ), CaK(Fe 1-x Mx)4As4(for example CaKFe4As4), NdFe 1-x MxAsO 0.85 (for example NdFeAsO 0.85 ) and the like.

[0022] Optionally, the phase change material is VO2, Ge15 Sb 85 , Ga 36 Sb 64 , Fe3O4, NbO2, PEG ((C2H4O)n), alloys of indium (In) and tin (Sn), C 60 , C 70 , etc.; RMS (Re x Mo 1-x S2), GST ((GeTe) x (Sb2Te3) y , AIST ((Ag 1-x In x )(Sb 1- x Te x )2, for example Ag5In5Sb 60 Te 30 ), GSST (for example Ge2Sb2Se1Te4, Ge2Sb2Se4Te1), Gd5(Si1Ge 1-X )4(for example Gd5Si2Ge2), LaFe 13-x Si x (for example LaFe 12 Si), La 0.5 Pr 0.5 Fe 11.5-x Co x Si 1.5 C 0.2 (for example La 0.5 Pr 0.5 Fe 10.7 Co 0.8 Si 1.5 C 0.2 (for example Ge2Sb2Te5), Sb2Te3, GSB ((GeSn) x (Sb) y (for example GeSnSb), AST ((AlSb2) x (Te) y , for example Al 1.5 Sb3Te), TASG (Ti 48 As 30 Si 12 Ge 10 ) or several of them.

[0023] Optionally, the magnetoelectric material is ZrTiO4, Fe2O3, Fe3O4, SrBaTiO3, Sr 1-x Ba x TiO3, Bi4Ge3O 12 , BaTiO3, Ba 0.8Sr 0.2 TiO3, NiO, NiZnFe2O4, LiNbO3, BTO-PZT, BaFe 12 O 19 , Cr2O3, BiFeO3, BiMnO3, and LuFe2O4, FCSB (Fe 90 Co 78 Si 12 B 10 ), PMN-PZT ((Pb(Mg 1 / 3 Nb 2 / 3 )O3) 1-x -(Pb(Zr 1-y Ti y )O3) x , for example Pb(Mg x Nb 1-x )O3-PbZrO3-PbTiO3), PMN-PT ((Pb(Mg 1 / 3 Nb 2 / 3 )O3) 1-x -(PbTiO3) x , for example Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3).

[0024] Optionally, the quantum effect material is one or more of YBCO, PbLaTiO3, CdSe, GaAs, PbSe, BBO, PPLN, and lead, zinc-tin alloy, cold atomic gas (such as rubidium, lithium, sodium), magnetic materials such as iron, nickel, cobalt, and the like.

[0025] Optionally, the resistance change effect material is one or more of ZrO2, TiO2, Ta2O5, BiFeO3, SrRuO3, SrZrO3, Fe3O4, ZnFe2O4, BaTiO3, Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3, Ba(Sr 0.7 Ba 0.3 )TiO3, In2O3-SnO2, Cu2ZnSnSe4, polystyrene (PS), La1-xSrxMnO3, (Pb, Fe)NbO3CuO x (such as CuO 0.5 ), MoS 2-x O4(such as MoS2O4), HfO x (such as HfO2), WO X (such as WO2), PCMO (Pr 1-x Ca x MnO3, for example Pr 0.7 Ca0.3 MnO3), LSMO (La x Sr 1-x MnO3, for example La 0.5 Sr 0.5 MnO3), LCMO (La x Ca 1-x MnO3, for example La 0.7 Ca 0.3 MnO3), and the like.

[0026] Optionally, the storage effect material is one or more of Fe3O4, Fe2O3, CoFe (cobalt iron alloy), FeCo, FeAlSi, FePt, MnFe, FeNi, CoPt, CoFeB, SbI3, polycarbonate, Si3N4, SiO2, SiO x N y , Se, BaFe 12 O 19 , NiFe, AgCl, AgBr, Ge2Sb2Te5, GeSbTe, Al2O3 / Fe, FeAlO x , polyaniline (PANI).

[0027] Optionally, the superconducting material is H2S, CeCu2Si, CeTIn5, CePt3Si, Ba 0.6 K 0.4 Fe2As2, LaNiC2, LaNiGa2, CaPtAs, Y3Fe5O 12 / Al, 2H-MX2 (M = transition metals; X = chalcogenides), 2H-NbSe2, (magic-angle twisted trilayer graphene) (MATTG), 2H-WS2, 2HeTaS2, 1Td-MoTe2, W2N3, 1T-PdTe2, Pb 10-x Cu x (PO4)6, (Li, Fe)OH FeSe, CuInCo2Te4, YBa2Cu3O7 (yttrium alloy copper oxide), Ba(Fe1-xCox)2As2, Pb, MgB2, CuInSe2, LaFeAsO, Ba(Fe, Co)2As2, BSCCO, GdBCO, IBi2Sr2Ca2Cu3O 10 (BSCCO), T l2 Ba2CuO6, YBa2Fe3Se5.

[0028] Optionally, the semiconductor effect material is one or more of Si, In2Se3, GaAs, GaP, CdSe, ZnSe, PbSe, BN, ZnS, PbS, InP, GaN, Al2Se3, AlAs, InAs, SiGe, CdSe.

[0029] Optionally, the perovskite material is one or more of CsPbBr3, MAPbI 3-x Cl x , SBT (SrBi 1-x Ti x O9, such as SrBiTiO9), BLT (Bi 4-x La x Ti3O 12 , such as Bi 3.5 La 0.5 Ti3O 12 ), PZT (PbZr 1-x T ix O3. For example, PbZr 0.7 Ti 0.3 O3), Cs 1-x FA x PbBr3, such as Cs 0.8 FA 0.2 PbBr3, CH3NH3PbX3(such as CH3NH3PbBr3, CH3NH3PbI3).

[0030] Optionally, the two-dimensional material is one or more of GaS, h-BN, As2Te3, Bi2S3, 2H-WS2, GaSe, GeS, GeSe, HfS2, HfSe2, In2Se3, MoS2, 2H-MoS2, MoTe2, MoSe2, MoSSe, MoWS2, MoWSe2, ReS2, ReSe2, Sb2Te3, SnS2, SnSe2, 1T-TaS2, WSe2, ZrSe2, ZrSe3, ACS.

[0031] The application also provides a semiconductor device comprising a plurality of the transistors.

[0032] Further, the plurality of transistors are connected to any one of the following single layers or composite layers stacked in any direction: metal layer, semiconductor, insulating layer.

[0033] Further, a control electrode is applied simultaneously to achieve device storage and / or logic output.

[0034] Optionally, the semiconductor device is a memory array cell, the channel electrode and the channel form a junction capacitor for storing charge; the gate and the channel electrode are input control electrodes of the memory cell.

[0035] The application also provides an electronic device comprising the semiconductor device according to any one of the above.

[0036] The semiconductor device provided by the application has the channel electrode connected to the channel, which can be used for controlling the channel, and can also be used as an input electrode, an output electrode, etc., so that the semiconductor device has more functions.

[0037] The application also provides a memory array comprising:

[0038] The semiconductor device, a plurality of semiconductor devices form an array in rows and columns, and the source regions of the plurality of semiconductor devices are connected to a fixed potential.

[0039] A plurality of word lines, the gates of the semiconductor devices in the same row of the plurality of semiconductor devices are connected to a corresponding word line.

[0040] A plurality of first bit lines, the channel control regions of the semiconductor devices in the same row or the same column of the plurality of semiconductor devices are connected to a corresponding first bit line; and

[0041] A plurality of second bit lines, the drain regions of the semiconductor devices in the same column of the plurality of semiconductor devices are connected to a corresponding second bit line,

[0042] The plurality of first bit lines are used to apply a control region voltage in a write operation, the plurality of second bit lines are used to apply a drain voltage in a write operation and a read operation, and are used to detect a drain current in the read operation, and the drain current is used to represent a storage state of the plurality of semiconductor devices.

[0043] Optionally, the plurality of semiconductor devices share a semiconductor substrate to form a common source structure.

[0044] The application also provides a data operation method of a memory array, comprising:

[0045] In a write operation, a gate voltage is applied via a selected word line of the plurality of word lines, a drain voltage is applied via a selected second bit line of the plurality of second bit lines, so that the selected semiconductor device is in a conductive state, and a control region voltage is applied to the selected semiconductor device via a selected first bit line of the plurality of first bit lines, so as to change the storage state of the selected semiconductor device; and

[0046] In the read operation, a gate voltage is applied via a selected word line among the plurality of word lines, and a drain voltage is applied via a selected second bit line among the plurality of second bit lines, so as to make the selected semiconductor device in the on state, and a drain current of the selected semiconductor device is detected via the selected second bit line among the plurality of second bit lines to obtain the storage state of the selected semiconductor device.

[0047] Optionally, in the read operation, the plurality of first bit lines are disconnected or connected to a fixed potential.

[0048] Optionally, the plurality of semiconductor devices respectively include a plurality of channel control regions, in the write operation, a corresponding control region voltage is respectively applied to the plurality of channel control regions to write a multi-bit digital value, and in the read operation, a drain current commonly modulated by the plurality of channel control regions is detected to read the multi-bit digital value.

[0049] The application also provides a semiconductor memory device comprising a plurality of the above-mentioned devices.

[0050] The voltage write-erase mode is arranged in combination with the port voltage and the control region voltage.

[0051] The application also provides a semiconductor device comprising a plurality of the above-mentioned transistors.

[0052] The voltage write-erase mode is arranged in combination with the gate voltage, the drain voltage and the control region voltage.

[0053] The structure of the application can be realized by using the existing process line, or can be realized based on the adjustment of the existing process steps. The channel electrode and the control region material can be a semiconductor material, a conductor material or a combination of several materials. The actual preparation process may vary due to factors such as manufacturers, device size and process technology. The structure of the application can be adjusted according to the patent subject.

[0054] The transistor of the application can be illustrated by a three-dimensional structure diagram or a two-dimensional structure diagram.

[0055] Advantages

[0056] The application provides a way to reduce the required circuit area and reduce the energy consumption of the device. The application greatly expands the application scenarios of the transistor, or can consider adding logic gate functions and artificial synapse bionic functions. When implementing logic functions, one function of the channel electrode is to extract the voltage from the channel. BRIEF DESCRIPTION OF DRAWINGS

[0057] Figure 1 Figure 1 is a schematic diagram of the structure of a transistor according to the present application; wherein 1 is a drain, 2 is a gate insulating layer, 3 is a gate, 4 is a channel, 5 is a source, 6 is a substrate, 7 is a channel electrode, and 8 is a material having a storage effect;

[0058] Figure 2 Figure 2 is a schematic diagram of the planar three-dimensional structure of a transistor according to the present application; wherein 101 is a metal layer, 102 is a material having a storage effect, 103 is a gate insulating layer, 104 is a drain, 105 is a source, 106 is a substrate, and 107 is a control gate;

[0059] Figure 3 Figure 3 is a schematic diagram of the vertical three-dimensional structure of a transistor according to the present application; wherein 201 is a drain, 202 is a gate insulating layer, 203 is a material having a storage effect, 204 is a gate insulating layer, 205 is a source, 206 is a substrate, and 207 is a control gate;

[0060] Figure 4 Figure 4 is another schematic diagram of the vertical three-dimensional structure of a transistor according to the present application;

[0061] Figure 5 Figure 5 is a schematic diagram of a storage array of a transistor according to the present application;

[0062] Figure 6 Figure 6 is a schematic diagram of the write and read operation of a transistor according to the present application;

[0063] Figure 7 Figure 7 is the working principle of an example device according to the present application;

[0064] Figure 8 Figure 8 is a schematic diagram of the random access memory test results provided by an example according to the present application;

[0065] Figure 9 Figure 9 is another schematic diagram of the random access memory test results provided by an example according to the present application;

[0066] Figure 10 Figure 10 is a schematic diagram of the typical process preparation flow of a transistor with a channel electrode according to the present application. DETAILED DESCRIPTION

[0067] The present application will be further described below with reference to specific examples. It should be understood that these examples are intended to illustrate the present application and are not intended to limit the scope of the present application. Furthermore, it should be understood that those skilled in the art can make various modifications or improvements to the present application after reading the content taught in the present application, and these equivalent forms are also within the scope of the appended claims.

[0068] The present application can be presented in various forms, some of which will be described below.

[0069] See Figures 1 to 3 In the embodiments of the present application, a transistor is provided, which comprises a substrate, a channel region, a source region and a drain region located on one side of the substrate, the channel region has opposite first and second ends in the extending direction, the source region is in electrical contact with the first end to form a source electrode, the drain region is in electrical contact with the second end to form a drain electrode, a gate electrode is located between the source region and the drain region, the gate electrode surrounds part of the channel region, and a gate insulating layer is located between the channel region and the gate electrode, a material with storage effect is located between the gate electrode and the gate insulating layer, and a channel electrode is arranged in the channel region and separated from the source electrode and the drain electrode.

[0070] The transistor can have a vertical transistor structure, which comprises a substrate, the channel region extends upward from the surface of the source electrode, the extending direction of the channel region is perpendicular to the plane in which the surface of the substrate is located, and the drain electrode is located on the surface of the side of the channel region away from the substrate. The sidewall of the channel region is provided with a gate insulating layer, and the gate electrode is arranged on the surface of the side of the gate insulating layer away from the channel region, i.e. the outer side of the gate insulating layer. The gate electrode can affect the channel region based on its own electric field, thereby controlling the on-off of the vertical transistor, i.e. the on-off of the semiconductor device body. In addition to being separated from the source electrode and the drain electrode to avoid direct contact, the channel electrode also needs to be separated from the gate electrode to avoid direct contact.

[0071] In the embodiments of the present application, in addition to being used as an input terminal or an output terminal, the channel electrode can also be used as a control terminal, and the semiconductor device is at least a four-terminal device. At this time, the channel electrode can have the functions of a control channel, an input electrode or an output electrode. Specifically, the channel electrode can comprise an insulating end portion in contact with the channel. That is, the channel electrode is specifically divided into a conductive end portion and an insulating end portion, and the channel electrode is in contact with the channel region through the insulating end portion. At this time, the channel electrode is similar to the gate electrode and can also control the channel region based on the electric field. At this time, the semiconductor device has two gate electrodes that can control the channel region. It should be noted that the gate electrode or the structure similar to the gate electrode can control other electrodes, or one gate electrode or the structure similar to the gate electrode can be controlled by other two ports or multiple ports, and the specific control relationship is determined by the specific application and is not limited herein.

[0072] For vertical transistors, this invention is based on a common vertical transistor fabrication process. It involves first adding a substrate, then sequentially growing the source, channel region, and gate. A channel electrode is then formed in the channel region not connected to the gate, and the storage or output voltage function is achieved based on the channel electrode. The channel electrode can be on any side, and there can be multiple channel electrodes. Finally, the drain is grown, completing the fabrication of the semiconductor device. The method for adding each of the above layers can be, but is not limited to, deposition, stripping, transfer, photolithography, etching, and so on.

[0073] The present invention provides a semiconductor device that integrates more functions by setting channel electrodes based on a vertical transistor.

[0074] Figure 4 This is a schematic diagram of another vertical three-dimensional structure of the transistor of the present invention:

[0075] It includes a semiconductor substrate, a semiconductor layer on the semiconductor substrate, and a doped region in the semiconductor layer.

[0076] The memory transistor will be described in detail using an N-channel transistor as an example. The semiconductor substrate is, for example, an N-type doped single-crystal silicon substrate, serving as the source region of the memory transistor, and the doped region is, for example, an N-type doped region, serving as the drain region of the memory transistor. The semiconductor layer is, for example, a P-type doped epitaxial layer. However, the present invention is not limited thereto; the memory transistor can be either an N-channel transistor or a P-channel transistor, and depending on the channel type, the layers and doped regions in the memory transistor have corresponding doping types.

[0077] The storage transistor also includes a first trench that controls the doped region and semiconductor layer and extends into the semiconductor substrate, and a second trench that controls the doped region and extends into the semiconductor layer.

[0078] A gate stack consisting of a gate dielectric layer and a gate conductor is formed in the first trench. The gate dielectric is located on the bottom and sidewalls of the first trench, and the gate conductor fills the first trench. The gate dielectric separates the gate conductor from the semiconductor substrate, the semiconductor layer, and the doped region. When the storage transistor is in the ON state, under the voltage applied by the gate conductor, a generally vertically extending channel region is formed along the sidewalls of the first trench in the semiconductor layer, extending from one surface of the semiconductor layer to the other.

[0079] A channel control region and a first insulating layer are formed at the lower and upper parts of the second trench, respectively. The top surface of the channel control region is located below the doped region, and the first insulating layer isolates the two from each other. In the storage transistor, the channel control region is in direct contact with the semiconductor layer. The channel control region is composed of a conductive material, such as a metal, and the semiconductor layer is composed of an N-type semiconductor. A junction capacitance is formed between the channel control region and the semiconductor layer.

[0080] The gate dielectric of the storage transistor consists, for example, of silicon oxide, the gate conductor consists, for example, of doped polysilicon, the channel control region consists, for example, of Pt, and the first insulating layer consists, for example, of silicon oxide. However, the application is not limited thereto, the respective layers and / or regions in the storage transistor can consist of materials known to the person skilled in the art. The channel control region consists, for example, of a material selected from the group consisting of a conductor, a semiconductor, or any stack of a conductor and a semiconductor. Preferably, the channel control region consists of any one of the metals selected from the group consisting of Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti or any alloy thereof, for example, the channel control region consists of Pt.

[0081] Optionally, the ferroelectric material is one or more of H3S, NbN, LaH 10 , BaTiO3, PbZr x Ti 1-x O3, BiFeO3, CIPS (CuIn x P (3-x) S y , for example CuInP2S6), HZO (HfZrO x ), MoTe2, ZrTiO4, PbTiO3, Ba(Zr,Ti)O3, SrTiO3, BaWO4, BaFe 12 O 19 , YBCO (YBa2Cu3O 7-x , for example YBa2Cu3O7), BFMO (BiFe 1-x MnxO3, for example BiFe 0.9 Mn 0.1 O3), PCMO (Pr 1-x CaxMnO3, for example Pr 0.7 Ca 0.3 MnO3), LBCO (La 2-x BaxCuO4, for example La 1.9 Ba 0.1 CuO4), SmFeAsO 1-x Fx, for example SmFeAsO 0.85 F 0.15 ), CaK(Fe 1-x Mx)4As4, for example CaKFe4As4, NdFe 1-x MxAsO 0.85 , for example NdFeAsO 0.85 , and the like.

[0082] Optionally, the phase change material is VO2, Ge 15 Sb 85 , Ga36 Sb 64 , Fe3O4, NbO2, PEG ((C2H4O)n), alloys of indium (In) and tin (Sn), C 60 , C 70 , etc.; RMS (Re x Mo 1-x S2), GST ((GeTe) x (Sb2Te3) y , AIST ((Ag 1-x In x )(Sb 1- x Te x )2, for example Ag5In5Sb 60 Te 30 ), GSST (for example Ge2Sb2Se1Te4, Ge2Sb2Se4Te1), Gd5(Si1Ge 1-X )4(for example Gd5Si2Ge2), LaFe 13-x Si x (for example LaFe 12 Si), La 0.5 Pr 0.5 Fe 11.5-x Co x Si 1.5 C 0.2 (for example La 0.5 Pr 0.5 Fe 10.7 Co 0.8 Si 1.5 C 0.2 (for example Ge2Sb2Te5), Sb2Te3, GSB ((GeSn) x (Sb) y (for example GeSnSb), AST ((AlSb2) x (Te) y , for example Al 1.5 Sb3Te), TASG (Ti 48 As 30 Si 12 Ge 10 ) or several of them.

[0083] Optionally, the magnetoelectric material is ZrTiO4, Fe2O3, Fe3O4, SrBaTiO3, Sr 1-x Ba x TiO3, Bi4Ge3O 12 , BaTiO3, Ba 0.8 Sr 0.2TiO3, NiO, NiZnFe2O4, LiNbO3, BTO-PZT, BaFe 12 O 19 , Cr2O3, BiFeO3, BiMnO3and LuFe2O4, FCSB (Fe 90 Co 78 Si 12 B 10 ), PMN-PZT ((Pb(Mg 1 / 3 Nb 2 / 3 )O3) 1-x -(Pb(Zr 1-y Ti y )O3) x , for example Pb(Mg x Nb 1-x )O3-PbZrO3-PbTiO3), PMN-PT ((Pb(Mg 1 / 3 Nb 2 / 3 )O3) 1-x -(PbTiO3) x , for example Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3).

[0084] Optionally, the quantum effect material is one or more of YBCO, PbLaTiO3, CdSe, GaAs, PbSe, BBO, PPLN and lead, zinc tin alloy, cold atomic gas (such as rubidium, lithium, sodium), magnetic materials such as iron, nickel, cobalt, etc.

[0085] Optionally, the resistance change effect material is one or more of ZrO2, TiO2, Ta2O5, BiFeO3, SrRuO3, SrZrO3, Fe3O4, ZnFe2O4, BaTiO3, Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3, Ba(Sr 0.7 Ba 0.3 )TiO3, In2O3-SnO2, Cu2ZnSnSe4, polystyrene (PS), La1-xSrxMnO3, (Pb, Fe)NbO3CuO x (for example CuO 0.5 ), MoS 2-x O4(for example MoS2O4), HfO x (for example HfO2), WO X (for example WO2), PCMO (Pr 1-x Ca x MnO3, for example Pr 0.7 Ca 0.3MnO3), LSMO (La x Sr 1-x MnO3, for example La 0.5 Sr 0.5 MnO3, for example La x Ca 1-x MnO3, for example La 0.7 Ca 0.3 MnO3, for example La

[0086] Optionally, the storage effect material is one or more of Fe3O4, Fe2O3, CoFe (cobalt iron alloy), FeCo, FeAlSi, FePt, MnFe, FeNi, CoPt, CoFeB, SbI3, polycarbonate, Si3N4, SiO2, SiO x N y , Se, BaFe 12 O 19 , NiFe, AgCl, AgBr, Ge2Sb2Te5, GeSbTe, Al2O3 / Fe, FeAlO x , polyaniline (PANI).

[0087] Optionally, the superconducting material is H2S, CeCu2Si, CeTIn5, CePt3Si, Ba 0.6 K 0.4 Fe2As2, LaNiC2, LaNiGa2, CaPtAs, Y3Fe5O 12 / Al, 2H-MX2 (M = transition metals; X = chalcogenides), 2H-NbSe2, (magic-angle twisted trilayer graphene) (MATTG), 2H-WS2, 2HeTaS2, 1Td-MoTe2, W2N3, 1T-PdTe2, Pb 10-x Cu x (PO4)6, (Li, Fe)OH FeSe, CuInCo2Te4, YBa2Cu3O7 (yttrium alloy copper oxide), Ba(Fe1-xCox)2As2, Pb, MgB2, CuInSe2, LaFeAsO, Ba(Fe, Co)2As2, BSCCO, GdBCO, IBi2Sr2Ca2Cu3O 10 (BSCCO), T l2 Ba2CuO6, YBa2Fe3Se5.

[0088] Optionally, the semiconductor effect material is one or more of Si, In2Se3, GaAs, GaP, CdSe, ZnSe, PbSe, BN, ZnS, PbS, InP, GaN, Al2Se3, AlAs, InAs, SiGe, CdSe.

[0089] Optionally, the perovskite material is one or more of CsPbBr3, MAPbI 3-x Cl x , SBT (SrBi 1-x Ti x O9, for example SrBiTiO9), BLT (Bi 4-x La x Ti3O 12 , for example Bi 3.5 La 0.5 Ti3O 12 ), PZT (PbZr 1-x T ix O3. For example PbZr 0.7 Ti 0.3 O3), Cs 1-x FA x PbBr3, for example Cs 0.8 FA 0.2 PbBr3, CH3NH3PbX3(for example CH3NH3PbBr3, CH3NH3PbI3).

[0090] Optionally, the two-dimensional material is one or more of GaS, h-BN, As2Te3, Bi2S3, 2H-WS2, GaSe, GeS, GeSe, HfS2, HfSe2, In2Se3, MoS2, 2H-MoS2, MoTe2, MoSe2, MoSSe, MoWS2, MoWSe2, ReS2, ReSe2, Sb2Te3, SnS2, SnSe2, 1T-TaS2, WSe2, ZrSe2, ZrSe3, ACS.

[0091] Further, the memory transistor includes a second insulating layer, a drain electrode on the second insulating layer, a gate electrode, and a channel electrode, and a source electrode on a surface of the semiconductor substrate opposite to the semiconductor layer. The second insulating layer covers a surface of the doped region as an interlayer dielectric layer. The drain electrode is connected to the doped region via conductive vias that control the second insulating layer. The gate electrode is connected to the gate conductor via conductive vias that control the second insulating layer. The channel electrode is connected to the channel control region via conductive vias that control the second insulating layer and the first insulating layer.

[0092] According to the memory transistor of the embodiment, the channel control region of the memory transistor is adjacent to one side surface of the gate conductor, and the channel control region and the gate conductor extend substantially vertically in the semiconductor layer, respectively. The gate conductor is sandwiched with the semiconductor layer by the gate dielectric. In the write operation and the read operation, the gate voltage applied on the gate conductor acts on the adjacent region of the semiconductor layer, so as to form a substantially vertically extending channel between the gate conductor and the channel control region, which extends from one surface of the semiconductor layer to another surface. The channel control region is in direct contact with the semiconductor layer to form a junction capacitance.

[0093] According to the transistor of the embodiment, a plurality of memory cells are arranged in a matrix, and the memory cells are formed by the channel electrodes and the inversion-mode RRAMs. The inversion-mode RRAMs have a vertical structure, and the channel electrodes are in contact with the channel regions of the inversion-mode RRAMs.

[0094] In the row direction, the memory cells of each row are connected by the gates and are commonly connected to a word line. The potential of the word line is controlled to read, write and erase the information of the selected memory cells. In the column direction, the memory cells of each column are connected by the drains and the sources in sequence from the first row to the last row. The source of the memory cell in the first row is connected to a source bit line, and the drain of the memory cell in the last row is connected to a drain bit line. The channel electrodes of the memory cells in each column are connected in sequence, or the channel electrodes of the memory cells in each row are connected in sequence to form a row / column line.

[0095] According to another aspect of the present application, a memory array is provided, which includes: a plurality of memory transistors arranged in rows and columns, and the source regions of the memory transistors are connected to a fixed potential; a plurality of word lines, the gates of the memory transistors in the same row are connected to a corresponding word line; a plurality of first bit lines, the channel control regions of the memory transistors in the same row or the same column are connected to a corresponding first bit line; and a plurality of second bit lines, the drain regions of the memory transistors in the same column are connected to a corresponding second bit line. The first bit lines are used to apply a control voltage in a programming operation, the second bit lines are used to apply a drain voltage and detect a drain current in a read operation, and the drain current is used to represent the storage state of the memory transistors.

[0096] Optionally, the plurality of memory transistors share a semiconductor substrate to form a common source structure.

[0097] Figure 5 and 6 A schematic diagram of the write operation of the memory cells in the memory array shown in FIG. 8.

[0098] The storage device comprises a word line driving module, a bit line driving module, and a storage array. The word line driving module is connected to the gate of the storage transistor 10 via a word line WL, the bit line driving module is connected to the channel electrode of the storage transistor 10 via a bit line BL1, and is connected to the drain of the storage transistor 10 via a bit line BL2.

[0099] In a write operation, a gate voltage Vgs is provided via the word line WL, a control region voltage Vc is provided via the bit line BL1, and a drain voltage Vds is provided via the bit line BL2. The source of the storage transistor 10 is grounded. At this time, the storage transistor 10 in the storage array is in an on state, and the unselected storage transistor in the storage array is in an off state. Preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5-50V, and the drain voltage Vds is 0.05-50V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5-25V, and the drain voltage Vds is 0.05-25V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5-15V, and the drain voltage Vds is 0.05-15V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5-10V, and the drain voltage Vds is 0.05-10V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7-5V, and the drain voltage Vds is 0.05-5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7-2.5V, and the drain voltage Vds is 0.05-2.5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7-1.8V, and the drain voltage Vds is 0.05-2V. Most preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7-1.5V, and the drain voltage Vds is 0.05-1.5V.

[0100] Further, in the write operation, a gate voltage Vgs is supplied via the word line WL, a control region voltage Vc is supplied via the bit line BLl, and a drain voltage Vds is supplied via the bit line BL2. The source of the memory transistor 10 is grounded. At this time, the memory transistor 10 in the memory array is in the on state, and the unselected memory transistor in the memory array is in the off state. Preferably, in the write operation, the gate voltage Vgs of the memory transistor 10 is 0.5-50 V, the drain voltage Vds is 0.05-50 V, and the control region voltage Vc is -50-50 V. More preferably, in the write operation, the gate voltage Vgs of the memory transistor 10 is 0.5-25 V, the drain voltage Vds is 0.05-25 V, and the control region voltage Vc is -20-20 V. More preferably, in the write operation, the gate voltage Vgs of the memory transistor 10 is 0.5-15 V, the drain voltage Vds is 0.05-15 V, and the control region voltage Vc is -10-10 V. More preferably, in the write operation, the gate voltage Vgs of the memory transistor 10 is 0.5-10 V, the drain voltage Vds is 0.05-10 V, and the control region voltage Vc is -10-10 V. More preferably, in the write operation, the gate voltage Vgs of the memory transistor 10 is 0.7-5 V, the drain voltage Vds is 0.05-5 V, and the control region voltage Vc is -5-5 V. More preferably, in the write operation, the gate voltage Vgs of the memory transistor 10 is 0.7-2.5 V, the drain voltage Vds is 0.05-2.5 V, and the control region voltage Vc is -5-5 V. More preferably, in the write operation, the gate voltage Vgs of the memory transistor 10 is 0.7-1.8 V, the drain voltage Vds is 0.05-2 V, and the control region voltage Vc is -2-2 V. Most preferably, in the write operation, the gate voltage Vgs of the memory transistor 10 is 0.7-1.5 V, the drain voltage Vds is 0.05-1.5 V, and the control region voltage Vc is -2-2 V.

[0101] Further, the write operation includes, for example, data erasing and data programming. In the data erasing, the control region voltage Vc of the memory transistor 10 is, for example, 1.5 V, and the junction capacitance of the memory transistor 10 is discharged to release the charge. In the data programming, the control region voltage Vc of the memory transistor 10 is, for example, -1.5 V, and the voltage difference of the gate voltage Vgs with respect to the control region voltage Vc exceeds a predetermined value, and the junction capacitance of the memory transistor 10 is charged to store the charge. The write operation can change the storage state of the memory transistor 10, for example, the erasing state of the memory transistor 10 is a high resistance state, which is used to represent the digital value 0, and the writing state is a low resistance state, which is used to represent the digital value 1.

[0102] In the read operation, a gate voltage Vgs is supplied via the word line WL, and a drain voltage Vds is supplied via the bit line BL2. The source of the memory transistor 10 is grounded. The channel electrode of the memory transistor 10 is in a floating state due to the disconnection of the bit line BLl. At this time, the memory transistor 10 in the memory array is in an on state, and the unselected memory transistor in the memory array is in an off state. Preferably, in the read operation, the gate voltage Vgs of the memory transistor 10 is 1.2 V, and the drain voltage Vds is 2 V.

[0103] Further, the read operation includes detecting the drain current Ids of the memory transistor 10. In the write operation of the memory transistor 10, the storage state of the memory transistor 10 is related to the resistance state. Even if the same bias condition is used, i.e., the same gate voltage, drain voltage, and source voltage, the drain current of the memory transistor in different storage states is not the same.

[0104] Therefore, by using the comparison of the drain current Ids and the current reference Iref, the storage state of the memory transistor 10 can be determined according to the size of the drain current Ids. For example, in the case where the drain current of the memory transistor 10 is greater than the current reference Iref, it is determined that the digital value stored in the memory transistor 10 is 1, and in the case where the drain current of the memory transistor 10 is less than or equal to the current reference Iref, it is determined that the digital value stored in the memory transistor 10 is 0. There can be multiple current references Iref, thereby realizing multi-state storage.

[0105] Therefore, by using the comparison of the channel electrode output voltage V CG and the voltage reference Vref, the storage state of the transistor 10 can be determined according to the size of the channel electrode output voltage V CG . For example, in the case where the channel electrode output voltage of the transistor 10 is greater than the voltage reference Vref, it is determined that the digital value output by the transistor 10 is 1, and in the case where the electrode output voltage V CG of the transistor 10 is less than or equal to the voltage reference Vref, it is determined that the digital value logically output by the transistor 10 is 0. There can also be multiple voltage references Vref, thereby realizing multi-state logic.

[0106] The semiconductor device body of the above-mentioned channel electrode reverse-mode resistance-change field effect transistor can adopt a transistor structure, specifically can adopt a conductive electrode layer, resistance-change memory layer stack structure, or universal

[0107] Channel electrode can be set by transistor structure, FINFET (Fin Field Effect Transistor) structure, FLASH (Flash Memory) structure, or GAA structure, and source region and drain region can adopt n / p type ion implantation structure or NiGe alloy structure.

[0108] The semiconductor device can simultaneously play the functions of storing information and switching in the formed memory array, and realizes the integration of the storage function and the switching control function in one transistor.

[0109] Based on Figure 7 The original transistor storage mechanism: the blue line after writing, the dielectric layer attracts the channel electrons after writing, the red line after erasing, the dielectric layer attracts holes after erasing, and the electron current in the channel decreases, which are two states in the XY direction; this embodiment adds a channel electrode, according to the junction capacitance mechanism, the channel of the transistor includes the channel electrode, the channel electrode and the channel form a junction capacitor, so that the transistor has the ability to store charges. By controlling the junction capacitance channel electrode at the same time during programming, the junction capacitance charge changes, and the channel electrons are adjusted in the XZ direction. According to the ferroelectric regulation channel current mechanism and the junction capacitance storage regulation channel current mechanism, three-dimensional control of storage can be realized.

[0110] As Figure 8 Because of the addition of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistance change effect materials, storage effect materials, superconducting effect materials, semiconductor effect materials, etc., the transistor can have two states of storage 0 and storage 1, and the logical states 0 and 1 given by the transistor storage 0 are different from the logical states 0 and 1 when the transistor stores 1, so multi-state storage can be realized.

[0111] As Figure 9 Because of the addition of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistance change effect materials, storage effect materials, superconducting effect materials, semiconductor effect materials, etc., the transistor can have two states of storage 0 and storage 1, and the logical states 0 and 1 given by the transistor storage 0 are different from the logical states 0 and 1 when the transistor stores 1, so multi-state storage can be realized.

[0112] By adding ferroelectric material, magnetoelectric material, phase change material, quantum effect material, resistance change effect material, storage effect material, superconducting effect material, semiconductor effect material, and combining with channel electrode to regulate the storage state of transistor, more states of storage can be realized than the device without channel electrode or only with channel electrode, without adding ferroelectric material, magnetoelectric material, phase change material, quantum effect material, resistance change effect material, storage effect material, superconducting effect material, and semiconductor effect material.

[0113] In addition, the manufacturing technology of the transistor used in the embodiment of the application is further introduced, Figure 10 A typical process preparation flowchart of the channel electrode transistor provided in the embodiment of the application is as follows: (1) preparation of the substrate: first, select appropriate semiconductor material as the substrate, and perform chemical and physical treatment to remove impurities and impurities. (2) forming each part of the transistor: using oxidation, photolithography, doping, deposition and etching technology, forming transistor channel, gate oxide layer, source, drain, channel electrode and gate. (3) forming contact: using photolithography and etching technology, forming metal contact on the gate, source region, drain region and control region to connect external circuit. (4) surface planarization: during the preparation process, uneven surface may occur. Surface planarization treatment is needed. (5) metallization: in the last step, the entire transistor is metallized to connect the transistor electrode to the external circuit.

[0114] The above is only a typical process flow of the channel electrode transistor preparation process. New structure can be realized by existing process line, or based on existing process step adjustment, and the control region material can be semiconductor material, conductor material or combination of several materials. The actual preparation process may vary due to factors such as manufacturer, device size and process technology.

Claims

1. A transistor with storage effect, characterized by: The transistor comprises: a substrate; a channel region, a source region and a drain region on one side of the substrate, the substrate and the doped region being the source region and the drain region of the transistor, respectively; the channel region has opposite first and second ends in the extension direction; the source region is in electrical contact with the first end to form a source electrode; the drain region is in electrical contact with the second end to form a drain electrode; a gate electrode between the source region and the drain region, the gate electrode surrounding part of the channel region, and the channel region and the gate electrode having a gate insulating layer between the regions opposite to each other; a ferroelectric material, a magnetoelectric material, a phase change material, a quantum effect material, a resistance change effect material, a storage effect material, a semiconductor material, a superconductor material, a conductor material, an insulator material, a dielectric material, a two-dimensional material, a one-dimensional material, a three-dimensional material, a perovskite material, an oxide, a sulfide, a cyanide, a hydride, a silicide, one or more of the materials having a storage effect, or a gate insulating layer between the gate electrode and the material having a storage effect, or the gate insulating layer itself being a material having a storage effect; at least one channel electrode is provided on the gate insulating layer between the gate electrode and the channel region or on the material having a storage effect, or at least one channel electrode is provided in the channel region, the at least one channel electrode being separated from the source electrode and the drain electrode; the at least one channel electrode is composed of a conductor, a semiconductor, or a combination of a conductor and a semiconductor; the transistor comprises at least one sub-channel electrode for storing the junction capacitance of the electric charge, the at least one sub-channel electrode being connected to the channel region and the gate insulating layer for regulating the storage charge of the transistor; by adding the charge of the junction capacitance of the channel electrode, the state is expanded from 2 to multiple states, and the regulation is changed from two-dimensional to multi-dimensional.

2. The transistor of claim 1, wherein: When there are multiple sub-channel electrodes, the multiple sub-channel electrodes are located on the same side or multiple different sides of the channel region.

3. The transistor of claim 1, wherein: The channel electrode is composed of any one metal selected from Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti or any alloy thereof.

4. The transistor of claim 1, wherein: The material with storage effect is one or several of H3S, NbN, LaH 10 , BaTiO3, PbZr x Ti 1-x O3, BiFeO 3、 CIPS, HZO, MoTe2, ZrTiO4, PbTiO3, Ba(Zr,Ti)O3, SrTiO3, BaWO4, BaFe 12 O 19 , YBCO, BFMO, PCMO, LBCO, SmFeAsO 1-x Fx, CaK(Fe 1-x Mx)4As4, NdFe 1-x MxAsO 0.85 .

5. The transistor of claim 1, wherein The channel electrode is processed by a doping process, or / and a deposition process, or / and an epitaxy process, or / and a self-assembly process, or / and a spin coating process, or / and a sputtering process, or / and a filling process, or / and a Roll-to-Roll process, or / and a hydrothermal process, or / and an imprint process, or / and a rolling process, or / and a printing process, or / and an evaporation process.

6. The transistor of claim 1, wherein: One or more of the ferroelectric material, the magnetoelectric material, the phase change material, the quantum effect material, the resistance change effect material, the storage effect material, the semiconductor material, the superconductor material, the conductor material, the insulator material, the dielectric material, the two-dimensional material, the one-dimensional material, the three-dimensional material, the perovskite material, the oxide, the sulfide, the cyanide, the hydride, and the silicide is added as an insulating layer, an insulating layer material, an insulating layer added material, a semiconductor layer material, a semiconductor channel material, or a channel electrode material.

7. A semiconductor device, characterized by: The transistor comprises a plurality of transistors as claimed in any one of claims 1-6.

8. The semiconductor device of claim 7, wherein: The plurality of transistors is connected to a single layer or a composite layer stacked in any direction of the following: a metal layer, a semiconductor, an insulating layer.

9. The semiconductor device of claim 7, wherein: Meanwhile, an external control electrode is applied to realize device storage and / or logic output.

10. An electronic device, comprising: A semiconductor device as claimed in any one of claims 7-9.

11. A memory array comprising: The transistors of any one of claims 1-6, a plurality of the transistors arranged in rows and columns, and the source regions of the plurality of transistors connected to a fixed potential; a plurality of word lines, the gates of the transistors in the same row of the plurality of transistors connected to a corresponding one of the plurality of word lines; a plurality of first bit lines, the channel control regions of the transistors in the same row or the same column of the plurality of transistors connected to a corresponding one of the plurality of first bit lines; and a plurality of second bit lines, the drain regions of the transistors in the same column of the plurality of transistors connected to a corresponding one of the plurality of second bit lines, wherein the plurality of first bit lines are used to apply a control region voltage in a write operation, the plurality of second bit lines are used to apply a drain voltage in a write operation and a read operation, and to detect a drain current in the read operation, the drain current used to characterize a storage state of the plurality of transistors. The plurality of transistors share a semiconductor substrate to form a common source structure.

12. The storage array of claim 11, wherein:

13. A method of data operation of the memory array of claim 11 or 12, comprising: in a write operation, applying a gate voltage via a selected one of the plurality of word lines, and a drain voltage via a selected one of the plurality of second bit lines to cause a selected transistor to be in an on state, and applying a control region voltage to the selected transistor via a selected one of the plurality of first bit lines to change a storage state of the selected transistor; and in a read operation, applying a gate voltage via a selected one of the plurality of word lines, and a drain voltage via a selected one of the plurality of second bit lines to cause a selected transistor to be in an on state, and detecting a drain current of the selected transistor via the selected one of the plurality of second bit lines to obtain the storage state of the selected transistor. In the read operation, the plurality of first bit lines are disconnected or connected to a fixed potential. The plurality of transistors respectively comprise a plurality of channel control regions, a corresponding control region voltage is respectively applied to the plurality of channel control regions in a write operation to write a multi-bit digital value, and a drain current collectively modulated by the plurality of channel control regions is detected in a read operation to read the multi-bit digital value.

14. The data manipulation method of claim 13, wherein: A plurality of semiconductor devices as claimed in any one of claims 7-9; 15. The data manipulation method of claim 13, wherein: The voltage write, erase mode is arranged in combination with both the port voltage and the control region voltage.

16. A semiconductor memory device, characterized by comprising: A plurality of transistors as claimed in any one of claims 1-6; The voltage write, erase mode is arranged in combination with all of the gate voltage, the drain voltage, and the control region voltage.

17. A semiconductor device, characterized by: ​ ​

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