Terminal structure of power device, manufacturing method and chip

Abstract

The embodiment of the invention provides a terminal structure of a power device, a manufacturing method and a chip. The terminal structure comprises an N-type substrate; the junction termination extension region, the junction gradient doping region and the field limiting rings are arranged on the N-type substrate, the junction termination extension region is connected with the junction gradient doping region, the depth of the junction gradient doping region is gradually reduced along the direction far away from the junction termination extension region, and the field limiting rings are arranged at one end, far away from the junction termination extension region, of the junction gradient doping region. The distances between the plurality of field limiting rings and the junction gradient doping region are gradually increased; p-type ions are doped in the junction termination expansion region, the junction gradient doping region and the plurality of field limiting rings; and the trench is arranged on one side, far away from the junction gradient doped region, of the field limiting ring farthest from the junction gradient doped region. Through a composite terminal structure comprising a junction terminal expansion region, a junction gradient doping region, a plurality of field limiting rings, a groove and a polycrystalline silicon field plate, the maximum electric field intensity of a chip can be effectively reduced, and the voltage withstanding performance of a device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a terminal structure, a manufacturing method and a chip of a power device. Background Art

[0002] Modern power devices (such as MOSFET, IGBT, etc.) are usually composed of thousands of identical cells connected in parallel. Each cell is a small power device. These cells are connected in parallel to increase the total current handling capacity of the device. The surface voltage of each cell is roughly the same because they share the same voltage source and load. In power devices, the voltage difference between the terminal cell (the cell near the edge of the device) and the substrate (the bottom layer of the device) can be large. This is because the terminal cell needs to withstand a higher voltage to prevent breakdown caused by electric field concentration. This voltage difference will cause electric field concentration in the terminal area, affecting the voltage withstand capability of the device. In order to improve the voltage withstand capability of the device, measures need to be taken to reduce the surface electric field, which is usually achieved by optimizing the terminal structure, such as using field limiting rings (FLR) and other technologies. The field limiting ring can introduce additional doping regions in the terminal area to disperse the electric field and prevent breakdown caused by electric field concentration. Modern silicon power devices usually adopt a shallow planar structure, which can improve the device's voltage resistance. In the field limiting ring design, field limiting rings are often used to reduce the surface electric field concentration caused by the junction curvature effect, thereby increasing the breakdown voltage. Although field limiting rings can increase the breakdown voltage, they will also significantly increase the chip area. This is because the field limiting rings need to introduce additional doped regions in the terminal area, which occupy a part of the chip area. The planar field limiting ring may have a peak electric field at the corner of the injection junction (i.e., the corner of the doped region). This peak electric field will cause the device's breakdown characteristics to degrade because the electric field concentration increases the risk of breakdown. In order to further increase the junction depth (i.e., the depth of the doped region) and reduce the peak electric field at the corner of the injection junction, a trench field limiting ring (TFLR) terminal structure can be used. The trench field limiting ring introduces a trench structure in the terminal region to further disperse the electric field and reduce the peak electric field. Although the trench field limiting rings can reduce the peak electric field, they will also increase the expansion capacity of the lateral space charge region at the field limiting ring terminal, which means that the terminal region needs a larger area to accommodate these expanded space charge regions, thereby increasing the terminal area.

[0003] In power devices, the main junction ring refers to the main PN junction or Schottky junction of the device. In order to improve the voltage resistance of the device, the surface of the main junction ring is usually doped with a high dose. The injection dose is usually 1e12~1e15 / cm 2The order of magnitude of . High dose doping injection will increase the surface electric field strength of the main junction ring. Since the electric field concentration effect is more obvious at the corner of the main junction ring (i.e., the corner of the doped area), the breakdown usually occurs at the corner of the main junction. This means that the electric field strength at the corner of the main junction is the largest, which is easy to cause breakdown. In the actual production process, the injection dose may be affected by the deviation of the production line machine. This deviation will cause uneven injection dose, thereby affecting the performance and reliability of the device. The JTE (Junction Termination Extension) lateral junction terminal extension structure is a terminal protection technology used to improve the voltage withstand capability of the device. The JTE structure introduces additional doping areas in the terminal area to disperse the electric field and prevent breakdown caused by electric field concentration. However, if the injection dose deviation causes the doping concentration of the JTE structure to be low, the effect of the JTE structure will be affected. If the doping concentration of the JTE structure is low, the electric field distribution will be uneven, causing the breakdown to occur at the JTE lateral junction terminal extension structure. This means that the JTE structure fails to effectively disperse the electric field and instead becomes the location of breakdown. Due to the low doping concentration of the JTE structure, the breakdown occurs at the JTE structure, which results in poor reliability of the terminal and insufficient voltage resistance. This means that the device is prone to failure in high voltage or high temperature environments, affecting the stability and life of the system. Summary of the invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a terminal structure, a manufacturing method and a chip of a power device that overcome the above problems or at least partially solve the above problems.

[0005] In order to solve the above problems, an embodiment of the present invention discloses a terminal structure of a power device, wherein the terminal structure comprises:

[0006] N-type substrate;

[0007] A junction terminal extension region, a junction gradient doping region and a plurality of field limiting rings are provided in the N-type substrate, the junction terminal extension region is connected to the junction gradient doping region, the depth of the junction gradient doping region gradually decreases along a direction away from the junction terminal extension region, the plurality of field limiting rings are provided at one end of the junction gradient doping region away from the junction terminal extension region, and the distances of the plurality of field limiting rings relative to the junction gradient doping region gradually increase; the junction terminal extension region, the junction gradient doping region and the plurality of field limiting rings are doped with P-type ions;

[0008] A groove is provided in the N-type substrate, wherein the groove is provided on a side of the field limiting ring farthest from the junction gradient doping region and away from the junction gradient doping region; polysilicon is deposited in the groove;

[0009] A P-well region and a cut-off ring N+ region are provided in the N-type substrate, the P-well region is connected to the junction terminal extension region, and the cut-off ring N+ region is provided on a side of the trench away from the field limiting ring;

[0010] An oxide layer disposed on the surface of the N-type substrate;

[0011] A polysilicon field plate disposed on a surface of a target region of the oxide layer, wherein the target region is a region of a preset width covering edges of the plurality of field limiting rings;

[0012] A metal layer is provided on the surface of the P-well region, the surface of a portion of the junction terminal extension region close to the P-well region, above the multiple field limiting rings, the surface of the cut-off ring N+ region, and the surface of a portion of the oxide layer close to the cut-off ring N+ region.

[0013] Optionally, the N-type substrate is an N-type substrate, and the terminal structure further includes:

[0014] An N+ type buffer layer formed on the other side of the N- type substrate;

[0015] A P+ type collector region formed on the N+ type buffer layer;

[0016] A collector terminal is formed on the P+ type collector region.

[0017] Optionally, the width of each field limiting ring is in the range of 5-12 um.

[0018] Optionally, the depth of the groove ranges from 4 to 6 um, and the width of the groove ranges from 0.6 to 2 um.

[0019] Optionally, the thickness of the metal layer is in the range of 3-5 um.

[0020] Accordingly, an embodiment of the present invention discloses a method for manufacturing a terminal structure of a power device, which is used to manufacture the terminal structure of the power device as described above. The method includes:

[0021] Providing an N-type substrate;

[0022] A junction terminal extension region, a junction gradient doping region and a plurality of field limiting rings are formed on the N-type substrate; the junction terminal extension region is connected to the junction gradient doping region, the depth of the junction gradient doping region gradually decreases in a direction away from the junction terminal extension region, and the plurality of field limiting rings are arranged at one end of the junction gradient doping region away from the junction terminal extension region;

[0023] In the N-type substrate, a groove is formed, wherein the groove is arranged on a side of the field limiting ring farthest from the junction gradient doping region and away from the junction gradient doping region;

[0024] depositing polysilicon in the trench;

[0025] A P-well region and a cut-off ring N+ region are formed on the N-type substrate; the P-well region is connected to the junction terminal extension region, and the cut-off ring N+ region is arranged on a side of the trench away from the field limiting ring;

[0026] Growing an oxide layer on the surface of the N-type substrate,

[0027] Removing the oxide layers corresponding to the surfaces of the P-well region, the central regions of the plurality of field limiting rings, and the cut-off ring N+ region;

[0028] Generating a polysilicon field plate on a surface of a target region of the oxide layer; the target region is a region of a preset width covering edges of the plurality of field limiting rings;

[0029] A metal layer is generated on the surface of the P-well region, on the surface of a portion of the junction terminal extension region close to the P-well region, above the multiple field limiting rings, on the surface of the cutoff ring N+ region, and on the surface of a portion of the oxide layer close to the cutoff ring N+ region.

[0030] Optionally, the N-type substrate is an N-type substrate, and the method further includes:

[0031] Performing backside thinning on the N-type substrate at the other side of the N-type substrate;

[0032] Performing high-concentration N-type doping on the N-type substrate on the other side of the N-type substrate to form an N+ type buffer layer;

[0033] Performing high-concentration P-type doping on the N+ type buffer layer to form a P+ type collector region;

[0034] A metal layer is deposited on the P+ type collector region to form a collector terminal.

[0035] Optionally, the distances between the multiple field limiting rings and the junction gradient doping region gradually increase; the junction terminal extension region, the junction gradient doping region and the multiple field limiting rings are doped with P-type ions; and the width range of each field limiting ring is 5-12um.

[0036] Optionally, the coverage range of the edges of the multiple field limiting rings is 0.5 to 1.5 um.

[0037] Optionally, the depth of the groove ranges from 4 to 6 um, and the width of the groove ranges from 0.6 to 2 um.

[0038] Optionally, the thickness of the metal layer is in the range of 3-5 um.

[0039] Correspondingly, an embodiment of the present invention discloses a chip including the terminal structure of the power device as described above.

[0040] The embodiments of the present invention include the following advantages:

[0041] The terminal structure of the power device of the embodiment of the present invention comprises an N-type substrate; a junction terminal extension region, a junction gradient doping region and a plurality of field limiting rings arranged on the N-type substrate, the junction terminal extension region is connected to the junction gradient doping region, the depth of the junction gradient doping region gradually decreases along the direction away from the junction terminal extension region, the plurality of field limiting rings are arranged at one end of the junction gradient doping region away from the junction terminal extension region, and the distances of the plurality of field limiting rings relative to the junction gradient doping region gradually increase; the junction terminal extension region, the junction gradient doping region and the plurality of field limiting rings are doped with P-type ions; a groove arranged on the N-type substrate, the groove being arranged at the field limiting ring farthest from the junction gradient doping region and away from the junction One side of the gradient doping area; polysilicon is deposited in the groove; the P-well area and the cut-off ring N+ area are arranged on the N-type substrate, the P-well area is connected to the junction terminal extension area, and the cut-off ring N+ area is arranged on the side of the groove away from the field limiting ring; an oxide layer is arranged on the surface of the N-type substrate; a polysilicon field plate is arranged on the surface of the target area of ​​the oxide layer, and the target area is an area of ​​a preset width covering the edges of multiple field limiting rings; a metal layer is arranged on the surface of the P-well area, the surface of the part of the junction terminal extension area close to the P-well area, the top of the multiple field limiting rings, the surface of the cut-off ring N+ area, and the surface of the part of the oxide layer close to the cut-off ring N+ area. Through the composite terminal structure including the junction terminal extension area, the junction gradient doping area, the multiple field limiting rings, the groove and the polysilicon field plate, the maximum electric field strength of the chip can be effectively reduced and the voltage resistance performance of the device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a schematic diagram of a terminal structure of a power device according to an embodiment of the present invention;

[0043] Figure 2 is a schematic diagram of a terminal structure of another power device according to an embodiment of the present invention;

[0044] Figure 3 is a flowchart of the steps of a method for manufacturing a terminal structure of a power device according to an embodiment of the present invention;

[0045] Figure 4 It is a structural diagram of a terminal structure manufacturing of a power device according to an embodiment of the present invention;

[0046] Figure 5 It is a structural diagram of another terminal structure manufacturing of a power device according to an embodiment of the present invention;

[0047] Figure 6 It is a structural diagram of another terminal structure manufacturing of a power device according to an embodiment of the present invention;

[0048] Figure 7 It is a structural diagram of another terminal structure manufacturing of a power device according to an embodiment of the present invention;

[0049] Figure 8 It is a structural diagram of another terminal structure manufacturing of a power device according to an embodiment of the present invention;

[0050] Fig. 9 It is a structural diagram of another terminal structure manufacturing of a power device according to an embodiment of the present invention;

[0051] Fig.10 is an electric field strength curve of a terminal structure of a power device according to an embodiment of the present invention;

[0052] Fig.11 is a concentration-dependent withstand voltage curve of a single-zone JTE terminal in an embodiment of the present invention;

[0053] Fig.12 It is a concentration-dependent withstand voltage curve of a terminal structure of a power device according to an embodiment of the present invention.

[0054] Figure numerals: N-type substrate 101, junction termination extension region 102, junction gradient doping region 103, field limiting ring 104, trench 105, P-well region 106, cut-off ring N+ region 107, oxide layer 108, polysilicon field plate 109, metal layer 110, N+ type buffer layer 111, P+ type collector region 112, collector terminal 113. DETAILED DESCRIPTION

[0055] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] Power semiconductor devices are one of the core components of power electronic circuits and are widely used in automobiles, power supplies, and motors. At present, the terminals of power semiconductor devices have a lateral terminal structure (Junction Termination Extension, JTE). However, the surface injection dose of the JTE terminal structure is relatively low, basically at the order of 1e12. In the absence of field plate protection, it is greatly affected by the charge introduced by the process line.

[0057] Modern power devices are mainly formed by connecting tens of thousands of identical cells in parallel inside the source region. The surface voltage of each cell is roughly the same, but the voltage between the terminal cell and the substrate is very different. Some measures need to be taken to reduce the surface electric field and increase the breakdown voltage. Modern silicon power devices generally adopt shallow planar structures. In the design of high-voltage devices, field limiting rings are often used to reduce the surface electric field concentration caused by the junction curvature effect and increase the breakdown voltage. However, this structure will significantly increase the chip area. In addition, the planar field limiting ring often has a peak electric field at the corner of the injection junction, causing the device breakdown characteristics to degrade. In order to further increase the junction depth and reduce the peak electric field at the corner of the injection junction, a trench field limiting ring terminal structure can be used to increase the junction depth. However, the use of a trench field limiting ring structure terminal also has disadvantages. The reduction of the peak electric field will increase the expansion capacity of the lateral space charge region of the field limiting ring terminal, resulting in an increase in the terminal area.

[0058] For the terminals of power devices, due to the high surface injection dose of the main junction ring, the specific injection dose is in the order of 1e12~1e15 / cm-2, which makes the terminal structure breakdown at the corner of the main junction, that is, the electric field strength borne by the corner of the main junction is the largest. However, in the actual process, due to the deviation of the injection dose of the production line machine, the JTE lateral junction terminal extension structure will be affected, and the concentration will be low, so the breakdown will occur at the JTE lateral junction terminal extension structure, resulting in poor terminal reliability and insufficient withstand voltage in the actual wafer.

[0059] One of the core concepts of the embodiments of the present invention is to solve the problems of insufficient withstand voltage and concentration dose sensitivity of traditional JTE terminals through a composite terminal structure including a junction terminal extension region, a junction gradient doping region, multiple field limiting rings, trenches and polysilicon field plates.

[0060] Reference Figure 1 , shows a schematic diagram of a terminal structure of a power device according to an embodiment of the present invention, which may specifically include the following structure:

[0061] N-type substrate 101 .

[0062] N-type substrate refers to the use of silicon (or other semiconductor materials) doped with donor impurities (such as phosphorus, arsenic, etc.) as the base material in the manufacture of semiconductor devices. The donor impurities in the N-type substrate will provide free electrons in the material, making the material as a whole negatively charged (Negative), so it is called N-type. Characteristics of N-type substrate: high electron concentration, N-type substrate is doped with donor impurities, so it has a high free electron concentration, and electrons are the majority carriers; low hole concentration, due to the high electron concentration, the hole (positive charge carrier) concentration is relatively low, and it is a minority carrier; high conductivity, due to the presence of free electrons, the N-type substrate has a high conductivity, which is suitable for application scenarios that require high conductivity.

[0063] A junction terminal extension region 102, a junction gradient doping region 103 and a plurality of field limiting rings 104 are provided on the N-type substrate 101, the junction terminal extension region 102 is connected to the junction gradient doping region 103, the depth of the junction gradient doping region 103 gradually decreases in a direction away from the junction terminal extension region 102, the plurality of field limiting rings 104 are provided at one end of the junction gradient doping region 103 away from the junction terminal extension region 102, and the distances of the plurality of field limiting rings 104 relative to the junction gradient doping region 103 gradually increase; the junction terminal extension region 102, the junction gradient doping region 103 and the plurality of field limiting rings 104 are doped with P-type ions.

[0064] The junction terminal extension region 102 is a key technology for improving the withstand voltage performance of semiconductor devices. By introducing a lightly doped extension region at the edge of the PN junction of the device to form a buffer layer, the electric field concentration phenomenon at the edge of the PN junction is effectively reduced, and the withstand voltage capability of the device is improved. At the edge of the PN junction, the electric field is usually concentrated in a smaller area, resulting in excessive local electric field strength, which is easy to cause breakdown. By introducing a lightly doped extension region at the edge of the PN junction, the electric field distribution is made more uniform, avoiding the problem of excessive local electric field. Through the buffering effect of the extension region, the withstand voltage capability of the device is significantly enhanced, and it can withstand higher reverse voltages, which can effectively increase the breakdown voltage of the device and reduce leakage current. It reduces the sensitivity to doping concentration, making the device performance more stable.

[0065] The junction gradient doping region 103 optimizes the electric field distribution by introducing a gradient distribution of doping concentration in the PN junction region, thereby improving the withstand voltage performance of the device. VLD (Variable Latticed Doping) is a special gradient doping technology that further optimizes the electric field distribution, reduces the maximum electric field strength, and improves the withstand voltage capability of the device by precisely controlling the change of doping concentration. In the traditional abrupt junction, the doping concentration on both sides of the PN junction is abrupt, resulting in the concentration of the electric field at the junction edge, which is easy to cause breakdown. By introducing the gradient doping region, the doping concentration gradually changes from one side to the other side, and the electric field distribution is more uniform, avoiding the problem of excessive local electric field, and can effectively disperse the electric field, reduce the maximum electric field strength, thereby improving the breakdown voltage of the device. By optimizing the doping distribution, the withstand voltage capability of the device is significantly enhanced. The gradient doping technology reduces the sensitivity to the doping concentration through structural optimization, making the device performance more stable. VLD technology allows the doping concentration to change gradually in the junction area to form a smooth doping gradient. The change in doping concentration can be achieved through processes such as ion implantation and diffusion. By precisely controlling the doping gradient, the electric field distribution is made more uniform, reducing the maximum electric field strength, and significantly improving the device's voltage resistance.

[0066] The field limiting ring (FLR) 104 forms an electric field limiting structure by introducing a series of annular doping regions at the edge of the PN junction of the device, thereby effectively reducing the electric field concentration phenomenon at the edge of the PN junction and improving the voltage resistance of the device. The working principle of the field limiting ring: At the edge of the PN junction, the electric field is usually concentrated in a smaller area, resulting in excessive local electric field strength, which is easy to cause breakdown. By introducing a series of annular doping regions at the edge of the PN junction, the electric field distribution is made more uniform, avoiding the problem of excessive local electric field. Through the buffering effect of the annular doping region, the voltage resistance of the device is significantly enhanced and can withstand higher reverse voltages. The core of FLR is to introduce a series of annular doping regions at the edge of the PN junction, which are usually opposite to the doping type of the substrate. It is usually composed of multiple annular doping regions to form a multi-level structure. The doping concentration and width of each annular doping region gradually change to form a buffer layer to further optimize the electric field distribution.

[0067] A trench 105 is provided in the N-type substrate 101 , and the trench 105 is provided on a side of the field limiting ring 104 farthest from the junction gradient doping region 103 away from the junction gradient doping region 103 ; polysilicon is deposited in the trench 105 .

[0068] A P-well region 106 and a stop ring N+ region 107 are provided in the N-type substrate 101 . The P-well region 106 is connected to the junction terminal extension region 102 . The stop ring N+ region 107 is provided on a side of the trench 105 away from the field limiting ring 104 .

[0069] The P-well region (P-Well) 106 is a region formed by injecting P-type impurities (such as boron) into an N-type substrate, and is used to isolate and construct NMOS devices. In the CMOS process, the P-well region is used to isolate NMOS transistors to avoid interference between different transistors. The P-well region isolates the NMOS device from the N-type substrate to form a local P-type region. The source and drain of the NMOS transistor can be formed in the P-well region. These regions are usually N-type doped. The P-well region forms a PN junction with the N-type source and drain region to constitute the basic structure of the NMOS transistor, which can reduce the formation of parasitic PNP transistors, thereby reducing parasitic effects and improving device performance.

[0070] Guard Ring N+ region 107, Guard Ring (GR) is a terminal technology used to improve the voltage resistance performance of semiconductor devices. N+ region refers to an N-type region with a higher doping concentration, which is usually used to construct a conductive channel or terminal structure of a device. The working principle of the guard ring: in the edge area of ​​the PN junction, the electric field is usually concentrated in a smaller area, resulting in excessive local electric field strength, which easily causes breakdown. The guard ring introduces a series of annular doping regions at the edge of the PN junction to make the electric field distribution more uniform, avoiding the problem of excessive local electric field. Through the buffering effect of the annular doping region, the voltage resistance of the device is significantly enhanced, and it can withstand higher reverse voltages, which can effectively increase the breakdown voltage of the device, while reducing leakage current and reducing sensitivity to doping concentration, making the device performance more stable.

[0071] An oxide layer 108 is disposed on the surface of the N-type substrate 101 .

[0072] The oxide layer 108 is an ILD (Interlayer Dielectric) oxide layer region. The function of the ILD oxide layer region is as follows: the main function of the ILD oxide layer region is to isolate the electrical connections between different metal layers to prevent short circuits and leakage. The oxide layer is filled between metal layers to ensure electrical insulation between the layers. The ILD oxide layer region provides mechanical support for the metal wiring of the chip to prevent physical contact between metal layers. The high hardness and stability of the oxide layer help protect the chip structure. The ILD oxide layer region achieves surface flatness through a chemical mechanical polishing process to provide a flat surface for subsequent processes (such as metal wiring), which can protect the underlying devices and metal wiring from environmental influences (such as moisture, pollutants, etc.).

[0073] The polysilicon field plate 109 is disposed on the surface of the target area of ​​the oxide layer 108, and the target area is an area of ​​a preset width covering the edges of the plurality of field limiting rings 104. The polysilicon field plate 109 can effectively reduce the electric field concentration phenomenon at the edge of the PN junction and improve the withstand voltage capability of the device.

[0074] A metal layer 110 is provided on the surface of the P-well region 106, the surface of a portion of the junction termination extension region 102 close to the P-well region 106, the top of the plurality of field limiting rings 104, the surface of the cut-off ring N+ region 107, and the surface of a portion of the oxide layer 108 close to the cut-off ring N+ region 107. The metal layer 110 provided on the surface of the P-well region 106 and the surface of a portion of the junction termination extension region 102 close to the P-well region 106 is a front metal layer, and the front metal layer can form an ohmic contact with Si (silicon).

[0075] The terminal structure of the power device of the embodiment of the present invention comprises an N-type substrate; a junction terminal extension region, a junction gradient doping region and a plurality of field limiting rings arranged in the N-type substrate, the junction terminal extension region is connected to the junction gradient doping region, the depth of the junction gradient doping region gradually decreases along the direction away from the junction terminal extension region, the plurality of field limiting rings are arranged at one end of the junction gradient doping region away from the junction terminal extension region, and the distances of the plurality of field limiting rings relative to the junction gradient doping region gradually increase; the junction terminal extension region, the junction gradient doping region and the plurality of field limiting rings are doped with P-type ions; a groove arranged in the N-type substrate, the groove being arranged at the field limiting ring farthest from the junction gradient doping region and away from the junction gradient doping region One side of the variable doping area; polysilicon is deposited in the groove; the P-well area and the cut-off ring N+ area are arranged in the N-type substrate, the P-well area is connected to the junction terminal extension area, and the cut-off ring N+ area is arranged on the side of the groove away from the field limiting ring; an oxide layer is arranged on the surface of the N-type substrate; a polysilicon field plate is arranged on the surface of the target area of ​​the oxide layer, and the target area is an area of ​​a preset width covering the edges of the multiple field limiting rings; a metal layer is arranged on the surface of the P-well area, the surface of the partial area of ​​the junction terminal extension area close to the P-well area, above the multiple field limiting rings, the surface of the cut-off ring N+ area, and the surface of the partial area of ​​the oxide layer close to the cut-off ring N+ area. Through the composite terminal structure including the junction terminal extension area, the junction gradient doping area, multiple field limiting rings, the groove and the polysilicon field plate, the maximum electric field strength of the chip can be effectively reduced and the voltage resistance performance of the device can be improved.

[0076] Reference Figure 2 In the embodiment of the present invention, the N-type substrate 101 is an N-type substrate, and the terminal structure further includes:

[0077] An N+ type buffer layer 111 is formed on the other side of the N- type substrate 101 .

[0078] The N-type substrate 101 is a lightly doped N-type material with a higher resistivity and a lower carrier concentration. The N+ type buffer layer 111 is a highly doped N-type material with a lower resistivity and a higher carrier concentration. The introduction of the N+ type buffer layer on the N-type substrate can optimize the electric field distribution and reduce the electric field concentration phenomenon at the edge of the PN junction. The N+ type buffer layer 111 can effectively disperse the electric field and reduce the maximum electric field strength, thereby increasing the breakdown voltage of the device. By optimizing the electric field distribution, the voltage resistance of the device is significantly enhanced.

[0079] A P+ type collector region 112 is formed on the N+ type buffer layer 111 .

[0080] The P+ collector region 112 is a highly doped P-type material with lower resistivity and higher hole concentration. Introducing the P+ collector region 112 on the N+ buffer layer 111 can optimize the electric field distribution and reduce the electric field concentration phenomenon at the edge of the PN junction.

[0081] A collector terminal 113 is formed on the P+ type collector region.

[0082] The collector terminal 113 forms an ohmic metal contact on the back. Ohmic metal refers to a metal material used to form a low-resistance, non-rectifying electrical contact with a semiconductor material (such as silicon) in the manufacture of semiconductor devices. The main function of the ohmic metal is to achieve low-loss current transmission between the semiconductor and the external circuit to ensure the normal operation of the device. The ohmic metal is Ni, Ti or Ti / Ni alloy and AlCu, etc.

[0083] In the embodiment of the present invention, the width of each field limiting ring is 5-12um, and the width of each field limiting ring is the same. For example, the width of the field limiting ring injection opening is 5-12um, the width of the field limiting ring is in the range of 3-8um, and the minimum spacing of the field limiting ring is in the range of 8-13um. Of course, the specific size can be set according to actual needs in actual applications.

[0084] In the embodiment of the present invention, the coverage range of the edges of the plurality of field limiting rings is 0.5 to 1.5 um. The polysilicon field plate 109 needs to cover the edges of the field limiting ring 104 by 0.5 to 1.5 um.

[0085] In the embodiment of the present invention, the depth of the groove is in the range of 4-6 um, and the width of the groove is in the range of 0.6-2 um. Of course, the specific dimensions can be set according to actual needs in practical applications.

[0086] In the embodiment of the present invention, the thickness of the metal layer is in the range of 3-5 um.

[0087] Reference Figure 3 , a flowchart of a method for manufacturing a terminal structure of a power device according to an embodiment of the present invention, which is used to manufacture the terminal structure of the power device as described above, may specifically include the following steps:

[0088] Step 201, providing an N-type substrate.

[0089] Reference Figure 4 , providing an N-type substrate, which is a lightly doped N-type material with a low doping concentration and a high resistivity.

[0090] Step 202, forming a junction terminal extension region 102, a junction gradient doping region 103 and a plurality of field limiting rings 104 on the N-type substrate 101; the junction terminal extension region 102 is connected to the junction gradient doping region 103, the depth of the junction gradient doping region 103 gradually decreases in a direction away from the junction terminal extension region 102, and the plurality of field limiting rings 104 are arranged at one end of the junction gradient doping region 103 away from the junction terminal extension region 102.

[0091] Reference Figure 5 On the basis of the N-type substrate 101, a P-type JTE injection window, a VLD gradient doping injection window and a field limiting ring injection window are made by growing a dielectric mask, photolithography and etching, and then P-type boron ion doping is performed, and the doping ion concentration range is about 1e12-1e13, and a high-temperature annealing treatment is performed, the annealing temperature is about 1050-1150C, and the time is about 200-350min, to form a junction terminal extension region 102, a junction gradient doping region 103 and a plurality of field limiting rings 104.

[0092] Growth medium mask is usually used to control the direction and area of ​​epitaxial growth. Growth medium mask forms a layer of mask material on the surface of the wafer to prevent the growth of epitaxial material in a specific area, thereby achieving precise control of the device structure. The role of growth medium mask: Growth medium mask is used to define the area of ​​epitaxial growth and prevent epitaxial material from growing in unnecessary areas. Through the design of the mask, precise control of the device structure can be achieved; the electrical performance of the device can be optimized, such as reducing leakage current, increasing breakdown voltage, etc. It can be used to optimize the electric field distribution and improve the voltage resistance of the device.

[0093] Photolithography is used to define micron- or nanometer-scale patterns and structures on semiconductor wafers. Photolithography technology transfers the designed pattern to the wafer surface through photosensitive materials (photoresists) and optical systems, thereby achieving precise control of the device structure. The process flow of photolithography: evenly coat a layer of photoresist on the surface of the wafer. Photoresist is a photosensitive material and is divided into two types: positive photoresist and negative photoresist. In positive photoresist, the exposed area is dissolved and the unexposed area is retained. In negative photoresist, the exposed area is retained and the unexposed area is dissolved. Align the mask with the wafer to ensure that the pattern on the mask accurately matches the position on the wafer. The mask contains the designed pattern, and the pattern is projected onto the wafer surface through an optical system. Use a light source (such as ultraviolet light, deep ultraviolet light, extreme ultraviolet light, etc.) to expose the photoresist through the mask, and the photoresist in the exposed area is exposed. Biochemical reaction changes its solubility; the exposed wafer is placed in a developer to dissolve the photoresist in the exposed or unexposed area to form a pattern. After development, a pattern corresponding to the mask pattern will be left on the wafer surface; the pattern is transferred to the material layer (such as an oxide layer, a polysilicon layer, etc.) on the wafer surface through an etching process (such as dry etching, wet etching) or an ion implantation process. After etching or ion implantation, a structure corresponding to the photoresist pattern will be formed on the wafer surface; the remaining photoresist is removed through a stripping process (such as wet stripping, plasma stripping) to complete the photolithography process.

[0094] After the ion implantation or diffusion process, the doped atoms are usually in an inactive state. High-temperature annealing can make the doped atoms enter the lattice position and become free carriers, thereby improving the conductivity of the semiconductor. The ion implantation or diffusion process will introduce lattice damage (such as vacancies, interstitial atoms, etc.) into the semiconductor material. High-temperature annealing can repair these damages, restore the integrity of the lattice, and improve the performance and reliability of the device. In the area where the metal contacts the silicon, high-temperature annealing can promote the reaction between the metal and silicon to form a low-resistance metal silicide. The metal silicide has a lower contact resistance and is a key step in forming an ohmic contact. High-temperature annealing can optimize the electrical properties of the device, such as reducing leakage current, increasing breakdown voltage, and improving electric field distribution.

[0095] In step 203 , a trench 105 is formed in the N-type substrate 101 . The trench 105 is disposed on a side of the field limiting ring 104 farthest from the junction gradient doping region 103 and away from the junction gradient doping region 103 .

[0096] Reference Figure 6 A trench 105 is formed on the right side of the field limiting ring by processes such as photolithography, etching, sacrificial oxidation, gate oxide oxidation, polysilicon deposition and etching, and oxide deposition.

[0097] Step 204: deposit polysilicon in the trench.

[0098] Polysilicon deposition and etching are performed to fill the trenches with polysilicon.

[0099] Step 205 , forming a P-well region 106 and a cutoff ring N+ region 107 on the N-type substrate 101 ; the P-well region 106 is connected to the junction terminal extension region 102 , and the cutoff ring N+ region 107 is arranged on a side of the trench 105 away from the field limiting ring 104 .

[0100] Reference Figure 7 , through the processes of growing dielectric mask, photolithography, etching, ion implantation, etc., a P well region 106 and a cutoff ring N+ region 107 are formed, wherein the P type ion concentration ranges from 5e12-5e13, and the N type ion concentration ranges from 1e14-2e15, and corresponding annealing treatment is performed, the annealing temperature is about 1050-1200°C, and the time is about 40-120min.

[0101] Step 206 , growing an oxide layer 108 on the surface of the N-type substrate 101 , and removing the oxide layer 108 corresponding to the surface of the P-well region 106 , the central region of the plurality of field limiting rings 104 , and the surface of the stop ring N+ region 107 .

[0102] Reference Figure 8 , an ILD oxide layer is deposited on the ion implantation area through a deposition process as isolation protection.

[0103] Step 207 , forming a polysilicon field plate 109 on the surface of a target region of the oxide layer 208 ; the target region is a region of a preset width covering the edges of the plurality of field limiting rings.

[0104] Reference Fig. 9 Then, a polysilicon field plate 109 of a certain length and thickness is formed near the field limiting ring. The polysilicon field plate 109 is located on the surface of the oxide layer 108 .

[0105] In step 208, a metal layer 110 is formed on the surface of the P-well region 106, on the surface of a portion of the junction terminal extension region 102 close to the P-well region 106, above the multiple field limiting rings 104, on the surface of the cut-off ring N+ region 107, and on the surface of a portion of the oxide layer 108 close to the cut-off ring N+ region 107.

[0106] Reference Figure 1 , through photolithography, metallization, and lift-off processes, a front metal is formed, and then high-temperature annealing is performed to form an ohmic contact with Si. The ohmic metal is Ni, Ti or Ti / Ni alloy and AlCu.

[0107] The terminal structure of the power device of the embodiment of the present invention comprises an N-type substrate; a junction terminal extension region, a junction gradient doping region and a plurality of field limiting rings arranged in the N-type substrate, the junction terminal extension region is connected to the junction gradient doping region, the depth of the junction gradient doping region gradually decreases along the direction away from the junction terminal extension region, the plurality of field limiting rings are arranged at one end of the junction gradient doping region away from the junction terminal extension region, and the distances of the plurality of field limiting rings relative to the junction gradient doping region gradually increase; the junction terminal extension region, the junction gradient doping region and the plurality of field limiting rings are doped with P-type ions; a groove arranged in the N-type substrate, the groove being arranged at the field limiting ring farthest from the junction gradient doping region and away from the junction gradient doping region One side of the variable doping area; polysilicon is deposited in the groove; the P-well area and the cut-off ring N+ area are arranged in the N-type substrate, the P-well area is connected to the junction terminal extension area, and the cut-off ring N+ area is arranged on the side of the groove away from the field limiting ring; an oxide layer is arranged on the surface of the N-type substrate; a polysilicon field plate is arranged on the surface of the target area of ​​the oxide layer, and the target area is an area of ​​a preset width covering the edges of the multiple field limiting rings; a metal layer is arranged on the surface of the P-well area, the surface of the partial area of ​​the junction terminal extension area close to the P-well area, above the multiple field limiting rings, the surface of the cut-off ring N+ area, and the surface of the partial area of ​​the oxide layer close to the cut-off ring N+ area. Through the composite terminal structure including the junction terminal extension area, the junction gradient doping area, multiple field limiting rings, the groove and the polysilicon field plate, the maximum electric field strength of the chip can be effectively reduced and the voltage resistance performance of the device can be improved.

[0108] In an embodiment of the present invention, the N-type substrate 101 is an N-type substrate, and the method further includes:

[0109] Performing backside thinning on the N-type substrate at the other side of the N-type substrate;

[0110] Performing high-concentration N-type doping on the N-type substrate on the other side of the N-type substrate to form an N+ type buffer layer 111;

[0111] Performing high-concentration P-type doping on the N+ type buffer layer 111 to form a P+ type collector region 112;

[0112] A metal layer is deposited on the P+ type collector region 112 to form a collector terminal 113 .

[0113] Specifically, refer to Figure 2, and carry out back-side processing. On the back side of the high-resistance semiconductor region of the N-substrate, the chip is first thinned to a suitable thickness through a back-side thinning process, and N-type doping with a concentration gradient is performed twice along the lateral direction of the device to obtain a heavily doped N+ type buffer layer 111 with an electric field cutoff effect. P-type heavy doping is performed on the buffer layer to obtain a P+ type collector region 112. Finally, a thin metal layer is deposited from the P+ type collector region 112 to lead out as a collector terminal 113, and an ohmic metal contact is formed on the back side. The ohmic metal is Ni, Ti or Ti / Ni alloy and AlCu.

[0114] In an embodiment of the present invention, the distances between the multiple field limiting rings and the junction gradient doping region gradually increase; the junction terminal extension region, the junction gradient doping region and the multiple field limiting rings are doped with P-type ions; and the width range of each field limiting ring is 5-12um.

[0115] In the embodiment of the present invention, the coverage range of the edges of the plurality of field limiting rings is 0.5-1.5 um.

[0116] In the embodiment of the present invention, the depth of the groove is in the range of 4-6 um, and the width of the groove is in the range of 0.6-2 um.

[0117] In the embodiment of the present invention, the thickness of the metal layer is in the range of 3-5 um.

[0118] Reference Fig.10 , shows an electric field strength curve of a terminal structure of a power device according to an embodiment of the present invention, Fig.10 The figure is the electric field intensity distribution along the horizontal direction of the terminal of the junction terminal extension (JTE) terminal structure and the structure of the present invention at the same length. The result is obtained by the tangent of the electric field distribution diagram after the device BV simulation. The ordinate represents the electric field intensity and the abscissa represents the distance along the horizontal direction of the terminal. The results show that under the same injection concentration, the electric field intensity of the JTE terminal is extremely unevenly distributed in the horizontal direction, and the electric field is concentrated near the main junction and the JTE end area, and its maximum electric field intensity is 2.32e5 V / m. The horizontal distribution of the electric field intensity of the terminal of the present invention is relatively uniform, and its maximum electric field intensity is only 2.23e5V / m, which is smaller than the previous structure, and has better withstand voltage performance.

[0119] Reference Fig.11 , shows a concentration-dependent withstand voltage curve of a single-zone JTE terminal according to an embodiment of the present invention, referring to Fig.12 , shows a concentration-dependent withstand voltage curve of a terminal structure of a power device according to an embodiment of the present invention, wherein the abscissa represents the injection concentration, the ordinate represents the withstand voltage value, and according to Fig.11 and Fig.12It can be seen that the withstand voltage of the single-zone JTE terminal changes dramatically with the change of the injection concentration, and is very sensitive to the concentration change; the BV (breakdown voltage) of the terminal of the present invention changes relatively little with the change of the injection concentration, and the sensitivity to concentration dependence is reduced, which is beneficial to the stability of the terminal structure of the power device.

[0120] Based on the traditional single-zone JTE terminal structure, the embodiment of the present invention constructs a composite terminal structure of junction gradient doping + field limiting ring + field plate + groove through reasonable structural design. Since the terminal structure has a gradient doping concentration, the electric field concentration phenomenon in the horizontal direction is significantly weakened, and the maximum concentrated electric field intensity is reduced by nearly 10% relative to the single-zone JTE terminal structure; in addition, the terminal structure of the present invention is less affected by changes in doping concentration, thereby improving the voltage resistance stability of the device.

[0121] Since trench technology is combined with the junction gradient doping terminal, on the one hand, the overall length of the terminal can be reduced and the cost can be reduced; on the other hand, the voltage resistance performance of the terminal can be optimized, the electric field concentration of the traditional JTE terminal can be improved, and the leakage current and the dependence on the doping concentration can be reduced.

[0122] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0123] An embodiment of the present invention discloses a chip, including the terminal structure of the power device as described above.

[0124] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0125] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0126] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0127] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0129] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0130] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0131] The terminal structure, manufacturing method and chip of a power device provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A terminal structure of a power device, characterized in that: The terminal structure comprises: N-type substrate; A junction terminal extension region, a junction gradient doping region and a plurality of field limiting rings are provided in the N-type substrate, the junction terminal extension region is connected to the junction gradient doping region, the depth of the junction gradient doping region gradually decreases along a direction away from the junction terminal extension region, the plurality of field limiting rings are provided at one end of the junction gradient doping region away from the junction terminal extension region, and the distances of the plurality of field limiting rings relative to the junction gradient doping region gradually increase; the junction terminal extension region, the junction gradient doping region and the plurality of field limiting rings are doped with P-type ions; A groove is provided in the N-type substrate, wherein the groove is provided on a side of the field limiting ring farthest from the junction gradient doping region and away from the junction gradient doping region; polysilicon is deposited in the groove; A P-well region and a cut-off ring N+ region are provided in the N-type substrate, the P-well region is connected to the junction terminal extension region, and the cut-off ring N+ region is provided on a side of the trench away from the field limiting ring; An oxide layer disposed on the surface of the N-type substrate; A polysilicon field plate disposed on a surface of a target region of the oxide layer, wherein the target region is a region of a preset width covering edges of the plurality of field limiting rings; A metal layer is provided on the surface of the P-well region, the surface of a portion of the junction terminal extension region close to the P-well region, above the multiple field limiting rings, the surface of the cut-off ring N+ region, and the surface of a portion of the oxide layer close to the cut-off ring N+ region.

2. The terminal structure of the power device according to claim 1, characterized in that: The N-type substrate is an N-type substrate, and the terminal structure further includes: An N+ type buffer layer formed on the other side of the N- type substrate; A P+ type collector region formed on the N+ type buffer layer; A collector terminal is formed on the P+ type collector region.

3. The terminal structure of the power device according to claim 1, characterized in that: The width of each field limiting ring is in the range of 5-12 um.

4. The terminal structure of the power device according to claim 1, characterized in that: The coverage range of the edges of the multiple field limiting rings is 0.5-1.5 um.

5. The terminal structure of the power device according to claim 1, characterized in that: The depth of the groove is in the range of 4-6 um, and the width of the groove is in the range of 0.6-2 um.

6. The terminal structure of a power device according to claim 1, characterized in that: The thickness of the metal layer is in the range of 3-5 um.

7. A method for manufacturing a terminal structure of a power device, characterized in that: A method for manufacturing a terminal structure of a power device according to any one of claims 1 to 6, the method comprising: Providing an N-type substrate; A junction terminal extension region, a junction gradient doping region and a plurality of field limiting rings are formed on the N-type substrate; the junction terminal extension region is connected to the junction gradient doping region, the depth of the junction gradient doping region gradually decreases in a direction away from the junction terminal extension region, and the plurality of field limiting rings are arranged at one end of the junction gradient doping region away from the junction terminal extension region; In the N-type substrate, a groove is formed, wherein the groove is arranged on a side of the field limiting ring farthest from the junction gradient doping region and away from the junction gradient doping region; depositing polysilicon in the trench; A P-well region and a cut-off ring N+ region are formed on the N-type substrate; the P-well region is connected to the junction terminal extension region, and the cut-off ring N+ region is arranged on a side of the trench away from the field limiting ring; Growing an oxide layer on the surface of the N-type substrate, and removing the oxide layers corresponding to the surfaces of the P-well region, the central regions of the plurality of field limiting rings, and the cut-off ring N+ region; Generating a polysilicon field plate on a surface of a target region of the oxide layer; the target region is a region of a preset width covering edges of the plurality of field limiting rings; A metal layer is generated on the surface of the P-well region, on the surface of a portion of the junction terminal extension region close to the P-well region, above the multiple field limiting rings, on the surface of the cutoff ring N+ region, and on the surface of a portion of the oxide layer close to the cutoff ring N+ region.

8. The method for manufacturing a terminal structure of a power device according to claim 7, characterized in that: The N-type substrate is an N-type substrate, and the method further comprises: Performing backside thinning on the N-type substrate at the other side of the N-type substrate; Performing high-concentration N-type doping on the N-type substrate on the other side of the N-type substrate to form an N+ type buffer layer; Performing high-concentration P-type doping on the N+ type buffer layer to form a P+ type collector region; A metal layer is deposited on the P+ type collector region to form a collector terminal.

9. The method for manufacturing a terminal structure of a power device according to claim 7, characterized in that: The distances between the multiple field limiting rings and the junction gradient doping region gradually increase; the junction terminal extension region, the junction gradient doping region and the multiple field limiting rings are doped with P-type ions; and the width range of each field limiting ring is 5-12um.

10. The method for manufacturing a terminal structure of a power device according to claim 7, characterized in that: The coverage range of the edges of the multiple field limiting rings is 0.5-1.5 um.

11. The method for manufacturing a terminal structure of a power device according to claim 7, characterized in that: The depth of the groove is in the range of 4-6 um, and the width of the groove is in the range of 0.6-2 um.

12. The method for manufacturing a terminal structure of a power device according to claim 7, characterized in that: The thickness of the metal layer is in the range of 3-5 um.

13. A chip comprising the terminal structure of the power device according to any one of claims 1 to 6.

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