Graphene / gallium nitride Van der Waals heterojunction interface potential barrier regulation and control method and application

Abstract

The invention discloses a graphene / gallium nitride Van der Waals heterojunction interface potential barrier regulation and control method and application. The junction interface potential barrier regulation and control method comprises the step of inserting a selected number of hexagonal boron nitride layers between a graphene layer and a gallium nitride substrate so as to regulate the interface potential barrier of the graphene / gallium nitride Van der Waals heterojunction formed by the graphene layer and the gallium nitride substrate. The graphene / gallium nitride Van der Waals heterojunction comprises a gallium nitride substrate, a selected number of hexagonal boron nitride layers and a graphene layer which are stacked in sequence. According to the technical scheme provided by the invention, the selected number of hexagonal boron nitride layers are inserted between the graphene layer and the gallium nitride substrate of the graphene / gallium nitride Van der Waals heterojunction, so that the interface potential barrier of the graphene / gallium nitride Van der Waals heterojunction can be accurately regulated and controlled.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a graphene / gallium nitride van der Waals heterojunction interface barrier regulation method and application. Background Art

[0002] The 2D / 3D mixed dimensional heterojunction interface between graphene and semiconductor formed by van der Waals forces is called a van der Waals heterojunction. The heterojunction formed by traditional epitaxial growth is always accompanied by problems such as interface stress, defects, and atomic interpenetration at the interface due to the lattice mismatch of the two different materials. The characteristic of the graphene / semiconductor van der Waals heterojunction is that there is no chemical bond at the interface of graphene and semiconductor, and they are combined together by weak van der Waals forces. This heterojunction formed by stacking is not affected by lattice matching. At the interface, both graphene and semiconductor can maintain the original lattice structure, electronic and optoelectronic properties, and have excellent physical and chemical stability.

[0003] Gallium nitride (GaN), as an outstanding representative of Group III nitride semiconductor materials, has been widely used in optoelectronic devices such as short-wavelength light-emitting diodes, lasers and ultraviolet detectors, as well as high-temperature, high-power, and high-frequency microwave electronic devices.

[0004] The application research of graphene and nitride semiconductor integration was first conducted on GaN materials. Based on the graphene / GaN van der Waals heterojunction, people have constructed many novel functional devices, such as Schottky photodiodes, or become a structural component of complex systems, such as Schottky junctions in Schottky field effect transistors and passivation layers in high electron mobility transistors (HEMTs). Therefore, the integration of graphene and semiconductor devices, especially in the application of III-nitride semiconductor devices, which are called the third-generation semiconductors, including Internet of Things sensors, solid-state lighting, solar cells, photoelectric detection, information storage, and biomedicine, has shown unique charm and broad application prospects.

[0005] The interface barrier is a key factor affecting device performance. Therefore, the measurement and control of the interface barrier of graphene / GaN heterojunction is particularly important for the development of future devices. However, there is no effective technical solution in the current existing technology that can accurately control the interface barrier of graphene / GaN heterojunction. Summary of the invention

[0006] In view of the deficiencies in the prior art, the object of the present invention is to provide a method for regulating the interface barrier of a graphene / gallium nitride van der Waals heterojunction and its application.

[0007] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes:

[0008] In a first aspect, the present invention provides a method for regulating the potential barrier of a graphene / gallium nitride van der Waals heterojunction interface, comprising:

[0009] A selected number of hexagonal boron nitride layers are inserted between the graphene layer and the gallium nitride substrate to adjust the interface barrier of the graphene / gallium nitride van der Waals heterojunction formed by the graphene layer and the gallium nitride substrate.

[0010] In a second aspect, the present invention further provides a graphene / gallium nitride van der Waals heterojunction, which includes a gallium nitride substrate, a selected number of hexagonal boron nitride layers, and a graphene layer stacked in sequence.

[0011] In a third aspect, the present invention further provides a method for preparing a graphene / gallium nitride van der Waals heterojunction, comprising:

[0012] Providing a first assembly, wherein the first assembly includes a first polymer film and a hexagonal boron nitride layer attached to one side of the first polymer film;

[0013] Laminating the first assembly to a gallium nitride substrate, with the hexagonal boron nitride layer facing the gallium nitride substrate, and removing the first polymer film to obtain a second assembly;

[0014] Optionally, the second assembly is attached to the new first assembly and the first polymer film is removed, and the cycle is repeated several times to obtain a stacked assembly;

[0015] The second assembly or stacked assembly is bonded to a third assembly, wherein the third assembly includes a second polymer film and a graphene layer attached to one side of the second polymer film, wherein the graphene layer faces the hexagonal boron nitride layer, and the second polymer film is removed to obtain a graphene / gallium nitride van der Waals heterojunction.

[0016] In a fourth aspect, the present invention further provides a method for characterizing an interface barrier of a graphene / gallium nitride van der Waals heterojunction, comprising:

[0017] Providing a graphene / gallium nitride van der Waals heterojunction prepared by the above preparation method;

[0018] Forming metal microspheres on the non-covered surface of the gallium nitride substrate, and contacting the metal microspheres with a dual-electrode probe to verify that there is ohmic contact between the metal microspheres and the gallium nitride substrate;

[0019] Under the premise that the metal microspheres and the gallium nitride substrate are in ohmic contact, an IV curve between the graphene layer and the gallium nitride substrate is measured, and an interface barrier between the graphene layer and the gallium nitride substrate is calculated according to the IV curve.

[0020] Based on the above technical solution, compared with the prior art, the beneficial effects of the present invention at least include:

[0021] The technical solution provided by the present invention can achieve precise control of the interface barrier of the graphene / gallium nitride van der Waals heterojunction by inserting a selected number of hexagonal boron nitride layers between the graphene layer and the gallium nitride substrate of the graphene / gallium nitride van der Waals heterojunction.

[0022] The above description is only an overview of the technical solution of the present invention. In order to enable those skilled in the art to more clearly understand the technical means of the present application and implement them according to the contents of the specification, the following is a description of the preferred embodiments of the present invention in conjunction with detailed drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is an IV test curve diagram of n-type device samples with different numbers of hexagonal boron nitride layers provided by a typical implementation case of the present invention;

[0024] Figure 2a It is a schematic diagram of the ideal factor calculation process of an n-type device sample without a hexagonal boron nitride layer provided in a typical implementation case of the present invention;

[0025] Figure 2b This is a schematic diagram of the ideal factor calculation process of an n-type device sample with a single-layer hexagonal boron nitride layer provided in a typical implementation case of the present invention;

[0026] Figure 3 This is a graph showing the variation of the ideal factor of n-type device samples with different numbers of hexagonal boron nitride layers provided in a typical implementation case of the present invention;

[0027] Figure 4 It is a graph showing the variation of the interface barrier height of n-type device samples with different numbers of hexagonal boron nitride layers provided by a typical implementation case of the present invention;

[0028] Figure 5 is an IV test curve diagram of n-type device samples with different numbers of hexagonal boron nitride layers provided by another typical embodiment of the present invention;

[0029] Figure 6a It is a schematic diagram of the ideal factor calculation process of an n-type device sample without a hexagonal boron nitride layer provided by another typical embodiment of the present invention;

[0030] Figure 6b This is a schematic diagram of the ideal factor calculation process of an n-type device sample with a single-layer hexagonal boron nitride layer provided in another typical embodiment of the present invention;

[0031] Figure 7 is a graph showing the variation of the ideal factor of n-type device samples with different numbers of hexagonal boron nitride layers provided by another typical implementation example of the present invention;

[0032] Figure 8This is a diagram of the variation of the interface barrier height of n-type device samples with different numbers of hexagonal boron nitride layers provided in another typical implementation case of the present invention. DETAILED DESCRIPTION

[0033] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0035] Moreover, relational terms such as “first” and “second” are merely used to distinguish one component or method step from another with the same name, but do not necessarily require or imply any such actual relationship or order between these components or method steps.

[0036] The present invention is dedicated to designing a graphene / GaN heterojunction structure with adjustable interface potential barriers. The present invention mainly inserts different numbers of h-BN (hexagonal boron nitride) layers into the graphene / GaN interface through a layer-by-layer transfer process, and clarifies the corresponding relationship between different numbers of h-BN layers and the interface spacing. Based on the probe station measurement technology, the change trend of the IV curve after the h-BN is inserted is accurately measured. Based on the thermal electron emission model theory, the potential barrier height formed by the graphene / h-BN / GaN heterojunction is accurately calculated to achieve the purpose of accurate regulation of the potential barrier.

[0037] For the above purpose, the embodiment of the present invention first provides a method for regulating the potential barrier of a graphene / gallium nitride van der Waals heterojunction interface, which comprises the following steps:

[0038] A selected number of hexagonal boron nitride layers are inserted between the graphene layer and the gallium nitride substrate to adjust the interface barrier of the graphene / gallium nitride van der Waals heterojunction formed by the graphene layer and the gallium nitride substrate.

[0039] In some embodiments, the number of the hexagonal boron nitride layers is 1-5.

[0040] The embodiment of the present invention further provides a graphene / gallium nitride van der Waals heterojunction, which includes a gallium nitride substrate, a selected number of hexagonal boron nitride layers, and a graphene layer stacked in sequence.

[0041] Correspondingly, an embodiment of the present invention further provides a method for preparing the above-mentioned graphene / gallium nitride van der Waals heterojunction, which comprises the following steps:

[0042] Providing a first assembly, wherein the first assembly includes a first polymer film and a hexagonal boron nitride layer attached to one side of the first polymer film;

[0043] Laminating the first assembly to a gallium nitride substrate, with the hexagonal boron nitride layer facing the gallium nitride substrate, and removing the first polymer film to obtain a second assembly;

[0044] Optionally, the second assembly is attached to the new first assembly and the first polymer film is removed, and the cycle is repeated several times to obtain a stacked assembly;

[0045] The second assembly or stacked assembly is bonded to a third assembly, wherein the third assembly includes a second polymer film and a graphene layer attached to one side of the second polymer film, wherein the graphene layer faces the hexagonal boron nitride layer, and the second polymer film is removed to obtain a graphene / gallium nitride van der Waals heterojunction.

[0046] In some embodiments, the preparation method may further include the following steps:

[0047] The step of annealing the stack of the gallium nitride substrate, the hexagonal boron nitride layer and the graphene layer.

[0048] In some embodiments, the preparation method may specifically include the following process flow:

[0049] Using a first metal substrate to support the hexagonal boron nitride layer;

[0050] Coating a first polymer solution on the surface of the hexagonal boron nitride layer and drying it to form a film to form the first polymer film;

[0051] The first metal substrate is removed by etching to obtain the first assembly.

[0052] And, in some embodiments, the preparation method may specifically include the following process flow:

[0053] Using a second metal substrate to support the graphene layer;

[0054] Coating a second polymer solution on the surface of the graphene layer and drying the solution to form a second polymer film;

[0055] The second metal substrate is removed by etching to obtain the third assembly.

[0056] As for how to perform van der Waals combination, in some embodiments, the preparation method may specifically include the following process flow:

[0057] The first assembly is floated on the surface of a liquid medium, and the hexagonal boron nitride layer contacts the liquid medium;

[0058] Using the gallium nitride substrate or the second assembly to carry and transfer the first assembly out of the liquid medium;

[0059] and / or, in some embodiments, floating the third assembly on a surface of a liquid medium, wherein the graphene layer contacts the liquid medium;

[0060] The third assembly is carried and transferred from the liquid medium by the second assembly or the stacked assembly.

[0061] As a typical application of the above technical solution, an embodiment of the present invention further provides a method for characterizing the interface barrier of a graphene / gallium nitride van der Waals heterojunction, which comprises the following steps:

[0062] Providing a graphene / gallium nitride van der Waals heterojunction prepared by the preparation method provided in any of the above embodiments;

[0063] Forming metal microspheres on the non-covered surface of the gallium nitride substrate, and contacting the metal microspheres with a dual-electrode probe to verify that there is ohmic contact between the metal microspheres and the gallium nitride substrate;

[0064] Under the premise that the metal microspheres and the gallium nitride substrate are in ohmic contact, an IV curve between the graphene layer and the gallium nitride substrate is measured, and an interface barrier between the graphene layer and the gallium nitride substrate is calculated according to the IV curve.

[0065] In some embodiments, the calculation method of the interface barrier is expressed as:

[0066]

[0067] in, represents the interface potential barrier; k represents the Boltzmann constant; T represents the temperature in Kelvin; q represents the electron charge; A represents the effective contact area between the metal microsphere and the gallium nitride substrate; A * represents the effective Richardson constant; I 0 Represents the reverse saturation current.

[0068] The technical solution of the present invention is further described in detail below through several embodiments and in conjunction with the accompanying drawings. However, the selected embodiments are only used to illustrate the present invention, and do not limit the scope of the present invention.

[0069] Example 1

[0070] This embodiment takes an n-type gallium nitride / graphene device as an example to regulate the interface barrier, as shown below.

[0071] ①Graphene-GaN sample preparation:

[0072] first step:

[0073] Prepare PMMA anisole solution: weigh 3 g of PMMA using an electronic balance, add it to 50 mL of anisole solution in a fume hood, and then move the whole to a heat-collecting constant-temperature magnetic stirrer. Set the temperature to 50°C, the speed of the stirrer to 2, and the time to 6 hours. After PMMA is dissolved, seal the PMMA anisole solution with sealing film and store it in a fume hood. Note: Since anisole is a slightly toxic organic solvent, the experiment must be carried out in a fume hood.

[0074] Prepare potassium persulfate etching solution: use an electronic balance to take 2.7032 mg of potassium persulfate, pour it into 50 ml of ultrapure water, stir with a glass rod in an ultrasonic machine to accelerate dissolution, and prepare 0.2 mM potassium persulfate etching solution.

[0075] Step 2:

[0076] Cut a copper-based graphene sample that is the same size as the surface of the n-type GaN material (or slightly smaller than the GaN material), place it on a clean glass slide, and flatten it with a cleaned cover glass. During the processing, use the back of the tweezers and apply moderate force to slowly press the copper foil to the flattest state visible to the naked eye.

[0077] The cut copper-based graphene sample was fixed on the glue machine, and the vacuum pump of the glue machine was turned on to prevent the sample from being displaced during the spin coating process. 20 μL of PMMA anisole solution (wt% is 6%) was added dropwise to the center of the graphene, and the glue machine was started (multi-step operation: the first step: 200rmp, 15s, acceleration is 100rmp / s; the second step: 800rmp, 15s, acceleration is 100rmp / s), so that the PMMA anisole solution is evenly coated on the graphene surface, and placed in an electronic moisture-proof cabinet to dry naturally after the spin coating is completed; Note: The experiment needs to be carried out in a fume hood.

[0078] After drying, the PMMA / Gr / Cu assembly was placed in a 0.2 mM potassium persulfate etching solution to etch copper (pay attention to the correct direction of the sample during the etching process to prevent the PMMA layer from contacting the potassium persulfate solution);

[0079] After the copper was completely etched, PMMA / Gr was repeatedly washed with deionized water for five times;

[0080] After thorough cleaning, use the cleaned gallium nitride to take out the PMMA / Gr and transfer it to an electronic moisture-proof cabinet to dry naturally.

[0081] After drying, place the PMMA / Gr / GaN sample on a constant temperature soldering station at 100°C for 30 minutes. After the sample is cooled to room temperature naturally, immerse it in cold acetone for 10 minutes to remove PMMA. Then immerse the sample in hot acetone at about 50°C for 30 minutes, immerse it three times, and deeply remove PMMA. Finally, rinse the sample with ultrapure water for 10 minutes to remove acetone. Note: Since acetone is a volatile and flammable organic reagent, this step needs to be performed in a fume hood.

[0082] Gr / GaN annealing process: Place the sample in an annealing furnace at 500°C for 2 hours. After annealing, the preparation of the Gr / GaN sample is completed. The purpose of annealing is to deeply remove the PMMA residual glue on the graphene surface.

[0083] ②Graphene-h-BN-GaN sample preparation:

[0084] Cut a small piece of copper-based boron nitride sample that is the same size as the surface of the n-type GaN material (or slightly smaller than the material), place it on a clean glass slide, and flatten it with a cleaned cover glass. During the processing, use the back of the tweezers and apply moderate force to slowly press the copper foil to the flattest effect visible to the naked eye.

[0085] Fix the copper-based boron nitride sample on the glue machine, turn on the vacuum pump of the glue machine, so that the sample will not be displaced during the spin coating process. Pipette 20μL PMMA anisole solution (wt% is 6%) and drop it into the center of the graphene, start the glue machine (multi-step operation: step 1: 200rmp, 15s, acceleration is 100rmp / s; step 2: 800rmp, 15s, acceleration is 100rmp / s), so that the PMMA anisole solution is evenly coated on the graphene surface. After spin coating, place it in an electronic moisture-proof cabinet to dry naturally; Note: The experiment needs to be carried out in a fume hood. After drying, place PMMA / h-BN / Cu in a potassium persulfate etching solution with a concentration of 0.2mM to etch copper (pay attention to the correct direction of the sample during the etching process to prevent the PMMA layer from contacting the potassium persulfate solution);

[0086] After the copper was completely etched, the PMMA / h-BN was repeatedly washed with deionized water for five times;

[0087] After thorough cleaning, use the cleaned gallium nitride to take out the PMMA / h-BN and transfer it to an electronic moisture-proof cabinet to dry naturally.

[0088] After drying, place the PMMA / h-BN / GaN sample on a constant temperature soldering station at 100°C for 30 minutes. After the sample is cooled to room temperature naturally, immerse it in cold acetone for 10 minutes to remove PMMA. Then immerse the sample in hot acetone at about 50°C for 30 minutes, immerse it three times, and deeply remove PMMA. Finally, rinse the sample with ultrapure water for 10 minutes to remove acetone. Note: Since acetone is a volatile and flammable organic reagent, this step needs to be performed in a fume hood.

[0089] h-BN / GaN annealing process: Place the sample in an annealing furnace at 500°C for 2 hours. After annealing, the preparation of the h-BN / GaN sample is completed. The purpose of annealing is to deeply remove the PMMA residue on the surface of boron nitride.

[0090] Note: If you need to study the effect of different numbers of h-BN insertion layers, you need to repeat the above steps. For example, for Graphene / 5-h-BN / GaN, you need to repeat the above experiment until there are 5 layers of h-BN superimposed on GaN (5 layers of h-BN need to overlap and overlap). Use different numbers of h-BN layers to accurately control the Gr / GaN interface barrier and make Graphene / h-BN / GaN samples with 1-5 layers of h-BN insertion layers.

[0091] After the h-BN layer on the GaN surface is stacked, a layer of graphene is stacked on the last layer of h-BN. Cut a copper-based graphene sample that is the same size as the surface of the n-type or p-type GaN material (or slightly smaller than the material), place it on a clean glass slide, and flatten it with a cleaned cover glass. During the processing, use the back of the tweezers and apply moderate force to slowly press the copper foil to the flattest effect visible to the naked eye.

[0092] The cut copper-based graphene sample was fixed on the glue machine, and the vacuum pump of the glue machine was turned on to prevent the sample from being displaced during the spin coating process. 20 μL of PMMA anisole solution (wt% is 6%) was added dropwise to the center of the graphene, and the glue machine was started (multi-step operation: the first step: 200rmp, 15s, acceleration is 100rmp / s; the second step: 800rmp, 15s, acceleration is 100rmp / s), so that the PMMA anisole solution is evenly coated on the graphene surface, and placed in an electronic moisture-proof cabinet to dry naturally after the spin coating is completed; Note: The experiment needs to be carried out in a fume hood.

[0093] After drying, PMMA / Gr / Cu was placed in a 0.2 mM potassium persulfate etching solution to etch copper (pay attention to the correct direction of the sample during the etching process to prevent the PMMA layer from contacting the potassium persulfate solution);

[0094] After the copper was completely etched, PMMA / Gr was repeatedly washed with deionized water for five times;

[0095] After thorough cleaning, PMMA / Gr was taken out with the previously prepared h-BN / GaN sample and transferred to an electronic moisture-proof cabinet to dry naturally.

[0096] After drying, place the PMMA / Gr / h-BN / GaN sample on a constant temperature soldering station at 100°C for 30 minutes. After the sample is cooled to room temperature naturally, immerse it in cold acetone for 10 minutes to remove PMMA. Then immerse the sample in hot acetone at about 50°C for 30 minutes, immerse it three times, and deeply remove PMMA. Finally, rinse the sample with ultrapure water for 10 minutes to remove acetone. Note: Since acetone is a volatile and flammable organic reagent, this step needs to be performed in a fume hood.

[0097] Gr / h-BN / GaN annealing process: Place the sample in an annealing furnace at 500°C for 2 hours. After annealing, the preparation of the Gr / h-BN / GaN sample is completed. The purpose of annealing is to deeply remove the PMMA residue on the graphene surface.

[0098] In order to ensure the successful construction of the Schottky interface, firstly, indium needs to be applied to the two vertices of the non-graphene area on the GaN surface using a welding gun and a DC power supply. The contact surface area between indium and GaN should be moderate, approximately 1mm. 2 . After the indium dot is completed, the Gr / GaN sample is placed on the probe station, the vacuum pump switch of the probe station is turned on, the sample is stably fixed on the sample station, the two needles of the needle holder are in contact with the dotted indium, and then the pin wires of the needle holder are connected to the source meter, and the voltage range of the source meter is set to -2.0V-2.0V. After power is turned on, the IV curve is recorded. When the IV curve shows ohmic contact, the Schottky contact between gallium nitride and graphene can be further verified. One needle tip is in contact with the indium dotted on the surface of gallium nitride. In order to prevent the graphene from being punctured by the needle tip, the other needle tip is in contact with the graphene through an indium ball with a radius of about 37um to verify the Schottky contact. The parameters of the probe station and the source meter are the same as those of the ohmic contact to obtain the corresponding IV curve.

[0099] According to the above experimental steps, in order to better study whether the number of h-BN layers can regulate the heterojunction interface barrier, we used n-type gallium nitride as the substrate and prepared 6 samples with different numbers of h-BN layers from 0 to 5 (a total of 12). The samples are numbered as Graphene / GaN, Graphene / 1-h-BN / GaN, Graphene / 2-h-BN / GaN, Graphene / 3-h-BN / GaN, Graphene / 4-h-BN / GaN, and Graphene / 5-h-BN / GaN.

[0100] First, we will conduct research based on n-type gallium nitride:

[0101] The IV curves of Graphene-GaN under different layers of h-BN were measured using a probe station:

[0102] Figure 1 It can be clearly seen that after the GaN surface is covered with Graphene, the rate of change of the current of the Graphene / GaN sample with the voltage increases rapidly, and in this state there is 0 layers of h-BN. As the number of h-BN layers increases, the slope of the IV curve gradually decreases, which shows that h-BN has a regulatory effect on Graphene / GaN.

[0103] According to the thermal electron emission model theory:

[0104]

[0105] Where n is the ideal factor, I 0 is the reverse saturation current, is the graphene / GaN interface barrier height, q is the electron charge, A * is the effective Richardson constant (A for n-type GaN * =26.4Acm -2 K -2 and p-type GaN * =96.1Acm -2 K -2 ) and A is the effective contact area between the indium ball and the graphene surface. According to formulas (1) and (2), we can get:

[0106]

[0107] Taking the differential of lnI with respect to V, we get:

[0108]

[0109] By rearranging formula (2), we can also obtain:

[0110]

[0111] First, we need to calculate the effective contact area A. Assuming that in an ideal state, indium and semiconductor are in perfect ohmic contact, the contact resistance is 0, so the physical contact area can be considered equal to the effective contact area. According to the contact radius r≈34.28μm of the indium ball measured under an optical microscope, the effective contact area A=3.7×10 -5 cm 2 .

[0112] Processed by formula (4) Figure 1 The IV curve under forward bias can be obtained as the lnI-V curve:

[0113] The ideal factors n of n-type samples Graphene / GaN and Graphene / 1-h-BN / GaN are calculated by formula (4), and a schematic diagram of partial data processing and calculation of the two samples is shown, as shown in Figure 4. Figure 2a and Figure 2b As shown. From formula (4), the ideal factor n of different samples can be obtained:

[0114] Figure 3 The change of the influence factor n of the Graphene / n-GaN sample under different numbers of h-BN layers is shown. It can be found that as the number of inserted h-BN layers increases, the performance of the Graphene / GaN sample deviates from the ideal state, but the deviation is small. The possible reason is that as the number of h-BN layers increases, the interface state between the semiconductor and the graphene insertion layer begins to be significant, indirectly changing the performance of electron transmission.

[0115] The barrier height of Graphene / GaN samples with different numbers of h-BN layers is calculated by formulas (5) and (6): Figure 4 As shown, Figure 4 The interface barrier height of graphene / n-GaN samples is shown with different h-BN layers. It can be seen that with the increase of the number of h-BN layers, the barrier height shows a significant increase, and the regulation accuracy can be controlled within a small range. This proves that the graphene / n-GaN interface barrier can be precisely controlled by h-BN.

[0116] Example 2

[0117] Compared with Example 1, in this embodiment, the n-type gallium nitride substrate is replaced by a p-type gallium nitride substrate.

[0118] The IV curves of Graphene / GaN under different layers of h-BN were measured by a probe station, such as Figure 5 It can be clearly seen that after the p-type GaN surface is covered with Graphene, the current of the Graphene / GaN sample also rises rapidly with the rate of change of voltage. In this state, there is 0 layers of h-BN. As the number of h-BN layers increases, the slope of the IV curve gradually decreases, which shows that h-BN has regulatory properties on Graphene / GaN.

[0119] The ideal factors n of the p-type samples Graphene / GaN and Graphene / 1-h-BN / GaN are calculated by formula (4), and a schematic diagram of partial data processing and calculation of the two samples is shown, as shown in Figure 4. Figure 6a and Figure 6b As shown. At the same time, the remaining sample graphs are processed in the same way. According to formula (4), the ideal factors n of different samples can be obtained: Figure 7 The change of the influence factor n of the Graphene / p-GaN sample under different numbers of h-BN layers is shown.

[0120] The barrier height of graphene / p-GaN samples with different numbers of h-BN layers is calculated by formulas (5) and (6): Figure 8 The interface barrier height of graphene / p-GaN samples is shown with different h-BN layers. It can be seen that with the increase of the number of h-BN layers, the barrier height shows a significant increase, and the regulation accuracy can be controlled within a small range. This proves that the graphene / p-GaN interface barrier can be precisely controlled by h-BN.

[0121] In summary, by inserting different numbers of h-BN layers between the graphene / GaN interface based on n-type gallium nitride and p-type gallium nitride, precise control of the interface barrier can be achieved.

[0122] Based on the above implementation cases, it can be clearly seen that the technical solution provided by the present invention can achieve precise control of the interface barrier of the graphene / gallium nitride van der Waals heterojunction by inserting a selected number of hexagonal boron nitride layers between the graphene layer and the gallium nitride substrate of the graphene / gallium nitride van der Waals heterojunction.

[0123] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for regulating the potential barrier of a graphene / gallium nitride van der Waals heterojunction interface, characterized in that: include: A selected number of hexagonal boron nitride layers are inserted between the graphene layer and the gallium nitride substrate to adjust the interface barrier of the graphene / gallium nitride van der Waals heterojunction formed by the graphene layer and the gallium nitride substrate.

2. The method for controlling the interface barrier according to claim 1, characterized in that: The number of the hexagonal boron nitride layers is 1-5.

3. A graphene / gallium nitride van der Waals heterojunction, characterized in that: The invention comprises a gallium nitride substrate, a selected number of hexagonal boron nitride layers and a graphene layer which are stacked in sequence.

4. A method for preparing a graphene / gallium nitride van der Waals heterojunction, characterized in that: include: Providing a first assembly, wherein the first assembly includes a first polymer film and a hexagonal boron nitride layer attached to one side of the first polymer film; Laminating the first assembly to a gallium nitride substrate, with the hexagonal boron nitride layer facing the gallium nitride substrate, and removing the first polymer film to obtain a second assembly; Optionally, the second assembly is attached to the new first assembly and the first polymer film is removed, and the cycle is repeated several times to obtain a stacked assembly; The second assembly or stacked assembly is bonded to a third assembly, wherein the third assembly includes a second polymer film and a graphene layer attached to one side of the second polymer film, wherein the graphene layer faces the hexagonal boron nitride layer, and the second polymer film is removed to obtain a graphene / gallium nitride van der Waals heterojunction.

5. The preparation method according to claim 4, characterized in that: Also includes: The step of annealing the stack of the gallium nitride substrate, the hexagonal boron nitride layer and the graphene layer.

6. The preparation method according to claim 4, characterized in that: Specifically include: Using a first metal substrate to support the hexagonal boron nitride layer; Coating a first polymer solution on the surface of the hexagonal boron nitride layer and drying it to form a film to form the first polymer film; The first metal substrate is removed by etching to obtain the first assembly.

7. The preparation method according to claim 4, characterized in that: Specifically include: Using a second metal substrate to support the graphene layer; Coating a second polymer solution on the surface of the graphene layer and drying the solution to form a second polymer film; The second metal substrate is removed by etching to obtain the third assembly.

8. The preparation method according to any one of claims 4 to 7, characterized in that: Specifically include: The first assembly is floated on the surface of a liquid medium, and the hexagonal boron nitride layer contacts the liquid medium; Using the gallium nitride substrate or the second assembly to carry and transfer the first assembly out of the liquid medium; and / or, The third assembly is floated on the surface of a liquid medium, wherein the graphene layer contacts the liquid medium; The third assembly is carried and transferred from the liquid medium by the second assembly or the stacked assembly.

9. A method for characterizing the interface barrier of a graphene / gallium nitride van der Waals heterojunction, characterized in that: include: Providing a graphene / gallium nitride van der Waals heterojunction prepared by the preparation method according to any one of claims 4 to 8; Forming metal microspheres on the non-covered surface of the gallium nitride substrate, and contacting the metal microspheres with a dual-electrode probe to verify that there is ohmic contact between the metal microspheres and the gallium nitride substrate; Under the premise that the metal microspheres and the gallium nitride substrate are in ohmic contact, an IV curve between the graphene layer and the gallium nitride substrate is measured, and an interface barrier between the graphene layer and the gallium nitride substrate is calculated according to the IV curve.

10. The method for characterizing the interface barrier according to claim 9, characterized in that: The calculation method of the interface barrier is expressed as: in, represents the interface potential barrier; k represents the Boltzmann constant; T represents the temperature in Kelvin; q represents the electron charge; A represents the effective contact area between the metal microsphere and the gallium nitride substrate; A * represents the effective Richardson constant; I0 ​​represents the reverse saturation current.

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