Double-gate MOS structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor preparation processes, and provides a double-gate MOS structure and a preparation method thereof, and the preparation method comprises the steps: providing a substrate; the base comprises a substrate primary body and a shallow trench isolation structure; wherein the substrate primary body comprises an active region defined by the shallow trench isolation structure; a lower concave hole is formed in the surface of the active region; filling the lower concave hole to form a first gate structure primary body, and forming a second gate structure located between the first gate structure primary body and the shallow trench isolation structure on the surface of the active region; cutting the first gate structure initial body and the substrate initial body by taking a plane vertical to the arrangement direction of the active region as a cutting surface to obtain a substrate, a first gate structure and a second gate structure of the double-gate MOS structure; wherein the contact surface of the first gate structure and the substrate is a non-planar surface. Therefore, the problem of short channel effect can be improved without additionally occupying the area of the wafer.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing process technology, and in particular to a dual-gate MOS structure and a manufacturing method thereof. Background Art

[0002] With the continuous advancement of semiconductor manufacturing technology, the size of transistors continues to shrink, allowing more transistors to be accommodated per unit area, thereby greatly improving the integration and performance of chips, and promoting the improvement of computing power and processing speed.

[0003] However, as the size of transistors continues to shrink, the accompanying technical challenges are becoming more complex, especially in MOSFET (metal-oxide-semiconductor field-effect transistor, MOS), where the short channel effect problem is becoming increasingly prominent. The short channel effect refers to the weakening of the gate's ability to influence the channel when the channel length of the transistor is shortened to a certain extent, resulting in unstable switching characteristics of the transistor, thereby increasing leakage current. This not only affects the operating efficiency of the MOSFET, but may also reduce its reliability in high-density integrated circuits. As the size of MOSFETs further decreases, the impact of the short channel effect on performance will become more significant. Therefore, how to effectively reduce or eliminate the short channel effect is an urgent problem to be solved in related technologies. Summary of the invention

[0004] In view of this, multiple embodiments of the present application are directed to providing a dual-gate MOS structure and a method for manufacturing the same, which can improve the short channel effect problem existing in the related art to a certain extent.

[0005] An embodiment of the present application provides a dual-gate MOS structure, comprising: a substrate, a surface of the substrate having a recessed concave portion, and the concave portion also has a recess formed on a side surface adjacent to the substrate surface; a first gate structure, the first gate structure is embedded in the concave portion; and a second gate structure is located on the surface of the substrate between the first gate structure and a shallow trench isolation structure; wherein a contact surface formed by the first gate structure contacting the side wall of the concave portion is non-planar.

[0006] Optionally, the substrate and the first gate structure of the dual-gate MOS structure are obtained by cutting the first gate structure precursor and the substrate precursor; wherein the substrate precursor has an active area defined by a shallow trench isolation structure; a recessed hole is formed on the surface of the active area, and the gate structure precursor is filled in the recessed hole; wherein the recessed portion is formed by part of the side wall and part of the bottom of the recessed hole after being cut.

[0007] Optionally, a contact contour line is formed at the interface between the contact surface and the substrate surface; the contact contour line has a bent shape, or the contact contour line is in an arc shape.

[0008] Optionally, source and drain regions are also formed in the substrate and are located on both sides of the first gate structure and the second gate structure; wherein the first gate structure and the second gate structure correspond to different channels respectively; wherein an extension direction of the channel corresponding to the first gate structure is consistent with an extension direction of the contact surface between the source and drain regions, so that the length of the channel corresponding to the first gate structure is greater than the spacing between the source and drain regions.

[0009] Optionally, the first gate structure and the second gate structure respectively form a first MOS structure and a second MOS structure with the substrate; wherein the first MOS structure and the second MOS structure have different threshold voltages respectively.

[0010] Optionally, contact holes are respectively arranged on the source and drain regions, the first gate structure and the second gate structure; wherein the contact holes are filled with metal material, and a connecting layer covered by the metal material is formed on the sidewalls and the bottom of the contact holes; wherein a contact connecting layer is also arranged between the contact holes on the source and drain regions and the source and drain regions.

[0011] Optionally, an extension direction of the channel is parallel to a surface of the substrate.

[0012] Another embodiment of the present application provides a method for preparing a dual-gate MOS structure, which is used to prepare the dual-gate MOS structure as described above; the preparation method comprises: providing a substrate; the substrate comprises a substrate precursor and a shallow trench isolation structure; wherein the substrate precursor comprises an active area defined by the shallow trench isolation structure; a recessed hole is formed on the surface of the active area; a first gate structure precursor is filled in the recessed hole, and a second gate structure located between the first gate structure precursor and the shallow trench isolation structure is formed on the surface of the active area; the first gate structure precursor and the substrate precursor are cut with a plane perpendicular to the arrangement direction of the active area as a cutting plane to obtain the substrate, the first gate structure and the second gate structure of the dual-gate MOS structure; wherein part of the sidewall and part of the bottom of the recessed hole form the recessed portion.

[0013] Optionally, in the step of cutting the first gate structure precursor and the substrate precursor using a plane perpendicular to the arrangement direction of the active regions as a cutting plane, the cutting plane passes through the center of the first gate structure precursor.

[0014] Optionally, the active area includes an outer hole area surrounding the recessed hole; the steps of filling the recessed hole to form a first gate structure precursor, and forming a second gate structure located between the first gate structure precursor and the shallow trench isolation structure on the surface of the active area include: setting a dielectric layer in the active area; wherein the dielectric layer located in the outer hole area has a different thickness and / or material from the dielectric layer located in the recessed hole; filling the recessed hole with the dielectric layer formed therein with a first gate material to form a first gate structure precursor, and setting a second gate material on the dielectric layer in the outer hole area to form a second gate structure.

[0015] Optionally, the preparation method of the dual-gate MOS structure also includes: forming source and drain regions on both sides of the first gate structure and the second gate structure in the substrate; wherein the first gate structure and the second gate structure correspond to different channels respectively; the extension direction of the channel corresponding to the first gate structure is consistent with the extension direction of the contact surface between the source and drain regions, so that the length of the channel corresponding to the first gate structure is greater than the spacing between the source and drain regions; forming a contact bonding layer on the surface of the source and drain regions, and making contact holes on the surfaces of the contact bonding layer, the first gate structure and the second gate structure respectively; forming a connecting layer on the sidewall and bottom of the contact hole, and filling it with metal material; wherein the connecting layer is covered by the metal material.

[0016] The unexpected effect of the multiple embodiments provided by the present application is that, by forming a recessed hole on the surface of the active area of ​​the substrate body, and forming a first gate structure and a second gate structure in the recessed hole and on the surface of the active area between the recessed hole and the shallow trench isolation structure, a double-gate MOS structure consisting of the second gate structure, the first sub-gate structure and the substrate can be obtained after cutting. In the double-gate MOS structure thus prepared, while the electric field control capability is improved by the second gate structure, the contact surface between the first gate structure and the substrate is a part of the side wall of the recessed hole, so that the length of the channel corresponding to the first gate structure is increased without occupying additional wafer area, thereby improving the short channel effect and improving the performance of the double-gate MOS structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0018] Figures 2 to 4 A schematic diagram of a substrate is provided in the method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0019] Figure 5 A schematic diagram of forming a dielectric layer in a method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0020] Figure 6 A schematic diagram of forming a preliminary body of a first gate structure in a method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0021] Figure 7 A schematic diagram of forming a second gate structure in the method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0022] Figure 8 A schematic diagram of forming a dual-gate MOS structure in the method for preparing the dual-gate MOS structure provided in an embodiment of the present application.

[0023] Fig. 9 A schematic cross-sectional view of a substrate in a method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0024] Fig.10 A three-dimensional reference schematic diagram of a substrate in a method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0025] Fig.11 A cross-sectional view of a dual-gate MOS structure in a method for preparing the dual-gate MOS structure provided in an embodiment of the present application.

[0026] Fig.12 A three-dimensional reference schematic diagram of a dual-gate MOS structure in a method for preparing the dual-gate MOS structure provided in an embodiment of the present application.

[0027] Fig.13 A schematic diagram of forming source and drain regions in a method for preparing a dual-gate MOS structure provided in an embodiment of the present application.

[0028] Fig.14 A schematic diagram of fabricating a contact connection layer and a contact hole in a method for fabricating a dual-gate MOS structure provided in an embodiment of the present application.

[0029] Description of reference numerals: 10. substrate; 11. shallow trench isolation structure; 12. substrate precursor; 121. substrate; 13. active area; 14. recessed hole; 141. part of the side wall; 142. part of the bottom; 15. area outside the hole; 16. dielectric layer; 161. dielectric layer in the recessed hole; 162. dielectric layer in the area outside the hole; 17. first gate material; 18. first gate structure precursor; 181. first gate structure; 19. second gate material; 20. dual-gate MOS structure; 21. second gate structure; 22. contact contour line; 23. recessed part; 24. source and drain area; 122. deep well area; 123. well area; 25. contact connection layer; 26. metal material; 27. connection layer; aa. active area arrangement direction; bb. extension direction of the channel corresponding to the first gate structure. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0031] In the present application, the drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show details of the local features.

[0032] Unless otherwise stated, all technical and scientific terms used in this application have the same meaning as those generally understood by those skilled in the art of the technical field of this application. The terms used in this application are only for the purpose of describing the specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above-mentioned" and "the" used in the embodiments of this application are also intended to include majority forms, unless the context clearly indicates other meanings.

[0033] In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0034] In the description of the present application, terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of simplified description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation on the present application.

[0035] In the description of this application, unless otherwise clearly defined, the terms "install", "connect", "connect", "fix", "set", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0036] In order to achieve higher integration and performance improvement within a limited chip area, the continuous reduction of semiconductor manufacturing process nodes has become a trend. This trend makes the size of transistors smaller and smaller, and the number of transistors that can be accommodated per unit area has increased significantly, thereby significantly improving the computing power and operating speed of the chip. However, the technical problems brought about by the reduction in transistor size are becoming more and more severe, especially the short channel effect. This problem will weaken the gate's ability to influence the channel and increase leakage current, which will seriously affect and limit the performance and reliability of the transistor.

[0037] In related technologies, in order to effectively alleviate the short channel effect, new dual-gate or multi-gate MOSFET structures such as FinFET and GAA (Gate-All-Around) have emerged. Compared with traditional MOSFET, dual-gate or multi-gate MOSFET structures can effectively reduce leakage current by enhancing the gate's ability to influence the channel's electric field, and maintain good switching characteristics at a smaller size to mitigate the negative impact of the short channel effect.

[0038] However, although these new dual-gate or multi-gate MOSFET structures can effectively improve transistor performance and alleviate the impact of short channel effects to a certain extent, they are also accompanied by more complex manufacturing processes. Taking FinFET as an example, its fin-shaped structure requires precise engraving of multiple vertical fins on the wafer and controlling their spacing and height. This not only requires more photolithography and etching process steps, but also requires additional wafer area. The wafer utilization rate under the same size conditions is not high, which increases the manufacturing cost and difficulty, resulting in higher requirements for semiconductor manufacturing processes.

[0039] Therefore, it is necessary to provide a method for preparing a dual-gate MOS structure, which can prepare a dual-gate MOS structure capable of improving the short channel effect while occupying the same wafer area.

[0040] See also Figure 1-Figure 14 An embodiment of the present application provides a method for preparing a dual-gate MOS structure. The dual-gate MOS structure may be a basic structure consisting of a substrate and a gate formed on the substrate, or may be a semiconductor structure formed after a back-end process such as an ion implantation process, a contact hole process, etc. The method for preparing the dual-gate MOS structure may include the following steps.

[0041] S110: providing a substrate.

[0042] In this embodiment, if Figure 4As shown in the figure, the substrate 10 includes a substrate body 12 and a shallow trench isolation structure 11; wherein the substrate body 12 includes an active area 13 defined by the shallow trench isolation structure 11, and a recessed hole 14 is formed on the surface of the active area 13. The active area 13 also includes an outer hole area 15 surrounding the recessed hole 14.

[0043] In this embodiment, the substrate precursor 12 can be used as the basic structure of the dual-gate MOS structure, not only for providing mechanical support, but also for affecting the electrical properties of the dual-gate MOS structure, such as threshold voltage and carrier mobility, by doping ions. Specifically, the substrate precursor 12 can be made of silicon (Si), or can be made of other semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN), etc., according to requirements.

[0044] In this embodiment, a shallow trench isolation structure 11 (Shallow Trench Isolation, STI) is used to form effective electrical isolation between different active regions 13 by etching a shallow trench in a substrate precursor 12 and filling it with an insulating material, such as silicon dioxide SiO2, thereby reducing parasitic capacitance and leakage current and improving the performance and reliability of the dual-gate MOS structure.

[0045] In this embodiment, reference Figure 2 and Figure 3 , a shallow trench isolation structure 11 can be first made on the surface of the wafer, the position and size of the active area can be defined by the shallow trench isolation structure 11, and then the well area can be formed by ion doping. Depending on the type of MOS structure prepared, the ion doping type of the well area is different. For example, for an NMOS structure, the ion doping type of the well area is P-type. For a PMOS structure, the ion doping type of the well area is N-type. In some embodiments, before forming the well area, a deep well area can also be formed by doping ions of the opposite ion doping type to the well area. The well area can be located on the deep well area. For example, for an NMOS structure, the ion doping type of the deep well area is N-type. For a PMOS structure, the ion doping type of the deep well area is P-type.

[0046] Then, if Figure 3 and Figure 4 As shown in , a concave lower hole 14 can be etched on the surface of the active area 13 by photolithography and etching processes to obtain a substrate 10. Specifically, the size of the lower hole 14 can be flexibly set according to actual needs, and the present application does not make specific restrictions on this. In this embodiment, an active area 13 (Active Area) can be defined on the substrate body 12 by a shallow trench isolation structure 11. The area of ​​the substrate body 12 between adjacent shallow trench isolation structures 11 is the active area 13. The active area 13 can be used as a specific area for making transistors and other active devices.

[0047] In this embodiment, the lower recessed hole 14 may be formed with a hole contour on the surface of the active area 13. The hole contour of the lower recessed hole 14 may serve as a boundary to divide the active area 13 into an inner hole area and an outer hole area 15 surrounding the lower recessed hole 14. Specifically, the shape of the hole contour may be an ellipse, a polygon, etc. In some embodiments, the depth of the lower recessed hole 14 relative to the surface of the active area 13 may be less than the thickness of the well area, that is, the lower recessed hole 14 does not penetrate the well area. In some embodiments, the hole contour of the lower recessed hole 14 is circular, and the diameter of the hole contour of the lower recessed hole 14 may be three times the gate width in a conventional MOS structure.

[0048] S120: Filling the recessed hole to form a first gate structure precursor, and forming a second gate structure located between the first gate structure precursor and the shallow trench isolation structure on the surface of the active region.

[0049] In this embodiment, the steps of filling the lower recessed hole to form a preliminary body of a first gate structure, and forming a second gate structure located between the lower recessed hole and the shallow trench isolation structure on the surface of the active area may include: setting a dielectric layer in the active area; wherein the dielectric layer located in the area outside the hole has a different thickness and / or material from the dielectric layer located in the lower recessed hole; filling the lower recessed hole with the dielectric layer formed therein with a first gate material to form a preliminary body of a first gate structure, and setting a second gate material on the dielectric layer in the area outside the hole to form a second gate structure.

[0050] In some embodiments, reference Figure 4 and Figure 5 , an oxide can be grown on the surface of the active area 13 by using a furnace tube process to form a dielectric layer 16, and the area where the oxide does not need to be grown is blocked by a hard mask, and the dielectric layer 16 covers the surface of the area outside the hole 15 and the sidewalls and bottom of the lower concave hole 14. Among them, the dielectric layer 162 in the area outside the hole and the dielectric layer 161 located in the lower concave hole can have different thicknesses by controlling the different durations of the furnace tube process. Of course, in some embodiments, the thickness of the dielectric layer 16 formed on the surface of the active area 13 can also be uniform, that is, the thickness of the dielectric layer 162 located in the area outside the hole and the dielectric layer 161 located in the lower concave hole can also be the same. Specifically, the thickness of the dielectric layer 16 can be flexibly set according to actual needs by controlling the duration of the furnace tube process. For example, if a dual-gate MOS structure for a high-voltage device needs to be prepared, the furnace tube is applied for a longer time to make the thickness of the dielectric layer 16 thicker.

[0051] In some embodiments, the dielectric layer 162 located in the area outside the hole may not completely cover the surface of the area outside the hole 15, but only cover part of the surface of the area outside the hole 15, such as covering the surface of the area outside the hole 15 between the recessed hole 14 and the shallow trench isolation structure 11, or only covering the surface of the area outside the hole 15 corresponding to the position where the second gate structure is subsequently set.

[0052] In some embodiments, Figure 6 As shown in , by filling the first gate material 17, such as polysilicon or metal, into the lower recess 14 formed with a dielectric layer and polishing it by CMP, a first gate structure precursor 18 consisting of the first gate material 17 and the dielectric layer 161 located in the lower recess on the side wall of the lower recess is formed, wherein the dielectric layer 161 located in the lower recess on the side wall of the lower recess serves as the gate dielectric layer of the first gate structure precursor 18. Specifically, in the first gate structure precursor 18, the height of the first gate material 17 can be flush with the substrate surface or higher than the substrate surface. Then, as shown in FIG. Figure 7 As shown in , a certain thickness (e.g., 800Å) of polysilicon can be deposited on the dielectric layer 162 in the area outside the hole, and a second gate material 19 disposed between the first gate structure body 18 and the shallow trench isolation structure 11 can be formed by using a photolithography and etching process, so as to form a second gate structure 21 composed of the second gate material 19 and the dielectric layer 162 in the area outside the hole, wherein the dielectric layer 162 in the area outside the hole covered by the second gate material 19 serves as the gate dielectric layer of the second gate structure. In some embodiments, the second gate material 19 can be the same material as the first gate material 17, or a different material. For example, in addition to polysilicon, the second gate material 19 can also be other materials such as metal.

[0053] In this embodiment, the size of the second gate material 19 along the active area arrangement direction may be consistent with the spacing between the first gate structure body 18 and the shallow trench isolation structure 11, or may be smaller than the spacing between the first gate structure body 18 and the shallow trench isolation structure 11. Specifically, for example, along the active area arrangement direction, the second gate material 19 may have a spacing with both the first gate structure body 18 and the shallow trench isolation structure 11, or may have a spacing with only one of them, for example Figure 7 As shown in the figure, the second gate material 19 is only spaced apart from the first gate structure precursor 18 , and the spacing can be flexibly set according to the requirements.

[0054] S130: Using a plane perpendicular to the arrangement direction of the shallow trench isolation structure as a cutting plane, the first gate structure initial body and the substrate initial body are cut to obtain a dual-gate MOS structure consisting of the first gate structure, the second gate structure and the substrate; wherein the substrate includes a recessed portion formed by a portion of the sidewall and a portion of the bottom of the recessed hole; the first gate structure contacts the sidewall of the recessed portion, and the contact surface is a non-planar surface.

[0055] In this embodiment, reference Figure 7 and Figure 8, a cutting process is performed perpendicular to the arrangement direction aa of the shallow trench isolation structure 11, wherein the cutting surface is a plane perpendicular to the arrangement direction aa of the active area, and passes through the substrate precursor 12 and the first gate structure precursor 18 at the same time, so as to realize the simultaneous cutting of the gate structure and the substrate precursor 12. Specifically, for example, for the first gate material 17 of polysilicon, a poly-cut process can be used to define the shape of a poly-cut at the center of the first gate structure precursor 18, and then two independent dual-gate MOS structures 20 are obtained by cutting. Each dual-gate MOS structure 20 is respectively composed of the cut second gate structure 21, the first gate structure 181 and the substrate 121.

[0056] In this embodiment, the cutting surface for cutting the first gate structure precursor 18 and the substrate precursor 12 can pass through the center of the first gate structure precursor 18 to obtain a dual-gate MOS structure 20 with a first gate structure 181 of the same size, or can pass through other positions of the gate structure to obtain a dual-gate MOS structure 20 with a first gate structure 181 of different sizes. The specific cutting surface can be flexibly adjusted according to actual needs.

[0057] In this embodiment, please refer to Figure 4 as well as Figures 8 to 12 , Fig. 9 and Fig.10 For along Figure 8 The cross-sectional diagram at the dotted line position, where: Fig. 9 is a schematic diagram of a substrate 121, Fig.11 Schematic diagram of a dual-gate MOS structure 20 composed of a second gate structure 21, a first gate structure 181 and a substrate 121. In some embodiments, the substrate 121 may be formed with a well region 123 and a deep well region 122. Fig.10 and Fig.12 They are three-dimensional reference diagrams of the substrate 121 and the dual-gate MOS structure 20 , respectively.

[0058] In this embodiment, since the first gate structure precursor 18 is cut while the lower recessed hole 14 filled with the first gate structure precursor 18 is also cut, in the cut substrate 121, as shown in FIG. Fig. 9 As shown, part of the sidewall 141 and part of the bottom 142 of the recessed hole 14 can form a recessed portion 23. In the cut dual-gate MOS structure 20, the Figure 4 as well as Figures 8 to 10 The first gate structure 181 is embedded in the concave portion 23 of the substrate 121. The contact surface between the first gate structure 181 and the concave portion 23 is the side wall of the concave portion 23, that is, part of the side wall 141 of the concave hole 14. It can be understood that the contact surface is non-planar.

[0059] In this embodiment, the unexpected effect is that by forming a recessed hole 14 on the surface of the active area 13 of the substrate precursor 12, and forming a first gate structure precursor 18 and a second gate structure 21 in the recessed hole 14 and on the surface of the active area 13 between the recessed hole 14 and the shallow trench isolation structure 11, respectively, a dual-gate MOS structure 20 consisting of the second gate structure 21, the first gate structure 181 and the substrate 121 can be obtained after cutting. In the dual-gate MOS structure 20 thus prepared, while the electric field control capability is improved by the second gate structure 21, since the contact surface between the first gate structure 181 and the substrate 121 is a part of the side wall 141 of the recessed hole 14, the length of the channel corresponding to the first gate structure 181 is increased without occupying additional wafer area, thereby improving the short channel effect and improving the performance of the dual-gate MOS structure 20.

[0060] Moreover, compared with some dual-gate or multi-gate structures in the related art, the dual-gate MOS structure 20 provided in this embodiment has a higher utilization rate of the active area under the premise of a pre-defined active area size. At the same time, the manufacturing process complexity is low, and the process flexibility is also strong under the premise of the same wafer area utilization rate.

[0061] In addition, the dual-gate process used in this embodiment can not only reduce the leakage current Ioff of the subsequently manufactured product, but also realize the efficient integration of circuits with different requirements, thereby improving product performance and the flexibility of process integration.

[0062] In some embodiments, the dielectric layer in the hole outer region and the dielectric layer in the recessed hole are made of different materials; and / or the first gate material and the second gate material are made of different materials.

[0063] In some embodiments, Figure 6 and Figure 7 As shown in , since the dielectric layer 162 in the outer region of the hole and the dielectric layer 161 in the lower recessed hole are respectively used as gate dielectric layers corresponding to different gates in the dual-gate MOS structure after being cut, the two are differentiated by different materials. The electric field control capability of the dual-gate MOS structure can be further improved, the leakage current can be reduced, and the adjustability and flexibility of the threshold voltage can be improved. Specifically, for example, the dielectric layer 161 in the lower recessed hole can be silicon dioxide, and the dielectric layer 162 in the outer region of the hole can be silicon nitride or a high-k material such as hafnium oxide or zirconium oxide. In some embodiments, based on similar principles, the use of a first gate material 17 and a second gate material 19 of different materials can also improve the performance and flexibility of the dual-gate MOS structure.

[0064] In some embodiments, a contact contour line is formed at the interface between the contact surface and the surface of the sub-substrate, and the contact contour line has a bend.

[0065] In some embodiments, Figure 8 As shown in FIG. 1 , in the dual-gate MOS structure 20 prepared, the contact surface between the first gate structure 181 and the substrate 121 can form a contact contour line 22 at the interface with the substrate 121. Fig. 9 Since the contact surface is a part of the side wall 141 of the concave hole during the preparation process, the shape of the contact contour line 22 can depend on the shape of the hole contour of the concave hole. Specifically, the contact contour line 22 can have a bending morphology, such as a fold line with one bend or multiple bends. In this way, the channel corresponding to the first gate structure 181 can extend along the contact contour line 22, thereby increasing the channel length under the same size conditions.

[0066] In some embodiments, the contact contour line 22 may be in the shape of an arc.

[0067] In some embodiments, when the hole contour of the recessed hole is circular, it can be understood that in the dual-gate MOS structure 20 obtained after cutting, the contact contour line 22 of the contact surface between the first gate structure 181 and the substrate 121 can be arc-shaped.

[0068] In some embodiments, when the contact contour line 22 is in an arc shape, the channel corresponding to the first gate structure 181 can be made smoother, which can reduce the occurrence of tip discharge due to the channel being not smooth enough compared to shapes such as a fold line.

[0069] In some embodiments, the preparation method of the dual-gate MOS structure may further include: forming source and drain regions located on both sides of the first gate structure and the second gate structure in the sub-substrate; wherein the first gate structure and the second gate structure correspond to different channels respectively; the extension direction of the channel corresponding to the first gate structure is consistent with the extension direction of the contact surface between the source and drain regions, so that the length of the channel corresponding to the first gate structure is greater than the spacing between the source and drain regions.

[0070] In some embodiments, reference Fig.13 ,against Figure 8 The dual-gate MOS structure 20 shown in the figure can also form source and drain regions 24 in the substrate 121 on both sides of the first gate structure 181 and the second gate structure 21 through an ion implantation process. In some embodiments, a lightly doped region (LDD) and a pocket region (Pocket) can also be formed. In this way, the length of the channel corresponding to the first gate structure 181 can be greater than the spacing between the source and drain regions 24, that is, the channel length under the same size condition is increased, thereby improving the short channel effect. Figure 4, taking the preparation process in which the hole profile of the lower concave hole 14 is circular and the cutting surface passes through the center of the first gate structure 18 as an example, the diameter of the hole profile can be 40nm, and the channel length of the first gate structure 181 can be 62.8nm, which is 57% longer. In some embodiments, the extension direction bb of the channel corresponding to the first gate structure 181 can be parallel to the surface of the substrate 121.

[0071] In some embodiments, the channel corresponding to the second gate structure 21 is different from the channel corresponding to the first gate structure 181. The channel direction corresponding to the second gate structure 21 can be the same as the arrangement direction of the source and drain regions 24. In this way, in the dual-gate MOS structure 20, since the channels corresponding to each gate structure are different, the first gate structure 181 and the second gate structure 21 can be respectively used as two independent components of MOS with different threshold voltages. Specifically, the first gate structure 181 and the second gate structure 21 respectively constitute the first MOS structure and the second MOS structure with the substrate 121, and the first MOS structure and the second MOS structure have different threshold voltages. Among them, the source and drain region 24 is a common area of ​​the first MOS structure and the second MOS structure. In this way, the performance of the dual-gate MOS structure 20 and the flexibility of integration for different needs can be further improved.

[0072] In some embodiments, the preparation method of the dual-gate MOS structure may also include: forming a contact bonding layer on the surface of the source and drain regions, and making contact holes on the surfaces of the contact bonding layer, the first gate structure and the second gate structure respectively; forming a connecting layer on the sidewall and bottom of the contact hole, and filling it with metal material; wherein the connecting layer is covered with the metal material.

[0073] In some embodiments, after forming the source and drain regions 24, as Fig.14 As shown, a contact layer 25 may be further formed on the surface of the source / drain region 24 to serve as a contact between the metal material 26 and the source / drain region 24. Specifically, the contact layer may be made of metal silicide, such as silicon nickel.

[0074] Then, contact holes are made on the surface of the contact connection layer 25 corresponding to the source and drain regions 24, and on the surfaces of the first gate structure 181 and the second gate structure 21, and metal material 26, such as metal tungsten, is filled in the contact holes. In some embodiments, a connection layer 27 that wraps the metal material may also be provided on the sidewalls and bottom of the contact hole. Specifically, the connection layer 27 may be located between the contact hole and the metal material 26. The connection layer 27 may be composed of metal titanium and titanium nitride. The connection layer 27 can prevent the diffusion of the metal material 26 and increase adhesion.

[0075] An embodiment of the present application provides a dual-gate MOS structure, and the dual-gate MOS structure is prepared by using the preparation method of the dual-gate MOS structure described in any of the aforementioned embodiments.

[0076] Specifically, in this embodiment, if Figures 8 to 12 As shown, the dual-gate MOS structure 20 may specifically include: a substrate 121 , a first gate structure 181 and a second gate structure 21 .

[0077] In this embodiment, a concave lower concave portion 23 is formed on the surface of the substrate 121, and the lower concave portion 23 is also concave on the side adjacent to the surface of the substrate 121. It should be noted that the concave direction of the lower concave portion 23 on the surface of the substrate 121 is different from that formed on the side. The concave portion 23 on the surface of the substrate 121 extends from the surface of the substrate 121 to the bottom of the lower concave portion 23 (part of the bottom 142 of the lower concave hole 14), while the concave portion 23 on the side adjacent to the surface of the substrate 121 extends from the side along the side wall of the lower concave portion 23 (part of the side wall 141 of the lower concave hole 14).

[0078] In this embodiment, the shape of the first gate structure 181 can match the concave portion 23 to be embedded in the concave portion 23. The contact surface formed by the first gate structure 181 contacting the sidewall of the concave portion 23 is a non-planar surface.

[0079] In this embodiment, the second gate structure 21 may be disposed on the substrate surface between the first gate structure 181 and the shallow trench isolation structure 11 .

[0080] In some embodiments, the substrate and the first gate structure of the dual-gate MOS structure are obtained by cutting the first gate structure precursor and the substrate precursor; wherein the substrate precursor has an active area defined by a shallow trench isolation structure; a recessed hole is formed on the surface of the active area, and the gate structure precursor is filled in the recessed hole; wherein the recessed portion is formed by part of the side wall and part of the bottom of the recessed hole after being cut.

[0081] In some embodiments, a contact contour line is formed at the interface between the contact surface and the substrate surface; the contact contour line has a bent shape, or the contact contour line is in an arc shape.

[0082] In some embodiments, source and drain regions are also formed in the substrate and are located on both sides of the first gate structure and the second gate structure; wherein the first gate structure and the second gate structure correspond to different channels respectively; wherein an extension direction of the channel corresponding to the first gate structure is consistent with an extension direction of the contact surface between the source and drain regions, so that the length of the channel corresponding to the first gate structure is greater than the spacing between the source and drain regions.

[0083] In some embodiments, the first gate structure and the second gate structure respectively form a first MOS structure and a second MOS structure with the substrate; wherein the first MOS structure and the second MOS structure respectively have different threshold voltages.

[0084] In some embodiments, contact holes are respectively provided on the source and drain regions, the first gate structure, and the second gate structure; wherein the contact holes are filled with metal material, and a connecting layer covered by the metal material is formed on the sidewalls and the bottom of the contact holes; wherein a contact connecting layer is also provided between the contact holes on the source and drain regions and the source and drain regions.

[0085] In some embodiments, an extension direction of the channel is parallel to a surface of the substrate.

[0086] It should be noted that, in this embodiment, the explanation of the dual-gate MOS structure and its various parts can refer to the aforementioned embodiments and will not be repeated here.

[0087] In this embodiment, an unexpected effect is that while the dual-gate MOS structure 20 improves the electric field control capability through the second gate structure 21, since the contact surface between the first gate structure 181 and the substrate 121 is a partial side wall 141 of the lower recess 14, the length of the channel corresponding to the first gate structure 181 is increased without occupying additional wafer area, thereby improving the short channel effect and improving the performance of the dual-gate MOS structure 20.

[0088] In this embodiment, the dual-gate MOS structure can also be applied to high-voltage devices, and can improve the breakdown voltage of the high-voltage devices under the same size conditions.

[0089] It should be understood that the specific examples in this article are only intended to help those skilled in the art to better understand the embodiments of the present application, rather than to limit the scope of the present invention.

[0090] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0091] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0092] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application are identical with the meanings generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments, and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above-mentioned" and "the" used in the embodiments of the present application are also intended to include majority forms, unless the context clearly indicates other meanings.

[0093] The above description is only a specific embodiment of the present application, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A dual-gate MOS structure, characterized in that: include: A substrate, wherein a concave portion is formed on the surface of the substrate, and a concave portion is also formed on a side surface adjacent to the substrate surface; a first gate structure, wherein the first gate structure is embedded in the recess; a second gate structure, the second gate structure being located on the surface of the substrate between the first gate structure and the shallow trench isolation structure; Wherein, a contact surface formed by the first gate structure contacting the side wall of the recessed portion is non-planar.

2. The dual-gate MOS structure according to claim 1, characterized in that: The substrate and the first gate structure of the dual-gate MOS structure are obtained by cutting the first gate structure precursor and the substrate precursor; wherein the substrate precursor has an active area defined by a shallow trench isolation structure; a recessed hole is formed on the surface of the active area, and the gate structure precursor is filled in the recessed hole; wherein the recessed portion is formed by part of the side wall and part of the bottom of the recessed hole after being cut.

3. The dual-gate MOS structure according to claim 1, characterized in that: A contact contour line is formed at the interface between the contact surface and the substrate surface; the contact contour line has a bent shape, or the contact contour line is in an arc shape.

4. The dual-gate MOS structure according to any one of claims 1 to 3, characterized in that: The substrate also has source and drain regions formed on both sides of the first gate structure and the second gate structure; wherein the first gate structure and the second gate structure correspond to different channels respectively; wherein an extension direction of the channel corresponding to the first gate structure is consistent with an extension direction of the contact surface between the source and drain regions, so that the length of the channel corresponding to the first gate structure is greater than the spacing between the source and drain regions.

5. The dual-gate MOS structure according to claim 4, characterized in that: The first gate structure and the second gate structure respectively form a first MOS structure and a second MOS structure with the substrate; wherein the first MOS structure and the second MOS structure respectively have different threshold voltages.

6. The dual-gate MOS structure according to claim 4, characterized in that: Contact holes are respectively arranged on the source and drain regions, the first gate structure and the second gate structure; wherein the contact holes are filled with metal material, and a connecting layer covered by the metal material is formed on the sidewalls and the bottom of the contact holes; wherein a contact connecting layer is also arranged between the contact holes on the source and drain regions and the source and drain regions.

7. The dual-gate MOS structure according to claim 4, characterized in that: An extension direction of the channel is parallel to a surface of the substrate.

8. A method for preparing a dual-gate MOS structure, characterized in that: Used to prepare a dual-gate MOS structure according to any one of claims 1 to 7; the preparation method comprises: Providing a substrate; the substrate comprises a substrate body and a shallow trench isolation structure; wherein the substrate body comprises an active area defined by the shallow trench isolation structure; a recessed hole is formed on the surface of the active area; Filling the lower recessed hole to form a first gate structure body, and forming a second gate structure located between the first gate structure body and the shallow trench isolation structure on the surface of the active area; The first gate structure precursor and the substrate precursor are cut with a plane perpendicular to the active area arrangement direction as a cutting plane to obtain the substrate, the first gate structure and the second gate structure of the dual-gate MOS structure; wherein part of the sidewall and part of the bottom of the recessed hole form the recessed portion.

9. The method for preparing a dual-gate MOS structure according to claim 8, characterized in that: In the step of cutting the first gate structure precursor and the substrate precursor by taking a plane perpendicular to the arrangement direction of the active regions as a cutting plane, the cutting plane passes through the center of the first gate structure precursor.

10. The method for preparing a dual-gate MOS structure according to claim 8, characterized in that: The active area includes an outer area surrounding the recessed hole; the steps of filling the recessed hole to form a first gate structure precursor, and forming a second gate structure located between the first gate structure precursor and the shallow trench isolation structure on the surface of the active area include: A dielectric layer is provided in the active area; wherein the dielectric layer located in the area outside the hole has a different thickness and / or material from the dielectric layer located in the recessed hole; A first gate material is filled in the recessed hole formed with the dielectric layer to form a first gate structure precursor, and a second gate material is disposed on the dielectric layer in the area outside the hole to form a second gate structure.

11. The method for preparing a dual-gate MOS structure according to claim 10, characterized in that: The preparation method of the dual-gate MOS structure also includes: Forming source and drain regions on both sides of the first gate structure and the second gate structure in the substrate; wherein the first gate structure and the second gate structure correspond to different channels respectively; an extension direction of the channel corresponding to the first gate structure is consistent with an extension direction of the contact surface between the source and drain regions, so that a length of the channel corresponding to the first gate structure is greater than a spacing between the source and drain regions; Forming a contact layer on the surface of the source and drain region, and making contact holes on the surface of the contact layer, the first gate structure and the second gate structure respectively; A connection layer is formed on the sidewall and the bottom of the contact hole and filled with a metal material; wherein the connection layer is covered by the metal material.

Images